Electrostatic protection device, preparation method and electronic product

Abstract

The invention provides an electrostatic protection device, a preparation method and an electronic product. The electrostatic protection device comprises a substrate, a first well region, a second well region, a third well region, a source region, a drain region and a gate structure, wherein the drain region is configured to be a plurality of doped regions with different conduction types, and the doped regions are arranged as required, so that an SCR structure is integrated in the ESD MOS, and the secondary breakdown current is improved; current-limiting resistors are formed in different areas, so that the purposes of improving secondary breakdown current and reducing the cost of the photomask are achieved; and the area is reduced through layout optimization, and the method is compatible with a CMOS (Complementary Metal Oxide Semiconductor) process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an electrostatic protection device, a preparation method and an electronic product. Background Art

[0002] Failure analysis statistics show that ESD (Electro-Static discharge) / EOS (Electrical Over Stress) causes up to 37% of integrated circuit failures, and ESD events cause economic losses to the electronics industry far exceeding $10 billion each year. Therefore, improving the chip's own resistance to ESD events is the key to reducing economic losses and improving product reliability.

[0003] GGNMOS and GDPMOS can transfer the current path from a thin layer under the gate to a deeper well region, widening the current path and increasing the heat dissipation area. The device can remain intact under the impact of large ESD current. Therefore, ESD MOS is a very important ESD device.

[0004] According to the principle that "ESD protection devices must remain closed when the circuit is in normal working state", the lower limit of the ESD design window should be higher than the normal working voltage VDD of the protected circuit. For the reliability of the design, a 10% margin should be reserved, that is, the lower limit of the window is 1.1VDD. In addition, the upper limit of the ESD design window needs to be determined according to the minimum breakdown voltage BV of the protected circuit. Similarly, the upper limit of the window should also ensure a 10% design margin, that is, the upper limit of the window is 0.9BV. Figure 1 Shown is the ESD design window for devices with hysteresis characteristics; Figure 2 The figure shows the ESD design window of the device without hysteresis characteristics. Among them, It2 is the secondary breakdown current of ESD. In an ESD event, when the current reaches the secondary breakdown current It2, the ESD protection device may be irreversibly damaged. It is the maximum value of the current that the device can safely discharge in an ESD event. The larger the secondary breakdown current It2, the stronger the protection capability of the ESD protection device.

[0005] Currently, the secondary breakdown current It2 of ESD MOS is generally low, and the area is large and the cost is high. How to increase the secondary breakdown current and reduce the area and cost has become one of the problems that technical personnel in this field need to solve urgently.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an electrostatic protection device, a preparation method and an electronic product, which are used to solve the problems of low secondary breakdown current, large area and high cost of ESD MOS in the prior art.

[0008] In order to achieve the above-mentioned object and other related objects, the present invention provides an electrostatic protection device, which at least comprises:

[0009] A substrate, a first well region, a second well region, a third well region, a source region, a drain region and a gate structure;

[0010] The first well region, the second well region and the third well region are formed in the substrate, and the first well region is located between the second well region and the third well region; the gate structure is formed on the first well region; the source region includes a first doped region formed in the second well region and the first well region;

[0011] Wherein, the drain region includes a second doped region formed in the third well region and the first well region, and a third doped region and a fourth doped region formed in the third well region, the third doped region and the fourth doped region are sequentially arranged outside the second doped region along the channel length direction, and the drain terminal electrode is arranged on the third doped region and the fourth doped region; the second doped region is covered with a metal silicide barrier layer; or, the drain region includes a fifth doped region formed in the third well region and the first well region, and a sixth doped region, a seventh doped region and an eighth doped region formed in the third well region, the sixth doped region, the seventh doped region and the eighth doped region are sequentially arranged outside the fifth doped region along the channel width direction, and the drain terminal electrode is arranged on the sixth doped region, the seventh doped region and the eighth doped region; the fifth doped region is covered with a metal silicide barrier layer;

[0012] The substrate, the first well region, the third doped region and the seventh doped region have a first conductivity type, and the second well region, the third well region, the first doped region, the second doped region, the fourth doped region, the fifth doped region, the sixth doped region and the eighth doped region have a second conductivity type.

[0013] In order to achieve the above-mentioned object and other related objects, the present invention further provides an electrostatic protection device, which at least comprises:

[0014] A substrate, a first well region, a second well region, a third well region, a source region, a drain region and a gate structure;

[0015] The first well region, the second well region and the third well region are formed in the substrate, and the first well region is located between the second well region and the third well region; the gate structure is formed on the first well region; the source region includes a first doped region formed in the second well region and the first well region;

[0016] Wherein, the drain region includes a second doped region formed in the third well region and the first well region, and a first shallow trench isolation structure, a third doped region and a fourth doped region formed in the third well region, the first shallow trench isolation structure is located outside the second doped region, the third doped region and the fourth doped region are sequentially arranged outside the first shallow trench isolation structure along the channel length direction, and the drain terminal electrode is arranged on the third doped region and the fourth doped region; or, the drain region includes a fifth doped region formed in the third well region and the first well region, and a second shallow trench isolation structure, a sixth doped region, a seventh doped region and an eighth doped region formed in the third well region; the second shallow trench isolation structure is located outside the fifth doped region, the sixth doped region, the seventh doped region and the eighth doped region are sequentially arranged outside the second shallow trench isolation structure along the channel width direction, and the drain terminal electrode is arranged on the sixth doped region, the seventh doped region and the eighth doped region;

[0017] The substrate, the first well region, the third doped region and the seventh doped region have a first conductivity type, and the second well region, the third well region, the first doped region, the second doped region, the fourth doped region, the fifth doped region, the sixth doped region and the eighth doped region have a second conductivity type.

[0018] More optionally, a body region is also provided in the substrate.

[0019] More optionally, a third shallow trench isolation structure is further formed in the second well region, and the third shallow trench isolation structure is located outside the first doped region.

[0020] More optionally, the first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

[0021] In order to achieve the above-mentioned object and other related objects, the present invention also provides a method for preparing an electrostatic protection device, which is used to prepare the above-mentioned electrostatic protection device. The method for preparing the electrostatic protection device at least comprises:

[0022] 1) providing a substrate, and forming a first well region, a second well region, and a third well region in the substrate;

[0023] 2) forming a gate structure on the first well region using a polysilicon gate process;

[0024] 3) performing source and drain implantation in the structure formed in step 2);

[0025] 4) forming a metal silicide barrier layer on the N-type doped region of the drain region close to the channel;

[0026] 5) Forming terminal electrodes on the structure formed in step 4).

[0027] In order to achieve the above-mentioned object and other related objects, the present invention also provides a method for preparing an electrostatic protection device, which is used to prepare the above-mentioned electrostatic protection device. The method for preparing the electrostatic protection device at least comprises:

[0028] 1) providing a substrate, forming a shallow trench isolation structure in a drain region by a shallow trench isolation process, and forming a first well region, a second well region and a third well region in the substrate;

[0029] 2) forming a gate structure on the first well region using a polysilicon gate process;

[0030] 3) performing source and drain implantation in the structure formed in step 2);

[0031] 4) Electrodes are formed on each end of the structure formed in step 3).

[0032] More optionally, in step 1), a shallow trench isolation structure of the source region is formed by a shallow trench isolation process to define an active region.

[0033] More optionally, in step 3), a body region is formed by ion implantation.

[0034] In order to achieve the above-mentioned object and other related objects, the present invention further provides an electronic product, which at least includes: the above-mentioned electrostatic protection device.

[0035] As described above, the electrostatic protection device, preparation method and electronic product of the present invention have the following beneficial effects:

[0036] 1. The electrostatic protection device and electronic product of the present invention integrates an SCR structure in the ESD MOS, so that the current flows at a deeper position, thereby increasing the secondary breakdown current.

[0037] 2. The electrostatic protection device of the present invention uses the doped region covering the SAB as a current limiting resistor, so that the current distribution of the multi-finger device is uniform, further improving the secondary breakdown current.

[0038] 3. The electrostatic protection device and electronic product of the present invention arrange the N+, P+, and N+ regions of the drain region alternately in the vertical direction, and effectively reduce the area of ​​the electrostatic protection device and the cost through layout optimization.

[0039] 4. The electrostatic protection device of the present invention forms a current limiting resistor in the well region through a shallow trench isolation structure, thereby reducing the use of masks and further reducing the cost of masks.

[0040] 5. The preparation method of the electrostatic protection device of the present invention is fully compatible with CMOS technology and does not increase costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagram of the ESD design window showing a device with snapback characteristics.

[0042] Figure 2 Schematic diagram of the ESD design window showing a device with no hysteresis.

[0043] Figure 3 Shown is a schematic diagram of the GGNMOS structure with SAB.

[0044] Figure 4 Shown is a schematic diagram of the structure of a GGNMOS with SAB and gate resistor RG.

[0045] Figure 5 Shown is a schematic diagram of the structure of a GGNMOS with SAB and ESD implants.

[0046] Figure 6 It is a schematic structural diagram of the electrostatic protection device of the present invention.

[0047] Figure 7 Display as Figure 6 Layout of the electrostatic protection device.

[0048] Figure 8 It is a schematic diagram showing an equivalent circuit of the electrostatic protection device of the present invention.

[0049] Fig. 9 Shown is a schematic structural diagram of a substrate provided for the present invention.

[0050] Fig.10 It is a schematic diagram showing the structure of forming a well region according to the present invention.

[0051] Fig.11 It is a schematic diagram showing the formation of a gate structure according to the present invention.

[0052] Fig.12 It is a schematic diagram of the structure of realizing source-drain injection according to the present invention.

[0053] Fig.13It is a schematic diagram showing the structure of forming a metal silicide barrier layer according to the present invention.

[0054] Fig.14 Another schematic diagram of the structure of the electrostatic protection device of the present invention is shown.

[0055] Fig.15 It is another structural schematic diagram of the electrostatic protection device of the present invention.

[0056] Fig.16 Display as Fig.15 Layout of the electrostatic protection device.

[0057] Fig.17 It is a schematic diagram showing the structure of forming a shallow trench isolation structure and a well region according to the present invention.

[0058] Fig.18 It is a schematic diagram showing the formation of a gate structure according to the present invention.

[0059] Fig.19 It is a schematic diagram of the structure of realizing source-drain injection according to the present invention.

[0060] Fig. 20 Shown is another structural schematic diagram of the electrostatic protection device of the present invention.

[0061] Fig.21 It is a schematic diagram showing the comparison of TLP curves of the GGNMOS of the present invention and the conventional GGNMOS.

[0062] Component number description

[0063] 1. Electrostatic protection device

[0064] 10 P-type substrate

[0065] 11a P-well

[0066] 11b First N well

[0067] 11c Second N well

[0068] 12 Gate structure

[0069] 13 First N-type doping region

[0070] 14a Second N-type doping region

[0071] 14b First P-type doping region

[0072] 14c The third N-type doping region

[0073] 14d Fourth N-type doping region

[0074] 14e Fifth N-type doping region

[0075] 14f Second P-type doping region

[0076] 14g Sixth N-type doping region

[0077] 14h The first shallow trench isolation structure

[0078] 14i Second shallow trench isolation structure

[0079] 15 Metal silicide barrier layer

[0080] 16. The third shallow trench isolation structure

[0081] 17 Body Area DETAILED DESCRIPTION

[0082] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0083] See also Figure 3 to Figure 21 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0084] Figure 3 It is a GGNMOS structure with SAB (salicide block). SAB is added at the drain end. Since the N+ junction is shallow, the current is concentrated on the surface of the device, resulting in a smaller secondary breakdown current It2. Figure 4 As another GGNMOS structure, Figure 3 On this basis, a gate resistor RG is added between the gate and the source. The gate resistor RG can effectively reduce the breakover voltage, but there is almost no improvement on the secondary breakdown current It2. Figure 5 It is another GGNMOS structure. Figure 3 On the basis of this, an ESD implant (P-ESD) is added to the drain end. This ESD protection device can effectively reduce the trigger voltage, making it easier to trigger and provide protection in an ESD event. However, the ESD implant requires an additional mask, which increases the cost, and the secondary breakdown current It2 is not improved.

[0085] Based on the above reasons, the present invention proposes an electrostatic protection device, which integrates an SCR structure (Silicon Controlled Rectifier) ​​in an ESD MOS and reduces the device area and cost by optimizing the layout.

[0086] Embodiment 1

[0087] like Figure 6 and Figure 7 As shown, this embodiment provides an electrostatic protection device 1, comprising:

[0088] A substrate, a first well region, a second well region, a third well region, a source region, a drain region and a gate structure; wherein the first doped region constitutes a source region, and the second doped region, the third doped region and the fourth doped region constitute a drain region. The substrate, the first well region and the third doped region have a first conductivity type, and the second well region, the third well region, the first doped region, the second doped region and the fourth doped region have a second conductivity type; in this embodiment, the electrostatic protection device is an NMOS device, therefore, the substrate is a P-type substrate, the first well region is a P-well, the second well region and the third well region are N-wells (defined as the first N-well and the second N-well, respectively), the first doped region, the second doped region and the fourth doped region are N-type doped regions (defined as the first N-type doped region, the second N-type doped region and the third N-type doped region, respectively), and the third doped region is a P-type doped region (defined as the first P-type doped region).

[0089] Specifically, the P-well 11a, the first N-well 11b and the second N-well 11c are formed in the P-type substrate 10, and the P-well 11a is located between the first N-well 11b and the second N-well 11c; the gate structure 12 is formed on the P-well 11a. Among them, the P-well 11a is used to form the channel of the MOS tube, and the first N-well 11b and the second N-well 11c are used to form the source region and the drain region respectively. The gate structure 12 includes but is not limited to a silicon oxide layer and a polysilicon layer sequentially stacked on the upper surface of the P-well 11a. Any structure that can be used for the transistor gate is applicable to the present invention and can be set according to actual needs, which will not be described one by one here.

[0090] Specifically, the first N-type doping region 13 is formed in the first N-well 11b and the P-well 11a to form a source region. As another implementation of the present invention, a third shallow trench isolation structure 16 (STI, shallow trench isolation) is also provided in the first N-well 11b, and the third shallow trench isolation structure 16 is located outside the first N-type doping region 13, for achieving electrical isolation and ensuring the performance and reliability of the electrostatic protection device 1.

[0091] Specifically, the second N-type doping region 14a, the first P-type doping region 14b and the third N-type doping region 14c (the whole) are formed in the second N-well 11c and the P-well 11a to form a drain region; wherein the second N-type doping region 14a is formed in the second N-well 11c and the P-well 11a, and the first P-type doping region 14b and the third N-type doping region 14c are formed in the second N-well 11c. The second N-type doping region 14a, the first P-type doping region 14b and the third N-type doping region 14c are arranged in sequence along the channel length direction, that is, the second N-type doping region 14a is close to the center of the device, the first P-type doping region 14b is next, and the third N-type doping region 14c is farthest from the center of the device.

[0092] Specifically, the second N-type doping region 14a is covered with a metal silicide barrier layer 15; in this embodiment, in order to ensure that the upper surface of the second N-type doping region 14a is completely covered, the metal silicide barrier layer 15 will slightly extend outward, resulting in the first P-type doping region 14b close to the second N-type doping region 14a is also covered with the metal silicide barrier layer 15, which does not affect the formation of the ohmic contact on the first P-type doping region 14b. The metal silicide barrier layer 15 is used to block the N+ diffusion of the second N-type doping region 14a, thereby reducing the diffusion square resistance of the second N-type doping region 14a and improving the ESD protection performance.

[0093] As another implementation of the present invention, a body region 17 is further provided in the substrate. In this embodiment, the body region 17 is a P-doped region for extracting the substrate potential.

[0094] Specifically, in this embodiment, the gate electrode is disposed on the gate structure 12, the source electrode is disposed on the first N-type doping region 13, the drain electrode is disposed on the first P-type doping region 14b and the third N-type doping region 14c, and the body electrode is disposed on the body region 17. As an example, the electrostatic protection device 1 of this embodiment is a GGNMOS with an integrated SCR structure, and its equivalent circuit is as follows: Figure 8As shown, it includes a current limiting resistor R, a first NPN transistor NPN1, a second NPN transistor NPN2 and a PNP transistor PNP; wherein, one end of the current limiting resistor R is a drain end Drain, and the other end is connected to the collector of the first NPN transistor NPN1; the base and emitter of the first NPN transistor NPN1 are source ends Source; the emitter of the PNP transistor PNP is a drain end Drain, the collector is a source end Source, and the base is connected to the collector of the second NPN transistor NPN2; the base and emitter of the second NPN transistor NPN2 are the source end Source. In this embodiment, the current limiting resistor R is an N+ resistor formed by the second N-type doping region 14a, the first NPN transistor NPN1 is a parasitic transistor formed by the second N-type doping region 14a, the P well 11a and the first N-type doping region 13, the PNP transistor PNP is a parasitic transistor formed by the first P-type doping region 14b, the second N-well 11c and the P well 11a, the second NPN transistor NPN2 is a parasitic transistor formed by the second N-well 11c, the P well 11a and the first N-type doping region 13 / first N well 11b, and the PNP transistor PNP and the second NPN transistor NPN2 form an SCR structure.

[0095] The preparation method of the electrostatic protection device 1 of this embodiment is as follows:

[0096] 1) A substrate is provided, and a first well region, a second well region and a third well region are formed in the substrate.

[0097] Specifically, in this embodiment, Fig. 9 As shown, a P-type substrate 10 is provided; as an example, a wafer with a crystal orientation of (100) is selected as the P-type substrate 10. Fig.10 As shown, a P-well 11a, a first N-well 11b and a second N-well 11c are formed in a P-type substrate 10 by a double-well process; as another implementation method, a shallow trench isolation structure (a third shallow trench isolation structure 16) of the source region is also formed by a shallow trench isolation process to define an active region; the sequence of the double-well process and the shallow trench isolation process can be set as needed, and will not be described in detail here.

[0098] 2) Forming a gate structure on the first well region.

[0099] Specifically, in this embodiment, Fig.11 As shown, a gate structure 12 is formed on the P well 11a using a polysilicon gate process. As an example, the gate structure 12 includes a silicon oxide layer and a polysilicon layer stacked in sequence from bottom to top.

[0100] 3) Perform source and drain implantation in the structure formed in step 2).

[0101] Specifically, in this embodiment, Fig.12As shown, the first N-type doping region 13, the second N-type doping region 14a, the first P-type doping region 14b and the third N-type doping region 14c are formed by ion implantation, thereby obtaining the source region and the drain region. As another implementation, the body region 17 is also formed by ion implantation.

[0102] 4) Forming a metal silicide barrier layer on the N-type doped region of the drain region close to the channel.

[0103] Specifically, in this embodiment, Fig.13 As shown, a metal silicide barrier layer 15 is formed on the second N-type doping region 14 a.

[0104] 5) Forming electrodes on the structure formed in step 4).

[0105] Specifically, the source, drain, gate and body electrodes are formed by deposition and etching; as an example, each electrode includes a metal silicide layer and a metal conductive layer disposed on the metal silicide layer, and the metal silicide layer is used to form an ohmic contact. Figure 6 The electrostatic protection device 1 is shown.

[0106] The electrostatic protection device 1 of the present embodiment is fully compatible with the CMOS process without adding any additional cost; the SCR structure is formed by the first P-type doping region 14b, the second N-well 11c, the P-well 11a and the first N-type doping region 13, so that the current flows at a deeper position, thereby increasing the secondary breakdown current It2; the second N-type doping region 14a covered with a metal silicide barrier layer is used on the current limiting resistor from the drain end to the silicon gate of the present embodiment, so that the current distribution of the multi-finger device is uniform, further increasing the secondary breakdown current It2.

[0107] It should be noted that in this embodiment, the first conductivity type is P type and the second conductivity type is N type. In actual use, the conductivity type can also be configured as: the first conductivity type is N type and the second conductivity type is P type; no further details are given here.

[0108] Embodiment 2

[0109] like Fig.14 As shown, this embodiment provides an electrostatic protection device 1, which is different from the first embodiment in that the N-type doping region, the P-type doping region and the N-type doping region sequentially arranged at the drain end are arranged along the channel width direction.

[0110] Specifically, the drain region includes a fifth doping region, a sixth doping region, a seventh doping region and an eighth doping region. In the present embodiment, the fifth doping region, the sixth doping region and the eighth doping region are N-type doping regions (defined as a fourth N-type doping region, a fifth N-type doping region and a sixth N-type doping region, respectively), and the seventh doping region is a P-type doping region (defined as a second P-type doping region).

[0111] More specifically, the fourth N-type doping region 14d, the fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g (the whole) are formed in the second N-well 11c and the P-well 11a to form a drain region; wherein the fourth N-type doping region 14d is formed in the second N-well 11c and the P-well 11a, and the fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g are formed in the second N-well 11c (located outside the fourth N-type doping region 14d). The fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g are arranged in sequence along the channel width direction, thereby effectively reducing the area occupied by the electrostatic protection device on the chip, and the reduced area is about 10%. In addition, the metal silicide barrier layer 15 covers the fourth N-type doping region 14d.

[0112] It should be noted that the other structures are the same as those in the first embodiment, and the first conductivity type and the second conductivity type can also be configured as needed, which will not be described one by one here. The preparation method of the electrostatic protection device of this embodiment is basically the same as that of the first embodiment, except that: the doping region of the drain region in step 3) is the fourth N-type doping region 14d, the fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g, and the fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g are arranged along the width direction of the channel, which will not be described one by one here.

[0113] The electrostatic protection device of this embodiment can further reduce the area of ​​the device and achieve miniaturization; at the same time, more devices can be prepared on a silicon wafer of the same area, further reducing the cost.

[0114] Embodiment 3

[0115] like Fig.15 and Fig.16 As shown, this embodiment provides an electrostatic protection device 1, which is different from the first embodiment in that an N-well is used as a current limiting resistor from the drain end to the silicon gate, and the use of masks is reduced in the process.

[0116] Specifically, based on the first embodiment, the drain region of this embodiment further includes a first shallow trench isolation structure 14h, which is disposed in the second N-well 11c and between the second N-type doping region 14a and the first P-type doping region 14b. In this case, the metal silicide barrier layer 15 is not required.

[0117] It should be noted that the other structures are the same as those in the first embodiment, and are not described in detail here. The equivalent circuit of the electrostatic protection device 1 of this embodiment is the same as that of the first embodiment (see Figure 8), the difference is that, in this embodiment, the current limiting resistor R is formed by the parasitic resistor of the second N well 11c. In addition, the electrostatic protection device 1 of this embodiment can also be configured with the first conductivity type and the second conductivity type as needed, which is not limited to this embodiment.

[0118] The preparation method of the electrostatic protection device of this embodiment is as follows:

[0119] 1) A substrate is provided, a shallow trench isolation structure is formed in a drain region by a shallow trench isolation process, and a first well region, a second well region and a third well region are formed in the substrate.

[0120] Specifically, in this embodiment, a P-type substrate 10 is provided; as an example, a wafer with a crystal orientation of (100) is selected as the P-type substrate 10. Fig.17 As shown, a shallow trench isolation structure (first shallow trench isolation structure 14h) of the drain region is formed in the P-type substrate 10 by a shallow trench isolation process, and a P well 11a, a first N well 11b and a second N well 11c are formed by a double well process; as another implementation, a shallow trench isolation structure (third shallow trench isolation structure 16) of the source region is also formed by a shallow trench isolation process. The order of the double well process and the shallow trench isolation process can be set as needed, and will not be described one by one here.

[0121] 2) Forming a gate structure on the first well region.

[0122] Specifically, Fig.18 As shown, a gate structure 12 is formed on the P well 11 a by using a polysilicon gate process.

[0123] 3) Perform source and drain implantation in the structure formed in step 2).

[0124] Specifically, in this embodiment, Fig.19 As shown, the first N-type doping region 13, the second N-type doping region 14a, the first P-type doping region 14b and the third N-type doping region 14c are formed by ion implantation, wherein the second N-type doping region 14a and the first P-type doping region 14b are respectively located on both sides of the first shallow trench isolation structure 14h to obtain a source region and a drain region. As another implementation method, the body region 17 is also formed by ion implantation.

[0125] 4) The end electrodes are formed on the structure formed in step 3); the method is the same as step 5) of embodiment 1, and will not be described in detail here.

[0126] The electrostatic protection device of this embodiment does not need to set up a metal silicide blocking layer 15. The second N-type doped region 14a and the first P-type doped region 14b are isolated by the first shallow trench isolation structure 14h. Therefore, a mask for preparing the metal silicide blocking layer 15 can be reduced, thereby simplifying the process and reducing production costs.

[0127] Embodiment 4

[0128] like Fig. 20 As shown, this embodiment provides an electrostatic protection device 1, which is different from the third embodiment in that the N-type doping region, the P-type doping region and the N-type doping region arranged in sequence at the drain end are arranged along the channel width direction.

[0129] Specifically, the drain region includes a fifth doped region, a second shallow trench isolation structure, a sixth doped region, a seventh doped region and an eighth doped region. In the present embodiment, the fifth doped region, the sixth doped region and the eighth doped region are N-type doped regions (defined as a fourth N-type doped region, a fifth N-type doped region and a sixth N-type doped region, respectively), and the seventh doped region is a P-type doped region (defined as a second P-type doped region).

[0130] More specifically, the fourth N-type doping region 14d, the second shallow trench isolation structure 14i, the fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g (the whole) are formed in the second N-well 11c and the P-well 11a to form a drain region; wherein the fourth N-type doping region 14d is formed in the second N-well 11c and the P-well 11a, and the second shallow trench isolation structure 14i, the fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g are formed in the second N-well 11c. The second shallow trench isolation structure 14i is located outside the fourth N-type doping region 14d; the fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g are located outside the second shallow trench isolation structure 14i, and are arranged in sequence along the channel width direction, thereby effectively reducing the area occupied by the electrostatic protection device by 10%.

[0131] It should be noted that the other structures are the same as those in the third embodiment, and the first conductivity type and the second conductivity type can also be configured as needed, which will not be described one by one here. The preparation method of the electrostatic protection device of this embodiment is basically the same as that of the third embodiment, except that: the doping region of the drain region in step 3) is the fourth N-type doping region 14d, the fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g, and the fifth N-type doping region 14e, the second P-type doping region 14f and the sixth N-type doping region 14g are arranged along the width direction of the channel on the outside of the second shallow trench isolation structure 14i, which will not be described one by one here.

[0132] The electrostatic protection device of this embodiment can further reduce the area of ​​the device and achieve miniaturization; at the same time, more devices can be prepared on a silicon wafer of the same area, further reducing the cost.

[0133] Embodiment 5

[0134] This embodiment provides an electronic product, which at least includes the electrostatic protection device 1 of the present invention. The electronic product includes but is not limited to chips, watches, mobile phones, computers and other electronic products used in process production, which are not described in detail here.

[0135] like Fig.21 As shown, taking 1.8V GGMOS as an example (BV Oxide ≈4.6V), the secondary breakdown current It2 of the electrostatic protection device of the first embodiment and the third embodiment of the present invention (the TLP curves of the first embodiment and the third embodiment are respectively a group of solid lines, and the two groups of solid lines basically coincide) are both about 1.8х10 -2 A / um; the secondary breakdown current It2 of the traditional GGNMOS is about 6.1х10 -3 A / um; It can be seen that the secondary breakdown current of the electrostatic protection device of the present invention is three times that of the traditional structure, the secondary breakdown current is effectively improved, and the ESD protection performance is greatly improved.

[0136] In summary, the present invention provides an electrostatic protection device, a preparation method and an electronic product, including: a substrate, a first well region, a second well region, a third well region, a source region, a drain region and a gate structure; wherein the drain region is configured as a plurality of doping regions with different conductivity types arranged as required to integrate an SCR structure in the ESD MOS, thereby increasing the secondary breakdown current; and using different regions to form a current limiting resistor, thereby increasing the secondary breakdown current and reducing the mask cost; and also reducing the area by optimizing the layout; and the preparation process of the electrostatic protection device of the present invention is compatible with the CMOS process. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0137] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An electrostatic protection device, characterized in that: The electrostatic protection device at least comprises: A substrate, a first well region, a second well region, a third well region, a source region, a drain region and a gate structure; The first well region, the second well region and the third well region are formed in the substrate, and the first well region is located between the second well region and the third well region; the gate structure is formed on the first well region; the source region includes a first doped region formed in the second well region and the first well region; Wherein, the drain region includes a second doped region formed in the third well region and the first well region, and a third doped region and a fourth doped region formed in the third well region, the third doped region and the fourth doped region are sequentially arranged outside the second doped region along the channel length direction, and the drain terminal electrode is arranged on the third doped region and the fourth doped region; the second doped region is covered with a metal silicide barrier layer; or, the drain region includes a fifth doped region formed in the third well region and the first well region, and a sixth doped region, a seventh doped region and an eighth doped region formed in the third well region, the sixth doped region, the seventh doped region and the eighth doped region are sequentially arranged outside the fifth doped region along the channel width direction, and the drain terminal electrode is arranged on the sixth doped region, the seventh doped region and the eighth doped region; the fifth doped region is covered with a metal silicide barrier layer; The substrate, the first well region, the third doped region and the seventh doped region have a first conductivity type, and the second well region, the third well region, the first doped region, the second doped region, the fourth doped region, the fifth doped region, the sixth doped region and the eighth doped region have a second conductivity type.

2. An electrostatic protection device, characterized in that: The electrostatic protection device at least comprises: A substrate, a first well region, a second well region, a third well region, a source region, a drain region and a gate structure; The first well region, the second well region and the third well region are formed in the substrate, and the first well region is located between the second well region and the third well region; the gate structure is formed on the first well region; the source region includes a first doped region formed in the second well region and the first well region; Wherein, the drain region includes a second doped region formed in the third well region and the first well region, and a first shallow trench isolation structure, a third doped region and a fourth doped region formed in the third well region, the first shallow trench isolation structure is located outside the second doped region, the third doped region and the fourth doped region are sequentially arranged outside the first shallow trench isolation structure along the channel length direction, and the drain terminal electrode is arranged on the third doped region and the fourth doped region; or, the drain region includes a fifth doped region formed in the third well region and the first well region, and a second shallow trench isolation structure, a sixth doped region, a seventh doped region and an eighth doped region formed in the third well region; the second shallow trench isolation structure is located outside the fifth doped region, the sixth doped region, the seventh doped region and the eighth doped region are sequentially arranged outside the second shallow trench isolation structure along the channel width direction, and the drain terminal electrode is arranged on the sixth doped region, the seventh doped region and the eighth doped region; The substrate, the first well region, the third doped region and the seventh doped region have a first conductivity type, and the second well region, the third well region, the first doped region, the second doped region, the fourth doped region, the fifth doped region, the sixth doped region and the eighth doped region have a second conductivity type.

3. The electrostatic protection device according to claim 1 or 2, characterized in that: A body region is also disposed in the substrate.

4. The electrostatic protection device according to claim 1 or 2, characterized in that: A third shallow trench isolation structure is also formed in the second well region, and the third shallow trench isolation structure is located outside the first doped region.

5. The electrostatic protection device according to claim 1 or 2, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

6. A method for preparing an electrostatic protection device, used for preparing the electrostatic protection device as claimed in claim 1, 3, 4 or 5, characterized in that: The preparation method of the electrostatic protection device at least comprises: 1) providing a substrate, and forming a first well region, a second well region, and a third well region in the substrate; 2) forming a gate structure on the first well region using a polysilicon gate process; 3) performing source and drain implantation in the structure formed in step 2); 4) forming a metal silicide barrier layer on the N-type doped region of the drain region close to the channel; 5) Forming terminal electrodes on the structure formed in step 4).

7. A method for preparing an electrostatic protection device, used for preparing the electrostatic protection device as claimed in claim 2, 3, 4 or 5, characterized in that: The preparation method of the electrostatic protection device at least comprises: 1) providing a substrate, forming a shallow trench isolation structure in a drain region by a shallow trench isolation process, and forming a first well region, a second well region and a third well region in the substrate; 2) forming a gate structure on the first well region using a polysilicon gate process; 3) performing source and drain implantation in the structure formed in step 2); 4) Electrodes are formed on each end of the structure formed in step 3).

8. The method for preparing an electrostatic protection device according to claim 6 or 7, characterized in that: In step 1), a shallow trench isolation structure is formed in the source region by a shallow trench isolation process to define the active region.

9. The method for preparing an electrostatic protection device according to claim 6 or 7, characterized in that: In step 3), a body region is also formed by ion implantation.

10. An electronic product, characterized in that: The electronic product at least comprises: an electrostatic protection device as described in any one of claims 1-5.

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