Self-aligned T-shaped gate GaN-based HEMT device structure and preparation method thereof

Abstract

The invention discloses a self-aligned T-shaped gate GaN-based HEMT device structure and a manufacturing method thereof. The structure sequentially comprises a substrate, a nucleating layer, a buffer layer, a channel layer and a barrier layer from bottom to top, wherein the barrier layer, the channel layer and the buffer layer adopt a III-nitride semiconductor. A T-shaped gate electrode is arranged above the barrier layer; grooves are formed in parts of the barrier layer and the channel layer on the two sides of the gate electrode, and one edge of each groove is aligned with one edge of the gate head of the T-shaped gate electrode in the vertical direction; a source electrode and a drain electrode are arranged in the groove, and the surfaces of the source electrode and the drain electrode are flush with the barrier layer. According to the scheme, the distance between the source electrode and the drain electrode is reduced, the on-resistance is reduced, meanwhile, the stray capacitance between the gate source electrode and the gate drain electrode is reduced, and the frequency characteristic of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a self-aligned T-gate GaN-based HEMT device structure and a preparation method thereof. Background Art

[0002] As a typical material of the third-generation semiconductor, GaN has the advantages of large bandgap (3.4eV), high electron mobility, and high electron saturation velocity, so it has broad application potential in the fields of next-generation radio frequency devices, power and electrical devices, etc. Due to the unique polarization effect of the III-GalN heterojunction structure, even when the material is not intentionally doped, a two-dimensional electron gas (2DEG) with high concentration and high electron mobility can be formed at the junction interface. Therefore, the high electron mobility transistor (HEMT) prepared based on the GaN heterojunction structure has the characteristics of high breakdown voltage, low on-resistance, high switching frequency, and small size, making it the preferred solution for the research and development of high-performance, low-power, and low-cost microwave devices, especially in the fields of wireless charging, lidar, electric vehicles, and intelligent transportation.

[0003] As the demand for high-frequency and high-power devices in fields such as wireless communications, radar, and power electronics continues to increase, traditional transistor structures have been unable to meet these requirements. As an advanced transistor based on gallium nitride materials, GaN HEMT has excellent electron mobility and saturation current density, but its performance is still affected by the gate structure. The T-type gate can effectively reduce the overlapping area between the gate and the source and drain through its unique shape design. However, the source and drain electrodes have a certain height, which reduces the distance between the source and drain electrodes and the gate electrode, increases the gate-source parasitic capacitance and the gate-drain parasitic capacitance, and thus affects the high-frequency characteristics of the device. In addition, the traditional transistor manufacturing process often includes multiple photolithography and etching steps. Summary of the invention

[0004] In order to overcome the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a self-aligned T-gate GaN-based HEMT device structure and a preparation method, which mainly solves the problems of large source-drain spacing and large parasitic capacitance of existing GaN-based HEMT devices.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A self-aligned T-gate GaN-based HEMT device structure, comprising a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer arranged in sequence from bottom to top, wherein the barrier layer, the channel layer and the buffer layer are made of group III nitride semiconductors; a two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer as a channel of the device;

[0007] A T-shaped gate electrode is arranged on the barrier layer, the vertical portion of the gate electrode is arranged above the barrier layer, and grooves are arranged in a part of the barrier layer and the channel layer on both sides of the gate electrode along the horizontal direction, and one edge of the groove is vertically aligned with the edge of the horizontal portion of the gate electrode;

[0008] A source electrode and a drain electrode are respectively arranged in the grooves on both sides, and the source electrode and the drain electrode form an ohmic contact with the side surface of the two-dimensional electron gas.

[0009] In one embodiment, the groove passes through the barrier layer and sinks into the channel layer, that is, the lower surfaces of the source electrode and the drain electrode contact the channel layer, and the side close to the horizontal portion of the gate electrode contacts the cross-section of the barrier layer and the channel layer.

[0010] In one embodiment, the sides of the source electrode and the drain electrode away from the horizontal portion of the gate electrode are flush with the edge of the device.

[0011] In one embodiment, upper surfaces of the source electrode and the drain electrode are flush with an upper surface of the barrier layer.

[0012] In one embodiment, the Group III nitride semiconductor is GaN, AlN or InN, or a multi-component compound of two or more thereof.

[0013] In one embodiment, the substrate is made of one of silicon, silicon nitride, sapphire, and diamond; the nucleation layer is made of AlN; the buffer layer is made of GaN or AlGaN, and the channel layer is made of GaN or InGaN; the barrier layer is made of AlGaN, InGaN, AlN or InAlGaN; the gate electrode metal layer is any one of TiN / Ni / Au, Ni / Au, and Ta / Au; the metal layers of the source electrode and the drain electrode are any one of Ti / Al / Ni / Au, Ta / Al / W, Ti / Al, and Ta / Al / Ti / TiN.

[0014] In one embodiment, the thickness of the nucleation layer is 100-300 nm, the thickness of the buffer layer is 100-3000 nm; the thickness of the channel layer is 50 nm-500 nm; the thickness of the barrier layer is 5-40 nm, and the depth of the groove is 50-300 nm.

[0015] In one embodiment, the distance between the horizontal portion of the gate electrode and the barrier layer is 10-200nm, wherein the gate foot is 50-300nm high and 100-300nm wide; the gate cap is 100-600nm high and 100-500nm wide. The distance between the vertical portion of the gate electrode and the source electrode and the distance between the vertical portion of the gate electrode and the drain electrode are both 10-300nm.

[0016] The present invention also provides a method for preparing a self-aligned T-gate GaN-based HEMT device, comprising the following steps:

[0017] Step 1, sequentially growing a nucleation layer, a buffer layer, a channel layer and a barrier layer on a substrate;

[0018] Step 2, photolithography is used to form a gate electrode on the barrier layer, and gate metal is deposited to form a Schottky contact with the barrier layer;

[0019] Step 3, using the gate electrode as a mask to partially etch the barrier layer and the channel layer to form the groove;

[0020] Step 4: growing a multilayer metal system on the groove, preparing the source electrode and the drain electrode, and performing annealing to form an ohmic contact with the two-dimensional electron gas.

[0021] In one embodiment, in step 2, double-layer photolithography is performed; in step 3, a self-alignment process is used to perform etching using the gate electrode as a mask; in step 4, the annealing time is 60 to 180 seconds.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. The present invention discloses a self-aligned T-gate GaN-based HEMT device. The T-gate structure can enhance the modulation effect of the gate on the channel current, help optimize the current path inside the device, and increase the switching speed of the device, reduce the on-resistance, enhance the withstand voltage, etc., and show good performance in high-frequency and high-power applications.

[0024] 2. The source and drain electrodes are etched using a self-aligned etching process with a T-type gate mask to minimize the source-drain spacing, making the spacing between the source and drain very small, reducing the gate-source resistance and gate-drain resistance, and increasing the transconductance and cutoff frequency characteristics of the device.

[0025] 3. The metal surface of the source and drain electrodes is flush with the surface of the barrier layer, which increases the vertical distance between the source electrode and the gate electrode edge, and the drain electrode and the gate electrode edge, reduces the high parasitic capacitance problem caused by the source and drain electrode self-alignment process, and improves the cutoff frequency of the device.

[0026] 4. The preparation method of the present invention has simple process, is compatible with conventional processes, has low cost, and has high stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of a self-aligned T-gate GaN-based HEMT device of the present invention.

[0028] Figure 2The present invention is a schematic flow diagram of a method for preparing a self-aligned T-gate GaN-based HEMT device, wherein a is substrate cleaning, b is growing a nucleation layer, a buffer layer, a channel layer and a barrier layer on the substrate, c is isolating the device from a table, d is photolithography to form a gate electrode, e is etching to form a groove based on a self-aligned process, and f is making a source-drain electrode in the groove and rapidly annealing.

[0029] Description of the drawings: 1-substrate; 2-nucleation layer; 3-buffer layer; 4-channel layer; 5-barrier layer; 6-gate electrode; 7-source electrode; 8-drain electrode DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings and examples.

[0031] A self-aligned T-gate GaN-based HEMT device structure of the present invention, such as Figure 1 As shown, it includes a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4 and a barrier layer 5 arranged in sequence from bottom to top. The barrier layer 5, the channel layer 4 and the buffer layer 3 are made of group III nitride semiconductors, namely GaN, AlN or InN, or a multi-component compound composed of two or more of them. Through this material selection, a two-dimensional electron gas with a higher concentration and higher electron mobility is formed at the interface between the channel layer 4 and the barrier layer 5, which serves as the channel of the GaN-based HEMT device of the present invention.

[0032] The gate electrode 6, source electrode 7 and drain electrode 8 of the device still adopt a distribution form in which the source and drain are located on both sides. The difference is that the gate electrode 6 adopts a T-shaped shape. Specifically, the T-shaped gate electrode 6 consists of a vertical part and a horizontal part. The top of the vertical part is connected to the lower side of the horizontal part, and is preferably connected to the midpoint position of the lower side of the horizontal part.

[0033] The bottom end of the vertical portion of the T-shaped gate electrode 6 is directly disposed on the barrier layer 5, and is preferably disposed in the middle of the barrier layer 5. There is a certain distance between the horizontal portion and the barrier layer 5, and obviously, the distance is the height of the vertical portion. The height, bottom, top, lower side, etc. of the present invention are all referred to as "from bottom to top" as mentioned above.

[0034] Along the horizontal direction of the gate electrode 6, grooves are provided in part of the barrier layer 5 and the channel layer 4 on both sides of the gate electrode 6, and one edge of the groove is vertically aligned with the edge of the horizontal portion of the gate electrode 6. In the present invention, the two ends of the horizontal portion of the gate electrode 6 can be defined as "gate heads".

[0035] The source electrode 7 and the drain electrode 8 of the present invention are respectively arranged in the grooves on both sides of the gate electrode 6 to form ohmic contacts with the side surfaces of the two-dimensional electron gas.

[0036] The present invention is based on a self-aligned T-gate GaN-based HEMT device structure, which can reduce the gate-source spacing and the gate-drain spacing, thereby reducing the gate-source resistance and the gate-drain resistance, and reducing the on-resistance of the device.

[0037] According to some embodiments of the present invention, the groove of the present invention can penetrate the barrier layer 5 in the vertical direction and sink into the channel layer 4, that is, the bottom surface of the groove is in the channel layer 4, the cross section of the channel layer 4 is convex, the barrier layer 5 is located on the top surface of the convex part, and the source electrode 7 and the drain electrode 8 are located on both sides. At this time, the lower surface of the source electrode 7 and the drain electrode 8 are in contact with the channel layer 4, and the side of the horizontal part close to the gate electrode 6 is in contact with the cross section of the barrier layer 5 and the channel layer 4, so that a reliable ohmic contact can be formed with the side of the two-dimensional electron gas. The cross section here refers to the side of the groove close to the gate electrode 6.

[0038] According to some embodiments of the present invention, the side of the source electrode 7 and the drain electrode 8 away from the horizontal portion of the gate electrode 6 is flush with the edge of the device. Different from the common process of arranging the source electrode 7 and the drain electrode 8 above the barrier layer 5, the present invention arranges the source electrode 7 and the drain electrode 8 inside the barrier layer 5 and the channel layer 4, while ensuring the thickness of the source electrode 7 and the drain electrode 8, the distance between the gate source and the gate drain is increased as much as possible, and the parasitic capacitance between the source electrode 7 and the gate electrode 6, and the parasitic capacitance between the drain electrode 8 and the gate electrode 6 is reduced.

[0039] According to some embodiments of the present invention, the upper surfaces of the source electrode 7 and the drain electrode 8 are flush with the upper surface of the barrier layer 5, which increases the distance between the edge of the source electrode 7 and the gate electrode 6 and the distance between the drain electrode 8 and the edge of the gate electrode 7. It can also reduce the gate-source parasitic capacitance and the gate-drain parasitic capacitance to a certain extent, thereby improving the cutoff frequency of the device.

[0040] According to some embodiments of the present invention, the substrate 1 of the present invention can selectively adopt one of silicon, silicon nitride, sapphire, and diamond; the nucleation layer 2 can selectively adopt AlN with a thickness of 100-300nm. The nucleation layer 2 can release the mismatch stress caused by the lattice mismatch between the buffer layer 3 and the substrate 1 and the thermal stress caused by the thermal expansion coefficient, optimize the flatness of the nucleation layer 2, and make the growth defects of the epitaxial layer lower.

[0041] According to some embodiments of the present invention, the buffer layer 3 may be GaN or AlGaN with a thickness of 100-3000nm. The channel layer 4 may be GaN or InGaN with a thickness of 50-500nm; the barrier layer 5 may be one of AlGaN, InGaN, AlN, and InAlGaN with a thickness of 5-40nm. A heterojunction is formed between the barrier layer 5 and the channel layer 4, and a two-dimensional electron gas channel is formed on one side of the channel layer 4 due to the polarization effect.

[0042] Correspondingly, the distance between the horizontal part of the gate electrode 6 of the present invention and the barrier layer 5, that is, the height of the vertical part of the gate electrode 6 (that is, the gate foot) is 50-300nm, which is the distance between the lower surface of the horizontal part and the upper surface of the barrier layer 5, that is, the height excluding the horizontal part. The height of the horizontal part (that is, the gate cap) can be 100-600nm.

[0043] The distance between the vertical part of the gate electrode 6 and the source electrode 7 is equal to the distance between the drain electrode 8 and is 10-300nm, which is the distance between the side of the vertical part close to the source electrode 7 and the side of the source electrode 7 close to the vertical part, that is, the horizontal dimension excluding the vertical part. The horizontal dimension of the vertical part, that is, the gate foot width, can be 100-300nm.

[0044] Accordingly, the distance between the source electrode 7 and the drain electrode 8 is only 20-600 nm, which greatly reduces the on-resistance and reduces the parasitic capacitance between the gate-source electrode and the gate-drain electrode, thereby improving the frequency characteristics of the device.

[0045] According to some embodiments of the present invention, the metal layer of the gate electrode 6 may be any one of TiN / Ni / Au, Ni / Au, Ta / Au; the metal layer of the source electrode 7 and the drain electrode 8 may be any one of Ti / Al / Ni / Au, Ta / Al / W, Ti / Al, Ta / Al / Ti / TiN.

[0046] The device of the present invention can be prepared by conventional processes, and can be specifically implemented according to the following steps:

[0047] S1: Cleaning the surface of substrate 1.

[0048] S2: using metal organic chemical vapor deposition to sequentially grow a nucleation layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5 on the substrate.

[0049] S3: Isolate the device on the mesa.

[0050] S4: using a double-layer resist to perform photolithography to form a T-shaped gate electrode 6 , ie, the T-shaped gate of the present invention, and then preparing a gate metal to form a Schottky contact with the barrier layer 5 .

[0051] S5: A self-aligned process is used to etch the end of the barrier layer 5 and the middle and upper part of the end of the channel layer 4 using a T-type gate as a mask to form the groove as the source and drain region. The self-aligned process is used here to avoid the error caused by photolithography, and the source and drain regions are etched more finely using the T-type gate as a mask, so that the spacing between the source and drain is reduced to the greatest extent. At the same time, the technical solution is simple, compatible with conventional processes, and has high stability and reliability, which greatly simplifies the manufacturing process, reduces manufacturing costs, and also improves efficiency.

[0052] S6: growing a multilayer metal system on the etched groove by electron beam evaporation to prepare a source electrode 7 and a drain electrode 8, and performing annealing to form an ohmic contact with the two-dimensional electron gas.

[0053] Several specific preparation examples are listed below.

[0054] Example 1

[0055] A method for preparing a self-aligned T-gate GaN-based HEMT device, such as Figure 2 As shown, the specific implementation steps are as follows:

[0056] Step 1: The substrate 1 is a silicon substrate with a thickness of 800 μm, and the surface is cleaned. Figure 2 As shown in a.

[0057] Specific cleaning process: At a high temperature of 1000° C., hydrogen is introduced into the reaction chamber to remove pollutants on the surface of the substrate 1 and form a microscopic step structure on the surface of the substrate 1 to facilitate the subsequent epitaxial growth process of various epitaxial layers.

[0058] Step 2: Metal organic chemical vapor deposition is used to sequentially grow a nucleation layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5 on the substrate 1.

[0059] The specific growth process is as follows: first, a 100nm AlN is grown on a substrate 1 as a nucleation layer 2 by MOCVD at a low temperature of 500°C, and then the temperature is raised to 1000°C, and a 1.5μm GaN is grown on the nucleation layer as a buffer layer 3, a 200nm GaN is grown as a channel layer 4, and a 22nm AlGaN is grown as a barrier layer 5 by MOCVD, wherein the aluminum component is 0.3, as shown in FIG. Figure 2 As shown in b.

[0060] Step 3: Clean the epitaxial wafer. The work mainly includes cleaning organic and inorganic substances. Use acetone solution to ultrasonically clean the sample for 5 minutes, then put the sample into isopropanol solution for ultrasonic cleaning for 2 minutes to remove the residual acetone solution on the surface of the sample. Finally, blow dry with a nitrogen gun.

[0061] Step 4: isolate the device from the table, such as Figure 2 As shown in c.

[0062] Specific isolation process: the entire barrier layer 5 and part of the channel layer 4 are etched away by inductively coupled plasma etching technology (ICP), the etching depth is 200nm, and the terrace should have neat edges and steep side walls.

[0063] Step 5: Photolithography is used to deposit gate metal to form a gate electrode 6, which forms a Schottky contact with the barrier layer 5. Figure 2 As shown in middle d.

[0064] Specific photolithography process: cleaning the epitaxial wafer, uniformly coating, using double-layer photoresist, the first step is to use photolithography to form a gate cap pattern of the T-type gate, that is, the horizontal part of the gate electrode 6, in the surface of the photoresist layer of the surface layer, and the second step is to continue to use photolithography to form a gate foot pattern of the T-type gate, that is, the vertical part of the gate electrode 6, in the surface of the photoresist layer below the gate cap pattern of the T-type gate, and the pattern of the T-type gate can be formed after two developments. The gate metal is prepared by magnetron sputtering technology, and the gate metal uses Ni / Au with a thickness of 50 / 300nm. In this embodiment, a photoresist PMMA with a thickness of 150nm is spin-coated on the barrier layer 5, and then a photoresist MMA with a thickness of 500nm is spin-coated on the photoresist PMMA. Photolithography technology is used for exposure to form a gate cap area and a gate foot area; the width of the gate cap area is 400nm and the height is 500nm, and the width of the gate foot area is 50nm and the height is 150nm.

[0065] Step six: fabricate a source electrode 7 and a drain electrode 8 to form an ohmic contact with the two-dimensional electron gas.

[0066] Specifically, the gate electrode 6 is used as a mask for etching by a self-aligned process, and a reactive ion etching (RIE) technique is used to vertically etch downward along the gate head of the gate electrode 6 to form a groove as a source and drain region, with an etching depth of 182 nm, and the barrier layer 5 and part of the channel layer 4 are etched away. Figure 2 As shown in figure e.

[0067] Four layers of metal were grown on the etched source and drain regions by electron beam evaporation. The metals used were Ti / Al / Ni / TiN with thicknesses of 2 / 100 / 20 / 60 nm, so that the surfaces of the source electrode 7 and the drain electrode 8 were parallel to the barrier layer 5. Finally, a rapid annealing was performed for 180 seconds in a nitrogen atmosphere at 465°C to form an ohmic contact with the two-dimensional electron gas. Figure 2 As shown in figure f.

[0068] Example 2

[0069] Step 1: The substrate 1 is a silicon carbide substrate with a thickness of 300 μm, and the surface is cleaned as follows: Figure 2 As shown in a.

[0070] Specific cleaning process: Place the substrate 1 in an organic acetone solution to wash away grease and pollutants on its surface, then wash it with flowing deionized water, and then blow dry it with high-purity nitrogen.

[0071] Step 2: Metal organic chemical vapor deposition is used to sequentially grow a nucleation layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5 on the substrate 1.

[0072] The specific growth process is as follows: first, a 200nm AlN is grown on the substrate as a nucleation layer 2 by MOCVD at a low temperature of 600℃, then the temperature is raised to 1000℃, and a 1μm GaN is grown on the nucleation layer as a buffer layer 3, a 300nm GaN is grown as a channel layer 4, and a 20nm AlGaN is grown as a barrier layer 5 by MOCVD. Figure 2 As shown in b.

[0073] Step 3: Clean the epitaxial wafer. The work mainly includes cleaning organic and inorganic substances. Use acetone solution to ultrasonically clean the sample for 5 minutes, then put the sample into isopropanol solution for ultrasonic cleaning for 2 minutes to remove the residual acetone solution on the surface of the sample. Finally, blow dry with a nitrogen gun.

[0074] Step 4: isolate the device from the table, such as Figure 2 As shown in c.

[0075] Specific isolation process: the entire barrier layer 5 and part of the channel layer 4 are etched away by inductively coupled plasma etching technology (ICP), the etching depth is 300nm, and the terrace should have neat edges and steep side walls.

[0076] Step 5: Photolithography is used to deposit gate metal to form a gate electrode 6, which forms a Schottky contact with the barrier layer 5. Figure 2 As shown in middle d.

[0077] Specific photolithography process: cleaning the epitaxial wafer, coating, using double-layer photoresist, the first step is to use photolithography to form a T-type gate cap pattern in the surface of the photoresist layer, that is, the horizontal part of the gate electrode 6, and the second step is to continue to use photolithography to form a T-type gate foot pattern in the photoresist layer surface below the T-type gate cap pattern, that is, the vertical part of the gate electrode 6, and the pattern of the T-type gate can be formed after two developments. The gate metal is prepared using magnetron sputtering technology, and the gate metal uses TiN / / Ni / Au with a thickness of 200 / 50 / 30nm.

[0078] Step six: fabricate a source electrode 7 and a drain electrode 8 to form an ohmic contact with the two-dimensional electron gas.

[0079] Specifically, through the self-alignment process, the gate electrode 6 is used as a mask for etching, and a reactive ion etching technology (RIE) is used to vertically etch downward along the gate head of the gate electrode 6 to form a groove as the source and drain region, and the etching depth is 200nm, and the barrier layer 5 and part of the channel layer 4 are etched away. Figure 2 As shown in figure e.

[0080] Electron beam evaporation was used to grow metal in the etched source and drain regions. The metal used was Ti / Al with a thickness of 50 / 150 nm, so that the surface of the source electrode 7 and the drain electrode 8 were parallel to the barrier layer 5. Finally, rapid annealing was performed in a nitrogen atmosphere at 500°C for 60 seconds to form an ohmic contact with the two-dimensional electron gas. Figure 2 As shown in figure f.

[0081] The above contents are further detailed descriptions of the invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A self-aligned T-gate GaN-based HEMT device structure, characterized in that: The device comprises a substrate (1), a nucleation layer (2), a buffer layer (3), a channel layer (4) and a barrier layer (5) which are arranged in sequence from bottom to top, wherein the barrier layer (5), the channel layer (4) and the buffer layer (3) are made of group III nitride semiconductors; a two-dimensional electron gas is formed at the interface between the channel layer (4) and the barrier layer (5) to serve as a channel of the device; A T-shaped gate electrode (6) is arranged on the barrier layer (5), the vertical portion of the gate electrode (6) is arranged above the barrier layer (5), and grooves are arranged on both sides of the gate electrode (6) in a part of the barrier layer (5) and the channel layer (4) along the horizontal direction, and one edge of the groove is aligned in a vertical direction with an edge of the horizontal portion of the gate electrode (6); A source electrode (7) and a drain electrode (8) are respectively arranged in the grooves on both sides, and the source electrode (7) and the drain electrode (8) form an ohmic contact with the side surface of the two-dimensional electron gas.

2. The self-aligned T-gate GaN-based HEMT device structure according to claim 1, characterized in that: The groove passes through the barrier layer (5) and sinks into the channel layer (4), that is, the lower surfaces of the source electrode (7) and the drain electrode (8) are in contact with the channel layer (4), and the side close to the horizontal portion of the gate electrode (6) is in contact with the cross-section of the barrier layer (5) and the channel layer (4).

3. The self-aligned T-gate GaN-based HEMT device structure according to claim 1 or 2, characterized in that: The side of the source electrode (7) and the drain electrode (8) away from the horizontal portion of the gate electrode (6) is flush with the edge of the device.

4. The self-aligned T-gate GaN-based HEMT device structure according to claim 1, characterized in that: The upper surfaces of the source electrode (7) and the drain electrode (8) are flush with the upper surface of the barrier layer (5).

5. The self-aligned T-gate GaN-based HEMT device structure according to claim 1, characterized in that: The group III nitride semiconductor is GaN, AlN or InN, or a multi-component compound composed of two or more thereof.

6. The self-aligned T-gate GaN-based HEMT device structure according to claim 1, characterized in that: The substrate (1) is made of one of silicon, silicon nitride, sapphire and diamond; the nucleation layer (2) is made of AlN; the buffer layer (3) is made of GaN or AlGaN, and the channel layer (4) is made of GaN or InGaN; the barrier layer (5) is made of AlGaN, InGaN, AlN or InAlGaN; the metal layer of the gate electrode (6) is any one of TiN / Ni / Au, Ni / Au and Ta / Au; the metal layers of the source electrode (7) and the drain electrode (8) are any one of Ti / Al / Ni / Au, Ta / Al / W, Ti / Al and Ta / Al / Ti / TiN.

7. The self-aligned T-gate GaN-based HEMT device structure according to claim 1, characterized in that: The thickness of the nucleation layer (2) is 100-300nm, the thickness of the buffer layer (3) is 100-3000nm; the thickness of the channel layer (4) is 50nm-500nm; the thickness of the barrier layer (5) is 5-40nm, and the depth of the groove is 50-300nm.

8. The self-aligned T-gate GaN-based HEMT device structure according to claim 1 or 6, characterized in that: The gate foot of the gate electrode (6) has a height of 50-300nm and a width of 100-300nm; the gate cap has a height of 100-600nm and a width of 100-500nm; the distances between the gate foot and the source electrode (7) and the drain electrode (8) are equal, both being 10-300nm.

9. The method for preparing a self-aligned T-gate GaN-based HEMT device according to any one of claims 1 to 8, characterized in that: The steps include: Step 1, sequentially growing a nucleation layer (2), a buffer layer (3), a channel layer (4) and a barrier layer (5) on a substrate (1); Step 2, photolithography is used to form a gate electrode (6) on the barrier layer (5), and gate metal is deposited to form a Schottky contact with the barrier layer (5); Step 3, using the gate electrode (6) as a mask, partially etching the barrier layer (5) and the channel layer (4) to form the groove; Step 4: growing a multilayer metal system on the groove, preparing the source electrode (7) and the drain electrode (8), and performing annealing to form an ohmic contact with the two-dimensional electron gas.

10. The method for preparing a self-aligned T-gate GaN-based HEMT device structure according to claim 9, characterized in that: In the step 2, a double-layered photoresist is used for photolithography; in the step 3, a self-alignment process is used to perform etching using the gate electrode (6) as a mask; in the step 4, an annealing time is 60 to 180 seconds.

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