Operational amplifier circuit and digital-to-analog converter

Abstract

The invention provides an operational amplifier circuit and a digital-to-analog converter, and relates to the technical field of microelectronic integrated circuits. In the application, the amplification multiplexing circuit is used as a common circuit of the first-stage amplification circuit and the auxiliary amplification circuit to realize multiplexing of the circuit. And the input end of the second-stage amplifying circuit is connected with the output end of the first-stage amplifying circuit. The first-stage amplification circuit performs first amplification on a to-be-processed residual error signal and outputs a first-stage amplification residual error signal, the second-stage amplification circuit performs second amplification on the first-stage amplification residual error signal and outputs a second-stage amplification residual error signal, and the auxiliary amplification circuit performs third amplification on the to-be-processed residual error signal and outputs an amplification error signal. And the amplification error signal is used for performing error elimination on the second-stage amplification residual signal and outputting an error-eliminated residual signal. Based on the content, the problems of relatively high power consumption and relatively high integration difficulty of an operational amplifier circuit in the prior art can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of microelectronic integrated circuits, and in particular to an operational amplifier circuit and a digital-to-analog converter. Background Art

[0002] In a pipeline ADC (analog-to-digital converter), a switched capacitor amplifier based on an MDAC (multiplying digital-to-analog converter) amplifies the residual signal (voltage) of each stage and transmits it to the next stage. However, since the gain of the operational amplifier circuit is limited, after the amplification is completed, the input end of the operational amplifier circuit is not a virtual short circuit, which will introduce errors in the output residual signal. Among them, the error in the gain of the operational amplifier circuit will cause the nonlinearity of the entire A / D conversion, resulting in a decrease in conversion accuracy. In the prior art, a corresponding auxiliary amplifier is generally specially configured to eliminate the error to ensure the reliability of the output residual signal. However, the inventors have found that the configuration of the auxiliary amplifier will make the power consumption of the entire operational amplifier circuit higher, and the increase in circuit area will also increase the difficulty of integration. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide an operational amplifier circuit and a digital-to-analog converter to improve the problems of relatively high power consumption and relatively high integration difficulty of the operational amplifier circuit in the prior art.

[0004] To achieve the above objectives, this application adopts the following technical solutions:

[0005] An operational amplifier circuit, comprising:

[0006] an amplification multiplexing circuit, wherein the amplification multiplexing circuit serves as a common circuit for the first-stage amplification circuit and the auxiliary amplification circuit to realize circuit multiplexing, and different circuit nodes in the amplification multiplexing circuit serve as an output end of the first-stage amplification circuit and an output end of the auxiliary amplification circuit respectively;

[0007] A second-stage amplifier circuit, wherein an input end of the second-stage amplifier circuit is connected to an output end of the first-stage amplifier circuit;

[0008] Among them, the first-stage amplifier circuit is used to perform a first amplification on the input residual signal to be processed, and output the corresponding first-stage amplified residual signal to the second-stage amplifier circuit; the second-stage amplifier circuit is used to perform a second amplification on the first-stage amplified residual signal, and output the corresponding second-stage amplified residual signal; the auxiliary amplifier circuit is used to perform a third amplification on the residual signal to be processed, and output the corresponding amplified error signal; the amplified error signal is used to perform error elimination on the second-stage amplified residual signal, and output the corresponding error-eliminated residual signal.

[0009] In a preferred embodiment of the present application, in the above operational amplifier circuit, the amplification multiplexing circuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a first resistor and a second resistor;

[0010] Among them, the source of the first field effect transistor is grounded, the gate of the first field effect transistor serves as a connection port for a first bias voltage, the drain of the first field effect transistor is connected to the source of the second field effect transistor and the source of the third field effect transistor respectively, the gate of the second field effect transistor and the gate of the third field effect transistor serve as connection ports for the residual signal to be processed, the drain of the second field effect transistor is connected to the source of the fourth field effect transistor, the drain of the third field effect transistor is connected to the source of the fifth field effect transistor, the gate of the fourth field effect transistor is connected to the gate of the fifth field effect transistor and serves as a connection port for a common-mode feedback voltage, and the drain of the fourth field effect transistor, the drain of the fifth field effect transistor, the first resistor and the second resistor are connected as a connection port for a power supply voltage.

[0011] In a preferred option of the present application, in the above-mentioned operational amplifier circuit, the drain of the fourth field effect transistor is connected to the first end of the first resistor, the drain of the fifth field effect transistor is connected to the first end of the second resistor, and the second end of the first resistor is connected to the second end of the second resistor and serves as a connection port for the power supply voltage.

[0012] In a preferred embodiment of the present application, in the above operational amplifier circuit, the source of the fourth field effect transistor and the source of the fifth field effect transistor serve as output terminals of the first-stage amplifier circuit, and are used to output the corresponding first-stage amplified residual signal to the second-stage amplifier circuit;

[0013] Furthermore, the drain of the fourth field effect transistor and the drain of the fifth field effect transistor serve as output terminals of the auxiliary amplifier circuit, and are used to output corresponding amplified error signals.

[0014] In a preferred selection of the present application, in the above operational amplifier circuit, the second stage amplifier circuit includes an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a seventeenth field effect transistor and an eighteenth field effect transistor;

[0015] Among them, the source of the eleventh field effect tube and the source of the twelfth field effect tube are grounded, the gate of the eleventh field effect tube and the gate of the twelfth field effect tube are respectively connected to the source of the fourth field effect tube and the source of the fifth field effect tube as the input end of the second stage amplifier circuit, the drain of the eleventh field effect tube is connected to the source of the thirteenth field effect tube, the drain of the twelfth field effect tube is connected to the source of the fourteenth field effect tube, the gate of the thirteenth field effect tube is connected to the drain of the fourteenth field effect tube and serves as a connection port for the fourth bias voltage, the drain of the thirteenth field effect tube is connected to the drain of the fifteenth field effect tube, and the drain of the fourteenth field effect tube is connected to the drain of the fifteenth field effect tube. The drain of the fifteenth field effect transistor is connected to the drain of the sixteenth field effect transistor, the drain of the fifteenth field effect transistor and the drain of the sixteenth field effect transistor serve as the output end of the second stage amplifier circuit, the gate of the fifteenth field effect transistor is connected to the gate of the sixteenth field effect transistor and serves as a connection port for a fifth bias voltage, the source of the fifteenth field effect transistor is connected to the drain of the seventeenth field effect transistor, the source of the sixteenth field effect transistor is connected to the drain of the eighteenth field effect transistor, the gate of the seventeenth field effect transistor is connected to the gate of the eighteenth field effect transistor and serves as a connection port for a sixth bias voltage, and the source of the seventeenth field effect transistor is connected to the source of the eighteenth field effect transistor and serves as a connection port for the power supply voltage.

[0016] In a preferred embodiment of the present application, in the above operational amplifier circuit, the amplification multiplexing circuit further includes a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor;

[0017] Among them, the drain of the fourth field effect transistor is connected to the first end of the first resistor, the drain of the fifth field effect transistor is connected to the first end of the second resistor, the second end of the first resistor is connected to the second end of the second resistor, the drain of the fourth field effect transistor is connected to the drain of the sixth field effect transistor, the drain of the fifth field effect transistor is connected to the drain of the seventh field effect transistor, the gate of the sixth field effect transistor is connected to the drain of the seventh field effect transistor and serves as a connection port for a second bias voltage, the source of the sixth field effect transistor is connected to the drain of the eighth field effect transistor, the source of the seventh field effect transistor is connected to the drain of the ninth field effect transistor, the gate of the eighth field effect transistor and the gate of the ninth field effect transistor serve as connection ports for a third bias voltage, the source of the eighth field effect transistor, the source of the ninth field effect transistor, and the drain of the tenth field effect transistor are connected, the gate of the tenth field effect transistor and the gate of the first field effect transistor serve as connection ports for the seventh bias voltage, and the source of the tenth field effect transistor serves as a connection port for a power supply voltage.

[0018] In a preferred embodiment of the present application, in the above operational amplifier circuit, the source of the fourth field effect transistor and the source of the fifth field effect transistor serve as output terminals of the first-stage amplifier circuit, and are used to output the corresponding first-stage amplified residual signal to the second-stage amplifier circuit;

[0019] Furthermore, the drain of the fourth field effect transistor and the drain of the fifth field effect transistor serve as output terminals of the auxiliary amplifier circuit, and are used to output corresponding amplified error signals.

[0020] In a preferred selection of the present application, in the above operational amplifier circuit, the second stage amplifier circuit includes an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a seventeenth field effect transistor and an eighteenth field effect transistor;

[0021] Among them, the source of the eleventh field effect tube and the source of the twelfth field effect tube are grounded, the gate of the eleventh field effect tube and the gate of the twelfth field effect tube are respectively connected to the source of the fourth field effect tube and the source of the fifth field effect tube as the input end of the second stage amplifier circuit, the drain of the eleventh field effect tube is connected to the source of the thirteenth field effect tube, the drain of the twelfth field effect tube is connected to the source of the fourteenth field effect tube, the gate of the thirteenth field effect tube is connected to the drain of the fourteenth field effect tube and serves as a connection port for the fourth bias voltage, the drain of the thirteenth field effect tube is connected to the drain of the fifteenth field effect tube, the drain of the fourteenth field effect tube is connected to the sixteenth field effect tube, and the gate of the thirteenth field effect tube is connected to the drain of the fifteenth field effect tube. The drain of the field effect transistor is connected, the drain of the fifteenth field effect transistor and the drain of the sixteenth field effect transistor serve as the output end of the second stage amplifier circuit, the gate of the fifteenth field effect transistor is connected to the gate of the sixteenth field effect transistor and serves as a connection port for the fifth bias voltage, the source of the fifteenth field effect transistor is connected to the drain of the seventeenth field effect transistor, the source of the sixteenth field effect transistor is connected to the drain of the eighteenth field effect transistor, the gate of the seventeenth field effect transistor and the gate of the eighteenth field effect transistor are respectively connected to the drain of the eighth field effect transistor and the drain of the ninth field effect transistor, and the source of the seventeenth field effect transistor is connected to the source of the eighteenth field effect transistor and serves as a connection port for the power supply voltage.

[0022] Based on the above, the present application also provides a digital-to-analog converter, which includes the above operational amplifier circuit.

[0023] In a preferred embodiment of the present application, in the above digital-to-analog converter, the digital-to-analog converter includes at least two operational amplifier circuits;

[0024] Among them, at least one of the operational amplifier circuits further includes a sampling capacitor, at least two of the operational amplifier circuits are cascaded, and the output end of the second-stage amplifier circuit in the previous operational amplifier circuit is connected to the top plate of the sampling capacitor in the next operational amplifier circuit, so that the second-stage amplified residual signal is applied to the top plate of the sampling capacitor, and the output end of the auxiliary amplifier circuit in the previous operational amplifier circuit is connected to the bottom plate of the sampling capacitor in the next operational amplifier circuit, so that the amplified error signal is applied to the bottom plate of the sampling capacitor, so that the corresponding error elimination residual signal is obtained by sampling through the sampling capacitor, and the error elimination residual signal is used as the residual signal to be processed of the next operational amplifier circuit.

[0025] In the operational amplifier circuit and digital-to-analog converter provided in the present application, the amplifier multiplexing circuit included in the operational amplifier circuit is used as a common circuit for the first-stage amplifier circuit and the auxiliary amplifier circuit to realize circuit multiplexing. The input end of the second-stage amplifier circuit is connected to the output end of the first-stage amplifier circuit. The first-stage amplifier circuit performs a first amplification on the residual signal to be processed, and outputs the first-stage amplified residual signal. The second-stage amplifier circuit performs a second amplification on the first-stage amplified residual signal, and outputs the second-stage amplified residual signal. The auxiliary amplifier circuit performs a third amplification process on the residual signal to be processed, and outputs an amplified error signal. The amplified error signal is used to eliminate the error of the second-stage amplified residual signal, and outputs the error-eliminated residual signal. Based on the above content, since the first-stage amplifier circuit and the auxiliary amplifier circuit are multiplexed, compared with the conventional technical solution of separately configuring the auxiliary amplifier circuit on the basis of the first-stage amplifier circuit and the second-stage amplifier circuit, it can have a smaller integrated circuit area (so that the integration difficulty can be reduced) and lower power consumption, thereby improving the problem that the power consumption of the operational amplifier circuit existing in the prior art is relatively large and the integration difficulty is relatively high. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings.

[0027] Figure 1 This is a structural block diagram of the operational amplifier circuit provided in an embodiment of the present application.

[0028] Figure 2 A circuit schematic diagram of an amplification and multiplexing circuit provided in an embodiment of the present application.

[0029] Figure 3 A circuit schematic diagram of an operational amplifier circuit provided in an embodiment of the present application.

[0030] Figure 4 Another circuit schematic diagram of the amplification and multiplexing circuit provided in an embodiment of the present application.

[0031] Figure 5 Another circuit schematic diagram of the operational amplifier circuit provided in an embodiment of the present application.

[0032] Figure 6 This is a structural block diagram of a digital-to-analog converter provided in an embodiment of the present application.

[0033] Icon: MN0-first field effect transistor, MN1-second field effect transistor, MN2-third field effect transistor, MN3-fourth field effect transistor, MN4-fifth field effect transistor, MP1-sixth field effect transistor, MP2-seventh field effect transistor, MP3-eighth field effect transistor, MP4-ninth field effect transistor, MP9-tenth field effect transistor, MN5-eleventh field effect transistor, MN6-twelfth field effect transistor, MN9-thirteenth field effect transistor, MN10-fourteenth field effect transistor, MP7-fifteenth field effect transistor, MP8-sixteenth field effect transistor, MP5-seventeenth field effect transistor, MP6-eighteenth field effect transistor, R1-first resistor, R2-second resistor. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0036] like Figure 1 As shown, an embodiment of the present application provides an operational amplifier circuit. Among them, the operational amplifier circuit may include an amplifier multiplexing circuit. The amplifier multiplexing circuit can be used as a common circuit for the first-stage amplifier circuit and the auxiliary amplifier circuit to achieve circuit multiplexing. In addition, different circuit nodes in the amplifier multiplexing circuit are respectively used as the output end of the first-stage amplifier circuit and the output end of the auxiliary amplifier circuit, that is, by outputting the signals (voltages) of different nodes in the amplifier multiplexing circuit, they are respectively used as corresponding amplified signals. In addition, the operational amplifier circuit may also include a second-stage amplifier circuit.

[0037] In detail, the input end of the second-stage amplifier circuit is connected to the output end of the first-stage amplifier circuit. The first-stage amplifier circuit is used to perform a first amplification on the input residual signal to be processed, and output the corresponding first-stage amplified residual signal to the second-stage amplifier circuit; the second-stage amplifier circuit is used to perform a second amplification on the first-stage amplified residual signal, and output the corresponding second-stage amplified residual signal; the auxiliary amplifier circuit is used to perform a third amplification on the residual signal to be processed, and output the corresponding amplified error signal; the amplified error signal is used to perform error elimination on the second-stage amplified residual signal, and output the corresponding error-eliminated residual signal.

[0038] Based on the above content, since the first-stage amplifier circuit and the auxiliary amplifier circuit are reused, compared with the conventional technical solution of separately configuring the auxiliary amplifier circuit based on the first-stage amplifier circuit and the second-stage amplifier circuit, it can have a smaller integrated circuit area (so that the integration difficulty can be reduced) and lower power consumption, thereby improving the problem of relatively large power consumption and relatively high integration difficulty of the operational amplifier circuit in the prior art.

[0039] It should be noted that the specific structure of the amplification and multiplexing circuit is not limited and can be selected according to actual needs.

[0040] For example, in an alternative implementation, considering that the amplification multiplexing circuit is a common circuit of the first-stage amplification circuit and the auxiliary amplification circuit, in order to avoid excessive amplification of the error signal, the amplification multiplexing circuit can be of low gain. Based on this, combined with Figure 2 The amplification multiplexing circuit may include a first field effect transistor MN0, a second field effect transistor MN1, a third field effect transistor MN2, a fourth field effect transistor MN3, a fifth field effect transistor MN4, a first resistor R1 and a second resistor R2.

[0041] In detail, the source of the first field effect transistor MN0 is grounded, and the gate of the first field effect transistor MN0 serves as a connection port for a first bias voltage (eg, Figure 2 VBN in the figure), the drain of the first field effect transistor MN0 is connected to the source of the second field effect transistor MN1 and the source of the third field effect transistor MN2 respectively, and the gate of the second field effect transistor MN1 and the gate of the third field effect transistor MN2 serve as the connection port of the residual signal to be processed (such as Figure 2 VIP and VIN in the circuit), the drain of the second field effect transistor MN1 is connected to the source of the fourth field effect transistor MN3, the drain of the third field effect transistor MN2 is connected to the source of the fifth field effect transistor MN4, the gate of the fourth field effect transistor MN3 is connected to the gate of the fifth field effect transistor MN4 and serves as a connection port for the common mode feedback voltage (such as Figure 2The drain of the fourth field effect transistor MN3, the drain of the fifth field effect transistor MN4, the first resistor R1 and the second resistor R2 are connected as a connection port for the power supply voltage (such as Figure 2 VDD in the .

[0042] It is understandable that the specific connection method of the drain of the fourth field effect transistor MN3, the drain of the fifth field effect transistor MN4, the first resistor R1 and the second resistor R2 is not limited and can be selected according to actual needs.

[0043] For example, in a first alternative implementation, in order to reduce the area of ​​the circuit and reduce the difficulty of circuit integration, the drain of the fourth field effect transistor MN3, the drain of the fifth field effect transistor MN4, the first resistor R1 and the second resistor R2 may be connected in a specific manner as follows:

[0044] The drain of the fourth field effect transistor MN3 is connected to the first end of the first resistor R1, the drain of the fifth field effect transistor MN4 is connected to the first end of the second resistor R2, and the second end of the first resistor R1 is connected to the second end of the second resistor R2 and serves as a connection port for the power supply voltage.

[0045] It can be understood that, in an alternative embodiment, the source of the fourth field effect transistor MN3 and the source of the fifth field effect transistor MN4 serve as the output end of the first stage amplifier circuit, and are used to output the corresponding first stage amplified residual signal to the second stage amplifier circuit. In addition, the drain of the fourth field effect transistor MN3 and the drain of the fifth field effect transistor MN4 serve as the output end of the auxiliary amplifier circuit (such as Figure 2 In this way, current multiplexing of the first-stage amplifier circuit and the auxiliary amplifier circuit can be achieved, thereby reducing power consumption.

[0046] In addition, it should be noted that the source of the fourth field effect transistor MN3 and the source of the fifth field effect transistor MN4 serve as the output end of the first-stage amplifier circuit and are a low-resistance node. Therefore, the pole frequency here is relatively high, the speed of the first stage is very fast, and the gain of the first stage is relatively low, which is roughly the ratio of the transconductance between the input pair of tubes (the second field effect transistor MN1 and the third field effect transistor MN2) and the load tube (the fourth field effect transistor MN3 and the fifth field effect transistor MN4).

[0047] In addition, it should be noted that the drain of the fourth field effect transistor MN3 and the drain of the fifth field effect transistor MN4 serve as the output end of the auxiliary amplifier circuit, and the gain thereof is the product of the transconductance of the input pair of the first stage amplifier circuit (the transconductance of the second field effect transistor MN1 or the third field effect transistor MN2) and the resistance value of the first resistor R1 (or the resistance value of the second resistor R2). Based on this, the gain of the auxiliary amplifier circuit can be adjusted by adjusting the transconductance and the resistance value, thereby outputting an adapted amplified error signal, thereby achieving the function of eliminating the gain error.

[0048] It is understandable that the specific structure of the second-stage amplifier circuit is not limited and can be selected according to actual needs.

[0049] For example, in an alternative implementation, considering that the gain of the first-stage amplifier circuit is relatively low, in order to ensure that the overall gain meets the requirements, the second-stage amplifier circuit may have a relatively high gain. Figure 3 The second stage amplifier circuit includes an eleventh field effect transistor MN5, a twelfth field effect transistor MN6, a thirteenth field effect transistor MN9, a fourteenth field effect transistor MN10, a fifteenth field effect transistor MP7, a sixteenth field effect transistor MP8, a seventeenth field effect transistor MP5 and an eighteenth field effect transistor MP6.

[0050] In detail, the source of the eleventh field effect transistor MN5 and the source of the twelfth field effect transistor MN6 are grounded, the gate of the eleventh field effect transistor MN5 and the gate of the twelfth field effect transistor MN6 are connected to the source of the fourth field effect transistor MN3 and the source of the fifth field effect transistor MN4 as the input end of the second stage amplifier circuit respectively, the drain of the eleventh field effect transistor MN5 is connected to the source of the thirteenth field effect transistor MN9, the drain of the twelfth field effect transistor MN6 is connected to the source of the fourteenth field effect transistor MN10, the gate of the thirteenth field effect transistor MN9 is connected to the drain of the fourteenth field effect transistor MN10 and serves as the fourth bias voltage (such as Figure 3 The drain of the thirteenth field effect transistor MN9 is connected to the drain of the fifteenth field effect transistor MP7, the drain of the fourteenth field effect transistor MN10 is connected to the drain of the sixteenth field effect transistor MP8, and the drain of the fifteenth field effect transistor MP7 and the drain of the sixteenth field effect transistor MP8 serve as the output end of the second stage amplifier circuit (such as Figure 3 The gate of the fifteenth field effect transistor MP7 is connected to the gate of the sixteenth field effect transistor MP8 and serves as a connection port for a fifth bias voltage (such as Figure 3The source of the fifteenth field effect transistor MP7 is connected to the drain of the seventeenth field effect transistor MP5, the source of the sixteenth field effect transistor MP8 is connected to the drain of the eighteenth field effect transistor MP6, the gate of the seventeenth field effect transistor MP5 is connected to the gate of the eighteenth field effect transistor MP6 and serves as a connection port for the sixth bias voltage (such as Figure 3 The source of the seventeenth field effect transistor MP5 is connected to the source of the eighteenth field effect transistor MP6 and serves as a connection port for the power supply voltage.

[0051] It should be noted that the output end of the first-stage amplifier circuit is connected to the gate of the pseudo-differential input pair of transistors (the eleventh field effect transistor MN5 and the twelfth field effect transistor MN6) of the second-stage amplifier circuit, and the second-stage amplifier circuit forms a common source and common gate circuit structure, so that the output impedance can be improved and a higher gain is guaranteed. The output impedance is approximately g*r ds 2 / 2, wherein g represents the transconductance of the eleventh field effect transistor MN5 or the twelfth field effect transistor MN6 (the transconductance of the eleventh field effect transistor MN5 is the same as the transconductance of the twelfth field effect transistor MN6), r ds represents the impedance between the source and drain of the eleventh field effect transistor MN5 or the twelfth field effect transistor MN6 (the impedance between the source and drain of the eleventh field effect transistor MN5 is the same as the impedance between the source and drain of the twelfth field effect transistor MN6). Combined with the above description, it can be known that the output end of the first-stage amplifier circuit is a low-resistance node (the output impedance is the reciprocal of the transconductance of the fourth field effect transistor MN3 or the fifth field effect transistor MN4, which is relatively small), so that the main pole of the frequency is located at the output end of the second-stage amplifier circuit. Therefore, there is no need to introduce a Miller compensation structure between the two stages, which can further reduce the circuit area.

[0052] For example, in a second alternative embodiment, in combination with Figure 4 The amplification multiplexing circuit may further include a sixth field effect transistor MP1, a seventh field effect transistor MP2, an eighth field effect transistor MP3, a ninth field effect transistor MP4 and a tenth field effect transistor MP9. Based on this, the drain of the fourth field effect transistor MN3, the drain of the fifth field effect transistor MN4, the first resistor R1 and the second resistor R2 may be connected in a specific manner as follows:

[0053] The drain of the fourth field effect transistor MN3 is connected to the first end of the first resistor R1, the drain of the fifth field effect transistor MN4 is connected to the first end of the second resistor R2, the second end of the first resistor R1 is connected to the second end of the second resistor R2 and serves as a connection port for the common mode output voltage (such as Figure 4 The drain of the fourth field effect transistor MN3 is connected to the drain of the sixth field effect transistor MP1, the drain of the fifth field effect transistor MN4 is connected to the drain of the seventh field effect transistor MP2, and the gate of the sixth field effect transistor MP1 is connected to the drain of the seventh field effect transistor MP2 and serves as a connection port for a second bias voltage (such as Figure 4 VB1 as shown), the source of the sixth field effect transistor MP1 is connected to the drain of the eighth field effect transistor MP3, the source of the seventh field effect transistor MP2 is connected to the drain of the ninth field effect transistor MP4, and the gate of the eighth field effect transistor MP3 and the gate of the ninth field effect transistor MP4 serve as the connection port of the third bias voltage (as shown in FIG. Figure 4 VPIP and VPIN shown, wherein VPIP and VPIN can be obtained by level shifting based on VIP and VIN respectively through corresponding capacitors, and the capacitor can refer to a level shift capacitor. In this way, VIP and VIN are directly added to the second field effect transistor MN1 and the third field effect transistor MN2, and these two signals are simultaneously obtained by level shifting VPIP and VPIN, and added to the eighth field effect transistor MP3 and the ninth field effect transistor MP4. In this way, the differential input voltage can be converted into a differential output current, which plays a transconductance role, and through this stacking design, the current can be reused, the energy efficiency is improved, and the power consumption is reduced), the source of the eighth field effect transistor MP3, the source of the ninth field effect transistor MP4, and the drain of the tenth field effect transistor MP9 are connected, and the gate of the tenth field effect transistor MP9 and the gate of the first field effect transistor MN0 are used as the connection port of the seventh bias voltage (such as Figure 4 The source of the tenth field effect transistor MP9 serves as a connection port for the power supply voltage.

[0054] It can be understood that, based on the above circuit configuration, in an alternative embodiment, the source of the fourth field effect transistor MN3 and the source of the fifth field effect transistor MN4 serve as the output end of the first stage amplifier circuit, and are used to output the corresponding first stage amplified residual signal to the second stage amplifier circuit. In addition, the drain of the fourth field effect transistor MN3 and the drain of the fifth field effect transistor MN4 serve as the output end of the auxiliary amplifier circuit, and are used to output the corresponding amplified error signal.

[0055] It is understandable that the specific structure of the second-stage amplifier circuit is not limited and can be selected according to actual needs.

[0056] For example, in an alternative implementation, considering that the gain of the first-stage amplifier circuit is relatively low, in order to ensure that the overall gain meets the requirements, the second-stage amplifier circuit can have a relatively high gain. On this basis, in order to further improve the current utilization efficiency, current reuse can be further performed to further reduce power consumption. Figure 5 The second stage amplifier circuit may include an eleventh field effect transistor MN5, a twelfth field effect transistor MN6, a thirteenth field effect transistor MN9, a fourteenth field effect transistor MN10, a fifteenth field effect transistor MP7, a sixteenth field effect transistor MP8, a seventeenth field effect transistor MP5 and an eighteenth field effect transistor MP6.

[0057] In detail, the source of the eleventh field effect transistor MN5 and the source of the twelfth field effect transistor MN6 are grounded, the gate of the eleventh field effect transistor MN5 and the gate of the twelfth field effect transistor MN6 are connected to the source of the fourth field effect transistor MN3 and the source of the fifth field effect transistor MN4 as the input end of the second stage amplifier circuit respectively, the drain of the eleventh field effect transistor MN5 is connected to the source of the thirteenth field effect transistor MN9, the drain of the twelfth field effect transistor MN6 is connected to the source of the fourteenth field effect transistor MN10, the gate of the thirteenth field effect transistor MN9 is connected to the drain of the fourteenth field effect transistor MN10 and serves as a connection port for the fourth bias voltage, the drain of the thirteenth field effect transistor MN9 is connected to the drain of the fifteenth field effect transistor MP7, the drain of the fourteenth field effect transistor MN10 is connected to the drain of the fourth field effect transistor MN10. The drain of the sixteenth field effect transistor MP8 is connected, the drain of the fifteenth field effect transistor MP7 and the drain of the sixteenth field effect transistor MP8 serve as the output end of the second stage amplifier circuit, the gate of the fifteenth field effect transistor MP7 is connected to the gate of the sixteenth field effect transistor MP8 and serves as a connection port for the fifth bias voltage, the source of the fifteenth field effect transistor MP7 is connected to the drain of the seventeenth field effect transistor MP5, the source of the sixteenth field effect transistor MP8 is connected to the drain of the eighteenth field effect transistor MP6, the gate of the seventeenth field effect transistor MP5 and the gate of the eighteenth field effect transistor MP6 are respectively connected to the drain of the eighth field effect transistor MP3 and the drain of the ninth field effect transistor MP4, and the source of the seventeenth field effect transistor MP5 is connected to the source of the eighteenth field effect transistor MP6 and serves as a connection port for the power supply voltage.

[0058] Based on this, on the basis of the first stage amplifier circuit and the auxiliary amplifier circuit being multiplexed to realize current multiplexing and thus reduce power consumption, the current of the second stage amplifier circuit is further multiplexed so that power consumption can be substantially reduced.

[0059] It can be understood that, in an alternative embodiment, the first field effect transistor MN0 can be an N-type field effect transistor, the second field effect transistor MN1 can be an N-type field effect transistor, the third field effect transistor MN2 can be an N-type field effect transistor, the fourth field effect transistor MN3 can be an N-type field effect transistor, the fifth field effect transistor MN4 can be an N-type field effect transistor, the sixth field effect transistor MP1 can be a P-type field effect transistor, the seventh field effect transistor MP2 can be a P-type field effect transistor, the eighth field effect transistor MP3 can be a P-type field effect transistor, and the ninth field effect transistor MP4 can be a P-type field effect transistor. The tenth field effect transistor MP9 may be a P-type field effect transistor, the eleventh field effect transistor MN5 may be an N-type field effect transistor, the twelfth field effect transistor MN6 may be an N-type field effect transistor, the thirteenth field effect transistor MN9 may be an N-type field effect transistor, the fourteenth field effect transistor MN10 may be an N-type field effect transistor, the fifteenth field effect transistor MP7 may be a P-type field effect transistor, the sixteenth field effect transistor MP8 may be a P-type field effect transistor, the seventeenth field effect transistor MP5 may be a P-type field effect transistor, and the eighteenth field effect transistor MP6 may be a P-type field effect transistor. In addition, each field effect transistor in the above content may refer to a metal oxide semiconductor field effect transistor, referred to as a MOSFET.

[0060] The embodiment of the present application further provides a digital-to-analog converter, which may include the above-mentioned operational amplifier circuit, and its specific structure is as described above.

[0061] It is understandable that the number of operational amplifier circuits included in the digital-to-analog converter is not limited and can be configured according to actual amplification requirements, for example, in combination with Figure 6 In an alternative implementation, the digital-to-analog converter may include at least two operational amplifier circuits.

[0062] Among them, at least one of the operational amplifier circuits further includes a sampling capacitor (each operational amplifier circuit may include the sampling capacitor, or only some operational amplifier circuits may include the sampling capacitor). Furthermore, at least two operational amplifier circuits are cascaded, that is, the output of the previous operational amplifier circuit serves as the input of the next operational amplifier circuit.

[0063] In detail, the output end of the second-stage amplifier circuit in the previous operational amplifier circuit is connected to the top plate of the sampling capacitor in the next operational amplifier circuit, so that the second-stage amplified residual signal is applied to the top plate of the sampling capacitor. The output end of the auxiliary amplifier circuit in the previous operational amplifier circuit is connected to the bottom plate of the sampling capacitor in the next operational amplifier circuit, so that the amplified error signal is applied to the bottom plate of the sampling capacitor. Based on this, the corresponding error elimination residual signal can be obtained by sampling the sampling capacitor, and the error elimination residual signal is used as the residual signal to be processed by the next operational amplifier circuit, that is, the error elimination residual signal output by the sampling capacitor is equal to the difference between the second-stage amplified residual signal and the amplified error signal.

[0064] In summary, in the operational amplifier circuit and digital-to-analog converter provided by the present application, the amplifier multiplexing circuit included in the operational amplifier circuit is used as a common circuit for the first-stage amplifier circuit and the auxiliary amplifier circuit to realize circuit multiplexing. The input end of the second-stage amplifier circuit is connected to the output end of the first-stage amplifier circuit. The first-stage amplifier circuit performs a first amplification on the residual signal to be processed, and outputs the first-stage amplified residual signal. The second-stage amplifier circuit performs a second amplification on the first-stage amplified residual signal, and outputs the second-stage amplified residual signal. The auxiliary amplifier circuit performs a third amplification process on the residual signal to be processed, and outputs an amplified error signal. The amplified error signal is used to eliminate the error of the second-stage amplified residual signal, and the error elimination residual signal is output. Based on the above content, since the first-stage amplifier circuit and the auxiliary amplifier circuit are multiplexed, compared with the conventional technical solution of separately configuring the auxiliary amplifier circuit on the basis of the first-stage amplifier circuit and the second-stage amplifier circuit, it can have a smaller integrated circuit area (so that the integration difficulty can be reduced) and lower power consumption, thereby improving the problem that the power consumption of the operational amplifier circuit existing in the prior art is relatively large and the integration difficulty is relatively high.

[0065] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An operational amplifier circuit, characterized in that: include: an amplification multiplexing circuit, wherein the amplification multiplexing circuit serves as a common circuit for the first-stage amplification circuit and the auxiliary amplification circuit to realize circuit multiplexing, and different circuit nodes in the amplification multiplexing circuit serve as an output end of the first-stage amplification circuit and an output end of the auxiliary amplification circuit respectively; A second-stage amplifier circuit, wherein an input end of the second-stage amplifier circuit is connected to an output end of the first-stage amplifier circuit; Among them, the first-stage amplifier circuit is used to perform a first amplification on the input residual signal to be processed, and output the corresponding first-stage amplified residual signal to the second-stage amplifier circuit; the second-stage amplifier circuit is used to perform a second amplification on the first-stage amplified residual signal, and output the corresponding second-stage amplified residual signal; the auxiliary amplifier circuit is used to perform a third amplification on the residual signal to be processed, and output the corresponding amplified error signal; the amplified error signal is used to perform error elimination on the second-stage amplified residual signal, and output the corresponding error-eliminated residual signal.

2. The operational amplifier circuit according to claim 1, characterized in that: The amplification multiplexing circuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a first resistor and a second resistor; Among them, the source of the first field effect transistor is grounded, the gate of the first field effect transistor serves as a connection port for a first bias voltage, the drain of the first field effect transistor is connected to the source of the second field effect transistor and the source of the third field effect transistor respectively, the gate of the second field effect transistor and the gate of the third field effect transistor serve as connection ports for the residual signal to be processed, the drain of the second field effect transistor is connected to the source of the fourth field effect transistor, the drain of the third field effect transistor is connected to the source of the fifth field effect transistor, the gate of the fourth field effect transistor is connected to the gate of the fifth field effect transistor and serves as a connection port for a common-mode feedback voltage, and the drain of the fourth field effect transistor, the drain of the fifth field effect transistor, the first resistor and the second resistor are connected as a connection port for a power supply voltage.

3. The operational amplifier circuit according to claim 2, characterized in that: The drain of the fourth field effect transistor is connected to the first end of the first resistor, the drain of the fifth field effect transistor is connected to the first end of the second resistor, and the second end of the first resistor is connected to the second end of the second resistor and serves as a connection port for the power supply voltage.

4. The operational amplifier circuit according to claim 3, characterized in that: The source of the fourth field effect transistor and the source of the fifth field effect transistor serve as output terminals of the first-stage amplifier circuit, and are used to output the corresponding first-stage amplified residual signal to the second-stage amplifier circuit; Furthermore, the drain of the fourth field effect transistor and the drain of the fifth field effect transistor serve as output terminals of the auxiliary amplifier circuit, and are used to output corresponding amplified error signals.

5. The operational amplifier circuit according to claim 3, characterized in that: The second stage amplifying circuit includes an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a seventeenth field effect transistor and an eighteenth field effect transistor; Among them, the source of the eleventh field effect tube and the source of the twelfth field effect tube are grounded, the gate of the eleventh field effect tube and the gate of the twelfth field effect tube are respectively connected to the source of the fourth field effect tube and the source of the fifth field effect tube as the input end of the second stage amplifier circuit, the drain of the eleventh field effect tube is connected to the source of the thirteenth field effect tube, the drain of the twelfth field effect tube is connected to the source of the fourteenth field effect tube, the gate of the thirteenth field effect tube is connected to the drain of the fourteenth field effect tube and serves as a connection port for the fourth bias voltage, the drain of the thirteenth field effect tube is connected to the drain of the fifteenth field effect tube, and the drain of the fourteenth field effect tube is connected to the drain of the fifteenth field effect tube. The drain of the fifteenth field effect transistor is connected to the drain of the sixteenth field effect transistor, the drain of the fifteenth field effect transistor and the drain of the sixteenth field effect transistor serve as the output end of the second stage amplifier circuit, the gate of the fifteenth field effect transistor is connected to the gate of the sixteenth field effect transistor and serves as a connection port for a fifth bias voltage, the source of the fifteenth field effect transistor is connected to the drain of the seventeenth field effect transistor, the source of the sixteenth field effect transistor is connected to the drain of the eighteenth field effect transistor, the gate of the seventeenth field effect transistor is connected to the gate of the eighteenth field effect transistor and serves as a connection port for a sixth bias voltage, and the source of the seventeenth field effect transistor is connected to the source of the eighteenth field effect transistor and serves as a connection port for the power supply voltage.

6. The operational amplifier circuit according to claim 2, characterized in that: The amplification multiplexing circuit also includes a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor and a tenth field effect transistor; Among them, the drain of the fourth field effect transistor is connected to the first end of the first resistor, the drain of the fifth field effect transistor is connected to the first end of the second resistor, the second end of the first resistor is connected to the second end of the second resistor, the drain of the fourth field effect transistor is connected to the drain of the sixth field effect transistor, the drain of the fifth field effect transistor is connected to the drain of the seventh field effect transistor, the gate of the sixth field effect transistor is connected to the drain of the seventh field effect transistor and serves as a connection port for a second bias voltage, the source of the sixth field effect transistor is connected to the drain of the eighth field effect transistor, the source of the seventh field effect transistor is connected to the drain of the ninth field effect transistor, the gate of the eighth field effect transistor and the gate of the ninth field effect transistor serve as connection ports for a third bias voltage, the source of the eighth field effect transistor, the source of the ninth field effect transistor, and the drain of the tenth field effect transistor are connected, the gate of the tenth field effect transistor and the gate of the first field effect transistor serve as connection ports for the seventh bias voltage, and the source of the tenth field effect transistor serves as a connection port for a power supply voltage.

7. The operational amplifier circuit according to claim 6, characterized in that: The source of the fourth field effect transistor and the source of the fifth field effect transistor serve as output terminals of the first-stage amplifier circuit, and are used to output the corresponding first-stage amplified residual signal to the second-stage amplifier circuit; Furthermore, the drain of the fourth field effect transistor and the drain of the fifth field effect transistor serve as output terminals of the auxiliary amplifier circuit, and are used to output corresponding amplified error signals.

8. The operational amplifier circuit according to claim 6, characterized in that: The second stage amplifying circuit includes an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a seventeenth field effect transistor and an eighteenth field effect transistor; Among them, the source of the eleventh field effect tube and the source of the twelfth field effect tube are grounded, the gate of the eleventh field effect tube and the gate of the twelfth field effect tube are respectively connected to the source of the fourth field effect tube and the source of the fifth field effect tube as the input end of the second stage amplifier circuit, the drain of the eleventh field effect tube is connected to the source of the thirteenth field effect tube, the drain of the twelfth field effect tube is connected to the source of the fourteenth field effect tube, the gate of the thirteenth field effect tube is connected to the drain of the fourteenth field effect tube and serves as a connection port for the fourth bias voltage, the drain of the thirteenth field effect tube is connected to the drain of the fifteenth field effect tube, the drain of the fourteenth field effect tube is connected to the sixteenth field effect tube, and the gate of the thirteenth field effect tube is connected to the drain of the fifteenth field effect tube. The drain of the field effect transistor is connected, the drain of the fifteenth field effect transistor and the drain of the sixteenth field effect transistor serve as the output end of the second stage amplifier circuit, the gate of the fifteenth field effect transistor is connected to the gate of the sixteenth field effect transistor and serves as a connection port for the fifth bias voltage, the source of the fifteenth field effect transistor is connected to the drain of the seventeenth field effect transistor, the source of the sixteenth field effect transistor is connected to the drain of the eighteenth field effect transistor, the gate of the seventeenth field effect transistor and the gate of the eighteenth field effect transistor are respectively connected to the drain of the eighth field effect transistor and the drain of the ninth field effect transistor, and the source of the seventeenth field effect transistor is connected to the source of the eighteenth field effect transistor and serves as a connection port for the power supply voltage.

9. A digital-to-analog converter, characterized in that: The digital-to-analog converter comprises the operational amplifier circuit according to any one of claims 1-8.

10. The digital-to-analog converter according to claim 9, characterized in that: The digital-to-analog converter comprises at least two operational amplifier circuits; Among them, at least one of the operational amplifier circuits further includes a sampling capacitor, at least two of the operational amplifier circuits are cascaded, and the output end of the second-stage amplifier circuit in the previous operational amplifier circuit is connected to the top plate of the sampling capacitor in the next operational amplifier circuit, so that the second-stage amplified residual signal is applied to the top plate of the sampling capacitor, and the output end of the auxiliary amplifier circuit in the previous operational amplifier circuit is connected to the bottom plate of the sampling capacitor in the next operational amplifier circuit, so that the amplified error signal is applied to the bottom plate of the sampling capacitor, so that the corresponding error elimination residual signal is obtained by sampling through the sampling capacitor, and the error elimination residual signal is used as the residual signal to be processed of the next operational amplifier circuit.

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