Method and device for realizing inter-coefficient multiple variable interpolation processing based on FPGA (Field Programmable Gate Array) in digital signal processing, processor and medium thereof

Abstract

The invention relates to a method for realizing inter-coefficient multiple variable interpolation processing based on an FPGA (Field Programmable Gate Array) in digital signal processing. The method comprises the following steps of: generating control signals of each module according to an update signal and a required interpolation multiple; generating a lower half part coefficient of the farrow filter according to the required interpolation multiple; receiving a serial data set; a farrow filtering operation is carried out; storing multiple groups of serial data, and performing permutation and combination; and caching the data and outputting the data at equal intervals. The invention discloses a method and a device for realizing inter-coefficient multiple variable interpolation processing based on an FPGA (Field Programmable Gate Array) in digital signal processing, a processor and a computer readable storage medium thereof. The whole farrow module is controlled to carry out multiple interpolation through indication signals, such as enable signals and trigger signals, of all subordinate modules generated by the signal control module and a generated filter lower half part coefficient, and when the data updating period is long or data needing to be interpolated in each updating period is small, the whole farrow module is controlled to carry out multiple interpolation. A user can select to carry out more times of interpolation, so that waste of time resources is avoided, and meanwhile, the precision of the data after interpolation is improved.

Description

Technical Field

[0001] The present invention relates to the field of FPGA hardware, in particular to the field of digital signal processing, and specifically refers to a method, device, processor and computer-readable storage medium thereof for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing. Background Art

[0002] The present invention is based on the theory of farrow filter. The ideal filter is divided into two parts, the upper part has fixed coefficients, and the lower part inputs a variable delay coefficient △k, and the fractional delay of the output signal is (1-△k)*Tclk. The value of △k is between 0.0 and 1.0. Figure 1 As shown, the upper part of the fourth-order farrow filter is five fir filters. The data of five adjacent update cycles are multiplied and accumulated with the corresponding coefficients respectively, and five new data are obtained and sent to the lower part of the farrow filter to perform multiplication and addition operations with △k.

[0003] The higher the order of the filter, the better the filtering effect, and the more chip resources are occupied in the FPGA. The more times the lower part of the Farrow filter is instantiated, that is, the more △k, the higher the accuracy of the interpolated data, and the corresponding increase in time resources and FPGA chip resources. The existing technology is mainly theoretical or processes the data model in MATLAB. When using FPGA to realize the interpolation between coefficients, it mainly focuses on realizing a fixed interpolation multiple, and cannot flexibly adjust the interpolation multiple of the coefficient according to the update rate and length of the coefficient. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a method, device, processor and computer-readable storage medium for implementing variable interpolation processing between coefficients based on FPGA in digital signal processing that meets the requirements of high precision, high accuracy and a wide range of applications.

[0005] In order to achieve the above-mentioned object, the method, device, processor and computer-readable storage medium thereof for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing of the present invention are as follows:

[0006] The method for realizing variable interpolation processing of coefficients based on FPGA in digital signal processing has the following main features:

[0007] (1) Generate control signals for each module according to the update signal and the required interpolation multiple;

[0008] (2) Generate the coefficients of the lower half of the farrow filter according to the required interpolation multiple;

[0009] (3) receiving a serial data group, storing it in a plurality of memories and performing a cache shift according to a control module enable signal;

[0010] (4) Perform farrow filtering operation;

[0011] (5) Storing multiple sets of serial data and performing permutations and combinations;

[0012] (6) The data is cached and output at equal intervals.

[0013] Preferably, the step (1) specifically comprises the following steps:

[0014] (1.1) According to the data update cycle and the interpolation multiple n, n new update signals are generated evenly and equidistantly between two update signals;

[0015] (1.2) Generate an enable signal based on the data length of the farrow module in one update cycle and the required interpolation multiple.

[0016] Preferably, the generated update signal is used to control the subsequent data to be output at equal intervals and as an update signal for subsequent modules of the farrow module; the generated enable signal is used to store the address of the module and to generate an indication signal for the lower half △k of the farrow filter.

[0017] Preferably, the step (3) is specifically as follows:

[0018] Shift the upper half of the farrow filter by 4 times.

[0019] Preferably, the step (4) is specifically as follows:

[0020] The serial data after 4 shifts are added to the original serial data into 5 groups to form a column, and a 4th-order farrow filter operation is performed.

[0021] Preferably, the step (5) specifically comprises the following steps:

[0022] The data after the operation of the lower half of the farrow filter are stored in eight groups of bram memories respectively, and the results of the eight groups of serial storage are switched by the state machine;

[0023] After storing one group, switch to store the next group;

[0024] While storing the second group, a read operation is performed on the first group of 8 parallel stored bram memories, and the data in the memories are read longitudinally to obtain rearranged data.

[0025] Preferably, the step (6) is specifically as follows:

[0026] The arranged and combined data is output through a layer of fifo cache, and the generated new update signal is used as fifo read enable to enable all data to be output at equal intervals.

[0027] The device for realizing variable interpolation processing of coefficients based on FPGA in digital signal processing has the following main features: the device comprises:

[0028] a processor configured to execute computer executable instructions;

[0029] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for implementing variable interpolation processing of coefficients based on FPGA in the above-mentioned digital signal processing are implemented.

[0030] The processor used for implementing variable interpolation processing between coefficients based on FPGA in digital signal processing has the main feature that the processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for implementing variable interpolation processing between coefficients based on FPGA in the above-mentioned digital signal processing are implemented.

[0031] The main feature of the computer-readable storage medium is that a computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for implementing variable interpolation processing between coefficients based on FPGA in the above-mentioned digital signal processing.

[0032] The method, device, processor and computer-readable storage medium thereof for implementing variable interpolation processing between coefficients based on FPGA in digital signal processing of the present invention are adopted. The overall farrow module is controlled to perform multiple interpolation through indication signals such as enable signals, trigger signals and the like of each lower module generated by a signal control module and the generated coefficients of the lower half of the filter. The user can flexibly adjust the interpolation multiples required by the user. When the data update cycle is long or the data to be interpolated in each update cycle is small, the user can choose to perform more multiple interpolations to avoid wasting time resources while improving the accuracy of the data after interpolation. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The present invention is a schematic diagram of a fourth-order farrow filter for implementing a method for variable interpolation processing between coefficients based on FPGA in digital signal processing.

[0034] Figure 2 The present invention is a flowchart of a method for implementing variable interpolation processing of coefficient multiples based on FPGA in digital signal processing.

[0035] Figure 3 This is a new update signal generation diagram for the method of implementing variable interpolation processing between coefficients based on FPGA in digital signal processing of the present invention.

[0036] Figure 4 This is a control signal generation diagram for each module of the method for implementing variable interpolation processing between coefficients based on FPGA in digital signal processing of the present invention.

[0037] Figure 5 The present invention is a graph for generating coefficients △k of the lower half of a farrow filter in a method for implementing variable interpolation processing of coefficient multiples based on FPGA in digital signal processing of the present invention.

[0038] Figure 6 It is a data cache shift output diagram of the method for implementing variable interpolation processing of multiples between coefficients based on FPGA in digital signal processing of the present invention.

[0039] Figure 7 It is a graph of eight uniform outputs of eight groups of parallel data in the method for implementing variable interpolation processing of multiples between coefficients based on FPGA in digital signal processing of the present invention.

[0040] Figure 8 It is a data arrangement and combination diagram of calculation results of the method for implementing variable interpolation processing of multiples between coefficients based on FPGA in digital signal processing of the present invention.

[0041] Fig. 9 This is a data uniform output diagram of the method for implementing variable interpolation processing of multiples between coefficients based on FPGA in digital signal processing of the present invention. DETAILED DESCRIPTION

[0042] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0043] The method for implementing variable interpolation processing of multiples between coefficients based on FPGA in the digital signal processing of the present invention comprises the following steps:

[0044] (1) Generate control signals for each module according to the update signal and the required interpolation multiple;

[0045] (2) Generate the coefficients of the lower half of the farrow filter according to the required interpolation multiple;

[0046] (3) receiving a serial data group, storing it in a plurality of memories and performing a cache shift according to a control module enable signal;

[0047] (4) Perform farrow filtering operation;

[0048] (5) Storing multiple sets of serial data and performing permutations and combinations;

[0049] (6) The data is cached and output at equal intervals.

[0050] As a preferred embodiment of the present invention, the step (1) specifically comprises the following steps:

[0051] (1.1) According to the data update cycle and the interpolation multiple n, n new update signals are generated evenly and equidistantly between two update signals;

[0052] (1.2) Generate an enable signal based on the data length of the farrow module in one update cycle and the required interpolation multiple.

[0053] As a preferred embodiment of the present invention, the generated update signal is used to control the equal-interval output of subsequent data and serves as an update signal for subsequent modules of the farrow module; the generated enable signal is used to store the address of the module and to generate an indication signal for the lower half △k of the farrow filter.

[0054] As a preferred embodiment of the present invention, the step (3) is specifically as follows:

[0055] Shift the upper half of the farrow filter by 4 times.

[0056] As a preferred embodiment of the present invention, the step (4) is specifically as follows:

[0057] The serial data after 4 shifts are added to the original serial data into 5 groups to form a column, and a 4th-order farrow filter operation is performed.

[0058] As a preferred embodiment of the present invention, the step (5) specifically comprises the following steps:

[0059] The data after the operation of the lower half of the farrow filter are stored in eight groups of bram memories respectively, and the results of the eight groups of serial storage are switched by the state machine;

[0060] After storing one group, switch to store the next group;

[0061] While storing the second group, a read operation is performed on the first group of 8 parallel stored bram memories, and the data in the memories are read longitudinally to obtain rearranged data.

[0062] As a preferred embodiment of the present invention, the step (6) is specifically as follows:

[0063] The arranged and combined data is output through a layer of fifo cache, and the generated new update signal is used as fifo read enable to enable all data to be output at equal intervals.

[0064] The device for implementing variable interpolation processing of coefficients based on FPGA in the digital signal processing of the present invention, wherein the device comprises:

[0065] a processor configured to execute computer executable instructions;

[0066] The memory stores one or more computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for implementing variable interpolation processing of coefficients based on FPGA in the above-mentioned digital signal processing are implemented.

[0067] The present invention discloses a processor for implementing variable interpolation processing between coefficients based on FPGA in the digital signal processing, wherein the processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for implementing variable interpolation processing between coefficients based on FPGA in the above-mentioned digital signal processing are implemented.

[0068] The computer-readable storage medium of the present invention stores a computer program thereon, and the computer program can be executed by a processor to implement the various steps of the method for implementing variable interpolation processing of coefficient multiples based on FPGA in the above-mentioned digital signal processing.

[0069] In a specific embodiment of the present invention, a method for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing is disclosed, wherein the method comprises the following steps:

[0070] (1) Generate control signals for each module according to the update signal and the required interpolation multiple;

[0071] (2) Generate the coefficients of the lower half of the farrow filter according to the required interpolation multiple;

[0072] (3) receiving a serial data group, storing it in a plurality of memories and performing a cache shift according to a control module enable signal;

[0073] (4) Perform farrow filtering operation;

[0074] (5) Storing multiple sets of serial data and performing permutations and combinations;

[0075] (6) The data is cached and output at equal intervals.

[0076] In a specific embodiment of the present invention, the specific steps of the embodiment are as follows:

[0077] 1. Generate control signals for each module:

[0078] 1.1 According to the data update cycle and interpolation multiple n, n new update signals are generated evenly and equidistantly between two update signals, which are used to control the subsequent data output at equal intervals and as the update signal of the subsequent module of the farrow module, as shown in the attached figure. Figure 3 As shown, 64 times interpolation is taken as an example;

[0079] 1.2 Generate an enable signal for the calculation module according to the data length of the farrow module input in an update cycle and the required interpolation multiple, an address for the storage module, and an indication signal for generating the lower half △k of the farrow filter, such as Figure 4 As shown, 64 times interpolation is taken as an example;

[0080] 2. Generation of coefficient △k of the lower part of the farrow filter: Generate the corresponding coefficient △k according to the indication signal sent by the control module, such as Figure 5 As shown, it should be noted that when this scheme is calculated inside the FPGA, △k is used as a fixed-point number, and the decimal point is before the highest bit;

[0081] 3. Receive the sent serial data group, store it in the memory and perform cache shift. Taking the 4th order farrow filter as an example, the upper part of the farrow needs to be shifted 4 times, such as Figure 6 As shown, in the example project, each set of serial data contains 1536 data, which is divided into 8 sets of parallel data, thereby saving a large part of time resources and facilitating subsequent data operations. When these 8 sets of data are output, they are output 8 times at equal intervals, 8 = 64 (interpolation multiple) / 8 (the number of parallel operations in the lower half of the farrow), and the output enable is provided by the control module, such as Figure 7 As shown, this will save FPGA chip resources for the next step of farrow filtering operation. At the same time, because the project has saved a lot of time resources in the previous data shifting process, this step will not cause adverse effects on timing.

[0082] 4. The serial data after 4 shifts plus 5 groups of original serial data are put into a row to perform the 4th-order farrow filter operation. In the FPGA project, the operation of the farrow filter is divided into two parts, the upper and lower parts. Taking the completion of 64 times interpolation as an example, the lower part of the farrow filter is instantiated eight times, that is, the eight lower parts of the farrow are calculated in parallel, one group at a time, and there are eight serial groups.

[0083] 5. After the data has completed all operations, it enters the permutation and combination part. The data that has been operated in the lower half of the farrow filter is stored in eight groups of bram memories. The results of the eight groups of serial storage are switched through the state machine. After storing one group, the next group is switched to store. While storing the second group, the first group of 8 parallel storage bram memories is read. The data in the memory can be read vertically to obtain the rearranged data, such as Figure 8 As shown;

[0084] 6. The data that has been arranged and combined is output through a layer of fifo cache, and the new update signal generated by the control module is used as the fifo read enable, so that all data can be output at equal intervals, such as Fig. 9 shown.

[0085] The technical solution of the present invention focuses on the fact that the interpolation multiple can be flexibly adjusted according to the needs of users when the Farrow interpolation structure has been implemented on the FPGA. The interpolation multiple of the technical solution can be adjusted during use according to the needs of users, rather than being a fixed interpolation multiple; the solution opens up two configuration factors, the data update cycle and the interpolation multiple n, so that the generation of the control signal of each module and the coefficient △k of the lower half of the farrow filter in step (1) and step (2) can be changed according to user needs, with higher mobility and flexibility.

[0086] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0087] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0088] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0089] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0090] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0091] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the corresponding program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0092] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0093] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0095] The method, device, processor and computer-readable storage medium thereof for implementing variable interpolation processing between coefficients based on FPGA in digital signal processing of the present invention are adopted. The overall farrow module is controlled to perform multiple interpolation through indication signals such as enable signals, trigger signals and the like of each lower module generated by a signal control module and the generated coefficients of the lower half of the filter. The user can flexibly adjust the interpolation multiples required by the user. When the data update cycle is long or the data to be interpolated in each update cycle is small, the user can choose to perform more multiple interpolations to avoid wasting time resources while improving the accuracy of the data after interpolation.

[0096] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing, characterized in that: The method comprises the following steps: (1) Generate control signals for each module according to the update signal and the required interpolation multiple; (2) Generate the coefficients of the lower half of the farrow filter according to the required interpolation multiple; (3) receiving a serial data group, storing it in a plurality of memories and performing a cache shift according to a control module enable signal; (4) Perform farrow filtering operation; (5) Storing multiple sets of serial data and performing permutations and combinations; (6) The data is cached and output at equal intervals.

2. The method for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing according to claim 1, characterized in that: The step (1) specifically comprises the following steps: (1.1) According to the data update cycle and the interpolation multiple n, n new update signals are generated evenly and equidistantly between two update signals; (1.2) Generate an enable signal based on the data length of the farrow module in one update cycle and the required interpolation multiple.

3. The method for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing according to claim 2, characterized in that: The generated update signal is used to control the subsequent data to be output at equal intervals and as an update signal for subsequent modules of the farrow module; the generated enable signal is used to store the address of the module and to generate an indication signal for the lower half △k of the farrow filter.

4. The method for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing according to claim 1, characterized in that: The step (3) is specifically as follows: Shift the upper half of the farrow filter by 4 times.

5. The method for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing according to claim 1, characterized in that: The step (4) is specifically as follows: The serial data after 4 shifts are added to the original serial data into 5 groups to form a column, and a 4th-order farrow filter operation is performed.

6. The method for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing according to claim 1, characterized in that: The step (5) specifically comprises the following steps: The data after the operation of the lower half of the farrow filter are stored in eight groups of bram memories respectively, and the results of the eight groups of serial storage are switched by the state machine; After storing one group, switch to store the next group; While storing the second group, a read operation is performed on the first group of 8 parallel stored bram memories, and the data in the memories are read longitudinally to obtain rearranged data.

7. The method for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing according to claim 1, characterized in that: The step (6) is specifically as follows: The arranged and combined data is output through a layer of fifo cache, and the generated new update signal is used as fifo read enable to enable all data to be output at equal intervals.

8. A device for implementing variable interpolation processing of coefficients based on FPGA in digital signal processing, characterized in that: The device comprises: a processor configured to execute computer executable instructions; A memory storing one or more computer executable instructions, wherein when the computer executable instructions are executed by the processor, the steps of the method for implementing variable interpolation processing of coefficient multiples based on FPGA in digital signal processing described in any one of claims 1 to 7 are implemented.

9. A processor for implementing variable interpolation processing between coefficients based on FPGA in digital signal processing, characterized in that: The processor is configured to execute computer executable instructions. When the computer executable instructions are executed by the processor, the various steps of the method for implementing variable interpolation processing between coefficients based on FPGA in digital signal processing described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the various steps of the method for implementing variable interpolation processing between coefficients based on FPGA in digital signal processing in any one of claims 1 to 7.

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