Intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation

Abstract

The invention discloses an intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation. The intermediate frequency digital power amplifier modulator comprises a high-speed ADC, a data buffer module, an envelope elimination module, a phase lag module, an envelope extraction module and an SPWM modulation module. The input end of the high-speed ADC is connected to a pre-stage communication system signal source, the output end of the high-speed ADC is connected with the input end of the data buffer module, the output end of the data buffer module is connected with the input end of the envelope elimination module and the input end of the envelope extraction module, and the output end of the envelope elimination module is connected with the input end of the phase lag module. The output end of the phase lag module is used as a PWM driving signal of a post-stage circuit, the output end of the envelope extraction module is connected with the input end of the SPWM modulation module, and the output end of the SPWM modulation module is used as an SPWM driving signal of the post-stage circuit. The power amplifier unit is suitable for a high-power intermediate-frequency transmitter system, so that the power amplifier unit can use full-digital topology, the efficiency of the system is greatly improved, and the size is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to an intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation. Background Art

[0002] The intermediate frequency digital transmission system mainly provides various message broadcast transmissions for ships at sea, such as navigation safety, piracy, search and rescue, weather information, navigation, port information, ship traffic system file transmission, and electronic chart update packages. In order to improve the efficiency of information transmission, QAM modulation under OFDM is introduced into the communication system. However, conventional intermediate frequency digital power amplifiers cannot transmit signals with amplitude and phase changes. Therefore, the existing mainstream method is to use linear power amplifiers for power cascade. This method not only has low power but also low efficiency. It requires a large heat sink and makes the equipment very large. Another method is to use Figure 1 The envelope elimination and restoration technology (EER) shown in FIG. 1 uses two digital power amplifiers. The half-bridge digital power amplifier is used to amplify the envelope signal of the original signal, and the full-bridge digital power amplifier is used to amplify the carrier signal of the original signal. Finally, the two signals are synthesized in the form of multiplication to restore the original signal.

[0003] However, since the system separates the input signal into two signals, the phase shifts on the two signals will not match and cause phase distortion. In addition, the phase shift of the low-frequency envelope path is much larger than that of the high-frequency carrier path, and may exceed several or even dozens of cycles. Therefore, phase matching of the two signals is a huge challenge. Currently, in the field of intermediate frequency transmitters, there are very few digital modulators of the same type used in EER systems. Therefore, providing a digital modulator with high phase lag accuracy, low complexity, and good adjustability for EER systems is an urgent problem to be solved. Summary of the invention

[0004] In order to solve the problems of phase distortion and large device size in the existing intermediate frequency digital power amplifier, the present invention proposes an intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation to solve the above problems.

[0005] An intermediate frequency digital power amplifier modulator for amplitude and phase modulation, comprising:

[0006] High-speed ADC: used to convert analog signals into parallel digital signals;

[0007] Data buffer module: used to buffer the parallel digital signals collected by the high-speed ADC and perform sampling rate conversion;

[0008] Envelope elimination module: used to eliminate the envelope change of the analog signal of the previous communication system collected by the high-speed ADC, and obtain a square wave signal with a constant envelope, and the square wave signal only carries frequency and phase information;

[0009] Phase lag module: used to control and adjust the phase lag of the square wave signal with only frequency and phase information, and output a PWM drive signal for driving the subsequent circuit;

[0010] Envelope extraction module: used to extract the envelope signal of the analog signal of the previous communication system collected by the high-speed ADC;

[0011] SPWM modulation module: used to perform SPWM modulation on the envelope signal extracted by the envelope extraction module, and output two SPWM drive signals with dead zone complementation;

[0012] The PWM driving signal output by the phase lag module for driving the subsequent circuit is consistent in phase with the envelope signal output by the subsequent circuit driven by the SPWM modulation module;

[0013] The data buffer module, envelope elimination module, phase lag module, envelope extraction module and SPWM modulation module are arranged inside an FPGA, the high-speed ADC input end is connected to the front-stage communication system signal source, the high-speed ADC output end is connected to the data buffer module input end, the data buffer module output end is respectively connected to the envelope elimination module input end and the envelope extraction module input end, the envelope elimination module output end is connected to the phase lag module input end, the phase lag module output end is used as the PWM driving signal of the rear-stage circuit, the envelope extraction module output end is connected to the SPWM modulation module input end, and the SPWM modulation module output end is used as the SPWM driving signal of the rear-stage circuit.

[0014] Preferably, the envelope elimination module includes a first input buffer register, a first symbol decision module, a first data selector, a first register and a second register, the input end of the first input buffer register is connected to the output end of the data buffer module, the highest bit reg11 output end of the first input buffer register is connected to the input end of the first symbol decision module, the output end of the first symbol decision module is connected to the control end of the first data selector, the input end of the first data selector is respectively connected to the output end of the first register storing a logic signal 0 and the output end of the second register storing a logic signal 1, and the output end of the first data selector is output as a PWM modulation signal for envelope elimination.

[0015] Preferably, the bit lag module includes a phase lag controller, an inverter, a read address adder, a write address controller, a write address accumulator, a phase lag buffer array, an input data buffer module and an output data buffer module, the output end of the phase lag controller is connected to the input end of the inverter, the output end of the inverter is connected to the input end of the read address adder, the output end of the read address adder is connected to the read address control input end of the phase lag buffer array, the output end of the write address controller is connected to the input end of the write address accumulator, the output end of the write address accumulator is respectively connected to the input end of the write address accumulator, the input end of the read address adder and the phase lag buffer array, the input end of the input data buffer module is connected to the PWM modulation signal output by the first data selector, the output end of the input data buffer module is connected to the read data output end of the phase lag buffer array, and the output end of the output data buffer module is output as a PWM modulation signal with phase lag.

[0016] Preferably, the phase lag module uses a buffer array phase lag method to buffer the PWM modulation signal, so that The phase lag accuracy of the first level is 1000, where f is the system clock, and the fine phase lag adjustment of more than one hundredth of the PWM modulation signal period can be achieved.

[0017] Preferably, the buffer array phase lag method comprises the following steps:

[0018] A RAM with a depth of n bits and a width of 1 inside the FPGA is used as a phase lag buffer array. The write address controller distributes the clock so that the write address accumulator accumulates at the frequency of the system clock f, and each accumulation is 1 bit. The output w_addr of the write address accumulator is used to control the write data address of the phase lag buffer array. The PWM modulation signal generated by the network elimination module is input through the data buffer module, and the output of the data buffer module is stored in the phase lag buffer array corresponding to the output address of the write address accumulator. The data interval time between adjacent addresses is The lag time is set to t, and the phase lag controller converts the lag time t into the address difference k according to the system clock f. The difference k is inverted by the inverter and output -k. The output -k of the inverter and the output w_addr of the write address accumulator are added through the read address adder to obtain the read address adder output r_addr, wherein r_addr=w_addr-k. The output data buffer module reads data from the corresponding address of the phase lag buffer array according to the read address adder output r_addr, and outputs it as a PWM signal with phase lag.

[0019] Preferably, the envelope extraction module includes a second input buffer register, a second symbol decision module, a symbol flip module, a second data selector and a FIR low-pass filter, the second input buffer register input end is connected to the output end of the output data buffer module, the second input buffer register highest bit reg11 output end is connected to the second symbol decision module input end, the input buffer register lowest bit to the second highest bit reg0~reg10 are connected to the second data selector input end and the symbol flip module input end, the second symbol decision module output end is connected to the second data selector control end, the second data selector output end is connected to the FIR low-pass filter input end, and the FIR low-pass filter output end outputs an envelope signal.

[0020] Preferably, the SPWM modulation module includes a triangular wave generating unit, a first comparator, a second comparator, a first dead zone generating unit and a second dead zone generating unit, the output end of the triangular wave generating unit is respectively connected to the negative input end of the first comparator and the positive input end of the second comparator, the positive input end of the first comparator and the negative input end of the second comparator are both connected to the output end of the FIR low-pass filter, the output end of the first comparator is connected to the input end of the first dead zone generating unit, the output end of the second comparator is connected to the input end of the second dead zone generating unit, the output end of the first dead zone generating unit outputs an N_SPWM signal, and the output end of the second dead zone generating unit outputs a P_SPWM signal, and the N_SPWM signal and the P_SPWM signal are two signals with complementary dead zones.

[0021] Beneficial effects of the present invention:

[0022] (1) The present invention adopts a buffer array phase lag method to achieve high-precision and long-term phase lag and matching, greatly improving the accuracy of the intermediate frequency digital transmitter.

[0023] (2) The present invention uses an FPGA chip to implement a fully digital digital modulator, which greatly reduces the circuit complexity and reduces the size of the modulator.

[0024] (3) The present invention proposes and designs an intermediate frequency digital power amplifier modulator for amplitude and phase modulation in an intermediate frequency transmitter, which can be used as a modulator of a full digital power amplifier topology, so that the intermediate frequency transmitter with amplitude and phase modulation can use the full digital power amplifier topology, which greatly improves the efficiency and power of the intermediate frequency transmitter and reduces the size of the intermediate frequency transmitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a typical structural diagram of the envelope elimination and restoration technology (EER);

[0026] Figure 2 A schematic diagram of the structure of an intermediate frequency digital power amplifier modulator applied to amplitude and phase modulation according to an embodiment of the present invention;

[0027] Figure 3 Schematic diagram of the structure of an envelope elimination module according to an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of the structure of a phase lag module according to an embodiment of the present invention;

[0029] Figure 5 Schematic diagram of the structure of an envelope extraction module according to an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of the structure of an SPWM modulation module according to an embodiment of the present invention;

[0031] Figure 7 is an input signal waveform diagram of an embodiment of the present invention;

[0032] Figure 8 The SPWM output waveform diagram of the embodiment of the present invention;

[0033] Fig. 9 PWM output waveform diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and examples.

[0035] The present application discloses an intermediate frequency digital power amplifier modulator for amplitude and phase modulation, such as Figure 2 As shown, it includes: a high-speed ADC, a data buffer module, an envelope elimination module, a phase lag module, an envelope extraction module and an SPWM modulation module. The data buffer module, the envelope elimination module, the phase lag module, the envelope extraction module and the SPWM modulation module are arranged inside an FPGA. In this embodiment, the FPGA adopts an AX035B development board with an onboard XC7A35T FPGA chip. The input end of the high-speed ADC is connected to the signal source of the front-stage communication system, the output end of the high-speed ADC is connected to the input end of the data buffer module, the output end of the data buffer module is respectively connected to the input end of the envelope elimination module and the input end of the envelope extraction module, the output end of the envelope elimination module is connected to the input end of the phase lag module, the output end of the phase lag module is used as the PWM driving signal of the rear-stage circuit, the output end of the envelope extraction module is connected to the input end of the SPWM modulation module, and the output end of the SPWM modulation module is used as the SPWM driving signal of the rear-stage circuit.

[0036] In this embodiment, the input original signal is a modulated signal with amplitude and phase changing at the same time, with a center frequency of 500kHz and a bandwidth of 10kHz. The original signal is collected into the FPGA through a high-speed ADC, and the original signal is divided into two paths for processing, respectively processing the phase information and amplitude information of the original signal, separating the phase information from the amplitude information and generating a signal for driving the Figure 1 The driving signals of the half-bridge and full-bridge amplifiers. Since the high-frequency carrier signal carries the phase information in the original signal, and the low-frequency envelope signal carries the amplitude information, the difference between the two periods is too large. Therefore, when the two signals are restored later, the phase lag caused by the low-frequency path will be much higher than that of the high-frequency path, which may be 10 times the period or even more.

[0037] The high-speed ADC is used to convert analog signals into parallel digital signals that can be processed by the FPGA. The high-speed ADC in this embodiment is an AD9226 module, the output interface of which is a 12-bit parallel interface that can be directly connected to the FPGA to receive data. The maximum sampling rate of the module is 65Msps, the input signal allowable range is ±5V, and the input characteristic impedance is 50Ω.

[0038] Data buffer module: used to buffer the parallel digital signals collected by the high-speed ADC, and has the function of sampling rate conversion. Since the maximum sampling rate of the front-stage high-speed ADC module is 65Msps, the sampling clock is selected as 50MHz, but in order to ensure the accuracy of the modules such as the phase lag of the subsequent stage, the FPGA sets the system operating frequency to 100MHz. Therefore, a buffer module is required to oversample the data, where the input of the data buffer module is the 12-bit parallel data of the front-stage high-speed ADC, which is stored in the register of the data buffer module at a frequency of 50MHz. The output of the buffer module uses a 100MHz clock to sample the register and send the data to the subsequent module.

[0039] The signal passing through the data buffer module is divided into two paths. The first path will first use the envelope elimination module to eliminate the envelope signal of the original signal, retaining only the carrier phase and frequency information, and the amplitude will be normalized. The first signal is a high-frequency carrier signal, which will have a lower delay than the second signal. Therefore, a phase lag is added to the first signal, and the buffer array phase lag method is used in the phase lag module to ensure that the first signal and the second signal are in phase when the final signal is synthesized. The second signal first uses the envelope extraction module to eliminate the frequency and phase signals of the original signal, retaining only the amplitude information and extracting the envelope line. Then the SPWM modulation module is used to convert the envelope information into an SPWM modulation signal for driving the subsequent module.

[0040] The envelope elimination module is used to eliminate the envelope changes of the analog signal of the previous communication system collected by the high-speed ADC, and obtain a square wave signal with normalized amplitude. The square wave signal only carries frequency and phase information. Figure 3 As shown, the envelope elimination module includes a 12-bit first input buffer register, a first symbol decision module, a two-bit 1-bit first data selector, a first register, and a second register. The input end of the first input buffer register is connected to the output end of the data buffer module, the output end of the highest bit reg11 of the first input buffer register is connected to the input end of the first symbol decision module, the output end of the first symbol decision module is connected to the control end of the first data selector, the input end of the first data selector is respectively connected to the output end of the first register storing a logic signal 0 and the output end of the second register storing a logic signal 1, and the output end of the first data selector is output as a PWM modulation signal for envelope elimination.

[0041] The input signal of the envelope elimination module is a parallel digital signal converted by a high-speed ADC in the form of a complement code. The highest bit of the input signal is the sign bit. The highest bit is 0 for positive and 1 for negative. The first input buffer register caches the input signal, and the first symbol determiner determines the current logic level of the highest bit of the input signal in the first input buffer register. When the highest bit is 0, it indicates that the input signal is positive, and the first data selector is controlled to output 1. When the highest bit is 1, it indicates that the input signal is negative, and the first data selector is controlled to output 0. In this way, the input signal amplitude is normalized and converted into a square wave signal containing only frequency and phase information. The square wave signal is used as a PWM drive signal after passing through the post-stage phase lag module.

[0042] The following is a principle analysis of the envelope elimination module. The original signal s(t) is a signal with amplitude and phase changes:

[0043] s(t)=A k sin(ωt+θ k );

[0044] Where ω is the angular frequency, t is the time, k = 1, 2, 3…, A k and θ k They represent the discrete amplitude and phase under different encodings respectively. It can be seen that the amplitude A in the original signal s(t) k With phase θ k With information.

[0045] The original signal s(t) will be converted into a square wave signal x(t) after passing through the envelope elimination module:

[0046]

[0047] Where n = 0, 1, 2, 3…, T is the signal period, A is the amplitude of the square wave signal, and the Fourier series expansion of x(t) yields:

[0048]

[0049] It can be seen that the frequency and phase of the original signal are preserved, while the amplitude information is eliminated.

[0050] The phase lag module is used to control and adjust the phase lag of the square wave signal with only frequency and phase information, and output a PWM drive signal for driving the subsequent circuit. Figure 4 As shown, the bit lag module includes a phase lag controller, an inverter, a read address adder, a write address controller, a write address accumulator, a phase lag buffer array, an input data buffer module and an output data buffer module, wherein the phase lag buffer array includes a read address control input terminal and a read data output terminal. The output terminal of the phase lag controller is connected to the input terminal of the inverter, the output terminal of the inverter is connected to the input terminal of the read address adder, the output terminal of the read address adder is connected to the read address control input terminal of the phase lag buffer array, the output terminal of the write address controller is connected to the input terminal of the write address accumulator, the output terminal of the write address accumulator is respectively connected to the input terminal of the write address accumulator, the input terminal of the read address adder and the phase lag buffer array, the input terminal of the input data buffer module is connected to the PWM modulation signal output by the first data selector, the output terminal of the input data buffer module is connected to the read data output terminal of the phase lag buffer array, and the output terminal of the output data buffer module is output as a PWM modulation signal with phase lag. Figure 4 In the figure, w_addr is the write address input of the phase lag buffer array, w_data is the write data input of the phase lag buffer array, r_addr is the read address input of the phase lag buffer array, r_data is the read data output of the phase lag buffer array, n is the data storage address of the phase lag buffer array, and dn is the data stored corresponding to the phase lag buffer array address n.

[0051] The phase lag module uses the buffer array phase lag method to buffer the PWM modulation signal. The phase lag accuracy of the level is 100, where f is the system clock, and the fine phase lag can be adjusted to more than one hundredth of the PWM modulation signal cycle. The steps of the buffer array phase lag method are as follows: use a RAM with a depth of n bits and a width of 1 inside the FPGA as the phase lag buffer array. The write address controller distributes the clock so that the write address accumulator accumulates at the frequency of the system clock f, and each accumulation is 1 bit. The output w_addr of the write address accumulator is used to control the write data address of the phase lag buffer array. The PWM modulation signal generated by the network elimination module is input through the data buffer module, and the output of the data buffer module is stored in the phase lag buffer array corresponding to the output address of the write address accumulator. The data interval time between adjacent addresses is The lag time is set to t, and the phase lag controller converts the lag time t into the address difference k according to the system clock f. The difference k is inverted by the inverter and output -k. The output -k of the inverter and the output w_addr of the write address accumulator are added through the read address adder to obtain the read address adder output r_addr, wherein r_addr=w_addr-k. The output data buffer module reads data from the corresponding address of the phase lag buffer array according to the read address adder output r_addr, and outputs it as a PWM signal with phase lag.

[0052] Since the system clock is f, that is, the system operating frequency is f, the phase lag time t0 is

[0053]

[0054] Then for the PWM modulation signal x(t) of the envelope elimination module, a phase-lag PWM modulation signal y(t) will be obtained:

[0055]

[0056] By comparing the PWM modulation signal x(t) with the phase-lag PWM modulation signal y(t), it can be found that y(t) has a phase lag compared to x(t).

[0057] Envelope extraction module: used to extract the envelope signal of the analog signal of the previous communication system collected by the high-speed ADC. Figure 5As shown, the envelope extraction module includes a second input buffer register, a second symbol decision module, a symbol flip module, a second data selector and a FIR low-pass filter, wherein the input end of the second input buffer register is connected to the output end of the output data buffer module, the output end of the second input buffer register's highest bit reg11 is connected to the input end of the second symbol decision module, the lowest bit to the second highest bit reg0-reg10 of the input buffer register are connected to the input end of the second data selector and the input end of the symbol flip module, the output end of the second symbol decision module is connected to the control end of the second data selector, the output end of the second data selector is connected to the input end of the FIR low-pass filter, and the output end of the FIR low-pass filter outputs an envelope signal.

[0058] The input signal of the envelope extraction module is a parallel digital signal converted by a high-speed ADC in the form of a complement code. The highest bit of the input signal is the sign bit, and the highest bit is 0 for positive, and the highest bit is 1 for negative. The second input buffer register caches the input signal, and the second symbol determiner determines the current logic level of the highest bit of the input signal in the second input buffer register. When the highest bit is 0, it indicates that the input signal is positive, and the second data selector is controlled to directly output the data in the second input buffer register. When the highest bit is 1, it indicates that the input signal is negative, and the second data selector is controlled to output the data after the sign flipper is reversed, so that the input signal is subjected to full-wave rectification. The signal after full-wave rectification will show the spectrum component of the envelope line in the spectrum. At this time, the high-frequency carrier frequency component is filtered out by the FIR low-pass filter, and the envelope signal of the original signal will be obtained.

[0059] In this embodiment, the FIR low-pass digital filter uses a window function method and selects a Hamming window, whose function is:

[0060]

[0061] Where n is the discrete sequence point, N is the window function length, R N (n) is a rectangular sequence.

[0062] The envelope signal frequency range of the full-wave rectified signal is 0-10kHz, and the carrier frequency is 500kHz, so the FIR low-pass digital filter order is 150, the sampling rate is 10MHz, and the passband cutoff frequency is 15kHz. The low-pass filter attenuates to -0.16dB at the passband of 10kHz and to -45.7dB at the carrier frequency of 500kHz.

[0063] The principle analysis is as follows. The original signal s(t) is a signal with amplitude and phase changes, and the function is:

[0064] s(t)=A k sin(ω c t+θk );

[0065] The discrete variable A k Using the function A0+m(t) to replace it, we can get:

[0066] s(t)=[A0+m(t)]sin(ω c t+θ k );

[0067] Its spectrum is:

[0068]

[0069] Among them, A0+m(t) is the envelope signal, M(ω) is the frequency domain expression of the function m(t), and the signal s(t) is full-wave rectified. The spectrum of the envelope signal will produce a periodic extension with an extension interval of ω. c , so we get the function S(ω):

[0070]

[0071] In the function S(ω), k is an integer. It can be found that when k is -1, there is a component a(ω) in the positive half cycle of the spectrum, which is the envelope signal:

[0072]

[0073] At this time, the signal is low-pass filtered and only the component a(ω) is retained to restore the envelope signal A0+m(t).

[0074] The SPWM modulation module is used to perform SPWM modulation on the envelope signal extracted by the envelope extraction module, and output two SPWM drive signals with dead zone complementarity. Figure 6 As shown, the SPWM modulation module includes a triangular wave generating unit, a first comparator, a second comparator, a first dead zone generating unit and a second dead zone generating unit. The output end of the triangular wave generating unit is respectively connected to the negative input end of the first comparator and the positive input end of the second comparator, the positive input end of the first comparator and the negative input end of the second comparator are both connected to the output end of the FIR low-pass filter, the output end of the first comparator is connected to the input end of the first dead zone generating unit, the output end of the second comparator is connected to the input end of the second dead zone generating unit, the output end of the first dead zone generating unit outputs an N_SPWM signal, the output end of the second dead zone generating unit outputs a P_SPWM signal, and the N_SPWM signal and the P_SPWM signal are two signals with complementary dead zones.

[0075] The triangular wave generating unit distributes the frequency through the FPGA main frequency, and generates a triangular wave with a frequency of 500kHz by constructing an accumulator. The triangular wave and the envelope signal output by the envelope extraction module are compared by the first comparator and the second comparator. When the triangular wave amplitude is greater than the envelope signal, the first comparator outputs 0 and the second comparator outputs 1. When the triangular wave amplitude is less than the envelope signal, the first comparator outputs 1 and the second comparator outputs 0. After that, a pair of SPWM signals with complementary dead zones are generated through the first and second dead zone generating units to drive the subsequent circuit.

[0076] In a specific embodiment, the input original signal is a modulated signal with amplitude and phase changing simultaneously, the carrier frequency is 500kHz, the phase changes periodically, and the envelope is a signal containing two frequencies of 5kHz and 10kHz superimposed, such as Figure 7 When a signal is input into the modulator disclosed in the embodiment of the present application, two signals will be obtained respectively, one signal carries the envelope information of the original signal, and the other signal carries the phase and carrier frequency information of the original signal. Among them, the signal with envelope information is modulated into an SPWM signal, and its modulation frequency is 500kHz, as shown in FIG. Figure 8 The signal with phase and carrier frequency information is modulated into a PWM signal, and its fundamental frequency and phase remain unchanged before modulation, as shown in Fig. 9 shown.

[0077] The above shows and describes the basic principles, main features and advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. An intermediate frequency digital power amplifier modulator for amplitude and phase modulation, characterized in that: include: High-speed ADC: used to convert analog signals into parallel digital signals; Data buffer module: used to buffer the parallel digital signals collected by the high-speed ADC and perform sampling rate conversion; Envelope elimination module: used to eliminate the envelope change of the analog signal of the previous communication system collected by the high-speed ADC, and obtain a square wave signal with a constant envelope, and the square wave signal only carries frequency and phase information; Phase lag module: used to control and adjust the phase lag of the square wave signal with only frequency and phase information, and output a PWM drive signal for driving the subsequent circuit; Envelope extraction module: used to extract the envelope signal of the analog signal of the previous communication system collected by the high-speed ADC; SPWM modulation module: used to perform SPWM modulation on the envelope signal extracted by the envelope extraction module, and output two SPWM drive signals with dead zone complementation; The PWM driving signal output by the phase lag module for driving the subsequent circuit is consistent in phase with the envelope signal output by the subsequent circuit driven by the SPWM modulation module; The data buffer module, envelope elimination module, phase lag module, envelope extraction module and SPWM modulation module are arranged inside an FPGA, the high-speed ADC input end is connected to the front-stage communication system signal source, the high-speed ADC output end is connected to the data buffer module input end, the data buffer module output end is respectively connected to the envelope elimination module input end and the envelope extraction module input end, the envelope elimination module output end is connected to the phase lag module input end, the phase lag module output end is used as the PWM driving signal of the rear-stage circuit, the envelope extraction module output end is connected to the SPWM modulation module input end, and the SPWM modulation module output end is used as the SPWM driving signal of the rear-stage circuit.

2. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 1, characterized in that: The envelope elimination module includes a first input buffer register, a first symbol decision module, a first data selector, a first register and a second register. The input end of the first input buffer register is connected to the output end of the data buffer module, the highest bit reg11 output end of the first input buffer register is connected to the input end of the first symbol decision module, the output end of the first symbol decision module is connected to the control end of the first data selector, the input end of the first data selector is respectively connected to the output end of the first register storing a logic signal 0 and the output end of the second register storing a logic signal 1, and the output end of the first data selector is output as a PWM modulation signal for envelope elimination.

3. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 2, characterized in that: The phase lag module includes a phase lag controller, an inverter, a read address adder, a write address controller, a write address accumulator, a phase lag buffer array, an input data buffer module and an output data buffer module. The output end of the phase lag controller is connected to the input end of the inverter, the output end of the inverter is connected to the input end of the read address adder, the output end of the read address adder is connected to the read address control input end of the phase lag buffer array, the output end of the write address controller is connected to the input end of the write address accumulator, the output end of the write address accumulator is respectively connected to the input end of the write address accumulator, the input end of the read address adder and the phase lag buffer array, the input end of the input data buffer module is connected to the PWM modulation signal output by the first data selector, the output end of the input data buffer module is connected to the read data output end of the phase lag buffer array, and the output end of the output data buffer module is output as a PWM modulation signal with phase lag.

4. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 3, characterized in that: The phase lag module uses a buffer array phase lag method to buffer the PWM modulation signal. The phase lag accuracy of the first level is 1000, where f is the system clock, and the fine phase lag adjustment of more than one hundredth of the PWM modulation signal period can be achieved.

5. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 4, characterized in that: The buffer array phase lag method comprises the following steps: A RAM with a depth of n bits and a width of 1 inside the FPGA is used as a phase lag buffer array. The write address controller distributes the clock so that the write address accumulator accumulates at the frequency of the system clock f, and each accumulation is 1 bit. The output w_addr of the write address accumulator is used to control the write data address of the phase lag buffer array. The PWM modulation signal generated by the network elimination module is input through the data buffer module, and the output of the data buffer module is stored in the phase lag buffer array corresponding to the output address of the write address accumulator. The data interval time between adjacent addresses is The lag time is set to t, and the phase lag controller converts the lag time t into the address difference k according to the system clock f. The difference k is inverted by the inverter and output -k. The output -k of the inverter and the output w_addr of the write address accumulator are added through the read address adder to obtain the read address adder output r_addr, wherein r_addr=w_addr-k. The output data buffer module reads data from the corresponding address of the phase lag buffer array according to the read address adder output r_addr, and outputs it as a PWM signal with phase lag.

6. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 5, characterized in that: The envelope extraction module includes a second input buffer register, a second symbol decision module, a symbol flip module, a second data selector and an FIR low-pass filter. The input end of the second input buffer register is connected to the output end of the output data buffer module, the output end of the second input buffer register (the highest bit reg11) is connected to the input end of the second symbol decision module, the lowest bit to the second highest bit reg0-reg10 of the input buffer register are connected to the input end of the second data selector and the input end of the symbol flip module, the output end of the second symbol decision module is connected to the control end of the second data selector, the output end of the second data selector is connected to the input end of the FIR low-pass filter, and the output end of the FIR low-pass filter outputs an envelope signal.

7. The intermediate frequency digital power amplifier modulator for amplitude and phase modulation according to claim 6, characterized in that: The SPWM modulation module includes a triangular wave generating unit, a first comparator, a second comparator, a first dead zone generating unit and a second dead zone generating unit. The output end of the triangular wave generating unit is respectively connected to the negative input end of the first comparator and the positive input end of the second comparator. The positive input end of the first comparator and the negative input end of the second comparator are both connected to the output end of the FIR low-pass filter. The output end of the first comparator is connected to the input end of the first dead zone generating unit, and the output end of the second comparator is connected to the input end of the second dead zone generating unit. The output end of the first dead zone generating unit outputs an N_SPWM signal, and the output end of the second dead zone generating unit outputs a P_SPWM signal. The N_SPWM signal and the P_SPWM signal are two signals with complementary dead zones.

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