Display device and method for manufacturing same

Abstract

A display device and a method for manufacturing the same are provided. The display device includes: a first pixel electrode disposed on a substrate; a sacrificial pattern disposed on an edge of the first pixel electrode; a pixel defining film including a body portion disposed on the substrate and a protruding portion disposed on the sacrificial pattern and exposing the first pixel electrode; a first light emitting layer disposed on the first pixel electrode; a first common electrode disposed on the first light emitting layer; a first bank layer disposed on the pixel defining film; and a second bank layer disposed on the first bank layer and having a side surface that protrudes more than a side surface of the first bank layer. A first side surface of the first sacrificial pattern is aligned with a side surface of the protruding portion of the pixel defining film or protrudes much than the side surface of the protruding portion of the pixel defining film.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0081614, filed on Jun. 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0003] As the information society develops, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. In such a flat panel display device, since each of the pixels of the display panel includes a light emitting element that can emit light by itself, the light emitting display device can display an image without a backlight unit that provides light to the display panel.

[0004] The display device has been applied to a glasses-type device for providing virtual reality and augmented reality. The display device is implemented in a very small size of 2 inches or less to be applied to the glasses-type device, but should have a high pixel integration so as to be implemented with a high resolution. For example, the display device may have a high pixel integration of 1000 pixels per inch (PPI) or more.

[0005] When a display device is implemented in a very small size but has a high pixel integration as described above, the area of ​​an emission region in which a light emitting element is provided is reduced, and thus it is difficult to implement light emitting elements separated from each other for each emission region through a mask process. Summary of the invention

[0006] Aspects of the present disclosure provide a display device capable of forming light emitting elements separated from each other for each emission region without a mask process.

[0007] Aspects of the present disclosure also provide a display device that improves reliability of a display panel of the display device by preventing a void space from occurring at a boundary between a pixel electrode, a sacrificial pattern, and a pixel defining film.

[0008] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to a disclosed embodiment, a display device includes: a first pixel electrode, which is arranged on a substrate; a first sacrificial pattern, which is arranged on an edge of the first pixel electrode; a pixel defining film, including a main portion arranged on the substrate and a protruding portion arranged on the first sacrificial pattern and exposing the first pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode; a first common electrode, which is arranged on the first light-emitting layer; a first embankment layer, which is arranged on the pixel defining film; and a second embankment layer, which is arranged on the first embankment layer and has a side surface that protrudes much more than the side surface of the first embankment layer, wherein the first side surface of the first sacrificial pattern is aligned with the side surface of the protruding portion of the pixel defining film, or protrudes much more than the side surface of the protruding portion of the pixel defining film.

[0010] The first sacrificial pattern may include molybdenum (Mo).

[0011] The first sacrificial pattern may have a second side surface opposite to the first side surface, and the pixel defining film may be disposed on the second side surface of the first sacrificial pattern.

[0012] A side surface of the protruding portion of the pixel defining film may protrude more than a side surface of the second bank layer.

[0013] The first sacrificial pattern may have a thickness of 50 angstroms (Å) to 600 Å.

[0014] An upper surface of the first sacrificial pattern may contact the protruding portion of the pixel defining film, and a lower surface of the first sacrificial pattern may contact the first pixel electrode.

[0015] The first pixel electrode may be a multi-layer film made of indium tin oxide (ITO) / silver (Ag) / ITO, aluminum (Al) / titanium nitride (TiN), or Al / Ti.

[0016] An entire lower surface of the protruding portion of the pixel defining film may be in contact with the first sacrificial pattern.

[0017] The first common electrode and the first light emitting layer may contact the first bank layer, and a contact area between the first common electrode and the first bank layer may be greater than a contact area between the first light emitting layer and the first bank layer.

[0018] The first bank layer may include aluminum (Al), and the second bank layer may include titanium (Ti).

[0019] The display device may further include a first inorganic layer disposed on an upper surface of the first common electrode, a side surface of the first bank layer, and a lower surface and an upper surface of the second bank layer.

[0020] The display device may also include: a second pixel electrode, which is arranged on the substrate to be separated from the first pixel electrode; a second sacrificial pattern, which is arranged on the edge of the second pixel electrode; a second light-emitting layer, which is arranged on the second pixel electrode; a second common electrode, which is arranged on the second light-emitting layer and is separated from the first common electrode; and a second inorganic layer, which is arranged on the upper surface of the second common electrode, the side surface of the first embankment layer, and the lower surface and the upper surface of the second embankment layer, wherein the pixel defining film exposes the second pixel electrode, the first inorganic layer and the second inorganic layer are arranged to be separated from each other, and a portion of the second embankment layer is exposed in the space between the first inorganic layer and the second inorganic layer which are separated from each other.

[0021] The display device may also include: a first organic pattern, which is arranged on the second bank layer and includes the same material as the first light-emitting layer; and a first electrode pattern, which is arranged on the first organic pattern and includes the same material as the first common electrode, wherein the first light-emitting layer and the first organic pattern are separated from each other, and the first common electrode and the first electrode pattern are separated from each other.

[0022] According to a disclosed embodiment, a display device includes: a first pixel electrode, which is arranged on a substrate; a sacrificial pattern, which is arranged on the first pixel electrode; a pixel defining film, which is arranged on the substrate and includes a main part and a protruding part protruding from the main part; a first light-emitting layer, which is arranged on the first pixel electrode; a first common electrode, which is arranged on the first light-emitting layer; a first embankment layer, which is arranged on the pixel defining film; and a second embankment layer, which is arranged on the first embankment layer and has a side surface that protrudes much more than a side surface of the first embankment layer, wherein the protruding part of the pixel defining film is arranged on the first pixel electrode and is spaced apart from the upper surface of the first pixel electrode, and the space between the protruding part of the pixel defining film and the first pixel electrode is filled with the sacrificial pattern.

[0023] A lower surface of the protruding portion of the pixel defining film may not contact the first light emitting layer.

[0024] An upper surface of the sacrificial pattern may contact the protruding portion of the pixel defining film, and a lower surface of the sacrificial pattern may contact the first pixel electrode.

[0025] According to the disclosed embodiments, a method for manufacturing a display device includes the following steps: forming a plurality of pixel electrodes and a sacrificial layer on a substrate, the plurality of pixel electrodes being spaced apart from each other, and the sacrificial layer being disposed on the pixel electrodes; forming a pixel defining material layer on the sacrificial layer, forming a first embankment material layer on the pixel defining material layer, and forming a second embankment material layer on the first embankment material layer; forming a hole exposing a first pixel electrode among a plurality of pixel electrodes by etching the pixel defining material layer, the first embankment material layer, and the second embankment material layer; etching a portion of the sacrificial layer exposed by the hole and a side surface of the first embankment material layer exposed by the hole so as to expose a portion of a lower surface of the second embankment material layer; forming a first light emitting layer on the first pixel electrode, and forming a first common electrode on the first light emitting layer; and forming a first inorganic material layer on the first common electrode.

[0026] The step of forming multiple pixel electrodes and a sacrificial layer on a substrate may include: forming a metal electrode layer on the substrate and forming a sacrificial material layer on the metal electrode layer; forming a mask pattern on the sacrificial material layer and etching portions of the sacrificial material layer and the metal electrode layer not covered by the mask pattern; and heat treating the remaining portions of the sacrificial material layer and the metal electrode layer covered by the mask pattern.

[0027] Etching the portion of the sacrificial layer exposed through the hole and the side surface of the first bank material layer exposed through the hole may include performing a wet etching process using an etchant including phosphorus (P), fluorine (F), or nitrogen (N).

[0028] In the step of forming a first light-emitting layer on the first pixel electrode and in the step of forming a first common electrode on the first light-emitting layer, a first organic pattern material layer separated from the first light-emitting layer can be formed on the second embankment material layer, and a first electrode pattern material layer separated from the first common electrode can be formed on the first organic pattern material layer, and in the step of forming a first inorganic material layer on the first common electrode, a single first inorganic material layer is formed to cover both the first common electrode and the first electrode pattern material layer.

[0029] Using a display device according to an embodiment and a method for manufacturing the display device, the display device includes a sacrificial pattern having a side surface that is aligned with or protrudes much more than a side surface of a pixel defining film, thereby preventing the occurrence of unevenness in the display device and improving the reliability of the display device.

[0030] In addition, with the display device and the method for manufacturing the display device according to the embodiment, by simultaneously performing the step of forming the undercut structure of the first bank layer and the step of etching the sacrificial layer, the process can be simplified.

[0031] The effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is a perspective view showing a display device according to an embodiment; Figure 2 Viewed from the side Figure 1 A cross-sectional view of a display device; Figure 3 is a plan view showing the arrangement of a light emitting element, a sacrificial pattern, a pixel defining film, a trace pattern, and a second bank layer of a display device according to an embodiment; Figure 4 is a cross-sectional view showing a portion of a display device according to an embodiment; Figure 5 It is shown Figure 4 An enlarged view of a first emission region (specifically, region A1); Figure 6 is an enlarged view showing a first emission region according to another embodiment; Figure 7 is a cross-sectional view of a case where the sacrificial pattern is recessed compared to the pixel definition film; Figure 8 is a flowchart showing a process for manufacturing a display device according to an embodiment; and Figures 9 to 16 are cross-sectional views sequentially illustrating processes for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0033] The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0034] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0035] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0036] The terms used here are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "the (described)" and "at least one (kind / person)" do not represent the limitation of quantity, and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as "one" or "one (kind / person)" of limitation. "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. It will also be understood that when used in this specification, the term "including" and / or "comprising" indicates the presence of the features, regions, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups. Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0037] Figure 1 is a perspective view showing a display device according to an embodiment.

[0038] Reference Figure 1 The display device 10 according to the embodiment may be included in an electronic device to provide a picture displayed on the electronic device. The electronic device may refer to all electronic devices that provide a display screen. For example, a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a video camera, etc. that provide a display screen may be included in the electronic device.

[0039] The shape of the display device 10 may be modified variously. For example, the display device 10 may have a shape similar to a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a circle with a curvature, but is not limited thereto, and may also be a right angle in another embodiment. The shape of the display device 10 in a plan view is not limited to a rectangular shape, and may also be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. As used herein, a "plan view" is a view in a third direction DR3.

[0040] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see Figure 2 ).

[0041] The display panel 100 may include a main area MA and a sub area SBA.

[0042] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining film defining an emission area or an opening area, and a self-luminous element.

[0043] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0044] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be provided in the display area DA. Each of the plurality of pixels may be defined as a minimum unit for emitting light, and each of the self-luminous elements described above may be each of the pixels. A plurality of scan lines may supply a scan signal received from a scan driver to a plurality of pixels. A plurality of data lines may supply a data voltage received from a display driver 200 to a plurality of pixels. A plurality of power lines may supply a power supply voltage received from a display driver 200 to a plurality of pixels.

[0045] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a scan driver supplying a scan signal to a scan line and a fan-out line connecting the display driver 200 and the display area DA to each other.

[0046] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material that may be bent, folded, and curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include a display driver 200 and a pad (also referred to as a "soldering pad" or "pad") portion connected to the circuit board 300. In another embodiment, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be disposed in the non-display area NDA.

[0047] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to data lines. The display driver 200 may supply power voltages to power lines, and supply scan control signals to scan drivers. The display driver 200 may be formed as an integrated circuit (IC), and may be mounted on the display panel 100 in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner. As an example, the display driver 200 may be disposed in a sub-region SBA, and may be overlapped with the main region MA in a thickness direction (third direction DR3) by bending the sub-region SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0048] The circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0049] Figure 2 Viewed from the side Figure 1 A cross-sectional view of a display device.

[0050] Reference Figure 2 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0051] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, and rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0052] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a scan line, a data line, a power line, a scan control line, a fan-out line connecting the display driver 200 and the data line to each other, and a lead connecting the display driver 200 and the pad portion to each other. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0053] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, the scan line, the data line, and the power line of each pixel of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0054] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining film defining a pixel, each light emitting element including a first electrode, a second electrode and a light emitting layer to emit light. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0055] In an embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light emitting layer to emit light.

[0056] In another embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0057] The thin film encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0058] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters, each corresponding to a plurality of emission regions. Each of the color filters may selectively transmit light of a specific wavelength therethrough, and block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light introduced from outside the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer CFL may prevent color distortion due to reflection of external light.

[0059] Since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0060] In some embodiments, the display device 10 may further include an optical device. The optical device may emit or receive light in infrared, ultraviolet, and visible light bands. For example, the optical device may be an optical sensor (such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor) that senses light incident on the display device 10.

[0061] Figure 3 is a plan view showing a part of a display device according to an embodiment. Figure 3 is a plan view showing the arrangement of the light emitting elements ED1 , ED2 , and ED3 , the sacrificial pattern SFP, the pixel defining film PDL, the trace patterns TRP1 , TRP2 , and TRP3 , and the second bank layer BN2 in the display area DA of the display device 10 .

[0062] Reference Figure 3 , the second bank layer BN2 may cover the display area DA but expose part of the display area DA. An opening may be formed in the exposed area not covered by the second bank layer BN2, and the pixel defining film PDL, the sacrificial pattern SFP, and the corresponding light emitting elements among the light emitting elements ED1, ED2, and ED3 may all be disposed within the opening. The light emitting elements ED1, ED2, and ED3 may be disposed at the center of the opening, the sacrificial pattern SFP may be disposed along the outline of the light emitting elements ED1, ED2, and ED3, and the pixel defining film PDL may be defined along the outline of the sacrificial pattern SFP. Figure 3 , the case where the sacrificial pattern SFP has a side surface that protrudes much more than the side surface of the pixel defining film PDL has been shown, and the sacrificial pattern SFP has been shown as being between the light emitting elements ED1, ED2, and ED3 and the pixel defining film PDL in a plan view. When the side surface of the sacrificial pattern SFP is aligned with the side surface of the pixel defining film PDL, the boundary of the sacrificial pattern SFP in a plan view may coincide with the boundary of the pixel defining film PDL.

[0063] The trace patterns TRP1, TRP2, and TRP3 may be disposed on the second bank layer BN2 along the contour of the exposed area not covered by the second bank layer BN2. Figure 3 It has been shown that the exposed area not covered by the second bank layer BN2 has a circular shape, but the exposed area may have a polygonal shape such as a triangular shape, a quadrilateral shape, or a hexagonal shape, and the shapes of the trace patterns TRP1, TRP2, and TRP3 set along the contour of the exposed area may also be changed. The trace patterns TRP1, TRP2, and TRP3 may be set at a level above the second bank layer BN2, and the pixel defining film PDL, the sacrificial pattern SFP, and the light emitting elements ED1, ED2, and ED3 may be set at a level below the second bank layer BN2.

[0064] The exposed regions not covered by the second bank layer BN2 may be disposed to be spaced apart from each other in the first direction DR1, and may also be disposed to be spaced apart from each other in the second direction DR2. The shape and arrangement of the exposed regions not covered by the second bank layer BN2 are not limited to Figure 3 , and the exposed areas not covered by the second bank layer BN2 can be PENTILE ® Type settings.

[0065] Figure 4 is a cross-sectional view showing a portion of a display device according to an embodiment. Specifically, Figure 4 It is along Figure 3 A sectional view taken along the line BB', and showing the Figure 3 The organic encapsulation film TFE2, the second inorganic encapsulation film TFE3, the color filters CF1, CF2 and CF3, the light blocking layer BM and the overcoat layer OC are arranged on the plan view of FIG. Figure 4 The cross sections of the substrate SUB, the thin film transistor layer TFTL, the light emitting element layer EML, the thin film encapsulation layer TFEL, and the color filter layer CFL are shown.

[0066] The thin film transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0067] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked.

[0068] The bottom metal layer BML may be disposed on the first buffer layer BF1. For example, the bottom metal layer BML may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0069] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked.

[0070] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0071] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the bottom metal layer BML in a plan view and overlap the gate electrode GE in a thickness direction (e.g., a third direction DR3), and may be insulated from the gate electrode GE by the gate insulating layer GI. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may become a conductor to form a source electrode SE and a drain electrode DE.

[0072] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in a thickness direction (eg, the third direction DR3) with the gate insulating layer GI interposed therebetween.

[0073] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 penetrates.

[0074] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0075] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1 . The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction (eg, the third direction DR3 ). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0076] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0077] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0078] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 penetrates.

[0079] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED to each other. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0080] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED penetrate.

[0081] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED, a pixel defining layer PDL, a cap layer CAP, and a bank structure BNS (see Figure 5 ). The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0082] Figure 5 It is shown Figure 4 An enlarged view of the first emission area (specifically, area A1). Figure 6 is an enlarged view showing a first emission region (specifically, region A1_1 ) according to another embodiment. Figure 7 This is a cross-sectional view showing a case where the sacrificial pattern is recessed relative to the pixel defining film.

[0083] Apart from Figure 4 In addition, refer to Figure 5 and Figure 6, the display device 10 may include a plurality of emission areas EA1, EA2, and EA3 disposed in the display area DA. The emission areas EA1, EA2, and EA3 may include areas where light is emitted from the light emitting elements ED1, ED2, and ED3 and passes through the color filter layer CFL in the third direction DR3. The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that are spaced apart from each other and emit light of different colors.

[0084] In an embodiment, the areas or sizes of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be the same as each other. For example, in the display device 10, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have the same area. However, the present disclosure is not limited to this. In the display device 10, in another embodiment, the areas or sizes of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different from each other. For example, the area of ​​the second emission area EA2 may be larger than the areas of the first emission area EA1 and the third emission area EA3, and the area of ​​the third emission area EA3 may be larger than the area of ​​the first emission area EA1. The intensity of light emitted from the emission areas EA1, EA2, and EA3 may be changed according to the areas of the emission areas EA1, EA2, and EA3, and the color sense of the picture displayed on the display device 10 can be controlled by adjusting the areas of the emission areas EA1, EA2, and EA3. Figure 4 In the embodiment of FIG. 5 , it has been illustrated that the areas of the emission areas EA1 , EA2 , and EA3 are the same as each other, but the present disclosure is not limited thereto.

[0085] In the display device 10, one first emission area EA1, one second emission area EA2, and one third emission area EA3 disposed adjacent to each other may form one pixel group. One pixel group may include emission areas EA1, EA2, and EA3 that emit light of different colors to express a white grayscale. However, the present disclosure is not limited thereto, and the combination of emission areas EA1, EA2, and EA3 constituting one pixel group may be modified differently according to the arrangement of the emission areas EA1, EA2, and EA3, the color of the light emitted by the emission areas EA1, EA2, and EA3, and the like.

[0086] A plurality of openings formed in the embankment structure BNS of the light emitting element layer EML are defined along the boundary of the embankment structure BNS. The first embankment layer BN1 and the second embankment layer BN2 of the embankment structure BNS may have a shape in which they surround the emission regions EA1, EA2, and EA3. The openings may include the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0087] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 disposed in a first emission area EA1, a second light emitting element ED2 disposed in a second emission area EA2, and a third light emitting element ED3 disposed in a third emission area EA3.

[0088] The light-emitting elements ED1, ED2 and ED3 may include pixel electrodes AE1, AE2 and AE3, light-emitting layers EL1, EL2 and EL3, and common electrodes CE1, CE2 and CE3, respectively, and the light-emitting elements ED1, ED2 and ED3 disposed in different emission areas EA1, EA2 and EA3 may emit light of different colors according to the materials of the light-emitting layers EL1, EL2 and EL3, respectively. For example, the first light-emitting element ED1 disposed in the first emission area EA1 may emit a first light (which is red light) having a peak wavelength in the range of 610nm to 650nm, the second light-emitting element ED2 disposed in the second emission area EA2 may emit a second light (which is green light) having a peak wavelength in the range of 510nm to 550nm, and the third light-emitting element ED3 disposed in the third emission area EA3 may emit a third light (which is blue light) having a peak wavelength in the range of 440nm to 480nm. The first emission area EA1, the second emission area EA2, and the third emission area EA3 constituting one pixel may include light emitting elements ED1, ED2, and ED3 that emit light of different colors to express a white grayscale. Optionally, the light emitting layers EL1, EL2, and EL3 may include two or more materials that emit light of different colors, so that one light emitting layer may emit mixed light. For example, the light emitting layers EL1, EL2, and EL3 may include both a red light emitting material and a green light emitting material to emit yellow light, or include all of a red light emitting material, a green light emitting material, and a blue light emitting material to emit white light.

[0089] The pixel electrodes AE1, AE2 and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2 and AE3 may be disposed in a plurality of emission areas EA1, EA2 and EA3, respectively. The pixel electrodes AE1, AE2 and AE3 may include a first pixel electrode AE1 disposed in a first emission area EA1, a second pixel electrode AE2 disposed in a second emission area EA2, and a third pixel electrode AE3 disposed in a third emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3 may be disposed on the second passivation layer PAS2 to be spaced apart from each other. Figure 4It has been shown that the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3 are spaced apart from each other in the first direction DR1, but the present disclosure is not limited thereto, and in another embodiment, the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3 may be spaced apart from each other in any direction within a plane formed by the first direction DR1 and the second direction DR2.

[0090] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. The edges of the pixel electrodes AE1, AE2, and AE3 spaced apart from each other are covered by a pixel definition film PDL so that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be insulated from each other.

[0091] The pixel electrodes AE1, AE2 and AE3 may include a transparent electrode material and / or a conductive metal material. The conductive metal material may be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti) and titanium nitride (TiN). The transparent electrode material may be one or more of indium tin oxide (ITO), indium zinc oxide (IZO) and indium tin zinc oxide (ITZO).

[0092] Each of the pixel electrodes AE1, AE2, and AE3 may have a multi-layer structure. Each of the pixel electrodes AE1, AE2, and AE3 may include a transparent electrode layer and a metal layer, or include different metal layers. The upper electrode layer of each of the pixel electrodes AE1, AE2, and AE3 adjacent to each of the light emitting layers EL1, EL2, and EL3 may be crystalline and may be formed with respect to a sacrificial layer SFL (see FIG. 1 ) which will be described later in wet etching. Fig.14 ) and the sacrificial pattern SFP are selective. In an embodiment, the pixel electrodes AE1, AE2, and AE3 may be a multilayer film made of ITO / Ag / ITO, Al / TiN, or Al / Ti, and ITO, TiN, or Ti may be a material of an upper electrode layer adjacent to each of the light emitting layers EL1, EL2, and EL3.

[0093] The pixel defining film PDL may be disposed on the second passivation layer PAS2 and the pixel electrodes AE1, AE2, and AE3. The pixel defining film PDL may be disposed entirely on the second passivation layer PAS2, but may expose portions of the upper surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. For example, the pixel defining film PDL may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be disposed directly on the first pixel electrode AE1.

[0094] The pixel defining film PDL may include a body portion PDL_B and a protruding portion PDL_P protruding from the body portion PDL_B toward each of the emission areas EA1, EA2, and EA3. The protruding portion PDL_P may be a portion protruding from a side surface of the body portion PDL_B toward each of the emission areas EA1, EA2, and EA3. The protruding portion PDL_P of the pixel defining film PDL may be disposed on a sacrificial pattern SFP to be described later, and the body portion PDL_B of the pixel defining film PDL may contact the second passivation layer PAS2.

[0095] The pixel defining layer PDL may include an inorganic insulating material and may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0096] The sacrificial pattern SFP may be disposed on the edge of the pixel electrodes AE1, AE2, and AE3. Specifically, the protruding portion PDL_P of the pixel defining film PDL and the pixel electrodes AE1, AE2, and AE3 may be spaced apart from each other, and the sacrificial pattern SFP may be disposed in the space between the protruding portion PDL_P of the pixel defining film PDL and the pixel electrodes AE1, AE2, and AE3, respectively. In an embodiment, the lower surface of the protruding portion PDL_P may directly contact the upper surface of the sacrificial pattern SFP, and may not contact the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3. When the pixel electrodes AE1, AE2, and AE3 have a circular shape, the sacrificial pattern SFP may have a ring shape.

[0097] The sacrificial pattern SFP may have a first side surface SFP_S1 adjacent to each of the emission areas EA1, EA2, and EA3 and a second side surface SFP_S2 opposite to the first side surface SFP_S1. The first side surface SFP_S1 of the sacrificial pattern SFP may be aligned with the side surface PDL_S of the protruding portion PDL_P of the pixel defining film PDL, or protrude more than the side surface PDL_S of the protruding portion PDL_P toward each of the emission areas EA1, EA2, and EA3. Figure 5 Regarding an embodiment in which the first side surface SFP_S1 of the sacrificial pattern SFP protrudes more toward each of the emission areas EA1, EA2, and EA3 than the side surface PDL_S of the protrusion portion PDL_P, Figure 6 Concerning an embodiment in which the first side surface SFP_S1 of the sacrificial pattern SFP is aligned with the side surface PDL_S of the protrusion portion PDL_P.

[0098] When Figure 7When the sacrificial pattern SFP shown in FIG. 1 has a side surface that is much more recessed than the side surface PDL_S of the protruding portion PDL_P of the pixel defining film PDL to have an undercut structure, the light emitting layers EL1, EL2, and EL3 may not be sufficiently deposited in the space between the protruding portion PDL_P of the pixel defining film PDL and the pixel electrodes AE1, AE2, and AE3. In a subsequent process after deposition, a void space may be formed at the boundary between the pixel defining film PDL, the sacrificial pattern SFP, and the pixel electrodes AE1, AE2, and AE3. The void space may cause unevenness (mura) or lighting defects on the display panel. As the driving time increases, the unevenness on the display panel may become larger, and the reliability of the display panel may deteriorate.

[0099] When the sacrificial pattern SFP does not have an undercut structure and has a first side surface SFP_S1 aligned with or protruding from the side surface PDL_S of the protruding portion PDL_P of the pixel defining film PDL, the light emitting layers EL1, EL2, and EL3 may be smoothly deposited at the boundaries between the pixel defining film PDL, the sacrificial pattern SFP, and the pixel electrodes AE1, AE2, and AE3. A void space due to the undercut structure may not be generated, and the reliability of the display panel may be improved.

[0100] An upper surface of the sacrificial pattern SFP may contact the protruding portion PDL_P of the pixel defining film PDL, and a lower surface of the sacrificial pattern SFP may contact the pixel electrodes AE1 , AE2 , and AE3 .

[0101] The protruding portion PDL_P of the pixel defining film PDL is disposed on the sacrificial pattern SFP, and the width of the protruding portion PDL_P of the pixel defining film PDL may be the distance from the second side surface SFP_S2 of the sacrificial pattern SFP to the side surface PDL_S of the protruding portion PDL_P of the pixel defining film PDL. The width of the sacrificial pattern SFP may be the distance between the first side surface SFP_S1 and the second side surface SFP_S2 of the sacrificial pattern SFP. Figures 4 to 6The case where the side surface PDL_S of the pixel defining film PDL and the first side surface SFP_S1 of the sacrificial pattern SFP are perpendicular to the substrate SUB has been shown, but when these side surfaces are inclined or have a circular shape, the length on the boundary surface between the sacrificial pattern SFP and the protruding portion PDL_P of the pixel defining film PDL may be considered. The width of the sacrificial pattern SFP may be greater than or equal to the width of the protruding portion PDL_P of the pixel defining film PDL. Therefore, the entire lower surface of the protruding portion PDL_P of the pixel defining film PDL may be in contact with the sacrificial pattern SFP, and may not be in contact with the light emitting layers EL1, EL2, and EL3. The light emitting layers EL1, EL2, and EL3 may not be disposed between the protruding portion PDL_P of the pixel defining film PDL and the pixel electrodes AE1, AE2, and AE3.

[0102] The sacrificial pattern SFP may include molybdenum (Mo). Molybdenum (Mo) included in the sacrificial pattern SFP may maintain an amorphous property even after being heat-treated, and thus may protect the pixel electrodes AE1, AE2, and AE3 disposed under the sacrificial pattern SFP in an etching process. In an etching process for forming the undercut structure of the first bank layer BN1, molybdenum (Mo) may also be etched, and thus a separate etching process for forming only the sacrificial pattern SFP may be omitted.

[0103] In an embodiment, the thickness of the sacrificial pattern SFP may be 50 angstroms (Å) to 600 Å measured in the third direction DR3. When the thickness of the sacrificial pattern SFP is less than 50 Å, the sacrificial layer SFL (see Fig.10 ) It is difficult to protect the pixel electrodes AE1, AE2 and AE3 in the etching process. When the thickness of the sacrificial pattern SFP is greater than 600Å, it may be difficult to form an undercut structure of the first bank layer BN1.

[0104] The number of the sacrificial pattern SFP may be plural, and the sacrificial patterns SFP may be disposed on the pixel electrodes AE1, AE2, and AE3, respectively. The sacrificial patterns SFP may be spaced apart from each other like the pixel electrodes AE1, AE2, and AE3, respectively, and may be insulated from each other by the pixel defining film PDL. The pixel defining film PDL may be disposed on the second side surface SFP_S2 of the sacrificial pattern SFP. The second side surface SFP_S2 of the sacrificial pattern SFP may contact the main body portion PDL_B of the pixel defining film PDL.

[0105] The light-emitting layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3, respectively. The light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers made of an organic material, and may be formed on the pixel electrodes AE1, AE2, and AE3, respectively, by a deposition process. When the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layers EL1, EL2, and EL3, respectively, through the hole transport layer and the electron transport layer, and may be recombined with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0106] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, each of which is disposed in different emission areas EA1, EA2, and EA3. The first light-emitting layer EL1 may be disposed on the first pixel electrode AE1 in the first emission area EA1, the second light-emitting layer EL2 may be disposed on the second pixel electrode AE2 in the second emission area EA2, and the third light-emitting layer EL3 may be disposed on the third pixel electrode AE3 in the third emission area EA3. The plurality of light-emitting layers EL1, EL2, and EL3 may emit light of different colors, respectively, or one light-emitting layer EL1, EL2, or EL3 may emit mixed light. In an embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light. In another embodiment, the first light-emitting layer EL1 may emit yellow light as a mixture of red light and green light, and the second light-emitting layer EL2 may emit blue light. In yet another embodiment, the first light-emitting layer EL1 may emit white light as a mixture of red light, green light, and blue light.

[0107] The light emitting layers EL1, EL2, and EL3 may be disposed on an upper surface of the pixel defining film PDL. The light emitting layers EL1, EL2, and EL3 may be disposed on a protruding portion PDL_P of the pixel defining film PDL.

[0108] The common electrodes CE1, CE2, and CE3 may be disposed on the light emitting layers EL1, EL2, and EL3, respectively. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material to emit light generated from the light emitting layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low potential voltage. When the pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, so that the light emitting layers EL1, EL2, and EL3 may emit light.

[0109] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3, each of which is disposed in different emission areas EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light emitting layer EL1 in the first emission area EA1, the second common electrode CE2 may be disposed on the second light emitting layer EL2 in the second emission area EA2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3 in the third emission area EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other.

[0110] The capping layer CAP may be disposed on the common electrodes CE1, CE2, and CE3. The capping layer CAP may include an organic or inorganic insulating material and cover a pattern disposed on the light emitting elements ED1, ED2, and ED3. The capping layer CAP may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, the capping layer CAP may include an organic material (such as α-NPD, NPB, TPD, m-MTDATA, Alq 3 , LiF and / or CuPc) or an inorganic material (such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride).

[0111] The display device 10 may include a plurality of embankment structures BNS disposed on the pixel defining film PDL. The embankment structure BNS may have a structure in which embankment layers BN1 and BN2 including different materials are sequentially stacked, may include a plurality of openings including emission areas EA1, EA2, and EA3, and may be disposed to overlap with a light blocking layer BM to be described later in a plan view. The light emitting elements ED1, ED2, and ED3 of the display device 10 may be disposed to overlap with the openings of the embankment structure BNS in a plan view.

[0112] The bank structure BNS may include a first bank layer BN1 disposed on the pixel defining layer PDL and a second bank layer BN2 disposed on the first bank layer BN1.

[0113] The first bank layer BN1 may be disposed on the pixel defining film PDL. A side surface of the first bank layer BN1 may be more recessed than a side surface of the pixel defining film PDL in a direction opposite to the direction toward the emission areas EA1, EA2, and EA3. A side surface of the first bank layer BN1 may be more recessed than a side surface of a second bank layer BN2 to be described later in a direction opposite to the direction toward the emission areas EA1, EA2, and EA3.

[0114] According to an embodiment, the first bank layer BN1 may include a metal material. The metal material of the first bank layer BN1 may be any material that is removed together with the second bank layer BN2 by dry etching, but can form an undercut structure by showing an etching rate different from that of the second bank layer BN2 relative to wet etching by an alkali etchant. In an embodiment, the first bank layer BN1 may include aluminum (Al).

[0115] In an embodiment, the thickness of the first bank layer BN1 may be in the range of 4000 Å to 10000 Å. When the thickness of the first bank layer BN1 is within the above range, the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 spaced apart from each other may be formed by deposition and etching processes instead of a mask process.

[0116] According to an embodiment, the common electrodes CE1, CE2 and CE3 may be in direct contact with the side surface of the first bank layer BN1. The common electrodes CE1, CE2 and CE3 of different light emitting elements ED1, ED2 and ED3 may be in direct contact with the corresponding first bank layer BN1, respectively, and the first bank layer BN1 may include a metal material so that the common electrodes CE1, CE2 and CE3 may be electrically connected to each other through the first bank layer BN1.

[0117] The light-emitting layers EL1, EL2, and EL3 may be in direct contact with the side surface of the corresponding first bank layer BN1, respectively. The contact area between the common electrodes CE1, CE2, and CE3 and the side surface of the first bank layer BN1 may be greater than the contact area between the light-emitting layers EL1, EL2, and EL3 and the side surface of the first bank layer BN1. The contact area between the common electrodes CE1, CE2, and CE3 and the side surface of the corresponding first bank layer BN1 may be set to be greater than the contact area between the side surface of the first bank layer BN1 and the corresponding light-emitting layers EL1, EL2, and EL3, or the contact length between the common electrodes CE1, CE2, and CE3 and the side surface of the corresponding first bank layer BN1 (the length in the third direction DR3) may be set to be greater than the contact length between the side surface of the first bank layer BN1 and the corresponding light-emitting layers EL1, EL2, and EL3 (the length in the third direction DR3). Since the common electrodes CE1, CE2, and CE3 of the different light emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank layer BN1, it may be advantageous for the common electrodes CE1, CE2, and CE3 to contact the first bank layer BN1 in a larger area.

[0118] The second bank layer BN2 may be disposed on the first bank layer BN1. The second bank layer BN2 may include a main body portion BN2_M disposed on the first bank layer BN1 and a tip TIP, which is a region that protrudes much more than the first bank layer BN1. The tip TIP of the second bank layer BN2 may have a shape in which it surrounds the main body portion BN2_M. The side surface of the second bank layer BN2 may protrude much more toward the emission areas EA1, EA2, and EA3 than the side surface of the first bank layer BN1.

[0119] The side surfaces of the second bank layer BN2 have a shape in which they protrude more toward the emission areas EA1, EA2, and EA3 than the side surfaces of the first bank layer BN1, and thus, an undercut structure of the first bank layer BN1 may be formed under the tip TIP of the second bank layer BN2. The second bank layer BN2 includes the tip TIP, and thus, light emitting elements ED1, ED2, and ED3 separated from each other may be formed without a mask process.

[0120] Because the first bank layer BN1 and the second bank layer BN2 include different materials, the shape of the side surface of the first bank layer BN1 and the second bank layer BN2 may be a structure formed due to the difference in etching rates in the etching process. According to an embodiment, the second bank layer BN2 may include a material having an etching rate slower than that of the first bank layer BN1, and the first bank layer BN1 may be further etched in the etching process, so that an undercut may be formed under the tip TIP of the second bank layer BN2. In an embodiment, the first bank layer BN1 may include aluminum (Al), and the second bank layer BN2 may include titanium (Ti).

[0121] In the process for manufacturing the display device, in order to form a light-emitting layer of a light-emitting element for each of the emission regions, a mask process is required. The display device may require a structure for mounting a mask to perform the mask process, or may require an unnecessary large area of ​​a non-display area to control dispersion according to the mask process. When such a mask process according to an embodiment of the present disclosure is minimized, unnecessary components such as a structure for mounting a mask can be omitted from the display device 10, and the area of ​​the non-display area NDA for controlling dispersion can be minimized.

[0122] In the display device 10 according to the embodiment, the embankment structure BNS includes a tip TIP protruding toward the emission areas EA1, EA2, and EA3, and therefore, the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 can be formed by a deposition and etching process instead of a mask process. In addition, even by a deposition process, it is possible to form different layers separately in different emission areas EA1, EA2, and EA3. For example, even if the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 are formed by a deposition process without using a mask, the deposited materials can be disconnected from each other by the tip TIP of the second embankment layer BN2 using the embankment structure BNS inserted therebetween, rather than being connected to each other between the emission areas EA1, EA2, and EA3. It is possible to form different layers separately in different emission areas EA1, EA2, and EA3 by a process of forming a material for forming a specific layer on the entire surface of the display device 10, and then etching and removing the layer formed in the unnecessary area. In the display device 10, different light-emitting elements ED1, ED2, and ED3 can be formed for each of the emission areas EA1, EA2, and EA3 through deposition and etching processes without using a mask process, unnecessary components can be omitted from the display device 10, and the area of ​​the non-display area NDA can be minimized.

[0123] The tip TIP of the second bank layer BN2 may overlap with the common electrodes CE1, CE2, and CE3 in a third direction DR3 perpendicular to the substrate SUB. In addition, the tip TIP of the second bank layer BN2 may overlap with the light-emitting layers EL1, EL2, and EL3 in a third direction DR3 perpendicular to the substrate SUB. In addition, the tip TIP of the second bank layer BN2 may overlap with the pixel defining film PDL in a third direction DR3 perpendicular to the substrate SUB. The common electrodes CE1, CE2, and CE3 may be formed below the lower surface of the tip TIP of the second bank layer BN2. The maximum distance from the substrate SUB to each of the common electrodes CE1, CE2, and CE3 may be less than the maximum distance from the substrate SUB to the second bank layer BN2.

[0124] According to an embodiment, a side surface PDL_S of the protruding portion PDL_P of the pixel defining film PDL may protrude more than a side surface of the second bank layer BN2. A width at which the side surface PDL_S of the protruding portion PDL_P of the pixel defining film PDL protrudes more than a side surface of the first bank layer BN1 may be greater than a width at which the side surface of the second bank layer BN2 protrudes more than a side surface of the first bank layer BN1.

[0125] The display device 10 may include trace patterns TRP1, TRP2, and TRP3 as traces of a deposition process on the bank structure BNS. The trace patterns TRP1, TRP2, and TRP3 may include organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and a cap pattern CLP, respectively, and may have a shape in which they surround the outlines of the emission areas EA1, EA2, and EA3 on the second bank layer BN2.

[0126] Since the embankment structure BNS includes a tip TIP, such trace patterns TRP1, TRP2, and TRP3 may be traces formed when the deposition material is disconnected from the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer CAP in the emission areas EA1, EA2, and EA3, rather than being connected to the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer CAP in the emission areas EA1, EA2, and EA3. The light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer CAP may be formed in the openings, the organic patterns ELP1, ELP2, and ELP3, and the light-emitting layers EL1, EL2, and EL3 may be disconnected from each other by the tip TIP of the embankment structure BNS, the electrode patterns CEP1, CEP2, and CEP3, and the common electrodes CE1, CE2, and CE3 may be disconnected from each other by the tip TIP of the embankment structure BNS, and the capping pattern CLP and the capping layer CAP may be disconnected from each other by the tip TIP of the embankment structure BNS. The trace patterns TRP1, TRP2, and TRP3 may be formed by performing patterning around the emission areas EA1, EA2, and EA3 or the openings, respectively.

[0127] The display device 10 according to the embodiment may include a plurality of organic patterns ELP1, ELP2, and ELP3, which include the same material as the light-emitting layers EL1, EL2, and EL3 and are disposed on the embankment structure BNS. Since the light-emitting layers EL1, EL2, and EL3 are formed by a process of depositing a material on the entire surface of the display device 10, the material forming the light-emitting layers EL1, EL2, and EL3 may be deposited on the embankment structure BNS and in the emission areas EA1, EA2, and EA2.

[0128] For example, the display device 10 may include organic patterns ELP1, ELP2, and ELP3 disposed over the bank structure BNS. The organic patterns ELP1, ELP2, and ELP3 may include first, second, and third organic patterns ELP1, ELP2, and ELP3 disposed on the second bank layer BN2 of the bank structure BNS.

[0129] The first organic pattern ELP1 may include the same material as the first light emitting layer EL1 of the first light emitting element ED1. The second organic pattern ELP2 may include the same material as the second light emitting layer EL2 of the second light emitting element ED2, and the third organic pattern ELP3 may include the same material as the third light emitting layer EL3 of the third light emitting element ED3. The organic patterns ELP1, ELP2, and ELP3 may be formed in a process of forming light emitting layers EL1, EL2, and EL3 including the same material as the organic patterns ELP1, ELP2, and ELP3, respectively. The organic patterns ELP1, ELP2, and ELP3 may be disposed adjacent to emission areas EA1, EA2, and EA3 in which the light emitting layers EL1, EL2, and EL3, respectively, are disposed.

[0130] The display device 10 according to the embodiment may include a plurality of electrode patterns CEP1, CEP2, and CEP3, which include the same material as the common electrodes CE1, CE2, and CE3 and are disposed on the embankment structure BNS. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be directly disposed on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. The arrangement relationship between the electrode patterns CEP1, CEP2, and CEP3 and the organic patterns ELP1, ELP2, and ELP3 may be the same as the arrangement relationship between the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3.

[0131] The display device 10 may include a cap pattern CLP disposed above the embankment structure BNS. The cap pattern CLP may be disposed directly on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 disposed on the second embankment layer BN2 of the embankment structure BNS. The arrangement relationship between the cap pattern CLP and the electrode patterns CEP1, CEP2, and CEP3 may be the same as the arrangement relationship between the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 and the cap layer CAP.

[0132] The thin film encapsulation layer TFEL may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS, and may cover the plurality of light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from foreign matter such as dust.

[0133] In an embodiment, the thin film encapsulation layer TFEL may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3 that are sequentially stacked.

[0134] Each of the first inorganic encapsulating film TFE1 and the second inorganic encapsulating film TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may be any one of silicon oxide, silicon nitride and silicon oxynitride, and may be, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride.

[0135] The organic encapsulation film TFE2 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. For example, the organic encapsulation film TFE2 may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The organic encapsulation film TFE2 may be formed by curing a monomer or applying a polymer.

[0136] The first inorganic encapsulation film TFE1 may be disposed on the light emitting elements ED1, ED2, and ED3, the trace patterns TRP1, TRP2, and TRP3, and the embankment structure BNS. The first inorganic encapsulation film TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3, each of which is disposed to correspond to different emission areas EA1, EA2, and EA3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include an inorganic insulating material and cover the light emitting elements ED1, ED2, and ED3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be disposed to cover the organic patterns ELP1, ELP2, and ELP3, the electrode patterns CEP1, CEP2, and CEP3, and the cover pattern CLP to prevent the pattern disposed on the embankment structure BNS from being peeled off during the process for manufacturing the display device 10.

[0137] The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be formed by chemical vapor deposition (CVD), and thus may be formed along the steps on which the layers thereof are deposited. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may form a thin film even under an undercut formed due to the tip TIP of the bank structure BNS.

[0138] The first inorganic layer TL1 may be disposed on the first light emitting element ED1 and the first electrode pattern CEP1. The first inorganic layer TL1 may be disposed along the side surfaces of the first light emitting element ED1, the cap layer CAP, and the second bank layer BN2 adjacent to the first common electrode CE1 to cover the side surfaces of the first light emitting element ED1, the cap layer CAP, and the second bank layer BN2 adjacent to the first common electrode CE1, and may also be disposed to cover the first organic pattern ELP1, the first electrode pattern CEP1, and the cap pattern CLP. However, the first inorganic layer TL1 may not overlap the second opening and the third opening in a plan view, and may be disposed only on the bank structure BNS in and around the first opening. Figures 4 to 6 It has been shown that the first inorganic layer TL1 seals the first trace pattern TRP1 and the light emitting element ED1 with uneven thickness along the outer surfaces of the first trace pattern TRP1 and the light emitting element ED1, but the first inorganic layer TL1 can be set with uniform thickness along the upper surface and side surfaces of the first trace pattern TRP1, the side surface and lower surface of the second bank layer BN2, the side surface of the first bank layer BN1 and the upper surface of the first common electrode CE1.

[0139] The second inorganic layer TL2 may be disposed on the second light emitting element ED2 and the second electrode pattern CEP2. However, the second inorganic layer TL2 may not overlap the first and third openings in a plan view, and may be disposed only on the bank structure BNS in and around the second opening.

[0140] The third inorganic layer TL3 may be disposed on the third light emitting element ED3 and the third electrode pattern CEP3. However, the third inorganic layer TL3 may not overlap the first and second openings in a plan view, and may be disposed only on the bank structure BNS in and around the third opening.

[0141] The first inorganic layer TL1 may be formed after forming the first common electrode CE1, the second inorganic layer TL2 may be formed after forming the second common electrode CE2, and the third inorganic layer TL3 may be formed after forming the third common electrode CE3. Therefore, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be arranged to cover different electrode patterns CEP1, CEP2, and CEP3 and organic patterns ELP1, ELP2, and ELP3, respectively. Figure 3In the plan view, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may have the same or similar boundaries as the boundaries of the first trace pattern TRP1, the second trace pattern TRP2, and the third trace pattern TRP3, respectively, and may have areas larger than the openings or emission areas EA1, EA2, and EA3 of the embankment structure BNS, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be arranged to be spaced apart from each other on the embankment structure BNS. Therefore, a portion of the second embankment layer BN2 may not overlap with the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 in the plan view, and a portion of the upper surface of the second embankment layer BN2 may be exposed in the space between the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 spaced apart from each other without being covered by the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3. The exposed upper surface of the second embankment layer BN2 may be in direct contact with the organic encapsulation film TFE2 of the thin film encapsulation layer TFEL.

[0142] The light blocking layer BM may be disposed on the thin film encapsulation layer TFEL. The light blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 disposed to overlap with the emission areas EA1, EA2, and EA3 in a plan view. For example, the first hole OPT1 may be disposed to overlap with the first emission area EA1. In a plan view, the second hole OPT2 may be disposed to overlap with the second emission area EA2, and the third hole OPT3 may be disposed to overlap with the third emission area EA3. The area or size of each of the holes OPT1, OPT2, and OPT3 may be larger than the area or size of each of the emission areas EA1, EA2, and EA3. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM are formed to be larger than the emission areas EA1, EA2, and EA3, and therefore, the light emitted from the emission areas EA1, EA2, and EA3 may be viewed by the user not only from the front surface of the display device 10, but also from the side surface of the display device 10.

[0143] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the present disclosure is not limited thereto. The light blocking layer BM may prevent color mixing caused by penetration of visible light between the first emission area EA1, the second emission area EA2, and the third emission area EA3 to improve the color gamut of the display device 10.

[0144] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 respectively disposed in the emission areas EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3 may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be disposed on a light blocking layer BM including a plurality of holes OPT1, OPT2, and OPT3, and the plurality of holes OPT1, OPT2, and OPT3 are disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM may be formed to overlap with the emission areas EA1, EA2, and EA3 or the openings of the embankment structure BNS in a plan view, and may form a light emitting area through which light emitted from the emission areas EA1, EA2, and EA3 is emitted. Each of the color filters CF1 , CF2 , and CF3 may have a larger area than each of the holes OPT1 , OPT2 , and OPT3 of the light blocking layer BM, and may completely cover the light emitting region formed by each of the holes OPT1 , OPT2 , and OPT3 .

[0145] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are arranged to correspond to different emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or a pigment that absorbs light of a wavelength band other than light of a specific wavelength band, and may be arranged to correspond to the color of the light emitted from the emission areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first emission area EA1 in a plan view and is only used to transmit the first light as red light through it. The second color filter CF2 may be a green color filter that is arranged to overlap with the second emission area EA2 in a plan view and is only used to transmit the second light as green light through it, and the third color filter CF3 may be a blue color filter that is arranged to overlap with the third emission area EA3 in a plan view and is only used to transmit the third light as blue light through it.

[0146] A plurality of color filters CF1, CF2 and CF3 may be spaced apart from other adjacent color filters CF1, CF2 and CF3 on the light blocking layer BM. The color filters CF1, CF2 and CF3 may have an area larger than the holes OPT1, OPT2 and OPT3 of the light blocking layer BM, while covering the holes OPT1, OPT2 and OPT3 of the light blocking layer BM respectively, but may have an area sufficient to be spaced apart from other color filters CF1, CF2 and CF3 on the light blocking layer BM. However, the present disclosure is not limited thereto. A plurality of color filters CF1, CF2 and CF3 may be arranged to partially overlap with other adjacent color filters CF1, CF2 and CF3 in a plan view. Different color filters CF1, CF2 and CF3 may overlap each other on the light blocking layer BM, and the light blocking layer BM is an area that does not overlap with the emission areas EA1, EA2 and EA3. In the display device 10, the color filters CF1, CF2, and CF3 are arranged to overlap each other in a plan view, so that the intensity of the reflected light due to the external light can be reduced. In addition, by adjusting the arrangement, shape, area, etc. of the color filters CF1, CF2, and CF3 in a plan view, the color sense of the reflected light due to the external light can be controlled.

[0147] An overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the upper ends of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0148] Hereinafter, a process for manufacturing the display device 10 according to the embodiment will be described with reference to other drawings.

[0149] Figure 8 is a flowchart showing a process for manufacturing a display device according to an embodiment, Figures 9 to 16 are detailed cross-sectional views sequentially illustrating processes for manufacturing a display device according to an embodiment.

[0150] exist Figures 9 to 16 , a process of forming a dam structure BNS and a light-emitting element ED as a light-emitting element layer EML of a display device 10 and a process of forming a thin film encapsulation layer TFEL are schematically shown. Hereinafter, the description of the process of forming each layer in the process of manufacturing the display device 10 will be omitted, and the order of forming each layer will be described.

[0151] Reference Fig. 9 , a metal electrode layer AE is entirely formed on the second passivation layer PAS2 , and then a sacrificial material layer SFLL is formed on the metal electrode layer AE.

[0152] Despite Fig. 91. However, a thin film transistor layer TFTL may be provided on the substrate SUB, and the structure of the thin film transistor layer TFTL is the same as that of the above reference. Figure 4 The structures described are the same. A detailed description thereof will be omitted.

[0153] Then, refer to Fig.10 , a photoresist PR as a mask pattern is formed on the sacrificial material layer SFLL, and a first etching process (first etching) to remove the sacrificial material layer SFLL and the metal electrode layer AE that are not covered by the photoresist PR as the mask pattern may be performed. The metal electrode layer AE may include an amorphous material. By etching the sacrificial material layer SFLL and the metal electrode layer AE together through the first etching process, a plurality of pixel electrodes AE1 and AE2 spaced apart from each other and the sacrificial layer SFL ( Figure 8 S10).

[0154] When the photoresist PR as a mask pattern on the plurality of pixel electrodes AE1 and AE2 and the sacrificial layer SFL is removed and heat-treated, the amorphous material of the pixel electrodes AE1 and AE2 may be crystallized. When the upper electrode layer of the pixel electrodes AE1 and AE2 is crystallized, the upper electrode layer may have selectivity with respect to the sacrificial layer SFL in a subsequent etching process.

[0155] Reference Fig.11 , a pixel definition material layer PDLL, bank material layers BNL1 and BNL2 ( Figure 8 The pixel definition material layer PDLL may be arranged to entirely cover the thin film transistor layer TFTL (see S20). Figure 4 ), and the first bank material layer BNL1 and the second bank material layer BNL2 may be provided to entirely cover the pixel definition material layer PDLL. The bank material layers BNL1 and BNL2 may be partially etched in a subsequent process to form Figure 4 The bank layers BN1 and BN2 of the bank structure BNS shown in FIG.

[0156] Next, refer to Fig.12 , a photoresist PR is formed on the bank material layers BNL1 and BNL2, and a second etching process (second etching) of etching the first and second bank material layers BNL1 and BNL2 and a portion of the pixel defining material layer PDLL to form a hole HOL is performed using the photoresist PR as a mask. The hole HOL may be formed in a region overlapping the plurality of pixel electrodes AE1 and AE2 in a plan view, and an opening of the bank structure BNS may be formed.

[0157] The photoresist PR may be disposed to be spaced apart from each other on the bank material layers BNL1 and BNL2. The photoresist PR may be disposed on the second bank material layer BNL2 to expose a portion of the second bank material layer BNL2 overlapping the first pixel electrode AE1 in a plan view.

[0158] In an embodiment, dry etching may be performed as the second etching process (second etching). The bank material layers BNL1 and BNL2 and the pixel defining material layer PDLL may be anisotropically etched, but due to the difference between the material of the bank material layers BNL1 and BNL2 and the material of the pixel defining material layer PDLL, the etching area of ​​the pixel defining material layer PDLL may be smaller than the etching area of ​​the bank material layers BNL1 and BNL2. In this process, the amorphous sacrificial layer SFL is not etched, and thus the pixel electrodes AE1 and AE2 may be protected. That is, as Figure 8 As described in the process S30 , the sacrificial layer SFL may be exposed through a second etching process (second etching).

[0159] Next, refer to Fig.13 , a portion of the sacrificial layer SFL is etched, and at the same time, an undercut structure of the first bank material layer BNL1 is formed through a third etching process (third etching).

[0160] The first bank material layer BNL1 may have a faster etching rate than the second bank material layer BNL2, and a side surface of the second bank material layer BNL2 may be formed to protrude more than a side surface of the first bank material layer BNL1. The side surface of the second bank material layer BNL2 protrudes more toward the hole HOL than a side surface of the first bank material layer BNL1 to form a tip TIP, and an undercut may be formed under the tip TIP.

[0161] While etching the side surface of the first bank material layer BNL1, the sacrificial layer SFL ( Figure 8 S40). A side surface of the sacrificial layer SFL may be aligned with a side surface of the pixel defining material layer PDLL, or may protrude much more than a side surface of the pixel defining material layer PDLL. In an embodiment, the sacrificial layer SFL includes molybdenum (Mo), and thus may be etched together with the first bank material layer BNL1 without forming an undercut structure.

[0162] In an embodiment, the third etching process (third etching) may be an isotropic wet etching process. The third etching process may use an etchant including phosphorus (P), fluorine (F), or nitrogen (N).

[0163] Then, if Fig.14As shown in FIG. 1 , the photoresist PR formed on the second bank material layer BNL2 is removed, and the first light emitting layer EL1, the first common electrode CE1 and the capping layer CAP are deposited on the first pixel electrode AE1 to form the first light emitting element ED1. In this case, the first light emitting layer EL1, the first common electrode CE1 and the capping layer CAP are formed on the substrate SUB (see FIG. 1 ). Figure 2 ), and thus, a trace pattern may be formed on the second bank material layer BNL2. The trace pattern may include a cap pattern material layer CLPL, a first electrode pattern material layer CEPL1, and a first organic pattern material layer ELPL1. A first organic pattern material layer ELPL1 separated from the first light emitting layer EL1 may be formed on the second bank material layer BNL2, and a first electrode pattern material layer CEPL1 separated from the first common electrode CE1 may be formed on the first organic pattern material layer ELPL1. That is, as Figure 8 As described in processes S50 , S60 and S70 shown in FIG, a light emitting layer, a common electrode and a capping layer CAP are formed on the pixel electrode, and an organic pattern material layer, an electrode pattern material layer and a capping pattern material layer are formed on the second bank material layer BNL2 .

[0164] The first light emitting layer EL1 and the first common electrode CE1 may be formed by a deposition process. Due to the tip TIP of the second bank material layer BNL2, the material may not be smoothly deposited in the first opening. However, the materials of the first light emitting layer EL1 and the first common electrode CE1 are relatively close to the substrate SUB (see FIG. 2 ). Figure 2 ) is deposited in an inclined direction on the upper surface, rather than in a direction aligned with the substrate SUB (see Figure 2 ), and thus may be deposited even in a region hidden by the tip TIP of the second bank material layer BNL2.

[0165] The deposition process of forming the common electrodes CE1, CE2 and CE3 may be performed in an inclined direction relatively close to the horizontal direction than the deposition process of forming the light emitting layers EL1, EL2 and EL3. Therefore, the common electrodes CE1, CE2 and CE3 may contact the side surface of the first bank material layer BNL1 in a region larger than the light emitting layers EL1, EL2 and EL3. Alternatively, the common electrodes CE1, CE2 and CE3 may be deposited at a position higher than the light emitting layers EL1, EL2 and EL3 on the side surface of the first bank material layer BNL1. Different common electrodes CE1, CE2 and CE3 may contact the first bank material layer BNL1 having high conductivity to be electrically connected to each other.

[0166] Subsequently, a first inorganic material layer TLL1 ( Figure 8S80). The first inorganic material layer TLL1 may be formed to completely cover the outer surfaces of the first light emitting element ED1, the bank material layers BNL1 and BNL2, the cap layer CAP, and the trace pattern. Specifically, the first inorganic material layer TLL1 is formed on the upper surface of the first common electrode CE1, the side surface of the first bank material layer BNL1, the lower surface and the side surface of the second bank material layer BNL2, and the upper surface and the side surface of the trace pattern.

[0167] Next, refer to Fig.15 , a photoresist PR as a mask pattern is formed on the first inorganic material layer TLL1, and a fourth etching process (fourth etching) of removing the first inorganic material layer TLL1 and the trace pattern not covered by the photoresist PR as the mask pattern is performed. That is, Figure 8 As described in the process S90, the organic pattern material layer of the trace pattern, the electrode pattern material layer and the cap pattern material layer are etched. In this case, the photoresist PR may be arranged to be aligned with the first emission area EA1 (see Figure 4 ) overlaps with the edge area surrounding the first emission area EA1.

[0168] Then, similarly execute Figures 12 to 15 The process shown in Fig.16 As shown in the figure, a second light-emitting layer EL2, a second common electrode CE2 and a cover layer CAP are formed on the second pixel electrode AE2, a second trace pattern TRP2 is formed around the second light-emitting layer EL2, the second common electrode CE2 and the cover layer CAP, and a second inorganic layer TL2 is formed covering the second light-emitting element ED2 and the second trace pattern TRP2.

[0169] Subsequently, although not shown in the drawings, the display device 10 is manufactured by forming an organic encapsulation film TFE2 and a second inorganic encapsulation film TFE3 of a thin film encapsulation layer TFEL, a light blocking layer BM, a color filter layer CFL, and an overcoat layer OC on the light emitting elements ED1, ED2, and ED3 and the dam structure BNS. The structures of the thin film encapsulation layer TFEL, the light blocking layer BM, the color filter layer CFL, and the overcoat layer OC are the same as described above, and thus a detailed description thereof will be omitted.

[0170] The embodiments of the present disclosure have been described above with reference to the accompanying drawings, but it will be understood by those skilled in the art that various modifications and changes may be made without departing from the technical spirit or basic features of the present disclosure. Therefore, it will be understood that the above embodiments are illustrative rather than restrictive in all aspects.

Claims

1. A display device, comprising: A first pixel electrode is disposed on the substrate; a first sacrificial pattern, arranged on an edge of the first pixel electrode; a pixel defining film, comprising a main portion disposed on the substrate and a protruding portion disposed on the first sacrificial pattern and exposing the first pixel electrode; A first light-emitting layer is disposed on the first pixel electrode; A first common electrode, disposed on the first light-emitting layer; A first bank layer is disposed on the pixel definition film; as well as a second bank layer disposed on the first bank layer and having a side surface that protrudes more than a side surface of the first bank layer, The first side surface of the first sacrificial pattern is aligned with the side surface of the protruding portion of the pixel defining film, or is more protruding than the side surface of the protruding portion of the pixel defining film.

2. The display device according to claim 1, wherein: The first sacrificial pattern includes Mo.

3. The display device according to claim 1, wherein: The first sacrificial pattern has a second side surface opposite to the first side surface, and The pixel defining film is disposed on the second side surface of the first sacrificial pattern.

4. The display device according to claim 1, wherein: The side surface of the protruding portion of the pixel defining film protrudes more than the side surface of the second bank layer.

5. The display device according to claim 1, wherein: The thickness of the first sacrificial pattern is 50Å to 600Å.

6. The display device according to claim 1, wherein: An upper surface of the first sacrificial pattern contacts the protruding portion of the pixel defining film, and A lower surface of the first sacrificial pattern contacts the first pixel electrode.

7. The display device according to claim 1, wherein: The first pixel electrode is a multi-layer film made of ITO / Ag / ITO, Al / TiN or Al / Ti.

8. The display device according to claim 1, wherein: An entire lower surface of the protruding portion of the pixel defining film contacts the first sacrificial pattern.

9. The display device according to claim 1, wherein: The first common electrode and the first light emitting layer are in contact with the first bank layer, and A contact area between the first common electrode and the first bank layer is greater than a contact area between the first light emitting layer and the first bank layer.

10. The display device according to claim 1, wherein: The first bank layer includes Al, and The second bank layer includes Ti. 11 . The display device of claim 1 , further comprising a first inorganic layer disposed on an upper surface of the first common electrode, a side surface of the first bank layer, and a lower surface and an upper surface of the second bank layer.

12. The display device according to claim 11, further comprising: a second pixel electrode, arranged on the substrate and spaced apart from the first pixel electrode; a second sacrificial pattern, arranged on an edge of the second pixel electrode; A second light emitting layer is disposed on the second pixel electrode; a second common electrode, disposed on the second light-emitting layer and spaced apart from the first common electrode; as well as a second inorganic layer disposed on an upper surface of the second common electrode, a side surface of the first bank layer, and a lower surface and an upper surface of the second bank layer; The pixel defining film exposes the second pixel electrode. The first inorganic layer and the second inorganic layer are disposed to be spaced apart from each other, and A portion of the second bank layer is exposed in a space between the first inorganic layer and the second inorganic layer which are spaced apart from each other.

13. The display device according to claim 1, further comprising: a first organic pattern disposed on the second bank layer and comprising the same material as the first light emitting layer; as well as a first electrode pattern disposed on the first organic pattern and comprising the same material as the first common electrode, wherein the first light emitting layer and the first organic pattern are separated from each other, and The first common electrode and the first electrode pattern are separated from each other.

14. A display device, comprising: A pixel electrode is disposed on the substrate; A sacrificial pattern, disposed on the pixel electrode; a pixel defining film disposed on the substrate and comprising a main body portion and a protruding portion protruding from the main body portion; A light-emitting layer is arranged on the pixel electrode; A common electrode is disposed on the light-emitting layer; A first bank layer is disposed on the pixel definition film; as well as a second bank layer disposed on the first bank layer and having a side surface that protrudes more than a side surface of the first bank layer, wherein the protruding portion of the pixel defining film is disposed on the pixel electrode and is spaced apart from an upper surface of the pixel electrode, and A space between the protruding portion of the pixel defining film and the pixel electrode is filled with the sacrificial pattern.

15. The display device according to claim 14, wherein: A lower surface of the protruding portion of the pixel defining film does not contact the light emitting layer.

16. The display device according to claim 14, wherein: The upper surface of the sacrificial pattern contacts the protruding portion of the pixel defining film, and A lower surface of the sacrificial pattern contacts the pixel electrode.

17. A method for manufacturing a display device, the method comprising the following steps: forming a plurality of pixel electrodes and a sacrificial layer on a substrate, the plurality of pixel electrodes being spaced apart from each other, and the sacrificial layer being disposed on the plurality of pixel electrodes; forming a pixel defining material layer on the sacrificial layer, forming a first bank material layer on the pixel defining material layer, and forming a second bank material layer on the first bank material layer; forming a hole exposing a pixel electrode among the plurality of pixel electrodes by etching the pixel definition material layer, the first bank material layer, and the second bank material layer; etching a portion of the sacrificial layer exposed through the hole and a side surface of the first bank material layer exposed through the hole so as to expose a portion of a lower surface of the second bank material layer; forming a light-emitting layer on the pixel electrode, and forming a common electrode on the light-emitting layer; as well as An inorganic material layer is formed on the common electrode.

18. The method for manufacturing a display device according to claim 17, wherein: The step of forming the plurality of pixel electrodes and the sacrificial layer on the substrate comprises: forming a metal electrode layer on the substrate, and forming a sacrificial material layer on the metal electrode layer; forming a mask pattern on the sacrificial material layer, and etching portions of the sacrificial material layer and the metal electrode layer that are not covered by the mask pattern; and The remaining portions of the sacrificial material layer and the metal electrode layer covered by the mask pattern are heat-treated.

19. The method for manufacturing a display device according to claim 17, wherein: The step of etching the portion of the sacrificial layer exposed through the hole and the side surface of the first bank material layer exposed through the hole includes performing a wet etching process using an etchant including P, F, or N.

20. The method for manufacturing a display device according to claim 17, wherein: In the step of forming the light emitting layer on the pixel electrode and the step of forming the common electrode on the light emitting layer, an organic pattern material layer separated from the light emitting layer is formed on the second bank material layer, and an electrode pattern material layer separated from the common electrode is formed on the organic pattern material layer, and In the step of forming the inorganic material layer on the common electrode, a single inorganic material layer is formed to cover both the common electrode and the electrode pattern material layer.

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