Structure and manufacturing method of infrared thermopile sensing chip

Abstract

The invention provides a structure and a manufacturing method of an infrared thermopile sensor chip, and the manufacturing method comprises the following steps: a, providing a substrate layer which is provided with an upper surface and a lower surface; b, depositing a dielectric couple layer group on the upper surface of the substrate layer, namely, b1, depositing a first dielectric on the upper surface of the substrate layer, and performing imaging processing on the first dielectric to obtain a first dielectric layer with a plurality of dielectric holes, the dielectric hole is communicated with the upper surface of the first dielectric layer and the substrate layer; b2, depositing a first galvanic couple layer on the upper surface of the first dielectric layer, wherein the dielectric holes are filled with the first galvanic couple layer; and e, corroding the substrate layer and the first galvanic couple layer in the dielectric hole on the lower surface of the substrate layer to prepare the infrared thermopile sensor chip with a back cavity, so that the heat dissipation capability is improved, and the thermopile semaphore is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of infrared thermopile sensors, and in particular to a structure and a manufacturing method of an infrared thermopile sensor chip. Background Art

[0003] The infrared thermopile sensor chip is a sensor based on the Seebeck effect principle. Its core is to convert the infrared light radiated by the object into an electrical signal to measure the temperature. Specifically, when infrared rays are irradiated onto the absorption film of the sensor, heat energy is generated, which is further transferred to the thermocouple in the thermopile, causing it to generate a thermoelectric potential. This thermoelectric potential is proportional to the temperature difference between the two ends of the thermocouple. By measuring this voltage signal, the temperature of the target can be inferred. Infrared thermopile sensor chips have the characteristics of wide measurement range, high precision, fast response, and high reliability. They are widely used in household appliances, industrial detection and other scenarios.

[0004] For example, a thermopile infrared detector and a manufacturing method thereof are disclosed in publication number CN112670397A. The thermopile infrared detector includes a thermopile structure, and a substrate and a back cavity located on one side of the thermopile structure. The thermopile structure includes a dielectric layer, an electric couple layer, and a welding pad. The number of dielectric layers and electric couple layers are both multiple layers, and the first dielectric layer is arranged between the substrate and the first electric couple layer.

[0005] Among them, the first layer of dielectric layer has a larger area, which is not conducive to heat dissipation. The heat dissipation capacity directly affects the temperature difference between the two ends of the thermocouple. If the heat dissipation capacity is insufficient, the temperature of the hot end of the thermocouple will continue to rise, resulting in an increase in the temperature difference, and then generate a larger thermoelectric potential. Therefore, good heat dissipation capacity helps to maintain the stability of the thermocouple temperature, thereby improving the stability of the signal output and generating sufficient signal volume. Summary of the invention

[0006] The purpose of the present invention is to provide a structure and a manufacturing method of an infrared thermopile sensor chip to improve the heat dissipation capacity, increase the thermopile signal amount, and thus improve the sensitivity of the sensor.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] A method for manufacturing an infrared thermopile sensor chip comprises the following steps:

[0009] a. providing a substrate layer, wherein the substrate layer has an upper surface and a lower surface;

[0010] b. Depositing a dielectric electric double layer group on the upper surface of the substrate layer, wherein the step of depositing the dielectric electric double layer group comprises:

[0011] b1. Depositing a first medium on the upper surface of the substrate layer, and performing image processing on the first medium to obtain a first dielectric layer having a plurality of dielectric holes, wherein the dielectric holes connect the upper surface of the first dielectric layer and the substrate layer;

[0012] b2. depositing a first electric double layer on the upper surface of the first dielectric layer, wherein the first electric double layer fills the dielectric holes;

[0013] e. Etching the substrate layer and the first electric double layer in the dielectric hole on the lower surface of the substrate layer to obtain an infrared thermopile sensor chip with a back cavity.

[0014] As a preferred embodiment, after step b2, step b further comprises the following steps:

[0015] b3, depositing a second dielectric layer on the upper surface of the first electric double layer;

[0016] b4, depositing a second electric couple on the upper surface of the second dielectric layer, and performing image processing on the second electric couple to obtain a second electric couple layer having a plurality of electric couple holes, wherein the electric couple holes connect the upper surface of the second electric couple layer and the second dielectric layer;

[0017] b5. Depositing a third dielectric layer on the upper surface of the second electric double layer, wherein the third dielectric layer fills the electric double holes.

[0018] As a preferred embodiment, the step b4 includes:

[0019] The second electric couple is patterned in a manner of staggering the dielectric holes, so that the electric couple holes of the second electric double layer are staggered with the dielectric holes.

[0020] As a preferred embodiment, between steps b and e, the method further comprises the following steps:

[0021] c. performing a hole-opening process on the dielectric electric double layer group, wherein the upper end of the hole is exposed on the upper surface of the dielectric electric double layer group, and the lower end of the hole is connected to each electric double layer;

[0022] d. Depositing metal on the upper surface of the dielectric electric double layer group so that the metal fills the inside of the hole and forms a pad on the upper surface of the dielectric electric double layer group.

[0023] As a preferred embodiment, the dielectric electric double layer group includes a first dielectric layer, a second dielectric layer, a third dielectric layer, a first electric double layer and a second electric double layer, and the first dielectric layer, the first electric double layer, the second dielectric layer, the second electric double layer and the third dielectric layer are arranged on the substrate layer from bottom to top, and then the step c includes the following steps:

[0024] c1. Drilling a hole above the second electric double layer, wherein the hole above the second electric double layer connects the upper surface of the third dielectric layer and the second electric double layer;

[0025] c2. Drill a hole above the first electric double layer, wherein the hole above the first electric double layer connects the upper surface of the third dielectric layer and the first electric double layer.

[0026] As a preferred embodiment, the second electric double layer has three electric double holes, and the second electric double layer is divided into two parts by the three electric double holes, and each part corresponds to a welding pad.

[0027] As a preferred embodiment, the back cavity includes a substrate cavity, a dielectric hole and a first galvanic cavity which are connected in sequence, and the step e includes the following steps:

[0028] e1. Etching the substrate layer to form a substrate cavity penetrating the substrate layer on the substrate layer;

[0029] e2, corroding the second electric double layer in the medium hole;

[0030] e3. Etching the first electric double layer along the dielectric hole to form a first electric double cavity penetrating the first electric double layer.

[0031] The present invention also provides a structure of an infrared thermopile sensor chip, comprising:

[0032] a substrate layer having an upper surface and a lower surface;

[0033] A dielectric electric double layer group, the dielectric electric double layer group comprising a first dielectric layer and a first electric double layer, wherein the first dielectric layer is located between the substrate layer and the first electric double layer;

[0034] A back cavity is disposed on the lower surface of the substrate layer, and the back cavity penetrates the substrate layer, the first dielectric layer, and the second dielectric layer.

[0035] As a preferred embodiment, the back cavity comprises:

[0036] a substrate cavity, wherein the substrate cavity penetrates the substrate layer;

[0037] A dielectric hole, wherein the dielectric hole penetrates the first dielectric layer;

[0038] A first electric couple cavity, wherein the first electric couple cavity penetrates the first electric double layer, and the first electric couple cavity corresponds to the dielectric hole.

[0039] As a preferred embodiment, it also includes:

[0040] A pad is provided on the upper surface of the dielectric electric double layer group, and the pad is connected to each electric double layer of the dielectric electric double layer group.

[0041] Compared with the prior art, this technical solution has the following advantages:

[0042] The first medium is imaged to obtain a first dielectric layer having a plurality of dielectric holes, the first electric double layer is filled in the dielectric holes and covers the upper surface of the first dielectric layer, and in the step e, the first electric double layer in the dielectric holes and the substrate layer are corroded to form the back cavity on the lower surface of the substrate layer, which greatly reduces the area of ​​the first dielectric layer to enhance the thermal isolation of the thermopile, thereby enhancing the signal quantity of the sensor.

[0043] The present invention is further described below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a flow chart of the method for manufacturing the infrared thermopile sensor chip of the present invention;

[0045] Figure 2 This is a schematic diagram of the structure of the infrared thermopile sensor chip of the present invention;

[0046] Figures 3 to 7 This is a diagram of the manufacturing process of the infrared thermopile sensor chip of the present invention.

[0047] In the figure: 100 substrate layer, 110 upper surface, 120 lower surface, 200 dielectric electric double layer group, 211 first dielectric layer, 211b first dielectric, 212 second dielectric layer, 213 third dielectric layer, 221 first electric double layer, 222 second electric double layer, 222b second electric double, 300 pad, 400 back cavity, 410 substrate cavity, 420 dielectric hole, 430 first electric double cavity, 500 hole. DETAILED DESCRIPTION

[0048] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0049] First embodiment

[0050] like Figures 1 to 7 As shown, the method for manufacturing the infrared thermopile sensor chip comprises the following steps:

[0051] a. providing a substrate layer 100, wherein the substrate layer 100 has an upper surface 110 and a lower surface 120;

[0052] b. Depositing a dielectric electric double layer group 200 on the upper surface of the substrate layer 100, wherein the step of depositing the dielectric electric double layer group 200 comprises:

[0053] b1. Depositing a first dielectric 211b on the upper surface of the substrate layer 100 and performing image processing on the first dielectric 211b to obtain a first dielectric layer 211 having a plurality of dielectric holes 420, wherein the dielectric holes 420 connect the upper surface of the first dielectric layer 211 and the substrate layer 100;

[0054] b2. depositing a first electric double layer 221 on the upper surface of the first dielectric layer 211 , wherein the first electric double layer 221 is filled in the dielectric hole 420 ;

[0055] e. Etching the substrate layer 100 and the first electric double layer 210 in the dielectric hole 420 on the lower surface of the substrate layer 100 to obtain an infrared thermopile sensor chip with a back cavity 400 .

[0056] The first dielectric 211b is imaged to obtain a first dielectric layer 211 having a plurality of dielectric holes 420. The first electric double layer 221 is filled in the dielectric holes 420 and covers the upper surface of the first dielectric layer 211. In the step e, the first electric double layer 221 in the dielectric holes 420 and the substrate layer 100 are corroded to form the back cavity 400 on the lower surface of the substrate layer 100, which greatly reduces the area of ​​the first dielectric layer 211 to enhance the thermal isolation of the thermopile, thereby enhancing the signal quantity of the sensor.

[0057] like Figure 3 As shown, in step a, the substrate layer 100 can be made of single crystal silicon, aluminum oxide and other materials to support the dielectric electric couple layer group 200. Aluminum oxide is a material with high thermal conductivity and low thermal expansion coefficient, which can significantly improve the rated current and output thermoelectric potential of the thermoelectric converter, thereby enhancing the signal of the sensor.

[0058] like Figures 3 to 6 As shown, in the step b, the dielectric electric double layer group 200 includes a first dielectric layer 211, a second dielectric layer 212, a third dielectric layer 213, a first electric double layer 221 and a second electric double layer 222, and the first dielectric layer 211, the first electric double layer 221, the second dielectric layer 212, the second electric double layer 222 and the third dielectric layer 213 are arranged on the substrate layer 100 from bottom to top.

[0059] The first dielectric layer 211, the second dielectric layer 212, and the third dielectric layer 213 can be made of materials such as aluminum oxide, silicon nitride, and silicon oxide, and have high thermal resistance (low thermal conductivity) to prevent the heat converted from infrared radiation from being dissipated through the dielectric layer and reducing the performance of the detector; at the same time, they also have good mechanical strength and thermal stability to support the upper structure and withstand high temperature treatment during the preparation process.

[0060] The first electric double layer 221 and the second electric double layer 222 are usually composed of materials having thermoelectric effect, including polysilicon, aluminum and other metals and alloys. These materials can generate potential difference under temperature difference, thereby realizing thermoelectric conversion.

[0061] refer to Figure 3 and Figure 4 The step b1 includes: depositing a first medium 211b on the upper surface of the substrate layer 100, and imaging the first medium 211b to obtain a first dielectric layer 211 having a plurality of dielectric holes 420, wherein the dielectric holes 420 connect the upper surface of the first dielectric layer 211 and the substrate layer 100.

[0062] The imaging process may be performed by photolithography and etching, etc., by forming the dielectric hole 420 on the first dielectric layer 211, so that in the step e, the first electric double layer 221 in the dielectric hole 420 is corroded, and the substrate layer 100 is corroded to form a back cavity, which not only reduces the area of ​​the first dielectric layer 211, but also allows the first dielectric layer 211 and the first electric double layer 221 to directly dissipate heat through the back cavity, thereby keeping the thermopile working within a relatively stable temperature range, which helps to reduce the thermoelectric potential fluctuation caused by temperature changes, improve the stability of the signal amount, and thus enhance the signal amount of the sensor.

[0063] refer to Figure 5 The step b2 includes: depositing a first electric double layer 221 on the upper surface of the first dielectric layer 211 , wherein the first electric double layer 221 is filled in the dielectric hole 420 .

[0064] The first electric double layer 221 not only fills the dielectric hole 420 , but also covers the upper surface of the first dielectric layer 211 .

[0065] The lower surface of the first dielectric layer 211 is connected to the substrate layer 100, wherein the first dielectric layer 211 is located between the first electric double layer 221 and the substrate layer 100, which provides a stable support, effectively preventing the first electric double layer 221 from directly contacting the substrate layer 100, and avoiding performance degradation caused by short circuit or heat conduction. In the step e, after the first electric double layer 221 in the dielectric hole 420 is corroded, the first dielectric layer 211 is supported between the first electric double layer 221 and the substrate layer 100, and the first electric double layer 221 and the substrate layer 100 are not in direct contact.

[0066] It should be noted that, first, the dielectric hole 420 is formed on the first dielectric layer 211 by imaging, and then in the step b2: the first electric double layer 221 is filled in the dielectric hole 420, and finally in the step e, the substrate layer 100 is corroded, and the first electric double layer 221 in the dielectric hole 420 is corroded to form a back cavity, thereby reducing the difficulty of forming the back cavity and providing a range for the formation of the back cavity.

[0067] If the dielectric holes 420 are not formed on the first dielectric layer 211 first, but the first dielectric layer 211 is directly corroded in the step e, the supporting ability of the first dielectric layer 211 is easily destroyed. In the step e, there is no need to etch the dielectric holes 420 on the first dielectric layer 211, which reduces the processing difficulty and the difficulty of forming the back cavity.

[0068] refer to Figure 5 After step b2, step b further comprises the following steps:

[0069] b3, depositing the second dielectric layer 212 on the upper surface of the first electric double layer 221;

[0070] b4, depositing a second electric couple 222b on the upper surface of the second dielectric layer 212, and performing image processing on the second electric couple 222b to obtain a second electric couple layer 222 having a plurality of electric couple holes 222a, wherein the electric couple holes 222a connect the upper surface of the second electric couple layer 222 and the second dielectric layer 212;

[0071] b5. Depositing a third dielectric layer 213 on the upper surface of the second electric double layer 222 , wherein the third dielectric layer 213 fills the electric double hole 222 a .

[0072] The second dielectric layer 212 is supported between the first electric double layer 221 and the second electric double layer 222. The electric double hole 222a is opened on the second electric double layer 222b, so that the third dielectric layer 213 can fill the electric double hole 222a and punch holes in the third dielectric layer 213.

[0073] Continue to refer Figure 5 , the step b4 comprises:

[0074] The second electric couple 222 b is patterned in a manner of staggering the dielectric holes 420 , so that the electric couple holes 222 b of the second electric couple layer 222 and the dielectric holes 420 are staggered.

[0075] The number of the electric double holes 222b is three, the number of the dielectric holes 420 is two, and one dielectric hole 420 is arranged between two adjacent electric double holes 222b, so that the third dielectric layer 213 and the second dielectric layer 212 have a connected part, and a hole can be punched in the part to form a hole 500 located above the first electric double layer 221.

[0076] like Figure 6 and Figure 7 As shown, between steps b and e, the method further comprises the following steps:

[0077] c. Performing hole processing on the dielectric electric double layer group 200, the upper end of the hole 500 is exposed on the upper surface of the dielectric electric double layer group 200, and the lower end of the hole 500 is connected to each electric double layer;

[0078] d. Depositing metal on the upper surface of the dielectric electric double layer group 200 so that the metal fills the inside of the hole 500 , and forming a pad 300 on the upper surface of the dielectric electric double layer group 200 .

[0079] refer to Figure 6 The dielectric electric double layer group 200 includes a first dielectric layer 211, a second dielectric layer 212, a third dielectric layer 213, a first electric double layer 221 and a second electric double layer 222, wherein the first dielectric layer 211, the first electric double layer 221, the second dielectric layer 212, the second electric double layer 222 and the third dielectric layer 213 are arranged from bottom to top on the substrate layer 100, and the step c includes the following steps:

[0080] c1. Drilling a hole above the second electric double layer 222 , wherein the hole 500 above the second electric double layer 222 connects the upper surface of the third dielectric layer 213 and the second electric double layer 222 ;

[0081] c2. A hole is opened above the first electric double layer 221 , wherein the hole 500 above the first electric double layer 221 connects the upper surface of the third dielectric layer 213 and the first electric double layer 221 .

[0082] In the step c1, the second electric double layer 222 is wrapped between the third dielectric layer 213 and the second dielectric layer 212 , so a hole 500 penetrating the third dielectric layer 213 is opened on the third dielectric layer 213 , so that the hole 500 above the second electric double layer 222 communicates with the upper surface of the third dielectric layer 213 and the second electric double layer 222 .

[0083] In step c2, since the electric double hole 222b of the second electric double layer 222 and the dielectric hole 420 are staggered, and the upper surface of the second dielectric layer 212 is connected to the third dielectric layer 213 and the second electric double layer 222 at the same time, and the lower surface of the second dielectric layer 212 is connected to the first electric double layer 221, the third dielectric layer 213 and the second dielectric layer 212 have a connected portion, and a hole can be punched in the portion to form a hole 500 located above the first electric double layer 221.

[0084] refer to Figure 6 The second electric double layer 222 has three electric double holes 222 a . The second electric double layer 222 is divided into two parts by the three electric double holes 222 a , and each part corresponds to a pad 300 .

[0085] refer to Figure 7 The metal fills the inside of the hole 500 and forms a pad 300 on the upper surface of the dielectric electric double layer group 200. The pad 300 serves as an electrical connection point between the thermopile and a circuit board or other electronic components.

[0086] like Figure 2 As shown, the back cavity 400 includes a substrate cavity 410, a dielectric hole 420 and a first galvanic cavity 430 which are connected in sequence, and then the step e includes the following steps:

[0087] e1. Etching the substrate layer 100 to form a substrate cavity 410 penetrating the substrate layer 100 on the substrate layer 100;

[0088] e2, corroding the second electric double layer 222 in the dielectric hole 420;

[0089] e3. Etching the first electric double layer 221 along the dielectric hole 420 to form a first electric double cavity 430 penetrating the first electric double layer 221 on the first electric double layer 221 .

[0090] The etching may be performed by wet etching, dry etching, etc. Wet etching includes chemically dissolving the substrate material with a corrosive solution (such as tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), etc.). Dry etching includes etching the substrate material using a physical or chemical method (such as plasma etching, reactive ion etching, etc.) to form a back cavity.

[0091] The first galvanic cavity 430 has the same area as the dielectric hole 420, and the two overlap. The substrate cavity 410 has a larger area, and each of the first galvanic cavity 430 is located in the area surrounded by the substrate cavity 410, that is, the first dielectric layer 211, the first galvanic layer 221, and the second dielectric layer 212 are directly exposed to the back cavity 400, thereby improving the heat dissipation capability and enhancing the signal quantity of the sensor.

[0092] In summary, without adding additional process steps, the excess dielectric of the first dielectric layer 211 can be etched away to form dielectric holes 420, that is, the structure of the thermopile is changed to enhance the thermal isolation of the thermopile, thereby enhancing the signal of the sensor. Specifically, the first dielectric 211b is imaged to obtain a first dielectric layer 211 having a plurality of dielectric holes 420, and the first electric double layer 221 is filled in the dielectric holes 420 and covers the upper surface of the first dielectric layer 211. In the step e, the first electric double layer 221 in the dielectric holes 420 and the substrate layer 100 are etched to form the back cavity 400 on the lower surface of the substrate layer 100, which greatly reduces the area of ​​the first dielectric layer 211 to enhance the thermal isolation of the thermopile, thereby enhancing the signal of the sensor.

[0093] By forming a back cavity 400 under the sensor, the thermal coupling with the substrate layer 100 is significantly reduced, and the thermal response speed and sensitivity of the sensor are improved; the structural strength and stability are enhanced: the back release process (i.e., the formation of the back cavity 400) allows more precise control of the shape and size of the microstructure, thereby improving the mechanical stability and durability of the structure.

[0094] Without adding extra process steps, the first dielectric layer 211 is patterned first, and the step of forming the first electric double layer 221 can be combined with the "first dielectric layer patterning" and the back cavity etching step to achieve self-aligned patterning to reduce the thermal conductivity of the device.

[0095] Second embodiment

[0096] like Figure 2 As shown, the structure of the infrared thermopile sensor chip includes:

[0097] A substrate layer 100, wherein the substrate layer 100 has an upper surface 110 and a lower surface 120;

[0098] A dielectric electric double layer group 200, wherein the dielectric electric double layer group 200 comprises a first dielectric layer 211 and a first electric double layer 221, wherein the first dielectric layer 211 is located between the substrate layer 100 and the first electric double layer 221;

[0099] A back cavity 400 is disposed on the lower surface of the substrate layer 100 , and the back cavity 400 penetrates the substrate layer 100 , the first dielectric layer 211 , and the second dielectric layer 212 .

[0100] The structure of the infrared thermopile sensor chip of the second embodiment is obtained by the manufacturing method of the first embodiment, so the beneficial effects of the structure of the infrared thermopile sensor chip can refer to the first embodiment, that is, the area of ​​the first dielectric layer 211 is greatly reduced to enhance the thermal isolation of the thermopile, thereby enhancing the signal quantity of the sensor.

[0101] refer to Figure 2 , the back cavity 400 comprises:

[0102] A substrate cavity 410, wherein the substrate cavity 410 penetrates the substrate layer 100;

[0103] A dielectric hole 420, wherein the dielectric hole 420 penetrates the first dielectric layer 211;

[0104] The first electric couple cavity 430 penetrates the first electric couple layer 221 , and the first electric couple cavity 430 corresponds to the dielectric hole 420 .

[0105] refer to Figure 2 , the structure of the infrared thermopile sensor chip also includes:

[0106] The pad 300 is disposed on the upper surface of the dielectric electric double layer group 200 and is connected to each electric double layer of the dielectric electric double layer group 200. The pad 300 serves as an electrical connection point between the thermopile and a circuit board or other electronic components.

[0107] The embodiments described above are only used to illustrate the technical ideas and features of the present invention, and their purpose is to enable technicians in this field to understand the content of the present invention and implement it accordingly. The patent scope of the present invention cannot be limited only by this embodiment, that is, any equivalent changes or modifications made according to the spirit disclosed by the present invention still fall within the patent scope of the present invention.

Claims

1. A method for manufacturing an infrared thermopile sensor chip, characterized in that: The following steps are involved: a. providing a substrate layer (100), wherein the substrate layer (100) has an upper surface (110) and a lower surface (120); b. depositing a dielectric electric double layer group (200) on the upper surface of the substrate layer (100), wherein the step of depositing the dielectric electric double layer group (200) comprises: b1, depositing a first medium (211b) on the upper surface of the substrate layer (100), and performing image processing on the first medium (211b) to obtain a first dielectric layer (211) having a plurality of dielectric holes (420), wherein the dielectric holes (420) connect the upper surface of the first dielectric layer (211) and the substrate layer (100); b2. depositing a first electric double layer (221) on the upper surface of the first dielectric layer (211), wherein the first electric double layer (221) fills the dielectric holes (420); e. Etching the substrate layer (100) and the first electric double layer (210) in the dielectric hole (420) on the lower surface of the substrate layer (100) to obtain an infrared thermopile sensor chip with a back cavity (400).

2. The method for manufacturing an infrared thermopile sensor chip according to claim 1, characterized in that: After step b2, step b further comprises the following steps: b3, depositing a second dielectric layer (212) on the upper surface of the first electric double layer (221); b4, depositing a second electric couple (222b) on the upper surface of the second dielectric layer (212), and performing image processing on the second electric couple (222b) to obtain a second electric couple layer (222) having a plurality of electric couple holes (222a), wherein the electric couple holes (222a) connect the upper surface of the second electric couple layer (222) and the second dielectric layer (212); b5. Depositing a third dielectric layer (213) on the upper surface of the second electric double layer (222), wherein the third dielectric layer (213) fills the electric double hole (222a).

3. The method for manufacturing an infrared thermopile sensor chip according to claim 2, characterized in that: The step b4 comprises: The second electric couple (222b) is patterned in a manner of staggering the dielectric holes (420), so that the electric couple holes (222b) of the second electric couple layer (222) and the dielectric holes (420) are staggered.

4. The method for manufacturing an infrared thermopile sensor chip according to claim 1, characterized in that: Between steps b and e, the method further comprises the following steps: c. performing a hole-opening process on the dielectric electric double layer group (200), wherein the upper end of the hole (500) is exposed on the upper surface of the dielectric electric double layer group (200), and the lower end of the hole (500) is connected to each electric double layer; d. Depositing metal on the upper surface of the dielectric electric double layer group (200) so that the metal fills the inside of the hole (500) and forming a pad (300) on the upper surface of the dielectric electric double layer group (200).

5. The method for manufacturing an infrared thermopile sensor chip according to claim 4, characterized in that: The dielectric electric double layer group (200) comprises a first dielectric layer (211), a second dielectric layer (212), a third dielectric layer (213), a first electric double layer (221) and a second electric double layer (222); the first dielectric layer (211), the first electric double layer (221), the second dielectric layer (212), the second electric double layer (222) and the third dielectric layer (213) are arranged from bottom to top on the substrate layer (100); and the step c comprises the following steps: c1. Opening a hole above the second electric double layer (222), wherein the hole (500) above the second electric double layer (222) connects the upper surface of the third dielectric layer (213) and the second electric double layer (222); c2. A hole is opened above the first electric double layer (221), wherein the hole (500) above the first electric double layer (221) connects the upper surface of the third dielectric layer (213) and the first electric double layer (221).

6. The method for manufacturing an infrared thermopile sensor chip according to claim 5, characterized in that: The second electric double layer (222) has three electric double holes (222a), and the second electric double layer (222) is divided into two parts by the three electric double holes (222a), and each part corresponds to a welding pad (300).

7. The method for manufacturing an infrared thermopile sensor chip according to claim 5, characterized in that: The back cavity (400) comprises a substrate cavity (410), a dielectric hole (420) and a first galvanic cavity (430) which are connected in sequence, and the step e comprises the following steps: e1. Etching the substrate layer (100) to form a substrate cavity (410) on the substrate layer (100) that penetrates the substrate layer (100); e2, corroding the second electric double layer (222) in the dielectric hole (420); e3. Etching the first electric double layer (221) along the dielectric hole (420) to form a first electric double cavity (430) on the first electric double layer (221) that penetrates the first electric double layer (221).

8. A structure of an infrared thermopile sensor chip, characterized in that: include: A substrate layer (100), the substrate layer (100) having an upper surface (110) and a lower surface (120); A dielectric electric double layer group (200), the dielectric electric double layer group (200) comprising a first dielectric layer (211) and a first electric double layer (221), the first dielectric layer (211) being located between the substrate layer (100) and the first electric double layer (221); A back cavity (400) is provided on the lower surface of the substrate layer (100), and the back cavity (400) penetrates the substrate layer (100), the first dielectric layer (211) and the second dielectric layer (212).

9. The structure of the infrared thermopile sensor chip according to claim 8, characterized in that: The back cavity (400) comprises: A substrate cavity (410), wherein the substrate cavity (410) penetrates the substrate layer (100); A dielectric hole (420), wherein the dielectric hole (420) penetrates the first dielectric layer (211); A first electric couple cavity (430), the first electric couple cavity (430) penetrates the first electric double layer (221), and the first electric couple cavity (430) corresponds to the dielectric hole (420).

10. The structure of the infrared thermopile sensor chip according to claim 8, characterized in that: Also includes: A soldering pad (300) is arranged on the upper surface of the dielectric electric double layer group (200), and the soldering pad (300) is connected to each electric double layer of the dielectric electric double layer group (200).

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