All-silicon vertical leadless packaging structure and preparation method thereof

Abstract

The invention relates to an all-silicon vertical leadless packaging structure and a preparation method thereof, the all-silicon vertical leadless packaging structure comprises a sensor chip, the sensor chip is connected to a ceramic substrate through a highly-doped silicon vertical conductive structure, the ceramic substrate is connected with a conductive pin, and the conductive pin is electrically connected with the highly-doped silicon vertical conductive structure. The outer sides of the sensor chip, the highly-doped silicon vertical conductive structure and the ceramic substrate are connected with an alloy shell; the sensor chip adopts an SOI (Silicon On Insulator) silicon wafer and a P-type highly-doped low-resistivity silicon wafer for a highly-doped silicon vertical conductive structure; according to the invention, a full-silicification packaging structure without participation of metal or conductive solder can be realized, and the packaging structure is suitable for application in an ultra-high-temperature environment, has the advantages of simple manufacturing process, stable electrical connection, low cost and the like, and is easy for mass production.

Description

Technical Field

[0001] The invention belongs to the technical field of sensor packaging, and in particular relates to an all-silicon vertical leadless packaging structure and a preparation method thereof. Background Art

[0002] In the field of high-temperature pressure measurement, the packaging structure has an important influence on the performance, stability and service life of the sensor. In high-temperature environments, most of the packaging structures used at home and abroad are currently two types: one is the packaging method of oil-filled packaging to protect the gold wire leads, and the other is the leadless packaging method of adding conductive solder to the glass through-hole after silicon-glass bonding. Since silicone oil has a certain thermal expansion coefficient, the volume of silicone oil will expand greatly in the oil-filled packaging method to protect the gold wire leads in an environment exceeding 200°C, resulting in liquid leakage, damage to the packaging structure, failure of the sensor electrical connection, and reduced service life of the sensor; at the same time, the oil-filled packaging process is relatively complicated and has a high preparation cost, which limits its mass production.

[0003] The traditional leadless packaging structure ([1] Li Junlong, Zhu Ping, Design of leadless packaged SOI piezoresistive pressure sensor [J]. Instrument Technology and Sensor, 2017(12):20-24; [2] Xu Jiao, Zhao Chenxi, Yang Jian, et al., Research on leadless packaging of high-temperature pressure sensor [J]. Telemetry and Remote Control, 2023,44(6):126-131; [3] Dong Zhichao, Lei Cheng, Liang Ting, et al., Research on leadless flip-chip packaging of SOI high-temperature pressure sensor [J]. Sensors and Microsystems, 2021,40(11):65-68.) uses the method of bonding silicon wafer to glass substrate. The airtightness of the package is achieved by using a through hole, and a through hole is opened on the glass substrate, and the hole is filled with conductive solder as an electrical connection; however, due to the inconsistency of the thermal expansion coefficients of the silicon wafer and the glass over a wide temperature range, when the ambient temperature changes from high temperature to low temperature, residual thermal stress will be generated at the bonding interface, which will cause cracks on the interface over a long period of time, destroying the cavity structure and seriously affecting the service life of the sensor; at the same time, the filling of the conductive solder is directly related to the effectiveness and stability of the sensor's electrical connection. Therefore, when filling the conductive solder in the glass through hole, the material, quality and uniformity of the conductive solder must be strictly selected, which increases the complexity of the package. Therefore, simplifying the packaging process while ensuring the stability of the electrical connection at ultra-high temperatures is a key technical difficulty that needs to be overcome in the high-temperature sensor packaging structure. Summary of the invention

[0004] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide an all-silicon vertical leadless packaging structure and a preparation method thereof, which can realize a fully siliconized packaging structure without the participation of metal or conductive solder, is suitable for application in ultra-high temperature environments, has the advantages of simple manufacturing process, stable electrical connection, low cost, etc., and is easy to mass produce.

[0005] In order to achieve the above object, the technical solution of the present invention is as follows:

[0006] A full silicon vertical leadless packaging structure includes a sensor chip 1, which is connected to a ceramic substrate 3 via a highly doped silicon vertical conductive structure 2, to which a conductive pin 4 is connected, and the conductive pin 4 is electrically connected to the doped silicon vertical conductive structure 2, and an alloy shell 5 is connected to the outside of the sensor chip 1, the highly doped silicon vertical conductive structure 2, and the ceramic substrate 3.

[0007] The sensor chip 1 comprises, from top to bottom, a device layer, an insulating layer and a supporting layer; wherein the device layer comprises four P-type doped piezoresistive strips 1-1 and five P-type highly doped silicon leads 1-2, the four P-type doped piezoresistive strips 1-1 are sequentially connected through the five P-type highly doped silicon leads 1-2 to form a Wheatstone bridge; adjacent P-type highly doped silicon leads 1-2 are separated by dividing slits; the supporting layer is provided with a square mass block 1-4 and a supporting frame 1-5, the area between the square mass block 1-4 and the supporting frame 1-5 is a stress concentration area, and the P-type doped piezoresistive strip 1-1 is arranged in the stress concentration area; the insulating layer 1-3 is located between the device layer and the supporting layer, and the material is SiO2, so as to realize electrical insulation between the device layer and the supporting layer.

[0008] The sensor chip 1 is made of SOI silicon wafer.

[0009] The device layer is single crystal silicon with a (100) crystal plane, and the four P-type doped piezoresistive strips 1-1 have the same crystal orientation, all along the

[011] crystal orientation.

[0010] The highly doped silicon vertical conductive structure 2 uses a P-type highly doped low resistivity silicon wafer, and the highly doped silicon vertical conductive structure 2 is connected to the P-type highly doped silicon lead 1-2 by anode bonding; the highly doped silicon vertical conductive structure 2 includes five highly doped silicon vertical wires 2-2 corresponding to the five P-type highly doped silicon leads 1-2, and the five highly doped silicon vertical wires 2-2 form a cavity 2-1; adjacent highly doped silicon vertical wires 2-2 are separated by dividing line segments 2-3, and the dividing line segments 2-3 are filled with SiO2 to achieve insulation between the highly doped silicon vertical wires 2-2; at the same time, after bonding, the surface of the highly doped silicon vertical conductive structure 2 is electroplated with point electrodes 2-4.

[0011] The conductive pin 4 is fixedly connected to the ceramic substrate 3 through a through hole by glass welding. An electrode pad is provided at the contact point between the top of the conductive pin 4 and the ceramic substrate 3. A layer of flux is coated on the electrode pad. The electrode pad is aligned and fitted with the point electrodes 2-4 on the surface of the highly doped silicon vertical conductive structure 2, and then the two are welded together by reflow soldering to achieve electrical connection from the sensor to the external device.

[0012] The ceramic substrate 3 is fixedly connected to the highly doped silicon vertical conductive structure 2 by sintering with glass glue.

[0013] The alloy shell 5 is bonded to the ceramic substrate 3 by high temperature epoxy adhesive.

[0014] The method for preparing the all-silicon vertical leadless packaging structure comprises the following steps:

[0015] (1) Cleaning the highly doped silicon vertical conductive structure 2 using standard RCA to remove impurities attached to the surface;

[0016] (2) wet-etching the highly doped silicon vertical conductive structure 2 to form a cavity 2-1 for the sensor chip 1 to move;

[0017] (3) using ICP technology to carve a dividing line segment 2 - 3 on the side of the highly doped silicon vertical conductive structure 2 containing the cavity 2 - 1 ;

[0018] (4) The sensor chip 1 is made of SOI silicon wafer, and the P-type highly doped silicon lead 1-2 of the sensor chip 1 is aligned with one side of the cavity 2-1 of the highly doped silicon vertical conductive structure 2 by using anodic bonding technology, and then bonded and connected;

[0019] (5) thinning the highly doped silicon vertical conductive structure 2 until the previously etched segmentation line 2-3 is exposed, the segmentation line 2-3 divides the highly doped silicon vertical conductive structure 2 into five highly doped silicon vertical conductive wires 2-2, and the highly doped silicon vertical conductive wires 2-2 correspond to the P-type highly doped silicon leads 1-2 of the device layer respectively;

[0020] (6) using PECVD technology to fill SiO2 in the dividing line segments 2-3 between the highly doped silicon vertical conductive structures 2 to achieve insulation between the highly doped silicon vertical conductive wires 2-2;

[0021] (7) using ICP to etch part of SiO2 on the surface of the highly doped silicon vertical conductive structure 2 to expose the area in contact with the electrode pad;

[0022] (8) electroplating metal on the surface of the highly doped silicon vertical conductive structure 2 by electroplating technology, and obtaining the point electrodes 2-4 after wet etching;

[0023] (9) Apply glass glue to the surface of the highly doped silicon vertical conductive structure 2 except for the point electrodes 2-4, and bond the ceramic substrate 3 to the surface of the highly doped silicon vertical conductive structure 2. After bonding, align the conductive pins 4 with the point electrodes 2-4 and weld them together by reflow soldering.

[0024] The shape of the dividing line segment 2-3 in step (3) is the same as the dividing slits between the five P-type highly doped silicon leads 1-2 on the device layer.

[0025] In step (8), the electroplated metal materials are three layers of Ti / Pt / Au metal in sequence.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention adopts a highly doped silicon vertical conductive structure 2 and anode bonding with the sensor chip 1 to achieve electrical connection in the vertical direction and airtightness of the packaging structure; in the traditional leadless packaging structure, a glass substrate containing a cavity is bonded to the sensor chip to achieve the airtightness of the packaging structure. Since the thermal expansion coefficients of glass and silicon are different in a wide temperature range, thermal stress will be generated at the bonding interface under thermal cycling, which has an adverse effect on the sensor packaging structure. However, the highly doped silicon vertical conductive structure 2 and the device layer of the sensor chip 1 of the present invention are both made of silicon material, and the thermal expansion coefficients of the same materials are the same, so thermal stress will not appear at the silicon-silicon bonding interface, thereby avoiding the problem of packaging failure caused by thermal cycling; at the same time, compared with the traditional leadless packaging that adopts the method of sintering conductive paste and conductive leads to achieve electrical connection, which has a complex process and high cost, the present invention adopts a highly doped silicon vertical conductive structure 2 as a vertical lead, and completes the electrical connection by welding a metal sputtering point electrode to an electrode pad, which greatly simplifies the process steps and reduces the packaging cost while improving the stability and reliability of electrical transmission.

[0028] The present invention adopts SOI silicon wafer as the material of the sensor chip 1, thereby avoiding the problem of current leakage caused by breakdown of PN junction of traditional silicon wafer when the temperature exceeds 150° C., and improving the operating temperature of the sensor.

[0029] The device layer of the sensor chip of the present invention adopts a method of replacing the metal sputtering lead with a P-type highly doped silicon lead 1-2, thereby avoiding the problem that the metal sputtering lead undergoes a metallization reaction at high temperature to produce intermetallic compounds, thereby increasing the circuit resistance and reducing the sensor output; at the same time, it also greatly simplifies the preparation process of the sensor chip, which is very suitable for mass production.

[0030] Compared with the prior art, the packaging structure of the present invention adopts a highly doped silicon vertical conductive structure and an all-silicon design of the sensor chip, so that the sensor failure problem caused by metallization reaction will not occur under ultra-high temperature. It has the characteristics of high temperature resistance, corrosion resistance, high precision, high linearity, high stability, low cost, etc., and is suitable for mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a partial cross-sectional isometric schematic diagram of the packaging structure of the present invention.

[0032] Figure 2 It is an axonometric diagram of the structure after bonding the highly doped silicon vertical conductive structure of the sensor of the present invention to the chip.

[0033] Figure 3This is a schematic diagram of the front axonometric view of the sensor chip of the present invention.

[0034] Figure 4 This is a schematic diagram of the back side axonometric view of the sensor chip of the present invention.

[0035] Figure 5 It is a schematic cross-sectional isometric view of the back side of the highly doped silicon vertical conductive structure of the present invention.

[0036] Figure 6 This is a front axonometric schematic diagram of the highly doped silicon vertical conductive structure of the present invention.

[0037] Figure 7 Schematic diagram of the method for preparing the packaging structure of the present invention: Figure (a) is a schematic diagram of the P-type highly doped low-resistivity silicon wafer used in the preparation method; Figure (b) is a schematic diagram of wet etching cavity; Figure (c) is a schematic diagram of dry etching dividing line segments; Figure (d) is a schematic diagram of bonding; Figure (e) is a schematic diagram of thinning the P-type highly doped low-resistivity silicon wafer; Figure (f) is a schematic diagram of depositing silicon dioxide; Figure (g) is a schematic diagram of etching local silicon dioxide; Figure (h) is a schematic diagram of sputtering point electrodes; Figure (i) is a schematic diagram of sintering and welding fixation. DETAILED DESCRIPTION

[0038] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0039] Reference Figure 1 , Figure 2 , an all-silicon vertical leadless packaging structure, including a sensor chip 1, a highly doped silicon vertical conductive structure 2, a ceramic substrate 3, a conductive pin 4 and an alloy shell 5, the sensor chip 1 is connected to the ceramic substrate 3 via the highly doped silicon vertical conductive structure 2, the ceramic substrate 3 is connected to the conductive pin 4, the conductive pin 4 is electrically connected to the doped silicon vertical conductive structure 2, and the alloy shell 5 is connected to the outside of the sensor chip 1, the highly doped silicon vertical conductive structure 2 and the ceramic substrate 3.

[0040] Reference Figure 3 , Figure 4The sensor chip 1 comprises a device layer, an insulating layer and a supporting layer from top to bottom; wherein the device layer comprises four P-type doped piezoresistive strips 1-1 and five P-type highly doped silicon leads 1-2, the P-type doped piezoresistive strips 1-1 are respectively along the crystal direction with the largest piezoresistive coefficient of the (100) crystal plane, the four P-type doped piezoresistive strips 1-1 have the same crystal direction, all along the

[011] crystal direction, the four P-type doped piezoresistive strips 1-1 are sequentially connected through five P-type highly doped silicon leads 1-2 to form a Wheatstone bridge, the P-type doped piezoresistive strips 1-1 and the P-type highly doped silicon leads 1-2 are connected in sequence to form a Wheatstone bridge, the P-type doped piezoresistive strips 1-1 and the P-type highly doped silicon leads 1-2 are connected to the P-type highly doped silicon leads 1-2. 2 constitutes the sensitive circuit of the sensor chip 1; adjacent P-type highly doped silicon leads 1-2 are separated by a dividing slit of about 30 μm to prevent the P-type highly doped silicon leads 1-2 from being directly connected to cause a short circuit; the support layer is provided with a square mass block 1-4 and a support frame 1-5, the area between the square mass block 1-4 and the support frame 1-5 is a stress concentration area, and the P-type doped piezoresistive strip 1-1 is arranged in the stress concentration area; the insulating layer 1-3 is located between the device layer and the support layer, and the material is SiO2 to achieve electrical insulation between the device layer and the support layer.

[0041] Reference Figure 5 , Figure 6 The highly doped silicon vertical conductive structure 2 uses a P-type highly doped low-resistivity silicon wafer. The highly doped silicon vertical conductive structure 2 is connected to the P-type highly doped silicon lead 1-2 by anodic bonding. In order to achieve alignment and ensure the stability of circuit conduction in the vertical direction, the highly doped silicon vertical conductive structure 2 includes five highly doped silicon vertical wires 2-2 corresponding to the five P-type highly doped silicon leads 1-2. The five highly doped silicon vertical wires 2-2 form a cavity 2-1. There are dividing line segments 2-3 of about 60 μm between adjacent highly doped silicon vertical wires 2-2. SiO2 is filled in the dividing line segments 2-3 to achieve insulation between the highly doped silicon vertical wires 2-2 and prevent the highly doped silicon vertical wires 2-2 from interconnecting and causing a short circuit. At the same time, after bonding, the surface of the highly doped silicon vertical conductive structure 2 is electroplated with point electrodes 2-4.

[0042] The conductive pin 4 is fixedly connected to the ceramic substrate 3 through a through hole by glass welding. An electrode pad is provided at the contact point between the top of the conductive pin 4 and the ceramic substrate 3. A layer of flux is coated on the electrode pad. The electrode pad is aligned and fitted with the point electrodes 2-4 on the surface of the highly doped silicon vertical conductive structure 2, and then the two are welded together by reflow soldering to achieve electrical connection from the sensor to the external device.

[0043] The ceramic substrate 3 is fixedly connected to the highly doped silicon vertical conductive structure 2 by sintering with glass glue, so as to achieve a compact internal structure.

[0044] The alloy shell 5 is bonded to the ceramic substrate 3 by high temperature epoxy adhesive to complete the packaging.

[0045] Reference Figure 7The method for preparing the all-silicon vertical leadless packaging structure comprises the following steps:

[0046] (1)Reference Figure 7 In (a), the highly doped silicon vertical conductive structure 2 is cleaned by standard RCA to remove impurities attached to the surface;

[0047] (2)Reference Figure 7 (b) in which the highly doped silicon vertical conductive structure 2 is wet-etched to form a cavity 2-1 for the sensor chip 1 to move;

[0048] (3)Reference Figure 7 In (c), the ICP technology is used to etch a dividing line segment 2-3 on the side of the high-doped silicon vertical conductive structure 2 containing the cavity 2-1, and the etching depth is about 2 / 3 of the thickness of the silicon wafer; the shape of the dividing line segment 2-3 is the same as the dividing slits between the five P-type high-doped silicon leads 1-2 on the device layer;

[0049] (4)Reference Figure 7 In (d), the sensor chip 1 is made of SOI silicon wafer, and the P-type highly doped silicon lead 1-2 of the sensor chip 1 is aligned with one side of the cavity 2-1 of the highly doped silicon vertical conductive structure 2 by using anodic bonding technology and then bonded;

[0050] (5)Reference Figure 7 In (e), the highly doped silicon vertical conductive structure 2 is thinned until the previously etched segment 2-3 is exposed, and the segment 2-3 divides the highly doped silicon vertical conductive structure 2 into five highly doped silicon vertical conductive wires 2-2, and the highly doped silicon vertical conductive wires 2-2 correspond to the P-type highly doped silicon leads 1-2 of the device layer, respectively, as vertical conductive wires;

[0051] (6)Reference Figure 7 In (f), SiO2 is filled in the dividing line segments 2-3 between the highly doped silicon vertical conductive structures 2 using PECVD technology to achieve insulation between the highly doped silicon vertical conductive wires 2-2;

[0052] (7)Reference Figure 7 In (g), ICP is used to etch part of SiO2 on the surface of the highly doped silicon vertical conductive structure 2 to expose the area in contact with the electrode pad;

[0053] (8)Reference Figure 7 In (h), metal is electroplated on the surface of the highly doped silicon vertical conductive structure 2 by electroplating technology, and point electrodes 2-4 are obtained after wet etching; the electroplated metal materials are three layers of Ti / Pt / Au metal in sequence;

[0054] (9)Reference Figure 7In (i), glass glue is applied to the surface of the highly doped silicon vertical conductive structure 2 except for the point electrodes 2-4, and the ceramic substrate 3 is bonded to the surface of the highly doped silicon vertical conductive structure 2. After bonding, the conductive pins 4 are aligned with the point electrodes 2-4 and the two are welded and fixedly connected by reflow soldering.

[0055] The present invention proposes for the first time to use a highly doped silicon vertical conductive structure 2 to bond a sensor chip 1 by anode bonding to achieve electrical connection in the vertical direction and airtightness of the packaging structure. In the conventional leadless packaging structure, a glass substrate containing a cavity 2-1 is bonded to the sensor chip 1 to achieve airtightness of the packaging structure. Since the thermal expansion coefficients of glass and silicon are different in a wide temperature range, thermal stress will be generated at the bonding interface under thermal cycles, which will have an adverse effect on the sensor packaging structure. However, the highly doped silicon vertical conductive structure 2 and the device layer of the sensor chip 1 of the present invention are both made of silicon material, and the thermal expansion coefficients of the same materials are the same, so thermal stress will not appear at the silicon-silicon bonding interface, thus avoiding the problem of packaging failure caused by thermal cycles. At the same time, compared with the conventional leadless packaging, which uses a conductive paste and a conductive lead sintering method to achieve electrical connection, the process is complex and the cost is high. The present invention uses a highly doped silicon vertical conductive structure 2 as a vertical lead, and completes the electrical connection by reflow soldering the electroplated point electrode 2-4 with the electrode pad, which greatly simplifies the process steps and reduces the packaging cost while improving the stability and reliability of electrical transmission.

[0056] The present invention adopts SOI silicon wafer as the material of the sensor chip 1, thereby avoiding the problem of current leakage caused by breakdown of PN junction of traditional silicon wafer when the temperature exceeds 150° C., and improving the operating temperature of the sensor.

[0057] The device layer of the sensor chip of the present invention adopts a method of replacing metal sputtering wires with highly doped silicon wires, thereby avoiding the problem that the metal sputtering wires undergo metallization reactions at high temperatures to produce intermetallic compounds, thereby increasing circuit resistance and reducing sensor output; at the same time, it also greatly simplifies the preparation process of the sensor chip, making it very suitable for mass production.

[0058] The above is only one embodiment of the present invention, not all or the only embodiment. Any equivalent changes made to the technical solution of the present invention by ordinary technicians in this field after reading the specification of the present invention are covered by the claims of the present invention.

Claims

1. An all-silicon vertical leadless package structure, comprising a sensor chip (1), characterized in that: The sensor chip (1) is connected to a ceramic substrate (3) via a highly doped silicon vertical conductive structure (2); a conductive pin (4) is connected to the ceramic substrate (3); the conductive pin (4) and the doped silicon vertical conductive structure (2) are electrically connected; and an alloy shell (5) is connected to the outside of the sensor chip (1), the highly doped silicon vertical conductive structure (2) and the ceramic substrate (3).

2. The all-silicon vertical leadless packaging structure according to claim 1, characterized in that: The sensor chip (1) comprises, from top to bottom, a device layer, an insulating layer, and a support layer; The device layer comprises four P-type doped piezoresistive strips (1-1) and five P-type highly doped silicon leads (1-2); the four P-type doped piezoresistive strips (1-1) are sequentially connected through the five P-type highly doped silicon leads (1-2) to form a Wheatstone bridge; adjacent P-type highly doped silicon leads (1-2) are separated by a dividing slit; the support layer is provided with a square mass block (1-4) and a support frame (1-5); the area between the square mass block (1-4) and the support frame (1-5) is a stress concentration area, and the P-type doped piezoresistive strips (1-1) are arranged in the stress concentration area; the insulating layer (1-3) is located between the device layer and the support layer, and the material is SiO2, so as to realize electrical insulation between the device layer and the support layer.

3. The all-silicon vertical leadless packaging structure according to claim 1, characterized in that: The sensor chip (1) adopts an SOI silicon wafer.

4. The all-silicon vertical leadless packaging structure according to claim 1, characterized in that: The device layer is single crystal silicon with a (100) crystal plane, and the four P-type doped piezoresistive strips (1-1) have the same crystal orientation, all along the [011] crystal orientation.

5. The all-silicon vertical leadless packaging structure according to claim 2, characterized in that: The highly doped silicon vertical conductive structure (2) uses a P-type highly doped low resistivity silicon wafer, and the highly doped silicon vertical conductive structure (2) is connected to the P-type highly doped silicon lead (1-2) by anodic bonding; the highly doped silicon vertical conductive structure (2) comprises five highly doped silicon vertical wires (2-2) corresponding to the five P-type highly doped silicon leads (1-2), and the five highly doped silicon vertical wires (2-2) form a cavity (2-1); adjacent highly doped silicon vertical wires (2-2) are separated by a dividing line segment (2-3), and the dividing line segment (2-3) is filled with SiO2 to achieve insulation between the highly doped silicon vertical wires (2-2); and at the same time, after bonding, the surface of the highly doped silicon vertical conductive structure (2) is electroplated with a dot electrode (2-4).

6. The all-silicon vertical leadless packaging structure according to claim 5, characterized in that: The conductive pin (4) is fixedly connected to the ceramic substrate (3) through a through hole by glass welding. An electrode pad is provided at the contact point between the top of the conductive pin (4) and the ceramic substrate (3). A layer of flux is coated on the electrode pad. The electrode pad is aligned and fitted with the point electrode (2-4) on the surface of the highly doped silicon vertical conductive structure (2). The two are then welded together by reflow soldering to achieve electrical connection from the sensor to an external device.

7. The all-silicon vertical leadless packaging structure according to claim 1, characterized in that: The ceramic substrate (3) is fixedly connected to the highly doped silicon vertical conductive structure 2 by sintering with glass glue.

8. The all-silicon vertical leadless packaging structure according to claim 1, characterized in that: The alloy shell (5) is bonded to the ceramic substrate (3) by means of high-temperature epoxy adhesive.

9. The method for preparing the all-silicon vertical leadless packaging structure according to any one of claims 1 to 8, characterized in that: The following steps are involved: 1) Cleaning the highly doped silicon vertical conductive structure (2) using standard RCA to remove impurities attached to the surface; 2) wet-etching the highly doped silicon vertical conductive structure (2) to etch out a cavity (2-1) for the sensor chip (1) to move; 3) using ICP technology to carve a dividing line segment (2-3) on one side of the highly doped silicon vertical conductive structure (2) containing the cavity (2-1); 4) The sensor chip (1) uses an SOI silicon wafer, and uses an anodic bonding technique to align the P-type highly doped silicon lead (1-2) of the sensor chip (1) with one side of the cavity (2-1) of the highly doped silicon vertical conductive structure (2) and then bond them together; 5) thinning the highly doped silicon vertical conductive structure (2) until the previously etched dividing line segment (2-3) is exposed, the dividing line segment (2-3) divides the highly doped silicon vertical conductive structure (2) into five highly doped silicon vertical conductive lines (2-2), and the highly doped silicon vertical conductive lines (2-2) respectively correspond to the P-type highly doped silicon leads (1-2) of the device layer; 6) using PECVD technology to fill SiO2 in the dividing line segments (2-3) between the highly doped silicon vertical conductive structures (2) to achieve insulation between the highly doped silicon vertical conductive wires (2-2); 7) using ICP to etch part of SiO2 on the surface of the highly doped silicon vertical conductive structure (2) to expose the area in contact with the electrode pad; 8) electroplating metal on the surface of the highly doped silicon vertical conductive structure (2) by electroplating technology, and obtaining a point electrode (2-4) after wet etching; 9) Applying glass glue to the surface of the highly doped silicon vertical conductive structure (2) except for the point electrode (2-4), bonding the ceramic substrate (3) to the surface of the highly doped silicon vertical conductive structure (2), aligning the conductive pin (4) with the point electrode (2-4) after bonding, and welding the two together by reflow soldering.

10. The preparation method according to claim 9, characterized in that: In step 3), the shape of the dividing line segment (2-3) is the same as the dividing slits between the five P-type highly doped silicon leads (1-2) on the device layer; in step 8), the electroplated metal materials are three layers of Ti / Pt / Au metal in sequence.

Images