Array substrate, liquid crystal lens and display device

Abstract

The invention provides an array substrate, a liquid crystal lens and a display device, and relates to the technical field of display, the array substrate comprises a substrate and a first conductive layer located on one side of the substrate, and the first conductive layer comprises a plurality of first signal lines; the first signal line comprises a first slope region, a flat region and a second slope region which extend along a first direction and are sequentially arranged along a second direction; wherein the widths of the first slope region and the second slope region in the second direction are both greater than or equal to a quarter of the width of the first signal line in the second direction. The first signal line in the array substrate has a relatively smooth surface, so that the probability that other signal lines are broken when crossing the upper part of the first signal line can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a liquid crystal lens and a display device. Background Art

[0002] As a new type of optical device, liquid crystal lens is widely used in various fields. It uses the property of liquid crystal material to change the refractive index under the action of electric field to achieve the focusing and dispersion of light. When the electric field is applied to the liquid crystal lens, the directional arrangement of liquid crystal molecules will change, thereby changing the refractive index distribution of the liquid crystal lens, thereby achieving the modulation of light.

[0003] At present, there are technical difficulties in the preparation process of liquid crystal lenses, which causes circuit disconnection in the array substrate of the liquid crystal lens. Summary of the invention

[0004] Embodiments of the present application provide an array substrate, a liquid crystal lens, and a display device. A first signal line in the array substrate has a relatively flat surface, thereby reducing the probability of other signal lines being broken when crossing over the first signal line.

[0005] The embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides an array substrate, comprising:

[0007] substrate;

[0008] A first conductive layer located at one side of the substrate, the first conductive layer comprising a plurality of first signal lines, the first signal lines comprising a first slope region, a flat region, and a second slope region extending along a first direction and sequentially arranged along a second direction;

[0009] The widths of the first slope region and the second slope region along the second direction are both greater than or equal to one quarter of the width of the first signal line along the second direction.

[0010] In some array substrates provided by embodiments of the present application, a portion of a surface of the first signal line away from the substrate and located in the flat area is substantially parallel to the substrate;

[0011] A first angle is formed between a portion of the first slope region and the substrate on a surface of the first signal line away from the substrate, and a second angle is formed between a portion of the second slope region and the substrate on a surface of the first signal line away from the substrate. The first angle and the second angle are in the range of 5° to 50°.

[0012] In some array substrates provided in embodiments of the present application, the width of the first slope region along the second direction is substantially equal to the width of the second slope region along the second direction, and the first angle is substantially equal to the second angle.

[0013] In some array substrates provided in the embodiments of the present application, the array substrate further includes:

[0014] A second conductive layer is located on a side of the first conductive layer away from the substrate, the second conductive layer comprises a plurality of second signal lines, and the second signal lines overlap with the first signal lines;

[0015] A first insulating layer, located between the first conductive layer and the second conductive layer, having a plurality of first through holes;

[0016] Among them, the second signal line includes a first line segment and a second line segment, the first line segment is consistent with the extension direction of the first signal line, the second line segment intersects with the extension direction of the first signal line, and the first line segment is electrically connected to the first signal line through the first through hole; at least a part of the positive projection of the first through hole on the first signal line falls into the slope area.

[0017] In some array substrates provided in embodiments of the present application, along the second direction, the distance between the center of the first through hole and one side of the first line segment is not equal to the distance between the center of the first through hole and the other side of the first line segment.

[0018] In some array substrates provided in embodiments of the present application, the orthographic projection of the first through hole on the first signal line falls into the first slope area.

[0019] In some array substrates provided in embodiments of the present application, a portion of the orthographic projection of the first through hole on the first signal line falls into the first slope area, and another portion of the orthographic projection of the first through hole on the first signal line falls into the flat area.

[0020] In some array substrates provided in embodiments of the present application, the orthographic projection of the first through hole on the first signal line falls into the second slope area.

[0021] In some array substrates provided in embodiments of the present application, the orthographic projection of the first through hole on the first signal line falls into the second slope area, and another part of the orthographic projection of the first through hole on the first signal line falls into the flat area.

[0022] In some array substrates provided by embodiments of the present application, the plurality of second signal lines include a plurality of driving electrode line groups, and the driving electrode line groups include a plurality of driving electrode lines that transmit signals that are not completely the same;

[0023] The plurality of first signal lines include a plurality of parallel lines; the parallel lines are used to electrically connect the driving electrode lines with the same transmission signals in different driving electrode line groups.

[0024] In some array substrates provided in the embodiments of the present application, the array substrate comprises a display area, a first line collection area and a second line collection area respectively located on two opposite sides of the display area, and a signal introduction area located on a side of the first line collection area away from the display area;

[0025] The plurality of parallel routing lines include a first parallel routing line and a second parallel routing line, the first wiring collection area is provided with a plurality of the first parallel routing lines, and the second wiring collection area is provided with a plurality of the second parallel routing lines;

[0026] A plurality of the driving electrode line groups are arranged in the display area; the plurality of driving electrode lines extend from the display area to the first line collection area and the second line collection area respectively, and are electrically connected to the first parallel wiring and the second parallel wiring respectively;

[0027] The number of the first parallel wirings, the number of the second parallel wirings, and the number of the driving electrode lines in the same driving electrode line group are equal.

[0028] In some array substrates provided in the embodiments of the present application, the signal introduction area includes:

[0029] A plurality of connecting wires located on the second conductive layer; the plurality of connecting wires extend from the signal introduction area to the first wiring collection area, and some of the connecting wires overlap with the orthographic projection of the first parallel wire on the substrate;

[0030] A plurality of signal lead-in wires are located on the first conductive layer; the first insulating layer has a plurality of second through holes, and the lapped wires are electrically connected to the signal lead-in wires through the second through holes;

[0031] The number of the plurality of overlapping wirings is the same as the number of the plurality of first parallel wirings.

[0032] In some array substrates provided in embodiments of the present application, the first insulating layer further includes a plurality of dummy vias disposed in the signal introduction region.

[0033] In some array substrates provided by embodiments of the present application, a total area of ​​the plurality of dummy via holes and the plurality of second through holes in the signal introduction region is substantially the same as an area of ​​the first through hole.

[0034] In a second aspect, an embodiment of the present application provides a liquid crystal lens, comprising an array substrate as described in any one of the first aspects, and further comprising a counter substrate and a liquid crystal layer located between the array substrate and the counter substrate.

[0035] In a third aspect, an embodiment of the present application provides a display device, comprising a display panel and a liquid crystal lens as described in the second aspect; the liquid crystal lens is arranged on a light emitting side of the display panel.

[0036] An embodiment of the present application provides an array substrate, a liquid crystal lens and a display device, wherein the array substrate includes a substrate and a first conductive layer located on one side of the substrate, the first conductive layer includes a plurality of first signal lines, the first signal lines include a first slope region, a flat region, and a second slope region extending along a first direction and arranged sequentially along a second direction; wherein the widths of the first slope region and the second slope region along the second direction are both greater than or equal to one quarter of the width of the first signal line along the second direction.

[0037] In the array substrate provided in the embodiment of the present application, a first signal line is provided including a first slope area, a flat area, and a second slope area extending along a first direction and arranged sequentially along a second direction, and the widths of the first slope area and the second slope area along the second direction are both greater than or equal to one quarter of the width of the first signal line along the second direction; since the widths of the two slope areas (including the first slope area and the second slope area) along the second direction are greater than or equal to half of the width of the first signal line along the second direction, the first signal line has a relatively flat surface, and when other signal lines are subsequently prepared on the first signal line, the probability of other signal lines breaking when crossing over the first signal line can be reduced, thereby improving the yield of the array substrate.

[0038] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A schematic diagram of a signal line break structure of an array substrate in a related technology provided in an embodiment of the present application;

[0041] Figure 2 A scanning electron microscope photograph of a signal line breakage of an array substrate in a related art provided in an embodiment of the present application;

[0042] Figure 3 A schematic diagram of a top view structure of an array substrate provided in an embodiment of the present application;

[0043] Figure 4 Figures (a) and (b) are microscope photos of over-etching of signal lines in two related technologies provided in the embodiments of the present application;

[0044] Figure 5 A schematic diagram of a cross-sectional structure of a first signal line provided in an embodiment of the present application;

[0045] Figure 6 and Figure 7 Scanning electron microscope photos of two first signal lines provided in the embodiments of the present application;

[0046] Figure 8 Etching speed analysis diagram of the signal line provided in the embodiment of the present application and the signal line in the related art;

[0047] Fig. 9 A top view of a local area of ​​an array substrate provided in an embodiment of the present application;

[0048] Fig.10 An analysis table of improvements to the signal line disconnection problem after changes to the design parameters or manufacturing process parameters provided in the embodiments of the present application;

[0049] Fig.11 A schematic diagram of a top view structure of another array substrate provided in an embodiment of the present application;

[0050] Figure 12 to Figure 15 A schematic diagram of a cross-sectional structure of an array substrate with four different arrangement positions of the first through hole provided in an embodiment of the present application;

[0051] Figures 16 to 20 An intermediate structural diagram of the preparation process of an array substrate with a first arrangement position of a first through hole provided in an embodiment of the present application;

[0052] Figure 21 to Figure 23 An intermediate structural diagram of the preparation process of an array substrate with a second arrangement position of the first through hole provided in an embodiment of the present application;

[0053] Figure 24 to Figure 26 An intermediate structural diagram of the preparation process of an array substrate with a third arrangement position of the first through hole provided in an embodiment of the present application;

[0054] Figure 27 to Figure 29This is an intermediate structural diagram during the preparation process of an array substrate with a fourth arrangement position of the first through hole provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0056] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0057] In the embodiments of the present application, the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0058] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" are intended to indicate that a specific feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0059] In the embodiments of the present application, “plurality” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0060] The features such as "parallel", "perpendicular", and "same" used in the embodiments of the present application include the features such as "parallel", "perpendicular", and "same" in a strict sense, as well as the cases where "approximately parallel", "approximately perpendicular", "approximately the same", etc. include certain tolerances, taking into account the tolerances related to the measurement of specific quantities (e.g., the limitations of the measurement system), and are expressed as being within the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of the value.

[0061] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0062] The polygon in this specification is not a strict polygon, and may be an approximate triangle, parallelogram, trapezoid, pentagon or hexagon, etc., and there may be some small deformations caused by tolerance.

[0063] In this specification, "electrically connected" and "coupled" include the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0064] In the related art, the wiring design space requirements of the array substrate are getting higher and higher. In order to increase the design space, it is usually achieved by reducing the line width or the distance between the lines. Figure 1 As shown in FIG. 1 , the line width of a trace (such as an ITO electrode) is L (also called Line), the distance between two adjacent traces is S (also called Space), and the sum of L and S is the line pitch (Pitch). In practical applications, as the line width (L) of the trace becomes smaller and smaller, the risk of the trace breaking is smaller when the trace is prepared on a relatively flat surface. However, for example Figure 1 In the area where ITO jumps over the gate, when thinner traces are prepared on a sloped surface, the risk of trace breakage is greatly increased. Figure 2 The scanning electron microscope (SEM) image shown shows that the ITO is broken at the climbing position. At the same time, due to the limitation of wiring space and the resolution of the exposure machine under the current situation, it is impossible to widen the ITO electrode at the climbing position for compensation.

[0065] Based on this, a new design is urgently needed to improve the above problems.

[0066] The embodiment of the present application provides the following technical solution: the first signal line in the array substrate has a relatively flat surface, thereby reducing the probability of other signal lines being broken when crossing over the first signal line.

[0067] The array substrate provided in the embodiments of the present application is explained and illustrated below with reference to the accompanying drawings.

[0068] An embodiment of the present application provides an array substrate, which includes:

[0069] Substrate 1;

[0070] The first conductive layer 2 is located on one side of the substrate 1, and the first conductive layer 2 includes a plurality of first signal lines 21, combined with Figure 3 and Figure 5 As shown, the first signal line 21 includes a first direction (eg Figure 3 The X direction in the figure) and along the second direction (e.g. Figure 3 The first slope area X1, the flat area P and the second slope area X2 are arranged in sequence (in the Y direction); wherein, Figure 5 for Figure 3 A schematic diagram of a cross-sectional structure of the first signal line 21 along the second direction (Y direction);

[0071] like Figure 5 As shown, the widths ( D1 and D2 ) of the first slope region X1 and the second slope region X2 along the second direction (Y direction) are both greater than or equal to one quarter of the width D of the first signal line 21 along the second direction (Y direction).

[0072] like Figure 5 As shown, the width of the first signal line 21 is D, the width of the left slope (first slope area X1) projected in a direction perpendicular to the substrate 1 is D1, the width of the right slope (second slope area X2) projected in a direction perpendicular to the substrate 1 is D2, and the width of the middle part (flat area P) is D3, D=D1+D2+D3.

[0073] Exemplarily, D1=D2>≥one quarter D.

[0074] Exemplarily, the substrate 1 may be a rigid substrate, such as a glass substrate or a silicon substrate.

[0075] The material of the first conductive layer 2 can be metal or metal oxide.

[0076] Exemplarily, the material of the first conductive layer 2 is molybdenum (Mo).

[0077] In an exemplary embodiment, the first direction and the second direction intersect, for example, the first direction and the second direction are perpendicular.

[0078] Since the widths (D1 and D2) of the first slope region X1 and the second slope region X2 along the second direction (Y direction) are both greater than or equal to one quarter of the width D of the first signal line 21 along the second direction (Y direction), the sum of the widths D1 and D2 of the first slope region X1 and the second slope region X2 along the second direction (Y direction) is greater than or equal to half of the width D of the first signal line 21 along the second direction (Y direction). In this way, the slope region in the first signal line 21 occupies at least half of the width, so that the first signal line 21 has a relatively gentle surface, and when other signal lines are subsequently prepared on the first signal line 21, the probability of other signal lines being broken when crossing over the first signal line 21 can be reduced, thereby improving the yield of the array substrate.

[0079] In some array substrates provided in the embodiments of the present application, such as Figure 5 As shown, the portion of the surface of the first signal line 21 away from the substrate 1 and located in the flat area P is substantially parallel to the substrate 1;

[0080] A first angle α is formed between a portion of the first signal line 21 located in the first slope area X1 and the substrate 1 on the surface away from the substrate 1, and a second angle β is formed between a portion of the first signal line 21 located in the second slope area X2 and the substrate 1 on the surface away from the substrate 1. The angle range of the first angle α and the second angle β is 5° to 50°.

[0081] For example, Figure 6 As shown, the first angle α is 8.26°, the second angle is 8.54°, and the first angle and the second angle are substantially equal.

[0082] For example, Figure 7 As shown, the first angle α is 19.41° and the second angle β is 18.01°

[0083] It should be noted that, in this specification, taking into account the measurement and the tolerances associated with the measurement of a particular quantity (e.g., the limitations of the measurement system), "approximately" means within an acceptable deviation range for a particular value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of the value.

[0084] In practical applications, the first signal line 21 is prepared by chemical liquid wet etching. Figure 6 or Figure 7As shown, a patterned photoresist (PR glue) is formed on the first conductive layer 2, and the first conductive layer 2 is etched using the patterned photoresist as a mask. By adjusting the composition ratio of the etching solution of the first conductive layer 2 (Mo), the phosphoric acid content in the etching solution is reduced, that is, the viscosity of the etching solution is reduced, so that the etching solution is easier to drill laterally, and a slope area with a wider size (such as D2 and D2) can be obtained. At the same time, it is also easy to make the slope angle (Profile) of the first signal line 21 very small.

[0085] The specific ratio of the etching solution is: 16% acetic acid, 2.5% nitric acid, 45-60% phosphoric acid, and the rest are additives and water.

[0086] In some array substrates provided in the embodiments of the present application, Figure 6 From the SEM photo of the cross-sectional schematic diagram of the first signal line 21 provided, it can be seen that the width D1 of the first slope area X1 along the second direction (Y direction) is approximately equal to the width D2 of the second slope area X2 along the second direction (Y direction), and the first angle α is approximately equal to the second angle β.

[0087] Among them, Figure 6 and Figure 7 In the SEM photo shown, the size of mark 1 is the width of the patterned photoresist (PR glue), the size of mark 2 is the width of the first signal line 21 obtained after actual etching, mark 3 is the first angle α, and mark 4 is the second angle β; the relevant values ​​are reflected in the upper left corner of the SEM photo.

[0088] exist Figure 6 In the figure, the width of the patterned photoresist (PR glue) is 6.6777 μm, the width of the first signal line 21 obtained after actual etching is 4.8874 μm, the first angle α is 8.26°, and the second angle β is 8.54°.

[0089] exist Figure 7 In the figure, the width of the patterned photoresist (PR glue) is 4.8503 μm, the width of the first signal line 21 obtained after actual etching is 3.5685 μm, the first angle α is 19.41°, and the second angle β is 18.01°.

[0090] In addition, when the array substrate is applied to a liquid crystal lens, Figure 3As shown, since the number of second signal lines 51 in the display area A is relatively large, the density of vias in the collection area (including B1 and B2) is much greater than the density of vias in the signal introduction area B3, so that in the process of forming vias in the insulating material using a dry etching process, the plasma consumption rate in the signal introduction area B3 is slower than that in the collection area, and the plasma density is larger than that in the collection area; thus, the insulating material in the signal introduction area B3 is easily etched at a faster rate, resulting in excessive etching of the conductive structure under the insulating material (such as the signal introduction line in the first conductive layer 2), and even causing the metal material under the via to be completely etched away.

[0091] Among them, the dry etching process is a process of removing materials by using plasma gas to undergo physical or chemical reactions with materials.

[0092] like Figure 4 Figures (a) and (b) provide schematic diagrams of over-etching of the signal lead-in line under the via, where some areas are set to have the phenomenon of light penetration. In addition, in order to achieve better optical effects in liquid crystal lenses, low-reflection metals are usually used to prepare the wiring, such as molybdenum (Mo), which is easier to be dry-etched and more prone to over-etching.

[0093] In order to improve the above problems, the inventors have conducted multiple test solutions, such as Fig.10 As shown in FIG. 1 , the adjustment is made by changing the design parameters or process parameters of the first signal line (Gate, the first conductive layer) or the second signal line (ITO, the second conductive layer). For the first signal line (Gate), the film thickness can be reduced (from 2200nm to 800nm) and the profile can be changed (Profile reduction). Fig.10 As can be seen, both methods have improved the problem of over-etching. In comparison, changing the profile (reducing the Profile) has a very significant improvement effect. For the second signal line (ITO), the film thickness can be reduced (ITO THK, from 700nm to 400nm) by changing the Target Life, changing the cleaning process of the mask of the second signal line 51 (the cleaning liquid is changed from water to TMAH), and increasing the thickness of the PR glue on the second signal line 51 (from 1.5μm to 2.2μm). In summary, it can be seen that changing the outer profile of the first signal line 21 has the best effect on improving the above problems.

[0094] Based on this, in the embodiment of the present application, the pattern of the via hole in the collection area is completely made on the slope on the side of the first signal line 21 in the collection area; or, part of the pattern of the via hole in the collection area is made on the slope on the side of the first signal line 21 in the collection area. In this way, the above-mentioned via hole problem can be improved, and the specific explanation is as follows.

[0095] In some array substrates provided in the embodiments of the present application, Figure 3 , Fig. 9 ,as well as Figure 12 to Figure 15 As shown, the array substrate further includes:

[0096] The second conductive layer 5 is located on a side of the first conductive layer 2 away from the substrate 1. The second conductive layer 5 includes a plurality of second signal lines 51. The second signal lines 51 overlap with the first signal lines 21.

[0097] The first insulating layer 3 is located between the first conductive layer 2 and the second conductive layer 5 and has a plurality of first through holes 31;

[0098] Among them, Fig. 9 As shown, the second signal line 51 includes a first line segment XD1 and a second line segment XD2, the first line segment XD1 and the first signal line 21 extend in the same direction (for example, both extend in the X direction), the second line segment XD2 (for example, extends in the Y direction) intersects with the extension direction of the first signal line 21, and the first line segment XD1 is electrically connected to the first signal line 21 through the first through hole 31;

[0099] like Figure 12 to Figure 15 As shown, at least a portion of the orthographic projection of the first through hole 31 on the first signal line 21 falls into the slope region (the first slope region X1 or the second slope region X2 ).

[0100] In an exemplary embodiment, the material of the second conductive layer 5 includes metal or metal oxide.

[0101] For example, the material of the second conductive layer 5 includes metal oxide. In the present specification, the material of the second conductive layer 5 is indium tin oxide (ITO) as an example for description.

[0102] The case where at least a portion of the orthographic projection of the first through hole 31 on the first signal line 21 falls into the slope area (the first slope area X1 or the second slope area X2) includes the following situations:

[0103] For example, Fig.14 and Fig.15 As shown, a partial area of ​​the orthographic projection of the first through hole 31 on the first signal line 21 falls into the slope area (the first slope area X1 or the second slope area X2);

[0104] For example, Fig.12 and Fig.13 As shown, the entire area of ​​the orthographic projection of the first through hole 31 on the first signal line 21 falls into the slope region (the first slope region X1 or the second slope region X2).

[0105] In the embodiment of the present application, by setting at least a part of the orthographic projection of the first through hole 31 on the first signal line 21 to fall into the slope area, due to the leveling effect of the material of the first insulating layer 3, such as Figure 8 As shown, the thickness d1 of the first insulating layer 3 in the slope area (area B) is smaller than the thickness d of the first insulating layer 3 in area C in the related art. In this way, during the dry etching process, the plasma concentration consumption rate in the collection area where the first signal line 21 is located is slowed down, so that it tends to be consistent with the plasma concentration in the signal introduction area B3, thereby improving the problem of excessive etching of the signal introduction area routing caused by the inconsistent via density and plasma concentration difference mentioned above.

[0106] Specific, combined Figure 8 As shown, assuming that the length of the positive projection of region B of the first insulating layer 3 on the slope of the first signal line 21 on one side of the collection area on the substrate 1 is L, and the corresponding region C of the first insulating layer 3 on the signal lead-in line 22 in the signal lead-in area of ​​the same length L, the length of the slope on one side of the first signal line 21 in the collection area is L1, and the thickness of the first insulating layer 1 in region B is d1; assuming that the thickness of region B and region C along the direction perpendicular to the cross section is 1, and the film thickness of the first insulating layer 3 in region C is d, it is easy to know that the film thickness of the first insulating layer 3 at the non-slope position on the first signal line 21 in the collection area is also d; according to the PECVD film forming principle, it can be known that for the same time, the volume of the insulating layer in region B and region C is equal, that is: L1×d1×1=L×d×1, assuming that the first angle α of the first signal line 21 in the collection area is 30° at this time, it is easy to know:

[0107]

[0108] It can be seen from this that the thickness d1 of the first insulating layer 3 in area B is smaller than the thickness d of the first insulating layer 3 on the signal introduction line 22 in the signal introduction area B3. It can be seen that the first insulating layer 3 on the slope of the first signal line 21 in the collection area will be etched to the bottom faster. In addition, combined with the difference in via density between the two areas, the concentration of plasma can be balanced during the etching process, so that the etching speed areas in the two areas are consistent, thereby improving the problem of excessive etching of the signal introduction area routing caused by the inconsistent via density and plasma concentration differences mentioned above.

[0109] In some array substrates provided in the embodiments of the present application, such as Fig. 9 As shown, along the second direction (Y direction), the distance H1 from the center of the first through hole 31 to one side of the first line segment XD1 is not equal to the distance H2 from the center of the first through hole 31 to the other side of the first line segment XD1.

[0110] For example, Fig. 9As shown, the first through hole 31 is disposed at a position close to the lower side of the first line segment XD1.

[0111] For example, the first through hole 31 may be disposed at a position close to an upper side of the first line segment XD1 .

[0112] in, Figure 12 to Figure 14 Four schematic cross-sectional structure diagrams of array substrates are provided.

[0113] In some array substrates provided in the embodiments of the present application, such as Fig.13 As shown, the orthographic projection of the first through hole 31 on the first signal line 21 falls into the first slope area X1.

[0114] In some array substrates provided in the embodiments of the present application, such as Fig.15 As shown, a portion of the orthographic projection of the first through hole 31 on the first signal line 21 falls into the first slope region X1 , and another portion of the orthographic projection of the first through hole 31 on the first signal line 21 falls into the flat region P.

[0115] In some array substrates provided in the embodiments of the present application, such as Fig.12 As shown, the orthographic projection of the first through hole 31 on the first signal line 21 falls into the second slope area X2.

[0116] In some array substrates provided in the embodiments of the present application, such as Fig.14 As shown, the orthographic projection of the first through hole 31 on the first signal line 21 falls into the second slope area X2 , and another part of the orthographic projection of the first through hole 31 on the first signal line 21 falls into the flat area P.

[0117] In the array substrate provided in the embodiment of the present application, at least part of the orthographic projection of the first through hole 31 on the first signal line 21 is arranged to fall into the slope area (the first slope area X1 or the second slope area X2). In this way, due to the leveling effect of the material of the first insulating layer 3, Figure 8 As shown, the thickness d1 of the first insulating layer 3 in the slope area (area B) is smaller than the thickness d of the first insulating layer 3 in area C in the related art. In this way, during the dry etching process, the plasma concentration consumption rate in the collection area where the first signal line 21 is located is slowed down, so that it tends to be consistent with the plasma concentration in the signal introduction area B3, thereby improving the problem of excessive etching of the signal introduction area routing caused by the inconsistent via density and plasma concentration difference mentioned above.

[0118] It should be noted that, combined with Fig. 9 and Fig.12 As shown, the orthographic projection position of the first through hole 31 on the first signal line 21 is set away from the axis of the first signal line 21, while the second through hole 31 is still set on the axis of the signal lead-in line 22. Fig.12 for Fig. 9 Schematic diagram of the cross-sectional structure along the AA' direction.

[0119] In some array substrates provided in the embodiments of the present application, such as Figure 3 As shown, the plurality of second signal lines 51 include a plurality of driving electrode line groups G, and the driving electrode line group G includes a plurality of driving electrode lines that transmit signals that are not completely the same;

[0120] The plurality of first signal lines 21 include a plurality of parallel wirings; the parallel wirings are used to electrically connect the driving electrode lines in different driving electrode line groups G that transmit the same signal together.

[0121] For example, Figure 3 As shown, the driving electrode line group G includes eight driving electrode lines that transmit different signals, for example, the first driving electrode line, the second driving electrode line, the third driving electrode line, the fourth driving electrode line, the fifth driving electrode line, the sixth driving electrode line, the seventh driving electrode line, and the eighth driving electrode line.

[0122] Exemplarily, the first type of parallel routing is used to electrically connect the first driving electrode lines in different driving electrode line groups G, the second type of parallel routing is used to electrically connect the second driving electrode lines in different driving electrode line groups G, the third type of parallel routing is used to electrically connect the third driving electrode lines in different driving electrode line groups G, the fourth type of parallel routing is used to electrically connect the fourth driving electrode lines in different driving electrode line groups G, the fifth type of parallel routing is used to electrically connect the fifth driving electrode lines in different driving electrode line groups G, the sixth type of parallel routing is used to electrically connect the sixth driving electrode lines in different driving electrode line groups G, the seventh type of parallel routing is used to electrically connect the seventh driving electrode lines in different driving electrode line groups G, and the eighth type of parallel routing is used to electrically connect the eighth driving electrode lines in different driving electrode line groups G. Each type of parallel routing may include a first parallel routing arranged in the first collection area B1 and a second parallel routing arranged in the second collection area B2.

[0123] In some array substrates provided in the embodiments of the present application, such as Figure 3 As shown, the array substrate includes a display area A, a first wiring area B1 and a second wiring area B2 located on opposite sides of the display area A, and a signal introduction area B3 located on a side of the first wiring area B1 away from the display area A;

[0124] The plurality of parallel wirings include first parallel wirings and second parallel wirings, the first wiring collection area B1 is provided with a plurality of first parallel wirings, and the second wiring collection area B2 is provided with a plurality of second parallel wirings;

[0125] A plurality of driving electrode line groups G are arranged in the display area A; the plurality of driving electrode lines extend from the display area A to the first line collection area B1 and the second line collection area B2, respectively, and are electrically connected to the first parallel wiring and the second parallel wiring, respectively;

[0126] The number of first parallel routing lines (for example, the first signal line 21 in the horizontal direction in the first collection area B1), the number of second parallel routing lines (for example, the first signal line 21 in the horizontal direction in the second collection area B2), and the number of driving electrode lines in the same driving electrode line group G (for example, the second signal line 51 pointing vertically downward in the display area A) are equal.

[0127] In some array substrates provided in the embodiments of the present application, Figure 3 and Fig. 9 As shown, the signal introduction area B3 includes:

[0128] A plurality of bonding traces 52 located on the second conductive layer 5; Figure 3 As shown, a plurality of bridging traces 52 extend from the signal introduction area B3 to the first collection area B1, and part of the bridging traces 52 overlap with the orthographic projection of the first parallel trace (e.g., the first signal line 21 in the horizontal direction in the first collection area B1) on the substrate 1;

[0129] A plurality of signal lead-in wires 22 are located on the first conductive layer 2; the first insulating layer 3 has a plurality of second through holes 32, and the lapped wires 52 are electrically connected to the signal lead-in wires 22 through the second through holes 32;

[0130] The number of the plurality of connecting wires 52 is the same as the number of the plurality of first parallel wires (eg, the first signal wires 21 in the horizontal direction in the first collection area B1 ).

[0131] The following describes the preparation process of the array substrate. Figure 12 to Figure 15 The differences between the four array substrates.

[0132] by Fig.12 Taking the combination of the array substrate shown in the figure as an example, the preparation process is described:

[0133] Step 1: Fig.16 As shown, a conductive pattern of the first conductive layer 2 is prepared on the substrate 1 by exposure, development, and wet etching. The material of the first conductive layer 2 is generally molybdenum (Mo). The conductive pattern of the first conductive layer 2 includes a signal lead-in line 22 in the signal lead-in area B3 and a first signal line 21 (such as a parallel line) in the collection area. The conductive pattern of the first conductive layer 2 is prepared using the etching solution optimized in the above text; wherein the first signal line 21 and the signal lead-in line 22 in the first conductive layer 2 have the same cross-sectional structure, that is, the signal lead-in line 22 also has the same cross-sectional structure as shown in FIG. Figure 5 Similar cross-sectional structure shown.

[0134] Step 2: Fig.17 As shown, the first insulating layer 3 is prepared by PECVD. The material of the first insulating layer 3 includes an inorganic material, such as SiNx, SiO2 or SiNxO y .

[0135] Step 3: Fig.18 As shown, a photoresist film layer 4 (PR glue) is formed, and a via mask is used to expose and develop the photoresist film layer, and a via 41 located in the first wiring collection area B1 and a via 42 located in the signal introduction area B3 are formed on the photoresist film layer 4. When the via mask is used for exposure, the mask is moved along the Fig. 9 By moving downward a certain distance in the vertical direction shown in the figure, the collection area via 41 can be made on the slope on the right side of the first signal line 21 in the collection area; and because the extension direction of the signal introduction line 22 is originally in the vertical direction, the via 42 of the signal introduction area B3 is still located in the middle position of the signal introduction line 22.

[0136] Step 4: Fig.19 As shown, dry etching is used to perform via etching using the above-mentioned photoresist pattern as a mask to prepare the second via 32 of the signal introduction area B3 and the first via 31 of the collection area on the first insulating layer 3. Fig.19 As shown, the via hole 31 of the collection area is made on the slope on the right side of the first signal line 21 of the collection area, while the second via hole 32 of the signal introduction area B3 is still located in the middle of the signal introduction line 22 of the signal introduction area B3.

[0137] Step 5: Fig. 20 As shown, a magnetron sputtering method is used to form an indium tin oxide (ITO) film. After exposure, development, etching and other processes, a film such as Fig. 9 The second signal line 51 and the bonding trace 52 are shown in FIG.

[0138] Step 6: Use the organic layer 6 to planarize the driving array substrate to obtain Fig.12 The structure shown in FIG. 1 is shown in FIG. 1 ; wherein the display area A completely covers the organic layer 6, and the area in the signal introduction area B3 for binding with the external circuit is hollowed out for binding with the external circuit. The main function of the organic layer 6 is to make the driving electric field of the driving panel of the liquid crystal lens more uniform; the thickness of the organic layer 6 is in the range of 2.0 to 5.0 μm.

[0139] For Fig.14 The structure of the array substrate shown in FIG. 1 is similar to that described in the previous text. Fig.12 The preparation process of the array substrate shown in FIG. 1 is similar, the main difference being that in step 3, the mask is moved along the Fig. 9When the vertical direction shown in the figure moves downward a certain distance, Fig.14 The structure shown moves the mask down a distance less than Fig.12 The structure shown moves the mask down by a certain distance, thereby obtaining Fig.24 , Fig.25 and Fig.26 The first via hole 31 is disposed on the slope and the flat area on the right side of the first signal line 21 .

[0140] For Fig.13 The structure of the array substrate shown in FIG. 1 is similar to that described in the previous text. Fig.12 The preparation process of the array substrate shown in FIG. 1 is similar, the main difference being that in step 3, the mask is moved along the Fig. 9 In the vertical direction shown in , move a certain distance upward to obtain Fig.21 , Fig. 22 and Fig.23 A first via hole 31 is provided on the slope on the left side of the first signal line 21.

[0141] For Fig.15 The structure of the array substrate shown in FIG. 1 is similar to that described in the previous text. Fig.13 The preparation process of the array substrate shown in FIG. 1 is similar, the main difference being that in step 3, the mask is moved along the Fig. 9 When the vertical direction shown in the figure moves downward a certain distance, Fig.15 The structure shown moves the mask down a distance less than Fig.13 The structure shown moves the mask down by a certain distance, thereby obtaining Fig. 27 , Fig.28 and Fig.29 The first via hole 31 is disposed on the slope and the flat area on the left side of the first signal line 21 .

[0142] It should be noted that the solutions mentioned above are all improvements made by adjusting the preparation process without changing the existing mask. On the basis of improving the over-etching problem, the cost is relatively low.

[0143] Next, an embodiment of the present application provides a solution to improve the over-etching problem by changing the design of the mask.

[0144] The first via 31 of the collection area can be directly prepared in the slope area of ​​the first signal line 21 by changing the design of the mask. At this time, when the preparation process involves the above step 3, there is no need to move the mask for exposure.

[0145] In addition, by changing the design of the mask, a dummy via design can be added around the second through hole 32 of the signal introduction area B3 so that the density of the vias in the signal introduction area B3 is comparable to that of the collection area.

[0146] In some array substrates provided in the embodiments of the present application, such as Fig.11 As shown, the first insulating layer 3 further includes a plurality of dummy vias Dummy vias arranged in the signal introduction area B3.

[0147] It should be noted that the above-mentioned dummy via is an isolated via (a hole opened on the first insulating layer) and has no electrical connection with other conductive structures.

[0148] It should be noted that a first insulating layer 3 is provided at the location of the above-mentioned dummy via Dummy via, and a second conductive layer 5 covering the dummy via Dummy via is also provided to better simulate the structure of the second through hole 32 .

[0149] In some array substrates provided in the embodiments of the present application, the total area of ​​the plurality of dummy vias Dummy vias and the plurality of second through holes 32 in the signal introduction region B3 is substantially the same as the area of ​​the first through holes 31 .

[0150] In some embodiments, when the sizes of the dummy vias Dummy via, the second vias 32 and the first vias 31 are the same, the total density of the dummy vias Dummy via and the second vias 32 in the signal introduction area B3 can be set to be equivalent to the total density of the first vias 31 in the collection area.

[0151] The above-mentioned “equivalent” includes but is not limited to equal, and there may be a fluctuation of 3% to 5% on the basis of equality.

[0152] It should be noted that the array substrate provided in the embodiments of the present application may also include other structures and components. This specification only introduces the structures and designs related to the invention. Other structures and components included in the array substrate can be referred to in the introduction of the relevant technology.

[0153] An embodiment of the present application provides a liquid crystal lens, comprising an array substrate as described in any of the above, and further comprising an opposing substrate and a liquid crystal layer located between the array substrate and the opposing substrate.

[0154] The liquid crystal lens adjusts the arrangement of liquid crystal molecules by applying an electric field or changing other external conditions, thereby changing its refractive index and phase of the incident light, thereby achieving the control of light. The basic structure of the liquid crystal lens consists of a counter substrate, a liquid crystal layer and an array substrate. Transparent electrodes (such as the second signal line 51 mentioned above) are respectively arranged on the counter substrate and the array substrate, and a driving circuit is also arranged on the array substrate. Among them, the transparent electrode is used to apply an electric field, the liquid crystal layer is used to accommodate liquid crystal molecules, and the driving circuit is used to control the size and direction of the electric field.

[0155] It should be noted that the liquid crystal lens also includes other components and structures. Here, only the structures related to the invention are described. For other components and structures included in the liquid crystal lens, reference can be made to related technologies and will not be repeated here.

[0156] Those skilled in the art can understand that the liquid crystal lens provided in the present application has the advantages of the array substrate in any of the above embodiments.

[0157] An embodiment of the present application provides a display device, including a display panel and a liquid crystal lens as described above; the liquid crystal lens is arranged on the light emitting side of the display panel.

[0158] Exemplarily, the display device may be a 3D display device, for example, a naked-eye 3D display device.

[0159] The display device provided by the embodiments of the present application has the characteristics of high manufacturing yield, stable performance and good product quality.

[0160] The display device provided in the present application can be: a display module, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a car display device, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.

[0161] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: substrate; A first conductive layer located at one side of the substrate, the first conductive layer comprising a plurality of first signal lines, the first signal lines comprising a first slope region, a flat region, and a second slope region extending along a first direction and sequentially arranged along a second direction; The widths of the first slope region and the second slope region along the second direction are both greater than or equal to one quarter of the width of the first signal line along the second direction.

2. The array substrate according to claim 1, characterized in that: A portion of a surface of the first signal line away from the substrate and located in the flat area is substantially parallel to the substrate; A first angle is formed between a portion of the first slope region and the substrate on a surface of the first signal line away from the substrate, and a second angle is formed between a portion of the second slope region and the substrate on a surface of the first signal line away from the substrate. The first angle and the second angle are in the range of 5° to 50°.

3. The array substrate according to claim 2, characterized in that: The width of the first slope region along the second direction is substantially equal to the width of the second slope region along the second direction, and the first angle is substantially equal to the second angle.

4. The array substrate according to any one of claims 1 to 3, characterized in that: The array substrate further includes: A second conductive layer is located on a side of the first conductive layer away from the substrate, the second conductive layer comprises a plurality of second signal lines, and the second signal lines overlap with the first signal lines; A first insulating layer, located between the first conductive layer and the second conductive layer, having a plurality of first through holes; Among them, the second signal line includes a first line segment and a second line segment, the first line segment is consistent with the extension direction of the first signal line, the second line segment intersects with the extension direction of the first signal line, and the first line segment is electrically connected to the first signal line through the first through hole; at least a part of the positive projection of the first through hole on the first signal line falls into the slope area.

5. The array substrate according to claim 4, characterized in that: Along the second direction, a distance from a center of the first through hole to one side of the first line segment is not equal to a distance from a center of the first through hole to the other side of the first line segment.

6. The array substrate according to claim 5, characterized in that: The orthographic projection of the first through hole on the first signal line falls into the first slope area.

7. The array substrate according to claim 5, characterized in that: A portion of the orthographic projection of the first through hole on the first signal line falls into the first slope region, and another portion of the orthographic projection of the first through hole on the first signal line falls into the flat region.

8. The array substrate according to claim 5, characterized in that: The orthographic projection of the first through hole on the first signal line falls into the second slope area.

9. The array substrate according to claim 5, characterized in that: The orthographic projection of the first through hole on the first signal line falls into the second slope area, and another part of the orthographic projection of the first through hole on the first signal line falls into the flat area.

10. The array substrate according to any one of claims 5 to 9, characterized in that: The plurality of second signal lines include a plurality of driving electrode line groups, and the driving electrode line groups include a plurality of driving electrode lines that transmit signals that are not completely the same; The plurality of first signal lines include a plurality of parallel lines; the parallel lines are used to electrically connect the driving electrode lines with the same transmission signals in different driving electrode line groups.

11. The array substrate according to claim 10, characterized in that: The array substrate comprises a display area, a first line collection area and a second line collection area respectively located on two opposite sides of the display area, and a signal introduction area located on a side of the first line collection area away from the display area; The plurality of parallel routing lines include a first parallel routing line and a second parallel routing line, the first wiring collection area is provided with a plurality of the first parallel routing lines, and the second wiring collection area is provided with a plurality of the second parallel routing lines; A plurality of the driving electrode line groups are arranged in the display area; the plurality of driving electrode lines extend from the display area to the first line collection area and the second line collection area respectively, and are electrically connected to the first parallel wiring and the second parallel wiring respectively; The number of the first parallel wirings, the number of the second parallel wirings, and the number of the driving electrode lines in the same driving electrode line group are equal.

12. The array substrate according to claim 11, characterized in that: The signal introduction area comprises: A plurality of connecting wires located on the second conductive layer; the plurality of connecting wires extend from the signal introduction area to the first wiring collection area, and some of the connecting wires overlap with the orthographic projection of the first parallel wire on the substrate; A plurality of signal lead-in wires are located on the first conductive layer; the first insulating layer has a plurality of second through holes, and the lapped wires are electrically connected to the signal lead-in wires through the second through holes; The number of the plurality of overlapping wirings is the same as the number of the plurality of first parallel wirings.

13. The array substrate according to any one of claims 5 to 9 and 11 to 12, characterized in that: The first insulating layer further includes a plurality of dummy vias disposed in the signal introduction region.

14. The array substrate according to claim 13, characterized in that: A total area of ​​the plurality of dummy via holes and the plurality of second through holes in the signal introduction region is substantially the same as an area of ​​the first through hole.

15. A liquid crystal lens, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 14, and further comprises a counter substrate and a liquid crystal layer located between the array substrate and the counter substrate.

16. A display device, characterized in that: It comprises a display panel and a liquid crystal lens as claimed in claim 15; the liquid crystal lens is arranged on the light emitting side of the display panel.

Images