Test method and device for interface in server, equipment and storage medium

Abstract

According to the method for testing the interface in the server provided by the embodiment of the invention, the to-be-tested interface is acquired to obtain a plurality of pin signals, the voltage information of the to-be-tested interface is determined according to the plurality of pin signals, and the handshake information in the test request is analyzed to obtain the waveform information; and determining a target protocol matched with the to-be-tested interface according to the waveform information, the plurality of pin signals and the voltage information, determining a target test module from a plurality of preset test modules according to the target protocol, and testing the to-be-tested interface by using the target test module. According to the embodiment of the invention, the protocol type corresponding to the to-be-tested interface is determined by analyzing the signal, the voltage and the waveform of the to-be-tested interface of the server, and the test is carried out through the target test module, so that the test requirements of various different types of interfaces in the server can be met without concerning the line sequence access of the test interface; and the test cost and the test difficulty of the traditional board card test are reduced.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a testing method, device, equipment and storage medium for an interface in a server. Background Art

[0002] In today's digital and information age, the performance and functionality of servers, as core devices for data processing and storage, directly affect the operating efficiency and stability of the entire system. The efficient and accurate data transmission between servers and external devices depends on various interface protocols, such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), DIO (Digital Input / Output), etc. These interface protocols each have unique characteristics and advantages, and together they build a diversified, efficient, and stable data transmission environment for servers, meeting the connection requirements of different application scenarios and devices, allowing servers to better play their core role in data processing and service provision.

[0003] Affected by the combined influence of various factors such as the application scenario, hardware configuration and test environment of the server, it is necessary to use multiple protocols and other boards to communicate on the server, so it is necessary to leave corresponding physical interfaces. Different physical interface forms and protocols supported by the interfaces are different, and different matching test boards are often required on the server to implement such tests, which causes problems such as the boards required for testing and the test operation methods are not unified. At the same time, when manufacturing FCT (Functional Test Fixture, functional test fixture) test servers, it also causes additional problems such as FCT design difficulties and debugging difficulties. In addition, the matching test board is expensive, generally a project-specific board, and its value may even be higher than the server to be tested, which brings a large test cost loss to the test. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a method, device, equipment and storage medium for testing interfaces in a server, so as to realize testing of various types of interfaces in the server, and to realize automatic parsing of the test interface protocol without caring about the line sequence access of the test interface, and to test the interface to be tested. The specific technical scheme is as follows:

[0005] In a first aspect of the present invention, a method for testing an interface in a server is provided, wherein the method comprises:

[0006] In response to a test request for the interface to be tested in the server, collecting a plurality of pin signals from the interface to be tested, and determining voltage information of the interface to be tested according to the plurality of pin signals;

[0007] Extracting handshake information from the test request, and parsing the handshake information to obtain waveform information;

[0008] Determine a target protocol matching the interface to be tested according to the waveform information, the plurality of pin signals and the voltage information;

[0009] A target test module is determined from a plurality of preset test modules according to the target protocol, and the interface to be tested is tested using the target test module.

[0010] In an optional embodiment of the present invention, determining a target protocol matching the interface to be tested according to the waveform information, the plurality of pin signals, and the voltage information includes:

[0011] Determine the pin types corresponding to the multiple pin signals according to the multiple pin signals;

[0012] A target protocol matching the interface to be tested is determined according to the waveform information, the pin types corresponding to the multiple pin signals, and the voltage information.

[0013] In an optional embodiment of the present invention, determining the pin types corresponding to the multiple pin signals according to the multiple pin signals includes:

[0014] Using a fine-tuning voltage to pull up or pull down the voltages corresponding to the plurality of pin signals; the pin types corresponding to the plurality of pin signals include a ground type, a floating type, a power type, and a signal type;

[0015] If the pin signal is in a low level maintenance state and the voltage of the pin signal is not pulled high, it is determined that the pin type corresponding to the pin signal is a ground type or a signal type;

[0016] If the pin signal is in a high level maintenance state and the voltage of the pin signal is not pulled down, it is determined that the pin type corresponding to the pin signal is a power type, and the voltage value corresponding to the pin signal is determined as the power supply voltage of the interface to be tested;

[0017] If the pin signal is in a high or low level change state, determine that the pin type corresponding to the pin signal is a signal type, or a suspended type;

[0018] The determining a target protocol matching the interface to be tested according to the waveform information, the pin types corresponding to the multiple pin signals, and the voltage information includes:

[0019] Determine the timing signal of the interface to be tested according to the waveform information;

[0020] A target protocol matching the interface to be tested is determined according to the timing signal, the pin types corresponding to the multiple pin signals, and the voltage information, wherein the voltage information includes a power supply voltage of the interface to be tested.

[0021] In an optional embodiment of the present invention, before collecting the plurality of pin signals from the interface to be tested, the method includes:

[0022] The voltage corresponding to the signal of the interface to be tested is converted into a constant voltage according to the target voltage value to obtain the converted signal of the interface to be tested.

[0023] In an optional embodiment of the present invention, the step of acquiring a plurality of pin signals from the interface to be tested includes:

[0024] The signal of the interface to be tested is collected according to a target sampling frequency to obtain a plurality of pin signals, wherein the target sampling frequency is 20 MHz.

[0025] In an optional embodiment of the present invention, the plurality of preset test modules include a first protocol type module set and a second protocol type module set, and determining a target test module from the plurality of preset test modules according to the target protocol includes:

[0026] Determine a target test module from the first protocol type module set according to the target protocol, wherein the first protocol type module includes at least a two-wire low-speed protocol module, a synchronous serial protocol module, a long-distance serial protocol module and a control domain protocol module; and the second protocol type module includes at least a digital input and output protocol module.

[0027] In an optional embodiment of the present invention, the method further comprises:

[0028] If the waveform analysis information corresponding to the waveform information does not match the preset character string, the digital input-output protocol module in the second protocol type module is used to test the interface to be tested.

[0029] In a second aspect of the present invention, a testing device for an interface in a server is provided, characterized in that it includes:

[0030] A first response module, configured to respond to a test request for the interface to be tested in the server, collect a plurality of pin signals from the interface to be tested, and determine voltage information of the interface to be tested according to the plurality of pin signals;

[0031] A first extraction module, used for extracting handshake information from the test request, and parsing the handshake information to obtain waveform information;

[0032] A protocol determination module, configured to determine a target protocol matching the interface to be tested according to the waveform information, the plurality of pin signals and the voltage information;

[0033] The first test is used to determine a target test module from a plurality of preset test modules according to the target protocol, and use the target test module to test the interface to be tested.

[0034] The embodiments of the present application also disclose a computer program product, including a computer program / instruction, which, when executed by a processor, implements a method for testing an interface in a server as described in one or more of the embodiments of the present application.

[0035] An embodiment of the present application also discloses an electronic device, including: a processor; and a memory, on which executable code is stored. When the executable code is executed, the processor executes a method for testing an interface in a server as described in one or more of the embodiments of the present application.

[0036] The embodiments of the present application also disclose one or more machine-readable media on which executable codes are stored. When the executable codes are executed, the processor executes the testing method of the interface in the server as described in one or more of the embodiments of the present application.

[0037] The method for an interface in a server provided by an embodiment of the present invention, in response to a test request for an interface to be tested in the server, collects a plurality of pin signals from the interface to be tested, determines voltage information of the interface to be tested based on the plurality of pin signals, extracts handshake information from the test request, and parses the handshake information to obtain waveform information, determines a target protocol matching the interface to be tested based on the waveform information, the plurality of pin signals, and the voltage information, determines a target test module from a plurality of preset test modules based on the target protocol, and uses the target test module to test the interface to be tested. The embodiment of the present invention determines the protocol type corresponding to the interface to be tested by analyzing the signal, voltage, and waveform of the interface to be tested in the server, and tests it through the target test module, thereby realizing that there is no need to care about the line sequence access of the test interface, and can meet the test requirements of various types of interfaces in the server, thereby reducing the test cost and test difficulty of traditional board testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0039] Figure 1 A schematic diagram of a server mainboard interface provided by an embodiment of the present invention;

[0040] Figure 2 A flow chart of the steps of a method for testing an interface in a server provided by an embodiment of the present invention;

[0041] Figure 3 A design block diagram of a test component provided for an embodiment of the present invention;

[0042] Figure 4 A schematic diagram of the connection of test components provided in an embodiment of the present invention;

[0043] Figure 5 An overall flow chart of a method for testing an interface in a server provided by an embodiment of the present invention;

[0044] Figure 6 It is a structural schematic diagram of a testing device for an interface in a server provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] To make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined and referenced with each other without contradiction.

[0046] As the core device for data processing and storage, the server relies on various interface protocols for efficient and accurate data transmission with external devices, such as I2C, SPI, CAN (Controller Area Network), RS485 (Recommended Standard 485), RS422 (Recommended Standard 422), RS232 (Recommended Standard 232), DIO and other interfaces.

[0047] Reference Figure 1The schematic diagram of the server interface to be tested provided in the embodiment of the present invention shows that if the interface to be tested on the server is to be tested, RISER (Riser Card), network card, hard disk backplane, hard disk, etc. need to be used as matching test. The structural design is extremely complex, and in order to adapt to the server to be tested, a whole set of boards and cards dedicated to the project will generally be designed, and their value will even be higher than the server to be tested, which will bring a large test cost loss to the test. When using matching test boards and cards, some projects must be equipped with other additional matching test equipment, such as PSU (Power Supply Unit), hard disk, power supply board, etc., which will generate additional consumption. The matching test structure is complex. In the case of high space for FCT structure, complex and large matching test boards and cards result in complex FCT structure design, long debugging time, complex debugging, and long delivery cycle.

[0048] Reference Figure 2 , shows a flow chart of the steps of a method for testing an interface in a server provided by an embodiment of the present invention, the method may include:

[0049] Step 201 , in response to a test request for a to-be-tested interface in the server, collects a plurality of pin signals from the to-be-tested interface, and determines voltage information of the to-be-tested interface according to the plurality of pin signals.

[0050] A server is a computer or computer program that is specially designed to provide various services to other computers or devices. Servers can provide many types of services. The characteristics of servers usually include: High-performance hardware: Servers are usually equipped with high-performance processors, large-capacity memory and storage devices, and high-speed network interfaces to ensure that they can handle a large number of data requests and concurrent users. High reliability: When designing servers, high availability and fault recovery capabilities are taken into consideration, such as redundant power supplies, hot-swappable hardware, storage technology, etc. to improve the reliability of the system. Network connection: The server is connected to the client through a network (such as the Internet or a local area network), and the client can access the services provided by the server through various network protocols. Servers can be deployed in different environments, including data centers, cloud platforms, and corporate intranets. Depending on the services provided, servers can be divided into many types, such as network servers, mail servers, database servers, file servers, application servers, etc. At the same time, there are many interfaces on the server, which are used to connect different hardware devices, expand functions, provide data transmission and power supply, etc. Including: network interface, storage interface, expansion interface, management interface, etc. Therefore, before the server is mass-produced or put into use, it is necessary to test the various interfaces in the server to ensure the function and performance of the server.

[0051] In a specific implementation, the test interface in the test component implementing the test method of the present invention can be connected to the interface to be tested of the server, wherein the test interface can be 16 PIN (pin) pin signals, and the number of PIN pins can meet the number of pins of all interface types of the server at this stage, providing a hardware basis for the server multi-interface test. The signal of any interface to be tested in the server is input by the interface. For the signal input of the interface to be tested, there is no need to care about the signal definition, voltage, polarity, sequence number, etc., and it can be accessed according to the interface form of 16 PIN pins. For example, the pins of the interface to be tested and the pins of the test interface can be fixed together by screws to achieve electrical connection, or the pins of the interface to be tested and the pins of the test interface can be welded together to achieve electrical connection. The present invention does not make specific restrictions on this. The input signal of the interface to be tested is input as a black box model, that is, the test interface is accessed without knowing what state the input signal is in.

[0052] like Figure 3 As shown, it is a design block diagram of the test component provided by an embodiment of the present invention. The test component will enter the handshake preparation state after receiving the handshake command. After the test component enters the handshake preparation state, the interface detection initialization is first performed, and the test component is connected to the interface to be tested through the constant voltage conversion module. The interface to be tested continuously outputs high and low level signals, and the FPGA (Field-Programmabl e Gate Array) module of the test component can obtain multiple pin signals. The voltage input of each pin of the interface to be tested of the server to be tested is collected by the ADC (Analog-to-Digital Converter Module) module, and the information collected by the ADC module is calculated by the FPGA module to obtain the voltage information of the interface to be tested.

[0053] Among them, the FPGA module is an integrated circuit that contains a large number of programmable logic blocks, input / output blocks, and interconnection resources. The main feature of the FPGA module is that users can configure its internal logic through programming as needed to achieve specific digital circuit functions. The FPGA contains a large number of logic units (usually called lookup tables or logic elements), which can be configured to implement various logic functions, such as AND gates, OR gates, NOT gates, multiplexers, etc. The IO (Input / Outpu t, input / output block) of the FPGA module is responsible for the input and output of signals with the outside world. The ADC module is an electronic device or circuit that can convert analog signals (such as voltage or current) into digital signals. The key parameters and characteristics of the ADC module include: resolution, ADC resolution refers to the minimum analog signal change it can distinguish, usually expressed in bits; for example, a 12-bit ADC can output 2 12(i.e. 4096) different digital values ​​to represent the input analog signal. Sampling rate, the sampling rate of the ADC refers to the number of samples it can convert per second, measured in Hertz (Hz). A high sampling rate means that the ADC can capture changes in the analog signal more quickly. Input range: The input range of the ADC refers to the maximum and minimum values ​​of the analog signal it can accept. Signals outside this range may cause inaccurate ADC output or damage the ADC. Accuracy: The accuracy of the ADC refers to how close its output digital value is to the actual analog input value. Accuracy is affected by many factors, including resolution, linearity, noise, and temperature drift.

[0054] In some embodiments of the present invention, before collecting the plurality of pin signals from the interface to be tested, the method includes:

[0055] The voltage corresponding to the signal of the interface to be tested is converted into a constant voltage according to the target voltage value to obtain the converted signal of the interface to be tested.

[0056] In a specific implementation, after the signal in the interface to be tested in the server is input through the test interface of the test component, the signal voltage cannot be determined due to the black box state, and it is impossible to ensure that the FPGA module can safely sample it. For example, the input signal voltage may be overvoltage or too high, which will cause the FPGA module to be unable to effectively collect or damage the FPGA module. Therefore, the voltage of the input signal is converted by a constant voltage conversion module, and the signal to be tested passes through the module. The module can clamp the excessively high voltage of the input signal and convert the excessively low voltage of the input signal to ensure that the FPGA module can work normally and sample correctly. Specifically, the constant voltage conversion module of the device can convert all 0-24V signal inputs into 3.3V signals, which can be applied to all communication occasions of the server interface.

[0057] In some embodiments of the present invention, the step of acquiring a plurality of pin signals from the interface to be tested includes:

[0058] The signal of the interface to be tested is collected according to a target sampling frequency to obtain a plurality of pin signals, wherein the target sampling frequency is 20 MHz.

[0059] For medium and low-speed interfaces in servers, the 20MHz sampling frequency provides sufficient resolution to capture key parameters such as signal rise and fall time, pulse width, etc., which can fully cover various interface types in servers.

[0060] Step 202: extract handshake information from the test request, and parse the handshake information to obtain waveform information.

[0061] In a specific implementation, after the test component is initialized, the information that the test component is ready is returned through the USB. The FPGA module enters the signal acquisition state and extracts the handshake information from the test request. For example, the handshake signal can be a predetermined string "A". The FPGA module parses the handshake information to obtain the parsed waveform information.

[0062] Step 203: Determine a target protocol that matches the interface to be tested according to the waveform information, the plurality of pin signals, and the voltage information.

[0063] By combining the multiple pin signals and voltage information obtained in step 201 with the waveform information analyzed in step 202, the protocol type of the input signal of the interface to be tested and the status of the connected PIN pins can be determined.

[0064] In a specific implementation, all pin signals collected in step 201 are recorded, for example, clock signals, data signals, control signals, etc. The voltage level of each pin is measured and recorded by the ADC module and the FPGA module, including high level (V_high), low level (V_low), threshold voltage, etc. The waveform information is obtained by analyzing the handshake information through the FPGA module. The waveform information is the waveform characteristics, which can be specifically observed for the frequency, duty cycle, rise time, fall time and other characteristics of the waveform, identify the periodic pattern in the waveform, such as the period of the clock signal, the frame structure of data transmission, etc., and check whether there is a specific encoding or modulation mode in the waveform, such as Manchester encoding, differential encoding, etc. The timing relationship between signals can also be identified through the FPGA module: the timing relationship between different pin signals is analyzed, such as the edge alignment mode of the data signal relative to the clock signal (leading edge, trailing edge or double edge). The electrical characteristics can also be compared through the FPGA module: the measured voltage level is compared with the electrical specifications of the known protocol. The FPGA module can also be used to check whether the swing, noise tolerance, driving capability, etc. of the signal meet the requirements of a specific protocol. Based on the above content, the built-in protocol identification function in the FPGA module is used to automatically identify the target communication protocol that matches the interface to be tested.

[0065] In some embodiments of the present invention, step 203 may include the following sub-steps:

[0066] Sub-step 11: Determine the pin types corresponding to the multiple pin signals according to the multiple pin signals.

[0067] In a specific implementation, the test component of the present invention may include 16 test pins, which can meet the number of pins of the commonly used interfaces of servers at this stage. When the pins of the interface to be tested are electrically connected to the pins of the test interface of the test component, if there are only 4, 8 or 12 pins of the interface to be tested, there will be dangling pins among the 16 pins of the test interface. Therefore, it is necessary to determine the pin type corresponding to each pin signal. The pin types are specifically: power pin: usually has a stable voltage level, such as 3.3V, 5V, 12V, etc. Ground pin: usually the voltage is close to 0V. Clock pin: has a periodic square wave signal. Data pin: a data signal that changes according to the clock signal, which may have a specific encoding mode. Control pins: such as chip select, read, write, interrupt, etc., are usually used to control data transmission or device operation. Reset pin: usually has a specific voltage or pulse signal when the device is started or reset. Reserved or unconnected pins: may have no signal or the signal does not change over time.

[0068] Sub-step 12: Determine a target protocol that matches the interface to be tested according to the waveform information, the pin types corresponding to the multiple pin signals, and the voltage information.

[0069] After the pin type corresponding to each pin signal is determined, the protocol of the interface to be tested can be determined based on the determined pin type, voltage, and waveform information.

[0070] In some embodiments of the present invention, sub-step 11 may further include the following sub-steps:

[0071] Sub-step 111: using a fine-tuning voltage to pull up or pull down the voltages corresponding to the plurality of pin signals; the pin types corresponding to the plurality of pin signals include a ground type, a floating type, a power type, and a signal type.

[0072] In a specific implementation, when the test component analyzes and judges multiple pin signals, the FPGA module can use a micro voltage to pull up or down the voltage of the pin signal. For example, a micro voltage of 0.5V can be used to pull up or down.

[0073] Sub-step 112: if the pin signal is in a low level maintenance state and the voltage of the pin signal is not pulled high, determining that the pin type corresponding to the pin signal is a ground type or a signal type;

[0074] Judgment of the power ground GND (Ground) signal: If a certain PIN of the test interface is connected to the power GND signal of the interface to be tested, the power GND signal is connected to the FPGA module through the constant voltage conversion module. The IO of the FPGA module continuously pulls up and down the signal input from the interface to be tested through the test interface. Since the GND signal cannot be pulled up by the IO, during the high and low changes of the IO of the FPGA module, if the FPGA module cannot pull down the voltage of a certain pin, the signal of the pin will always remain at a low level. This can be used to determine that the PIN pin may be a GND pin or a signal type. The reason why it cannot be determined that the pin must be GND is that if the input signal is always at a low level, the FPGA module will not be able to pull up the voltage of the pin. Therefore, if the pin signal is in a low-level maintenance state, and the voltage of the pin signal is not pulled up, it is determined that the pin type corresponding to the pin signal is a ground type, or a signal type.

[0075] Sub-step 113: if the pin signal is in a high level maintenance state and the voltage of the pin signal is not pulled down, determining that the pin type corresponding to the pin signal is a power type, and determining the voltage value corresponding to the pin signal as the power supply voltage of the interface to be tested;

[0076] In the specific implementation, the power supply VCC signal is judged: if a certain PIN of the test interface is connected to the power supply VCC signal of the interface to be tested, the IO of the FPGA module uses a micro voltage to continuously pull up and pull down the signal input from the interface to be tested through the test interface. If a certain PIN is a power supply VCC signal, since the VCC signal cannot be pulled down by the IO, during the high and low changes of the FPGA IO, if the FPGA module cannot lower the voltage of a certain pin, the signal of the pin will always remain in a high level state, so it can be judged that the PIN pin is the VCC pin. The FPGA module collects the voltage of the PIN pin through the ADC and saves the collected voltage in a log.

[0077] Sub-step 114: if the pin signal is in a high-low level change state, determining that the pin type corresponding to the pin signal is a signal type, or a floating type;

[0078] In the specific implementation, for other signal judgments: during the high and low changes of the FPGA module IO, the IO of the FPGA module corresponding to a pin of the interface to be tested remains the same as the IO output of the FPGA module, then the pin may be connected to the signal pin of the interface to be tested; or the pin may be in a floating state, that is, the pin is not connected to any signal.

[0079] In some embodiments of the present invention, sub-step 12 may further include the following sub-steps:

[0080] Sub-step 121: determining a timing signal of the interface to be tested according to the waveform information;

[0081] The FPGA module collects and analyzes the waveform information corresponding to the handshake information sent by the interface to be tested, and records the signals of all relevant pins, especially those that may be related to timing, such as clock signals, data signals, control signals, etc. Analyze waveform characteristics: Observe the frequency, duty cycle, rise time, fall time and other characteristics of the waveform. Identify periodic patterns in the waveform, such as the period of the clock signal, the frame structure of data transmission, etc. Check whether there is a specific encoding or modulation method in the waveform, such as Manchester encoding, differential encoding, etc. Identify timing relationships: Analyze the timing relationship between signals on different pins, such as the edge alignment of the data signal relative to the clock signal (leading edge, trailing edge or double edge). Determine how control signals affect data transmission, such as chip select signals, read and write signals, etc. Determine timing parameters: Measure the period (T) and frequency (f = 1 / T) of the clock signal. Determine the valid window of the data signal, that is, at which edge of the clock signal the data signal is sampled or changed. Measure the setup time (Setup Time) and hold time (Hold Time), that is, the time the data signal needs to be stable before and after the clock edge. If there are multiple clock signals, determine the relationship between them, such as synchronous, asynchronous, or cascaded. Verify the timing signals: Verify that the interface's response meets the identified timing signals by sending known data packets or commands. You can also use the built-in timing analysis function in the FPGA template to further verify the timing parameters.

[0082] Sub-step 122: determining a target protocol matching the interface to be tested based on the timing signal, the pin types corresponding to the multiple pin signals, and the voltage information, wherein the voltage information includes a power supply of the interface to be tested.

[0083] After the timing signal is determined, the matching target protocol can be determined through the pin type and recorded voltage information.

[0084] In a specific implementation, the timing characteristics of various protocols such as I2C, SPI, CAN, and the electrical characteristics of each pin can be preset in the test component. The test component finds the corresponding matching items by comparing the preset timing characteristics with the actually measured waveform characteristics and electrical characteristics. Among them, I2C, SPI and CAN are three common serial communication protocols, which are used for data transmission between devices in different application scenarios.

[0085] The following is a detailed explanation of these three protocols: 1. I2C (Inter-Integrated Circuit) is a bidirectional two-wire serial communication protocol used to connect low-speed peripheral devices. I2C uses two lines for communication: SDA (Serial Data Line) for data transmission; SCL (Serial Clock Line) for clock signal transmission and synchronous data transmission. The I2C data transmission rate is relatively low, usually between a few hundred kbps and a few Mbps. 2. SPI (Serial Peripheral Interface) is a four-wire full-duplex synchronous serial communication protocol. SPI uses four lines for communication. The SPI protocol provides a higher data transmission rate than I2C, usually between a few Mbps and tens of Mbps, but the hardware cost and wiring complexity are relatively high. 3. CAN (Controller Area Network), CAN uses two lines for communication. The CAN protocol is characterized by high reliability, error detection and automatic retransmission functions, and is suitable for use in noisy environments.

[0086] Step 204: Determine a target test module from a plurality of preset test modules according to the target protocol, and use the target test module to test the interface to be tested.

[0087] In the specific implementation, the test component is pre-configured with CAN module, I2C module, SPI module, RS485 module, RS422 module, RS232 module, DIO, etc. After determining the target protocol corresponding to the interface to be tested, the test component can switch the signal pin of the interface to be tested to the corresponding protocol module, and at the same time, the USB sends a sign of successful pairing analysis to the server to be tested. After receiving the USB transmission pairing success command, the server to be tested controls the interface to be tested to perform data interaction. If the data interaction process between the two parties is normal, the test is considered normal; if the data exchange process is abnormal, the test is considered abnormal. After the interaction is completed, a USB command is issued to end the working state of the test component. The test component transmits the log information such as voltage collected by the test interface to the server to be tested through the USB interface. The server to be tested uses the test results to determine the in-place information, enable status, voltage status, etc., where the in-place information refers to whether a device, module or component is physically connected or installed in the system, and the enable status refers to whether a device, module or function is activated or allowed to run. That is to say, the in-place information and the enable status describe the existence status and functional status of the device or component respectively. The server to be tested determines whether various interfaces to be tested meet the interface design requirements based on the in-place information, enable status, and voltage status, and then completes the detection test, thereby improving the test efficiency and reducing the test cost.

[0088] In some embodiments of the present invention, the plurality of preset test modules include a first protocol type module set and a second protocol type module set, and determining a target test module from the plurality of preset test modules according to the target protocol includes:

[0089] Determine a target test module from the first protocol type module set according to the target protocol, wherein the first protocol type module includes at least a two-wire low-speed protocol module, a synchronous serial protocol module, a long-distance serial protocol module and a control domain protocol module; and the second protocol type module includes at least a digital input and output protocol module.

[0090] In a specific implementation, the FPGA module of the test component will parse the sampled waveform after sampling the handshake information. If the string "A" can be parsed, the protocol type of the input signal, i.e., the target protocol, can be determined based on the pin type, voltage information, and timing signal. The target test module is determined from the first protocol type module set according to the target protocol. The first protocol type module includes a two-wire low-speed protocol module (I2C module), a synchronous serial protocol module (SPI module), a long-distance serial protocol module (RS485 module, RS422 module, RS232 module), and a control domain protocol module (CAN module). For example, if the determined target protocol is the SPI protocol, the corresponding target test module is determined from the first protocol type module set to be a synchronous serial protocol module; if the determined target protocol is the I2C protocol, the corresponding target test module is determined from the first protocol type module set to be a two-wire low-speed protocol module. The test component switches the signal pin to the corresponding protocol test module, and at the same time, the USB sends a sign of successful pairing analysis to the server. After receiving the USB transmission successful pairing command, the server to be tested controls the interface to be tested to perform data interaction, thereby realizing the test of the interface to be tested in the server to be tested in black box mode. There is no need to worry about the line sequence, signal, or voltage, and the correct test module can be determined to test the interface to be tested.

[0091] In some embodiments of the present invention, the test component may further include a cache module, which is specifically used to store the data sampled by the FPGA. Since a large amount of sampled data is generated when the FPGA is sampled, the cache module can be used to store the sampled data when necessary, so as to retrieve the data analysis and acquisition waveform. The test component may also include a switching module. After the FPGA module collects the signal of the interface to be tested and analyzes it, it can determine what protocol data the signal of the interface to be tested specifically corresponds to, and the role of the PIN pin of the signal in the input signal protocol. At this time, the FPGA module can control the switching module to switch the PIN pin of the input signal of the interface to be tested to the PIN pin corresponding to the target test module for subsequent testing. The test component may also include a universal serial bus module (USB module), which is specifically used to realize the data interaction between the server to be tested and the FPGA module, and can parse the command issued by the server to be tested to the device through the serial bus interface (USB interface, Universal Serial Bus) to realize the subsequent test logic of the test component. The test component may also include a power supply module, which is specifically used to convert the voltage input by the power supply interface to provide the required 1.8V, 3.3V, 5V and other voltages for all modules.

[0092] In the specific implementation, Figure 4 The figure shows a connection diagram of the test component provided in some embodiments of the present invention. When the test component is connected to the server to be tested, the standard serial interface (USB interface) of the server to be tested is connected to the standard serial interface (USB interface) of the device through a standard serial cable (USB cable), and the server interface to be tested is connected to the test interface of the test component. The test component is powered from the outside through a modified cable or a standard cable connection, so that the test component can be used to test the server to be tested.

[0093] In some embodiments of the present invention, it further includes:

[0094] If the waveform analysis information corresponding to the waveform information does not match the preset character string, the digital input-output protocol module in the second protocol type module is used to test the interface to be tested.

[0095] In a specific implementation, if the character string in the handshake information cannot be parsed, the input is considered to be a non-standard protocol, and the interface to be tested is tested according to the DIO protocol.

[0096] The scheme of the present invention is described as a whole through a complete implementation step. Figure 5As shown, it is an overall flow chart of the interface test method in the server provided by the embodiment of the present invention. The server to be tested sends a handshake command to the test component through the connected USB, and the test component enters the handshake preparation state; the test component performs interface detection initialization, and the test component is connected to the constant voltage conversion module. The test interface connected to the interface to be tested in the test component continuously outputs high and low level signals, and the FPGA module reads the actual output state of the test interface IO. Through the feedback state of the IO, it can preliminarily detect the access signal PIN pin, which is the power signal, which may be the GND signal, which may be the signal type, or the suspended state. After the test component is initialized, the test component is returned through the standard serial interface. The FPGA module enters the signal acquisition state and prepares to collect the signal of the test interface in real time. The server to be tested controls the interface to be tested and sends a handshake signal, and the handshake signal is a certain string "A". The FPGA module of the test component samples the signal fluctuation of the test interface, saves the data in the cache after sampling, and performs data analysis after the sampling is completed. After sampling, the FPGA module of the test component will parse the sampled waveform. If the string can be parsed as "A", the protocol type of the input signal and the state of the connected PIN pin can be determined. If the string cannot be parsed, the input is considered to be a non-standard protocol and is processed according to the digital input and output protocol. The device switches the signal pin to the corresponding protocol module, and the standard serial interface sends a sign of successful pairing parsing to the server. After receiving the USB transmission pairing success command, the server to be tested controls the interface to be tested to interact with data. If the data interaction process between the two parties is normal, the test is considered normal. Otherwise, the test is abnormal. After the interaction is completed, a USB command is issued to end the working status of the test component. The device transmits the voltage and other log information collected by the test interface to the server to be tested through the USB interface. The server to be tested determines whether various in-place information, enable status, voltage status, etc. meet the interface design requirements and completes the detection test.

[0097] The method for an interface in a server provided by an embodiment of the present invention, in response to a test request for an interface to be tested in the server, collects a plurality of pin signals from the interface to be tested, determines voltage information of the interface to be tested based on the plurality of pin signals, extracts handshake information from the test request, and parses the handshake information to obtain waveform information, determines a target protocol matching the interface to be tested based on the waveform information, the plurality of pin signals, and the voltage information, determines a target test module from a plurality of preset test modules based on the target protocol, and uses the target test module to test the interface to be tested. The embodiment of the present invention determines the protocol type corresponding to the interface to be tested by analyzing the signal, voltage, and waveform of the interface to be tested in the server, and tests it through the target test module, thereby realizing that there is no need to care about the line sequence access of the test interface, and can meet the test requirements of various types of interfaces in the server, thereby reducing the test cost and test difficulty of traditional board testing.

[0098] Reference Figure 6 , shows a schematic diagram of the structure of a testing device for an interface in a server provided by an embodiment of the present invention, such as Figure 6 As shown, the device may include:

[0099] The first response module 601 is used to respond to a test request for the interface to be tested in the server, collect multiple pin signals from the interface to be tested, and determine voltage information of the interface to be tested according to the multiple pin signals;

[0100] A first extraction module 602, configured to extract handshake information from the test request, and parse the handshake information to obtain waveform information;

[0101] A protocol determination module 603, configured to determine a target protocol matching the interface to be tested according to the waveform information, the plurality of pin signals and the voltage information;

[0102] The first test module 604 is used to determine a target test module from a plurality of preset test modules according to the target protocol, and use the target test module to test the interface to be tested.

[0103] In an optional embodiment of the present invention, the protocol determination module 603 further includes:

[0104] A type determination submodule, used to determine the pin types corresponding to the multiple pin signals according to the multiple pin signals;

[0105] The protocol determination submodule is used to determine a target protocol matching the interface to be tested according to the waveform information, the pin types corresponding to the multiple pin signals, and the voltage information.

[0106] In an optional embodiment of the present invention, the type determination submodule further includes:

[0107] The first subunit is used to use a fine-tuning voltage to pull up or pull down the voltages corresponding to the plurality of pin signals; the pin types corresponding to the plurality of pin signals include a ground type, a floating type, a power type, and a signal type;

[0108] A second subunit is used to determine that the pin type corresponding to the pin signal is a ground type or a signal type if the pin signal is in a low level maintenance state and the voltage of the pin signal is not pulled high;

[0109] A third subunit is used for determining that the pin type corresponding to the pin signal is a power type if the pin signal is in a high level maintenance state and the voltage of the pin signal is not pulled down, and determining the voltage value corresponding to the pin signal as the power supply voltage of the interface to be tested;

[0110] A fourth subunit is used to determine that the pin type corresponding to the pin signal is a signal type or a suspended type if the pin signal is in a high or low level change state;

[0111] The protocol determination submodule also includes:

[0112] A fifth subunit, configured to determine a timing signal of the interface to be tested according to the waveform information;

[0113] The sixth subunit is used to determine a target protocol matching the interface to be tested based on the timing signal, the pin types corresponding to the multiple pin signals, and the voltage information, wherein the voltage information includes a power supply voltage of the interface to be tested.

[0114] In an optional embodiment of the present invention, the first response module 601 further includes:

[0115] The constant voltage conversion submodule is used to perform constant voltage conversion on the voltage corresponding to the signal of the interface to be tested according to the target voltage value to obtain the converted signal of the interface to be tested.

[0116] In an optional embodiment of the present invention, the first response module 601 further includes:

[0117] The first acquisition submodule is used to acquire the signal of the interface to be tested according to a target sampling frequency to obtain a plurality of pin signals, wherein the target sampling frequency is 20 MHz.

[0118] In an optional embodiment of the present invention, the plurality of preset test modules include a first protocol type module set and a second protocol type module set, and the first test module 604 further includes:

[0119] The protocol determines the second submodule, which is used to determine the target test module from the first protocol type module set according to the target protocol, wherein the first protocol type module includes at least a two-line low-speed protocol module, a synchronous serial protocol module, a long-distance serial protocol module and a control domain protocol module; the second protocol type module includes at least a digital input and output protocol module.

[0120] In an optional embodiment of the present invention, the device further comprises:

[0121] The digital protocol determination module is used to test the interface to be tested using the digital input-output protocol module in the second protocol type module if the waveform parsing information corresponding to the waveform information does not match the preset character string.

[0122] The method for an interface in a server provided by an embodiment of the present invention, in response to a test request for an interface to be tested in the server, collects a plurality of pin signals from the interface to be tested, determines voltage information of the interface to be tested based on the plurality of pin signals, extracts handshake information from the test request, and parses the handshake information to obtain waveform information, determines a target protocol matching the interface to be tested based on the waveform information, the plurality of pin signals, and the voltage information, determines a target test module from a plurality of preset test modules based on the target protocol, and uses the target test module to test the interface to be tested. The embodiment of the present invention determines the protocol type corresponding to the interface to be tested by analyzing the signal, voltage, and waveform of the interface to be tested in the server, and tests it through the target test module, thereby realizing that there is no need to care about the line sequence access of the test interface, and can meet the test requirements of various types of interfaces in the server, thereby reducing the test cost and test difficulty of traditional board testing.

[0123] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the above-mentioned method for testing an interface in a server when the computer program / instruction is executed by a processor.

[0124] An embodiment of the present invention further provides an electronic device, which may include a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and when the computer program is executed by the processor, the test method of the interface in the server as described above is implemented.

[0125] An embodiment of the present invention further provides a non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the test method of the interface in the server as described above is implemented.

[0126] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0127] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0128] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0129] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0130] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0131] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0132] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0133] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0134] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the above elements.

[0135] The dead time testing method and device of a switching power supply provided above are introduced in detail. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for testing an interface in a server, characterized in that: The method comprises: In response to a test request for the interface to be tested in the server, collecting a plurality of pin signals from the interface to be tested, and determining voltage information of the interface to be tested according to the plurality of pin signals; Extracting handshake information from the test request, and parsing the handshake information to obtain waveform information; Determine a target protocol matching the interface to be tested according to the waveform information, the plurality of pin signals and the voltage information; A target test module is determined from a plurality of preset test modules according to the target protocol, and the interface to be tested is tested using the target test module.

2. The method according to claim 1, characterized in that The step of determining a target protocol matching the interface to be tested according to the waveform information, the plurality of pin signals, and the voltage information includes: Determine the pin types corresponding to the multiple pin signals according to the multiple pin signals; A target protocol matching the interface to be tested is determined according to the waveform information, the pin types corresponding to the multiple pin signals, and the voltage information.

3. The method according to claim 2, characterized in that The step of determining the pin types corresponding to the plurality of pin signals according to the plurality of pin signals comprises: Using a fine-tuning voltage to pull up or pull down the voltages corresponding to the plurality of pin signals; the pin types corresponding to the plurality of pin signals include a ground type, a floating type, a power type, and a signal type; If the pin signal is in a low level maintenance state and the voltage of the pin signal is not pulled high, it is determined that the pin type corresponding to the pin signal is a ground type or a signal type; If the pin signal is in a high level maintenance state and the voltage of the pin signal is not pulled down, it is determined that the pin type corresponding to the pin signal is a power type, and the voltage value corresponding to the pin signal is determined as the power supply voltage of the interface to be tested; If the pin signal is in a high or low level change state, determine that the pin type corresponding to the pin signal is a signal type, or a suspended type; The determining a target protocol matching the interface to be tested according to the waveform information, the pin types corresponding to the multiple pin signals, and the voltage information includes: Determine the timing signal of the interface to be tested according to the waveform information; A target protocol matching the interface to be tested is determined according to the timing signal, the pin types corresponding to the multiple pin signals, and the voltage information, wherein the voltage information includes a power supply voltage of the interface to be tested.

4. The method according to claim 1, characterized in that: Before acquiring a plurality of pin signals from the interface to be tested, the method includes: The voltage corresponding to the signal of the interface to be tested is converted into a constant voltage according to the target voltage value to obtain the converted signal of the interface to be tested.

5. The method according to any one of claims 1 to 4, characterized in that: The step of acquiring a plurality of pin signals from the interface to be tested includes: The signal of the interface to be tested is collected according to a target sampling frequency to obtain a plurality of pin signals, wherein the target sampling frequency is 20 MHz.

6. The method according to claim 1, characterized in that The plurality of preset test modules include a first protocol type module set and a second protocol type module set, and determining a target test module from the plurality of preset test modules according to the target protocol includes: Determine a target test module from the first protocol type module set according to the target protocol, wherein the first protocol type module includes at least a two-wire low-speed protocol module, a synchronous serial protocol module, a long-distance serial protocol module and a control domain protocol module; and the second protocol type module includes at least a digital input and output protocol module.

7. The method according to claim 6, characterized in that The method further comprises: If the waveform analysis information corresponding to the waveform information does not match the preset character string, the digital input-output protocol module in the second protocol type module is used to test the interface to be tested.

8. A testing device for an interface in a server, characterized in that: include: A first response module, configured to respond to a test request for the interface to be tested in the server, collect a plurality of pin signals from the interface to be tested, and determine voltage information of the interface to be tested according to the plurality of pin signals; A first extraction module, used for extracting handshake information from the test request, and parsing the handshake information to obtain waveform information; A protocol determination module, configured to determine a target protocol matching the interface to be tested according to the waveform information, the plurality of pin signals and the voltage information; The first test module is used to determine a target test module from a plurality of preset test modules according to the target protocol, and use the target test module to test the interface to be tested.

9. An electronic device, characterized in that: The invention comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the method for testing an interface in a server as claimed in any one of claims 1 to 7 is implemented.

10. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for testing an interface in a server according to any one of claims 1 to 7 is implemented.

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