Processing chip and related method

Abstract

The invention provides a processing chip and a related method, and relates to the field of data storage. The processing chip comprises a static random access memory array and a computing unit array. Wherein each static random access memory in the static random access memory array comprises a plurality of storage units, and each storage unit is used for storing 1 bit of data. And the output end of each storage unit is connected with the input end of one computing unit in the computing unit array through an active component. According to the processing chip provided by the invention, based on the characteristic that the weight information is not changed in the convolution operation process of the neural network, the weight information in the storage unit is not read to a register any more, and the weight information is directly transmitted to the calculation unit after the driving is enhanced through the active component. Therefore, a large number of register circuits are saved for the processing chip, the area and the power consumption of the processing chip are greatly reduced, and the computing power of the processing chip is greatly improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of data storage, and more particularly to a processing chip and related methods. Background Art

[0002] With the development of artificial intelligence, convolutional neural networks, as one of the representative algorithms of feedforward neural networks, have evolved rapidly. Convolutional neural networks are based on convolution operations, which are the process of multiplying input data and weights in the analog domain. Among them, traditional AI chips all use a storage-computation separation architecture to perform convolution calculations. However, the amount of data in neural networks is very large, and this architecture is bound to seriously affect its computing power due to the problem of high energy consumption in data transfer.

[0003] In order to meet the demand for massive AI computing power in the future and improve the computing power of AI chips, a digital storage and computing integrated architecture for AI chips is proposed. Specifically, the computing units and storage modules are connected at the end to form a storage and computing network, and then the weight information of each layer is stored in the storage module of each convolutional layer, and the input data is directly input into the computing unit of the first layer. In this way, the computing unit of the first layer reads the weight information of the first layer, outputs the intermediate result, and then inputs the intermediate result into the computing unit of the second layer... and finally obtains the weighted accumulation result of the input data. Since the intermediate data flows internally without leaving the storage and computing core, the energy consumption of data handling is greatly reduced, thereby greatly improving the computing power of the AI ​​chip.

[0004] However, under the existing digital storage and computing integrated architecture, in order to make the data reading of the storage module match the calculation process of the computing unit, the digital storage and computing integrated AI chip reads the weight information in the storage module into the register in advance, and then passes it to the computing unit through the register. In this way, the digital storage and computing integrated AI chip will have the same number of registers as the computing units. The area and power consumption of the registers are quite large, which will cause the area of ​​the entire digital storage and computing integrated AI chip to be very large and the power consumption to be very high. Summary of the invention

[0005] The embodiment of the present application provides a processing chip and related methods. Based on the characteristic that the weight information remains unchanged during the convolution operation of the neural network, the new processing chip no longer reads the weight information in the storage unit into the register, but directly transmits the weight information to the calculation unit through the driven components. In this way, the processing chip saves a large number of register circuits, and its area and power consumption will be greatly reduced, thereby greatly improving the computing power of the processing chip.

[0006] In a first aspect, an embodiment of the present application provides a processing chip, the processing chip comprising:

[0007] The processing chip is a digital storage and computing integrated structure, including a static random access memory (SRAM) array for storing weight information and a computing unit array for performing data operations. Among them, each static random access memory in the static random access memory array is composed of orderly arranged storage units, and each storage unit is used to store 1 bit of data. When the static random access memory is connected to the computing unit, each storage unit in the static random access memory corresponds to an input bit of the computing unit, and the output end of each storage unit is connected to the input bit of a computing unit through an active component.

[0008] In the above structure, the data stored in the storage unit is no longer read into the register for temporary storage, but is directly input into the input of the computing unit after being driven by the connected active components. This is because the weight information does not change during the convolution operation of the neural network. Therefore, there is no time constraint problem when storing the weight information in the static random access memory. In this way, the processing chip saves a large number of register circuits, greatly reducing the area and power consumption of the entire chip, thereby improving the computing power of the processing chip.

[0009] In an optional embodiment, the bit width of each static random access memory in the processing chip is M, and the bit depth is N. Then, each static random access memory includes M*N storage cells. Specifically, in the static random access memory, each row includes M storage cells, and the M storage cells in each row are connected to the same word line. The static random access memory has a total of N word lines, that is, a total of N rows of storage cells. Among them, the N storage cells in each column are connected to the same bit line and the same bit line output line. In this way, the arrangement of the storage cells presents a rectangular structure, with a higher degree of integration, further reducing the area of ​​the static random access memory.

[0010] In an optional implementation, the active components may be components with a driving power supply such as an inverter and a buffer, which is used to enhance the driving and directly transmit the data stored in the storage unit to the computing unit. The active components replace the register to reduce the area of ​​the processing chip.

[0011] In an optional embodiment, when the number of input bits t of the computing unit is equal to the bit width M of the static random access memory, the M storage cells in each row of the SRAM are connected to the input end of a computing unit in turn. At this time, the entire SRAM will be connected to N (bit depth) computing units. When the number of input bits t of the computing unit is less than the bit width M of the static random access memory, each row of storage cells of the SRAM can be connected to multiple computing units. Specifically, when M=t*s+d, each row of storage cells is connected to the input ends of s extreme units in turn, and the entire static random access memory is connected to s*N computing units accordingly. It can be understood that in order to optimize the area power consumption, SRAM is usually customized to a fixed bit depth * fixed bit width size. This embodiment can solve the problem that the number of input bits of the computing unit does not match the bit width. When the bit width is greater than the number of input bits of the computing unit, a row of storage cells can be connected to multiple computing units, which can improve the integration.

[0012] In an optional implementation, the number of storage cells in each row of the SRAM is not necessarily an integer multiple of the number of input bits t of the computing unit, and there may be d excess storage cells. In this case, only the d storage cells in each row need to be left floating.

[0013] In an optional implementation, the number of input bits t of the computing unit can also be greater than the bit width M of the SRAM. For example, if the number of input bits t of the computing unit is t=M*p, then it is necessary to connect every p rows of storage units in the SRAM to the input end of the same computing unit. In this case, the SRAM is connected to N (bit depth) / P computing units.

[0014] Similarly, in this embodiment, the SRAM area power consumption can be optimized first, and the size of the SRAM can be designed. When the SRAM size is fixed, bit splicing can be performed by connecting multiple rows of storage cells to a computing unit to expand the bit position to adapt to the computing unit, so as to achieve the maximum utilization of the SRAM.

[0015] In an optional implementation, the bit depth N is not necessarily an integer multiple of p, that is, there may be a few extra rows of storage cells. In this case, if N = i*p+m, then each P rows of storage cells are connected to the input end of a computing unit, and the entire SRAM is connected to i computing units, and the remaining m rows of storage cells are set to a floating state.

[0016] In an optional embodiment, each storage unit in the SRAM is composed of 6 transistors. It includes a first field effect tube, a second field effect tube, a first inverter and a second inverter. Among them, the gate of the first field effect tube and the gate of the second field effect tube are connected to the same word line, the drain of the first field effect tube is connected to the bit line, and the drain of the second field effect tube is connected to the bit line output line. The input end of the first inverter is connected to the output end of the second inverter, and the output end of the first inverter is connected to the input end of the second inverter to form a lock structure. One end of the lock structure is connected to the source of the first field effect tube, and the other end is connected to the source of the second field effect tube. Among them, the SRAM has a small structure and a fast reading speed, which further reduces the area of ​​the entire processing chip and has higher performance.

[0017] In a second aspect, an embodiment of the present application provides a digital processing method, which is applied to the processing chip provided in the first aspect, and the method includes:

[0018] The processing chip includes a static random access memory and a computing unit connected thereto. Two specific connection methods are that the storage unit included in the static random access memory is connected to an input bit of the computing unit through active components. Among them, the static random access memory stores input data that does not change during the calculation process, such as weight data in the convolution operation. Based on the above structure, when performing calculations, the computing unit first obtains the input first data through an input end, and then receives the data in the random access memory on the link after being driven by active components through another input end. Then the computing unit can operate on the first data and the second data to obtain the operation result.

[0019] Based on the above structure, there is no need to read the second data stored in the static random access memory, because the active components can enhance the drive and directly transmit the second data to the computing unit. Therefore, the processing chip no longer reads data during the data calculation process. This can greatly reduce computing power consumption and improve the computing power of the processing chip.

[0020] In an optional implementation, before using the processing chip to perform data operations, the data that does not change during the operation needs to be written into the static random access memory. Specifically, the address of each storage unit needs to be determined first, and then the corresponding storage unit is selected to write the data.

[0021] In an optional embodiment, the bit width of each static random access memory in the processing chip is M, and the bit depth is N. Then, each static random access memory includes M*N storage cells. Specifically, in the static random access memory, each row includes M storage cells, and the M storage cells in each row are connected to the same word line. The static random access memory has a total of N word lines, that is, a total of N rows of storage cells. Among them, the N storage cells in each column are connected to the same bit line and the same bit line output line. In this way, the arrangement of the storage cells presents a rectangular structure, with a higher degree of integration, further reducing the area of ​​the static random access memory.

[0022] In an optional implementation, the active components may be components with a driving power supply such as an inverter and a buffer, which is used to enhance the driving and directly transmit the data stored in the storage unit to the computing unit. The active components replace the register to reduce the area of ​​the processing chip.

[0023] In a third aspect, an embodiment of the present application provides a data storage and computing chip, which includes a scheduling control unit and a storage and computing unit. The scheduling control unit and the storage and computing unit are coupled. The scheduling control unit is used to store computer instructions, and the storage and computing unit is any processing chip provided in the first aspect. The computer instructions are loaded and executed by the scheduling control unit so that the digital storage and computing chip implements any digital processing method provided in the second aspect.

[0024] In a fourth aspect, an embodiment of the present application provides a data processing system, comprising: a processing chip and a processor. The processor is coupled to the processing chip; the processing chip is any one of the processing chips provided in the first aspect, and the processor is used to execute any one of the digital processing methods provided in the second aspect.

[0025] In an embodiment of the present application, the processing chip is a digital storage and computing integrated structure, including a static random access memory array for storing weight information and a computing unit array for performing data operations. Among them, each static random access memory in the static random access memory array is composed of orderly arranged storage units, and each storage unit is used to store 1 bit of data. When the static random access memory is connected to the computing unit, each storage unit in the static random access memory corresponds to an input bit of the computing unit, and the output end of each storage unit is connected to the input bit of a computing unit through an active component.

[0026] In the above structure, the data stored in the storage unit is directly input to the input end of the computing unit after being enhanced and driven by the connected active components. This is because the weight information does not change during the convolution operation of the neural network. Based on this feature, there is no time constraint problem when the weight information is stored in the static random access memory, so there is no need to read the weight information in the storage module into the register, and the weight information can be directly transmitted to the computing unit through the driven components. In this way, the processing chip saves a large number of register circuits, greatly reducing the area and power consumption of the entire chip, thereby improving the computing power of the processing chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a network architecture diagram of an existing digital storage and computing integrated structure;

[0028] Figure 2 A schematic diagram of the structure of a storage unit of an SRAM provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a processing chip provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of the structure of another processing chip provided in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of the structure of another processing chip provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of the structure of another processing chip provided in an embodiment of the present application;

[0033] Figure 7 A schematic diagram of the structure of another processing chip provided in an embodiment of the present application;

[0034] Figure 8 A schematic diagram of the structure of another processing chip provided in an embodiment of the present application;

[0035] Fig. 9 A schematic diagram of the structure of another processing chip provided in an embodiment of the present application;

[0036] Fig.10 It is a flowchart of a digital processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The embodiment of the present application provides a processing chip and related methods. Based on the characteristic that the weight information remains unchanged during the convolution operation of the neural network, the new processing chip no longer reads the weight information in the storage unit into the register, but directly transmits the weight information to the calculation unit through the driven components. In this way, the processing chip saves a large number of register circuits, and its area and power consumption will be greatly reduced, thereby greatly improving the computing power of the processing chip.

[0038] In the description of this application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship between associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0039] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0040] In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference.

[0041] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0042] It is understood that the "embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the various embodiments in the entire specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It is understood that in various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0043] It can be understood that some optional features in the embodiments of the present application may be implemented independently in certain scenarios without relying on other features, such as the solution on which they are currently based, to solve corresponding technical problems and achieve corresponding effects, or may be combined with other features according to needs in certain scenarios. Accordingly, the devices provided in the embodiments of the present application may also realize these features or functions accordingly, which will not be elaborated here.

[0044] In this application, unless otherwise specified, the same or similar parts between the various embodiments can refer to each other. In this application, if there is no special description or logical conflict between the various embodiments, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and different embodiments can be combined to form new embodiments according to their inherent logical relationships. The following implementation methods of this application do not constitute a limitation on the scope of protection of this application.

[0045] In order to facilitate understanding of the technical solutions of the embodiments of the present application, a brief introduction to the relevant technologies of the embodiments of the present application is given below:

[0046] With the development of artificial intelligence, convolutional neural networks have evolved rapidly as one of the representative algorithms of feedforward neural networks. Convolutional neural networks are based on convolution operations, which are the process of multiplying input data and weights in the analog domain. For example, convolutional neural networks used for image processing can achieve layer filtering through multiplication and addition operations of weights and input pixels.

[0047] The embedded neural processor unit (NPU) is an AI chip designed specifically for IoT artificial intelligence. It adopts the architecture of "data-driven parallel computing" and is particularly good at processing massive multimedia data such as videos and images. Among them, the traditional NPU uses centralized computing and integrated storage (storage and computing separation) to perform convolution calculations. In this way, the computing speed of the computing unit depends on the data transmission speed of the storage module. If the data transmission speed of the storage module cannot keep up with the performance of the computing unit, the computing power of the computing unit will inevitably be limited. At the same time, the amount of data in the neural network is very large, and this storage and computing method will bring about very large energy consumption due to the problem of data handling. These will seriously limit the computing power of the NPU, resulting in the NPU being unable to cope with the massive computing power requirements of future AI.

[0048] To this end, in-memory computing technology has effectively solved the above bottleneck. In-memory computing technology means embedding the computing unit into the storage module, and then making modifications to the core circuit of the storage module so that the process of reading data is the process of data calculation, that is, the calculation and storage of data are integrated (storage and computing in one). In-memory computing technology eliminates the need for frequent data migration between the computing unit and the storage module, and can effectively eliminate the situation where data transmission between the storage module and the computing unit consumes too much energy and has limited speed.

[0049] Based on the above in-memory computing technology, Figure 1 The figure shows a network architecture diagram of an existing digital storage and computing integrated structure. Figure 1 As shown, in the digital storage and computing integrated structure, the computing unit and the storage module are connected to form a storage and computing network to perform convolution calculations. Exemplarily, the storage module can be composed of a static random access memory SRAM, which has the characteristics of small area, low power consumption and fast access speed. The computing unit can be composed of a multiplier for performing point multiplication operations on data.

[0050] Specifically, the convolution weight information is stored in the storage module corresponding to each convolution layer in the order of each convolution layer. When performing a convolution operation, the data is input into the calculation unit of the first layer. In this way, the calculation unit of the first layer reads the weight information of the first layer, outputs the intermediate result, and then inputs the intermediate result into the calculation unit of the second layer... Finally, the weight accumulation result of the initial data is obtained. In this way, the intermediate data will flow internally without leaving the storage and computing core. This greatly reduces the energy consumption of data transfer, solves the memory wall problem, and greatly improves the computing power of the hardware.

[0051] Since the read and write speed of the storage module is inconsistent with the calculation speed of the computing unit, in order to make the data reading of the storage module match the calculation process of the computing unit, the weight information in the storage module needs to be read into the register first, and then passed to the computing unit through the register. In this way, there will be the same number of registers as computing units in the entire structure. Since the area and power consumption of the register are quite large, the area of ​​the entire structure will be very large and the power consumption will be very high.

[0052] Based on the above description, the embodiment of the present application provides a new processing chip and related methods, which can save a large number of register circuits. This is because the weight information remains unchanged during the convolution operation, and the weight information data stored in the storage module will not be frequently refreshed. Therefore, it is not necessary to read it into the register for temporary storage, but the weight information can be directly transmitted to the calculation unit through the driven components. In this way, the processing chip saves a large number of register circuits, and its area and power consumption will be greatly reduced, thereby greatly improving the computing power of the processing chip. The following is a detailed introduction to the embodiment of the present application.

[0053] Before introducing the overall structure of the processing chip provided in the embodiment of the present application, the storage module in the processing chip is first introduced. In the embodiment of the present application, in order to further reduce the area of ​​the processing chip, a static random access memory SRAM is used in the processing chip to store weight information. SRAM has the characteristics of fast working speed and high working performance. As long as this memory remains powered on, the stored data can be kept permanently, and the data will only disappear after the power is turned off. At the same time, SRAM does not require a refresh circuit, and the stored data itself will not be destroyed when the data is read out. Once the data is written, it can be read out multiple times. Therefore, using SRAM to store weight information will have very high reliability.

[0054] Figure 2 The schematic diagram of the structure of a storage unit (SRAM bitcell) of the SRAM provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, a storage unit is composed of 6 transistors. Specifically, the two inverters are each composed of two transistors to achieve a 180-degree flip of the input signal phase. The gate of the first transistor and the gate of the second transistor are connected to the same word line WL, and then the drain of the first transistor is connected to the bit line BL, and the drain of the second transistor is connected to the bit line output line BLB.

[0055] Specifically, when the content stored in the bitcell is 1 and 0 is to be written, the voltage at point Q is VDD. At this time, the voltage value of WL needs to be increased to VDD and the voltage value of BL needs to be 0. Then, the voltage at point Q will be pulled down through the second transistor, and the voltage value at point P will be pulled up through the first transistor. After the push-pull of the two inverters, the content stored in the bitcell changes from 1 to 0. Then the voltage of WL is pulled down to complete the data latching.

[0056] When reading the content stored in the bitcell, BL and BLB need to be pulled to the same potential first, which is generally VDD. When the potentials at both ends of BL and BLB are equal, they can be floated or connected to a voltage source through an impedance, and then WL is turned on. The parasitic capacitance of Q and P is used to produce a voltage divider effect through the second transistor, the first transistor, BL, and BLB, thereby creating a voltage difference between BL and BLB. Finally, an external amplifier circuit is used to amplify the difference signal to read out 1 or 0.

[0057] It is understandable that in the prior art, the content stored in the bitcell needs to be read out to the register for temporary storage according to the external amplification circuit, and then input into the calculation unit by the register for data calculation. In this way, there are more registers with the same number of calculation units, which seriously affects the area and power consumption of the entire structure. In the embodiment of the present application, the weight information stored in the bitcell is unchanged, so there is no need for registers for temporary storage. Instead, the SRAM is kept powered on, and the content stored in the bitcell is directly pulled into the calculation unit using active components.

[0058] Figure 3 This is a schematic diagram of the structure of a processing chip provided in an embodiment of the present application. It can be understood that Figure 3 Taking a bitcell as an example, the basic structure of a processing chip is described. Figure 3 As shown, the output of the SRAM bitcell is connected to the input of the computing unit through an active component R.

[0059] Specifically, in the SRAM bitcell, the gate of the first field effect transistor and the gate of the second field effect transistor are connected to the same word line WL, and then the drain of the first field effect transistor is connected to the bit line BL, and the drain of the second field effect transistor is connected to the bit line output line BLB. The first inverter and the second inverter are connected end to end to form a lock structure, and then one end is connected to the source of the first field effect transistor, and the other end is connected to the source of the second field effect transistor. Then, the connection point Q between the first inverter and the second inverter is used as the output end of the SRAM bitcell, connected to one end of the active component R, and then connected to the input end of the calculation unit through the active component R.

[0060] Understandably, in Figure 3 In the example, the active component R is a NOT gate (inverter). The function of the NOT gate is to enhance the drive, that is, the inverted bit characteristic data in the SRAM bit cell is directly input to the calculation unit after being enhanced by the NOT gate R, and no external amplifier circuit is required to read the data stored in the SRAM bit cell. Therefore, the active component R can also be other active components with enhanced driving functions, such as buffers, etc., which are not limited here.

[0061] Exemplarily, point P at the connection point of the first inverter and the second inverter can also be used as the output end of the SRAM bitcell, that is, point P is connected to the active component R, and then connected to the input end of the calculation unit through R. It can be understood that the data output through point P is opposite to the data stored in the SRAM bitcell, and can be directly input into the calculation unit in some negation operations. If the calculation unit needs to input the data stored in the SRAM bitcell, the data output from point P can be processed, and then the processed and restored data can be input into the calculation unit.

[0062] In view of the above structure, the reading and writing process of the basic structure in the processing chip is briefly introduced. First, the weight information needs to be written into the SRAM. Specifically, write data to each SRAM bitcell in turn, select the SRAM bitcell by selecting the corresponding word line and bit line, and then write the corresponding data to the SRAM bitcell. After the SRAM bitcell stores the data, the data will be input into the input bit corresponding to the calculation unit through the active component R connected to the SRAM bitcell, wherein the calculation unit includes multiple data input terminals, one of which is used to input the data stored in the SRAM, and the other data input terminals are used to input other data. After receiving multiple data, the calculation unit operates on the multiple data and outputs the calculation result. Exemplarily, if the calculation unit is a multiplier, the first input terminal of the multiplier is used to obtain the weight information data W in the SRAM, and the second input terminal is used to input the pixel data F, then the multiplier can output the dot product result O of the weight information and the pixel, that is, O=WF.

[0063] In the above structure, the data stored in the SRAM bitcell is directly output to the computing unit after being enhanced and driven by the active component R. This structure is used in scenarios where the data stored in the SRAM bitcell does not need to be changed during the data calculation process. In this scenario, the memory has no time constraint problem and can directly output the driven digital signal to the link of the computing unit without the need for registers to temporarily store data. In this way, the processing chip saves a large number of register circuits, and its area and power consumption will be greatly reduced, thereby greatly improving the computing power of the processing chip.

[0064] according to Figure 3 The basic structure of the processing chip shown is taken as an example. The structure of the processing chip provided in the embodiment of the present application is introduced in detail below, taking 1MByte SRAM as an example. Figure 4 A schematic diagram of the structure of another processing chip provided in an embodiment of the present application, such as Figure 4 As shown, the corresponding bit width of SRAM is 2048 bits and the bit depth is 4096 bits, that is, the SRAM in the processing chip has 2048 SRAM bitcells (storage units) connected to one word line WL, and there are 4096 word lines in total, and 4096 SRAM bitcells in a column are connected to the same bit line BL and the same bit line output line BLB. For example, storage cell 1 is connected to word line 0, and storage cell 2 is connected to word line 1.

[0065] In this structure, the SRAM includes 2048*4096 storage cells, each storage cell is used to store one bit of data, and the storage cells connected to the same word line are used to connect to the input end of a computing unit, that is, each row of storage cells corresponds to an input bit of a computing unit. Figure 3 In the example, there are 4096 computing units connected to the SRAM, and the number of input bits of each computing unit is 2048.

[0066] Specifically, in this structure, each storage unit is connected to an active component R at the output end, and is connected to an input bit of the computing unit through the active component R. In this way, the data of each storage unit is directly transmitted to the link of the computing unit through the enhanced drive of the active component R, so as to omit the intermediate register. In this way, the structure of the entire processing chip is simpler and more compact, with higher integration, smaller area and lower power consumption, all of which will greatly improve the computing power of the processing chip.

[0067] It is understandable that the bit width and bit depth of the SRAM in the processing chip are not limited and can be customized according to actual computing requirements. At the same time, the active component R can be an inverter, a buffer, etc., which is not limited here. In addition, the connection method between each SRAM bitcell in the SRAM and the input end of the computing unit is also flexible. Several embodiments will be provided below to describe in detail the connection form between the SRAM in the processing chip and the computing unit.

[0068] It is understandable that the logic of SRAM in depth can be reused but the logic in width cannot be reused. However, if the bit depth of SRAM is too large, the area power consumption will increase due to insufficient driving. Therefore, SRAM is generally customized into a relatively square shape. In the processing chip, although SRAM can be customized according to the number of input bits of the computing unit, in order to achieve the optimal area power consumption of SRAM, the size of SRAM can be designed first to determine its bit depth and bit width. At the same time, if SRAM is customized for each computing unit, it will inevitably cost a lot of manpower design costs. However, for SRAM of fixed size, the bit width and bit depth of SRAM are likely to not match the number of input bits of the computing unit. The following will describe the connection between the computing unit and SRAM in detail for several situations.

[0069] First, assume that the bit width of the SRAM is M and the bit depth is N, where M and N are both positive integers greater than 0. Then, the SRAM includes M*N SRAM bitcells. The specific arrangement can be that each row includes M SRAM bitcells, and the M SRAM bitcells are connected to the same word line WL. The entire SRAM has a total of N word lines WL, that is, there are a total of N rows of SRAM bitcells, and the N SRAM bitcells in each column are connected to the same bit line BL and the bit line output line BLB. It can be understood that the connection form of each SRAM bitcell with the word line WL, the bit line BL and the bit line output line BLB refers to Figure 3 The illustrated embodiments are not described in detail here.

[0070] It can be understood that each SRAM bitcell is connected to an input bit of a computing unit. Therefore, based on the above SRAM structure, the connection mode between the computing unit and the SRAM can be determined according to the number of input bits of the computing unit.

[0071] Exemplarily, the number of input bits of a computing unit is M, that is, the number of SRAM bitcells in each row is the same as the number of input bits of the computing unit. Then, a whole row of SRAM bitcells can be connected to the input end of a computing unit in sequence. At this time, the SRAM is connected to N computing units. In a specific example, the bit width of the SRAM is 16 bits and the bit depth is 32 bits. Then, the SRAM can be connected to 32 computing units with an input bit number of 16 bits. For specific connection relationships, please refer to Figure 5 .

[0072] Exemplarily, the number of input bits of a computing unit is less than the bit width, and the number of SRAM bitcells in each row is a multiple of the number of input bits of the computing unit. That is, assume that the number of input bits of the computing unit is t, and M=t*s. Then, a whole row of SRAM bitcells can be connected to the input ends of s computing units in sequence, and the entire SRAM can be connected to s*N computing units accordingly. In a specific example, the bit width of the SRAM is 16 bits and the bit depth is 32 bits. When the SRAM corresponds to a computing unit with an input bit number of 4 bits, each row of SRAM bitcells is connected to the input ends of 4 computing units in sequence, and the entire SRAM can be connected to 4*32 computing units accordingly. For specific connection relationships, please refer to Figure 6 .

[0073] For example, although the number of input bits of a computing unit is less than the bit width, the number of SRAM bitcells in each row is not exactly the number of input bits of the computing unit. That is, assuming that the number of input bits of a computing unit is t, M=t*s+d, and d is a positive integer greater than 0. Then, a whole row of SRAM bitcells can be connected to the input ends of s computing units in sequence, and the remaining d SRAM bitcells can be left floating, while the entire SRAM is connected to s*N computing units. In a specific example, the bit width of the SRAM is 24 bits and the bit depth is 32 bits. When the SRAM corresponds to a computing unit with an input bit number of 16 bits, each row of SRAM bitcells is connected to the input end of one computing unit in sequence, and the remaining 8 SRAM bitcells can be left floating, and the entire SRAM can be connected to 32 computing units. For specific connection relationships, please refer to Figure 7 .

[0074] Exemplarily, the number of input bits of a computing unit can be expanded, that is, the number of input bits of a computing unit is greater than the number of SRAM bitcells in each row. In this case, multiple rows of SRAM bitcells can be connected to the input end of a computing unit in sequence. For example, the number of input bits of a computing unit can be M*p, where p is a positive integer greater than 1. Then, it is necessary to connect p rows of SRAM bitcells to the input end of the same computing unit. And the entire SRAM will be connected to N / p computing units accordingly. In a specific example, the bit width of the SRAM is 8 bits and the bit depth is 32 bits. The SRAM can be connected to a computing unit with an input bit number of 16 bits. Specifically, every two rows of SRAM bitcells are connected to the input end of a computing unit in sequence, and the entire SRAM can be connected to 16 computing units accordingly. For specific connection relationships, please refer to Figure 8 .

[0075] It can be understood that in the above example, the bit depth N is not necessarily an integer multiple of p, that is, N=i*p+m may occur. At this time, the entire SRAM will correspond to the connection of i computing units, and the remaining m rows of SRAM bitcells can be set to a floating state. In a specific example, the bit width of the SRAM is 8 bits and the bit depth is 32 bits. The SRAM can correspond to the connection of a computing unit with an input bit number of 24 bits. Specifically, every three rows of SRAM bitcells are connected to the input end of a computing unit in turn, and the entire SRAM can correspond to the connection of 10 computing units, and the remaining two rows of SRAM bitcells will be in a floating state. For specific connection relationships, please refer to Fig. 9 .

[0076] Based on the above description, when designing a processing chip, the size of the SRAM can be determined based on the optimal area and power consumption, and then the connection method between the SRAM and the computing unit can be determined based on the fixed SRAM. In this way, the maximum utilization of the SRAM can be guaranteed, and the power consumption of the processing chip can be further reduced. It can be understood that the connection method between the SRAM and the computing unit is flexible, and the input bit of each computing unit can be arbitrarily connected to each SRAM bitcell in the SRAM. The connection methods shown in the above figures are only examples, and the specific connection methods are not limited.

[0077] Based on the above structure, Fig.10 is a flow chart of a digital processing method provided in an embodiment of the present application, and the digital processing method is applied to a processing chip shown in any of the above embodiments, such as Fig.10 As shown, the method comprises the following steps:

[0078] 1001. A computing unit obtains first data through a first input terminal.

[0079] It can be understood that the processing chip includes a static random access memory and a computing unit connected thereto. The two specific connection methods are that the storage unit included in the static random access memory is connected to an input bit of the computing unit through active components. Among them, the role of the active components is to enhance the drive, and the data stored in the storage unit can be directly transmitted to the link of the computing unit, without the need to read the amplifier circuit to read the data in the SRAM. Then, before performing data calculations, the computing unit needs to write the unchanged data during the calculation process into the static random access memory, so that the computing unit obtains the input change data from the other input end, and the data in the static random access memory can be reused. Exemplarily, the unchanged data can be weight data in the convolution operation, etc., which is not limited here.

[0080] Exemplarily, the bit width of each static random access memory in the processing chip is M and the bit depth is N. Then, each static random access memory includes M*N storage cells. In the static random access memory, each row is distributed with M storage cells, and the M storage cells in each row are connected to the same word line. The static random access memory has a total of N word lines, that is, a total of N rows of storage cells. Among them, the N storage cells in each column are connected to the same bit line and the same bit line output line. In this way, the arrangement of the storage cells presents a rectangular structure, with a higher degree of integration, further reducing the area of ​​the static random access memory. The active components used to enhance the drive can be inverters, buffers and other components with a driving power supply, and their function is to enhance the drive and directly transmit the data stored in the storage unit to the computing unit. Active components replace registers to reduce the area of ​​the processing chip.

[0081] 1002. The computing unit obtains second data from the static random access memory through a second input terminal.

[0082] After the second data stored in the static random access memory is written, the second data stored in the static random access memory will be automatically introduced into the computing unit, and the computing unit can directly obtain the second data on the link through the second input terminal.

[0083] 1003. The calculation unit outputs the calculation result of the first data and the second data.

[0084] Based on the above structure, there is no need to read the second data stored in the static random access memory, because the active components can enhance the drive and directly transmit the second data to the computing unit. Therefore, the processing chip does not need to read data when performing data calculations. In this way, the computing power consumption can be greatly reduced and the computing power of the processing chip can be improved.

[0085] Based on the above description, the processing chip provided in the embodiment of the present application can be coupled and connected with an electronic device and scheduled by the central processing unit of the electronic device. Specifically, the central processing unit schedules and controls the data writing process of the static random access memory in the processing chip and the calculation process of the calculation unit. It can also be packaged with an independent hardware circuit structure to form an independent data storage and calculation chip with control function. Exemplarily, the data storage and calculation chip includes a scheduling control unit and a storage and calculation unit. Among them, the scheduling control unit and the storage and calculation unit are coupled. The scheduling control unit is used to store scheduling instructions and control instructions. The internal structure of the storage and calculation unit is the same as the internal structure of the above-mentioned processing chip, including a static random access memory and a calculation unit, and the output end of each storage unit in the static random access memory is connected to the input end of the calculation unit through active components. Among them, the data writing process of the static random access memory of the scheduling control unit and the calculation process of the calculation unit enable the entire digital storage and calculation chip to implement the method shown in the above-mentioned embodiment 10.

[0086] The present application also provides a data processing system, including: a processing chip and a processor. The processor is coupled to the processing chip. The processing chip is Figures 1 to 9 Any one of the processing chips provided in the embodiments, the processor is used for Fig.10 Any one of the digital processing methods based on a processing chip in the illustrated embodiments.

[0087] It is understandable that in the embodiments of the present application, the execution subject may execute some or all of the steps in the embodiments of the present application, and these steps or operations are only examples. The embodiments of the present application may also execute other operations or variations of various operations. In addition, the various steps may be executed in different orders presented in the embodiments of the present application, and it is possible that not all operations in the embodiments of the present application need to be executed.

[0088] It should be noted that the message names between the devices or the names of the parameters in the messages in the following embodiments of the present application are only examples, and other names may be used in the specific implementation, and the embodiments of the present application do not specifically limit this.

[0089] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, all or part of the processes (or functions) described in the embodiments of the present application are implemented. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or may contain one or more servers, data centers and other data storage devices that can be integrated with the medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)), etc. In the embodiment of the present application, the computer may include the aforementioned device.

[0090] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in a claim. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

Claims

1. A processing chip, characterized in that: The processing chip comprises: static random access memory array and computing unit array; Wherein, each static random access memory in the static random access memory array includes a plurality of storage units; each storage unit in the plurality of storage units is used to store 1 bit of data; The output end of each storage unit is connected to the input end of a computing unit in the computing unit array through a target component; the target component is an active component.

2. The processing chip according to claim 1, characterized in that: Each static random access memory includes M*N storage units; wherein M is the bit width of each static random access memory, and N is the bit depth of each static random access memory; both M and N are positive integers greater than 0; Wherein, in each of the static random access memories, The M memory cells in each row are connected to the same word line; The N memory cells in each column are connected to the same bit line and the same bit line output line.

3. The processing chip according to any one of claims 1 to 2, characterized in that: The target component is an inverter or a buffer.

4. The processing chip according to claim 3, characterized in that: The number of input bits of the input end of the computing unit is t, and t is a positive integer greater than 0 and less than or equal to M; in each static random access memory, When M=t*s+d, the output ends of the M storage units in each row are connected to the input ends of s computing units in sequence; each static random access memory is used to connect s*N computing units; s is a positive integer greater than or equal to 1, and d is a positive integer greater than or equal to 0 and less than t.

5. The processing chip according to claim 4, characterized in that: In each row of M storage cells, The output end of each t storage units is connected to the input end of the same calculation unit, and the d storage units are suspended; the output end of each storage unit in the t storage units corresponds to an input bit number of the input end of the same calculation unit.

6. The processing chip according to claim 3, characterized in that: The number of input bits at the input end of the computing unit is t=M*p; p is a positive integer greater than 1; In each static random access memory, each p rows of storage cells are sequentially connected to the input end of the same computing unit; each static random access memory is used to connect i computing units; wherein N = i*p+m; The m is a positive integer greater than or equal to 0 and less than the N.

7. The processing chip according to claim 6, characterized in that: When m is greater than 0, in each state random access memory, there are m rows of memory cells that are suspended.

8. The processing chip according to any one of claims 2 to 7, characterized in that: Each of the storage units comprises: A first field effect transistor, a second field effect transistor, a first inverter, and a second inverter; Wherein, the gate of the first field effect transistor and the gate of the second field effect transistor are connected to the same word line; The drain of the first field effect transistor is connected to the bit line, and the drain of the second field effect transistor is connected to the bit line output line; The input end of the first inverter and the output end of the second inverter are connected to the source of the first field effect transistor; The output end of the first inverter and the input end of the second inverter are connected to the source of the second field effect transistor.

9. A digital processing method, characterized in that: The method is applied to a processing chip, the processing chip includes a static random access memory and a computing unit, and the method includes: The calculation unit obtains first data through the first input terminal; The computing unit obtains second data from the static random access memory through a second input terminal; The calculation unit outputs the operation result of the first data and the second data; Among them, the output end of at least one storage unit included in the static random access memory is connected to the second input end of the computing unit through an active component; the static random access memory stores second data; after being driven by the active component, the static random access memory inputs the second data to the second input end.

10. The digital processing method according to claim 9, characterized in that: The second data is written into the static random access memory through the address of the storage unit.

11. The digital processing method according to claim 9 or 10, characterized in that: The static random access memory includes M*N storage units; wherein M is the bit width of the static random access memory, and N is the bit depth of the static random access memory; both M and N are positive integers greater than 0; Wherein, in the static random access memory, The M memory cells in each row are connected to the same word line; The N memory cells in each column are connected to the same bit line and the same bit line output line.

12. The digital processing method according to any one of claims 9 to 11, characterized in that: The target component is an inverter or a buffer.

13. A data storage and computing chip, characterized in that: The data storage and computing chip includes a scheduling control unit and a storage and computing unit; wherein, the scheduling control unit and the storage and computing unit are coupled; the scheduling control unit is used to store computer instructions, and the storage and computing unit is a processing chip as described in any one of claims 1 to 8; the computer instructions are loaded and executed by the scheduling control unit to enable the digital storage and computing chip to implement the method as described in any one of claims 9-12.

14. A data processing system, characterized in that: The data processing system includes a processing chip and a processor, the processor is coupled to the processing chip, the processing chip is the processing chip according to any one of claims 1 to 8, and the processor is used to execute the method according to any one of claims 9 to 12.

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