Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a first dielectric layer on the upper surface of the substrate; forming first through holes distributed at intervals in the first dielectric layer; forming a sacrificial layer in the first through hole; forming a second dielectric layer on the surface of the first dielectric layer, wherein the second dielectric layer covers the upper surface of the first dielectric layer and the exposed sacrificial layer; forming a second through hole in the second dielectric layer, wherein the second through hole exposes the sacrificial layer; and removing the sacrificial layer to form an etched through hole. The etching through hole is formed through the two-step through hole, the unexpected effect is that the problem that the bottom of the through hole is not opened or the resistance of the wire in the through hole is too large due to the high aspect ratio and the micro-load effect of etching in the prior art is solved, it is ensured that the bottom of the through hole is completely opened, the resistance of the wire in the through hole is reduced, and the service life of the through hole is prolonged. Therefore, the performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In existing through-hole manufacturing technology, due to the high aspect ratio and the micro-load effect of etching, the critical dimension of the bottom of the through-hole formed is smaller than the critical dimension of the top of the through-hole, resulting in the bottom of the through-hole occasionally not being opened, making the resistance (Rc) of the wire in the through-hole too large.

[0003] In order to avoid the situation where the bottom of the via is not open and to reduce the resistance of the wire in the via, the size of the bottom of the via (such as width) needs to be set to meet the specification requirements. In order to ensure that the size of the bottom of the via meets the specification requirements, the size of the top of the via needs to be increased; as the key size of semiconductors becomes smaller and smaller, more and more devices are required to be formed in a unit area, which makes the distance between the tops of adjacent vias smaller than the distance between the bottoms of adjacent vias, which easily forms parasitic capacitance and affects the performance of the device. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor structure and a preparation method thereof, which forms an etched through hole by a two-step through hole, thereby preventing the problem of the bottom of the through hole not being opened or the resistance of the wire in the through hole being too large due to the high aspect ratio and the micro-load effect of etching in the prior art, and has the advantages of ensuring that the bottom of the through hole is fully opened, reducing the resistance of the wire in the through hole, avoiding the formation of parasitic capacitance, and ensuring the performance of the device.

[0005] To achieve the purpose of this application, this application provides the following technical solutions:

[0006] In a first aspect, the present application provides a semiconductor structure, comprising:

[0007] providing a substrate;

[0008] forming a first dielectric layer on the upper surface of the substrate;

[0009] Forming first through holes distributed at intervals in the first dielectric layer;

[0010] forming a sacrificial layer in the first through hole;

[0011] forming a second dielectric layer on the surface of the first dielectric layer, wherein the second dielectric layer covers the upper surface of the first dielectric layer and the exposed sacrificial layer;

[0012] forming a second through hole in the second dielectric layer, wherein the second through hole exposes the sacrificial layer;

[0013] The sacrificial layer is removed to form an etched through hole.

[0014] In the preparation method of the semiconductor structure of the present application, an etched through hole is formed by two-step through holes, which prevents the problem of the bottom of the through hole not being opened or the resistance of the wire in the through hole being too large due to the high aspect ratio and the micro-load effect of etching in the prior art. It has the advantages of ensuring that the bottom of the through hole is fully opened, reducing the resistance of the wire in the through hole, avoiding the formation of parasitic capacitance, and ensuring the performance of the device.

[0015] In one embodiment, under the condition of the same etching gas, the etching selectivity ratio between the sacrificial layer and the first dielectric layer is greater than 1:1.

[0016] In one embodiment, an etching selectivity ratio of the second dielectric layer to the first dielectric layer is greater than or equal to 1.

[0017] In one embodiment, an etching selectivity ratio between the second dielectric layer and the first dielectric layer is 1:1-5:1.

[0018] In one embodiment, after forming the sacrificial layer in the first through hole and before forming the second dielectric layer on the surface of the first dielectric layer, the method further includes:

[0019] A portion of the first dielectric layer is removed so that an upper surface of the sacrificial layer is higher than an upper surface of the retained first dielectric layer.

[0020] In the embodiment of the present application, by removing part of the first dielectric layer, the upper surface of the sacrificial layer is made higher than the upper surface of the retained first dielectric layer, so that the pad area of ​​the first through hole and the second through hole contacting each other becomes larger, which can prevent the contact area from being reduced due to overlay offset when etching the second through hole and developing the light, thereby playing a role of self-alignment.

[0021] In one embodiment, the longitudinal cross-section of the first through hole is an inverted trapezoid.

[0022] In the embodiment of the present application, by setting the longitudinal cross-sectional shape of the first through hole to an inverted trapezoid, the pad area of ​​the first through hole and the second through hole is enlarged, which can prevent the contact area from being reduced due to overlay offset when etching the second through hole and developing it, thereby achieving a self-alignment effect.

[0023] In one of the embodiments, a height difference between an upper surface of the sacrificial layer and an upper surface of the retained first dielectric layer is 1-50 nm.

[0024] In one embodiment, the sacrificial layer is removed, and a convex portion is formed at the junction of the second through hole and the first through hole; after removing the sacrificial layer, the method further comprises:

[0025] The first through hole and the second through hole that are connected are pre-processed so that the convex portion is rounded or removed to obtain the etched through hole.

[0026] In one embodiment, a dilute hydrofluoric acid cleaning solution is used to pre-treat the first through hole and the second through hole that are connected, so that the protrusions are rounded or removed to obtain the etched through hole.

[0027] In the embodiment of the present application, the first through hole and the second through hole connected to each other are pre-treated with a dilute hydrofluoric acid cleaning solution to ensure that the protrusions at the contact point between the first through hole and the second through hole are rounded. The protrusions are rounded or removed, ensuring the smoothness of the etched through hole area. At the same time, the contact interface between the through hole area, the first dielectric layer and the second dielectric layer is smooth, avoiding the phenomenon that the chemical cleaning agent will drill into the gap of the contact interface in the subsequent wet cleaning process and cause severe side etching.

[0028] In a second aspect, the present application further provides a semiconductor structure, comprising:

[0029] substrate;

[0030] A first dielectric layer, located on the upper surface of the substrate;

[0031] A second dielectric layer, located on an upper surface of the first dielectric layer;

[0032] An etched through hole penetrates the second dielectric layer and extends into the first dielectric layer; the etched through hole is formed by a two-step etching process.

[0033] In the semiconductor structure of the present application, an etched through hole is formed by two-step through holes, which prevents the problem of the bottom of the through hole not being opened or the resistance of the wire in the through hole being too large due to the high aspect ratio and the micro-load effect of etching in the prior art. It has the advantages of ensuring that the bottom of the through hole is fully opened, reducing the resistance of the wire in the through hole, avoiding the formation of parasitic capacitance, and ensuring the performance of the device.

[0034] In summary, the present application provides a semiconductor structure and a method for preparing the same, which forms an etched through hole through a two-step through hole. The unexpected effect is that it prevents the problem of the bottom of the through hole not being opened or the resistance of the wire in the through hole being too large due to the high aspect ratio and the micro-load effect of etching in the prior art. It has the advantages of ensuring that the bottom of the through hole is fully opened, reducing the resistance of the wire in the through hole, avoiding the formation of parasitic capacitance, and ensuring the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] FIG1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0037] FIG2 is a schematic cross-sectional view of a structure obtained in step S11 of a method for preparing a semiconductor structure provided in an embodiment;

[0038] FIG3 is a schematic cross-sectional view of a structure obtained in step S12 of a method for preparing a semiconductor structure provided in an embodiment;

[0039] FIG4 is a schematic cross-sectional view of a structure obtained in step S13 of a method for preparing a semiconductor structure provided in an embodiment;

[0040] 5 and 6 are schematic cross-sectional views of a structure obtained in step S14 of a method for preparing a semiconductor structure provided in one embodiment;

[0041] 7 is a schematic cross-sectional view of a structure obtained by removing a portion of the first dielectric layer so that the upper surface of the sacrificial layer is higher than the upper surface of the retained first dielectric layer in a method for preparing a semiconductor structure provided in an embodiment;

[0042] FIG8 is a schematic cross-sectional view of a structure obtained in step S15 of a method for preparing a semiconductor structure provided in an embodiment;

[0043] FIG9 is a schematic cross-sectional view of a structure obtained in step S16 of a method for preparing a semiconductor structure provided in an embodiment;

[0044] FIG10 is a schematic cross-sectional view of a structure obtained in step S17 of a method for preparing a semiconductor structure provided in an embodiment;

[0045] FIG. 11 is a schematic diagram of a cross-sectional structure of a method for preparing a semiconductor structure provided in an embodiment, in which a first through hole and a second through hole that are connected are pre-processed to obtain a structure obtained by etching a through hole.

[0046] Description of Reference Numerals

[0047] 10. substrate; 20. shallow trench isolation structure; 30. device structure; 301. gate oxide layer; 302. gate conductive layer; 303. sidewall; 40. barrier layer; 50. first dielectric layer; 60. first through hole; 70. sacrificial layer; 80. second dielectric layer; 90. second through hole; 100. protrusion; 110. etched through hole. DETAILED DESCRIPTION

[0048] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0050] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0051] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0052] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0054] Due to the high aspect ratio and the micro-loading effect of etching, the critical dimension of the bottom of the formed through-hole is smaller than the critical dimension of the top of the through-hole, resulting in the situation that the bottom of the through-hole is occasionally not opened, making the resistance (Rc) of the wire in the through-hole too large.

[0055] In order to avoid the situation where the bottom of the via is not open and to reduce the resistance of the wire in the via, the size of the bottom of the via (such as width) needs to be set to meet the specification requirements. In order to ensure that the size of the bottom of the via meets the specification requirements, the size of the top of the via needs to be increased; as the key size of semiconductors becomes smaller and smaller, more and more devices are required to be formed in a unit area, which makes the distance between the tops of adjacent vias smaller than the distance between the bottoms of adjacent vias, which easily forms parasitic capacitance and affects the performance of the device.

[0056] Referring to FIG. 1 , an embodiment of the present application provides a method for preparing a semiconductor structure. The method for preparing a semiconductor structure may include:

[0057] S11: providing a substrate;

[0058] S12: forming a first dielectric layer on the upper surface of the substrate;

[0059] S13: forming first through holes distributed at intervals in the first dielectric layer;

[0060] S14: forming a sacrificial layer in the first through hole;

[0061] S15: forming a second dielectric layer on the surface of the first dielectric layer, wherein the second dielectric layer covers the upper surface of the first dielectric layer and the exposed sacrificial layer;

[0062] S16: forming a second through hole in the second dielectric layer, wherein the second through hole exposes the sacrificial layer;

[0063] S17: removing the sacrificial layer to form an etched through hole.

[0064] In the embodiment of the present application, an etched through hole is formed by a two-step through hole, which prevents the problem of the bottom of the through hole not being opened or the resistance of the wire in the through hole being too large due to the high aspect ratio and the micro-load effect of etching in the prior art. It has the advantages of ensuring that the bottom of the through hole is fully opened, reducing the resistance of the wire in the through hole, avoiding the formation of parasitic capacitance, and ensuring the performance of the device.

[0065] For example, under the condition of the same etching gas, the etching selectivity ratio of the sacrificial layer to the first dielectric layer is greater than 1:1.

[0066] For example, an etching selectivity ratio of the second dielectric layer to the first dielectric layer is greater than or equal to 1:1.

[0067] For example, the etching selectivity ratio of the second dielectric layer to the first dielectric layer is 1:1-5:1.

[0068] In some embodiments, after step S14 and before step S15, the method for preparing the semiconductor structure further includes: removing a portion of the first dielectric layer so that the upper surface of the sacrificial layer is higher than the upper surface of the retained first dielectric layer.

[0069] For example, the longitudinal section of the first through hole is an inverted trapezoid.

[0070] For example, the height difference between the upper surface of the sacrificial layer and the upper surface of the retained first dielectric layer is 1-50 nm.

[0071] In some embodiments, the sacrificial layer is removed, and a convex portion is provided at the junction of the second through hole and the first through hole; after step S17, the method for preparing the semiconductor structure further includes: pre-processing the connected first through hole and the second through hole so that the convex portion is rounded or removed to obtain an etched through hole.

[0072] For example, since the bottom width of the second through hole is smaller than the top width of the first through hole, a convex portion is provided at the junction of the second through hole and the first through hole after the sacrificial layer is removed. The contact area between the convex portion and the chemical cleaning agent in the wet cleaning process is large, so the etching rate is relatively high. Therefore, a dilute hydrofluoric acid cleaning solution can be used to pre-treat the connected first through hole and the second through hole, so that the convex portion is rounded or removed to obtain an etched through hole, and in the etched through hole area, the contact interface between the first dielectric layer and the second dielectric layer is relatively smooth, which can avoid the chemical cleaning agent from drilling into the contact interface gap between the first dielectric layer and the second dielectric layer in the subsequent wet cleaning process, causing serious side etching.

[0073] It should be understood that, although the various steps in the flowchart of FIG. 1 are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in FIG. 1 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages does not have to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0074] In order to more clearly illustrate the method for preparing the semiconductor device structure in some of the above embodiments, please understand the following embodiments in conjunction with FIG. 1 to FIG. 11 .

[0075] In step S11 , referring to step S11 in FIG. 1 and FIG. 2 , a substrate 10 is provided.

[0076] As an example, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a silicon germanium wafer; in the present embodiment, the substrate 10 is a silicon substrate.

[0077] As an example, in step S11 , please continue to refer to FIG. 2 , the substrate 10 may further include a shallow trench isolation structure 20 .

[0078] As an example, in step S11 , the method for preparing the semiconductor structure may further include the following steps: S21 - S22 .

[0079] S21: forming a device structure 30 on the upper surface of the substrate 10, as shown in FIG. 2;

[0080] S22 : forming a barrier layer 40 on the upper surface of the substrate 10 , wherein the barrier layer 40 covers the device structure 30 , as shown in FIG. 2 .

[0081] Specifically, in this embodiment, the device structure 30 may include a gate structure, and the gate structure may include a gate oxide layer 301, a gate conductive layer 302, and a sidewall 303; more specifically, the gate oxide layer 301 may include but is not limited to a silicon dioxide (SiO2) layer; the gate conductive layer 302 may include but is not limited to a doped polysilicon layer or a metal layer. Specifically, in this embodiment, the gate conductive layer 302 is a doped polysilicon layer. The barrier layer 40 may include but is not limited to a silicon nitride layer.

[0082] In another example, after step S11, the method for preparing the semiconductor structure may further include the step of cleaning the substrate 10. In this way, by cleaning the substrate 10, impurities on the surface of the substrate 10 can be removed to prevent the impurities from affecting subsequent processes, thereby ensuring the performance of the device. Specifically, the substrate 10 can be cleaned with a cleaning solution to achieve cleaning of the substrate 10, or the substrate 10 can be purged with a gas such as nitrogen to achieve cleaning of the substrate 10. It should be noted that when the substrate 10 is cleaned with a cleaning solution, the step of drying the substrate 10 is also included after cleaning. Specifically, the substrate 10 can be purged with a gas such as nitrogen to dry the substrate 10, but is not limited to.

[0083] In step S12 , referring to step S12 in FIG. 1 and FIG. 3 , a first dielectric layer 50 is formed on the upper surface of the substrate 10 .

[0084] As an example, the first dielectric layer 50 may be formed on the upper surface of the substrate 10 by, but not limited to, a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma chemical vapor deposition process (HDP-CVD), or a high aspect ratio process (HARP). The first dielectric layer 50 may include, but not limited to, a borophospho-silicate glass layer (BPSG), a high density plasma layer (HDP), or a high aspect ratio process film layer (HARP).

[0085] In step S13 , referring to step S13 in FIG. 1 and FIG. 4 , first through holes 60 are formed in the first dielectric layer 50 at intervals. The width of the top of the first through hole 60 is L1 as shown in FIG. 4 .

[0086] As an example, the first dielectric layer 50 may be etched using, but not limited to, photolithography and etching processes (such as dry etching processes) to form the first through holes 60 that are distributed at intervals. The intervals between the first through holes 60 may be determined according to actual conditions.

[0087] In step S14 , referring to step S14 in FIG. 1 and FIG. 5 , a sacrificial layer 70 is formed in the first through hole 60 .

[0088] As an example, step S14 may include the following steps:

[0089] S141: forming a sacrificial layer 70 in the first through hole 60 and on the upper surface of the first dielectric layer 50, as shown in FIG. 5;

[0090] S142: removing the sacrificial layer 70 located on the upper surface of the first dielectric layer 50, as shown in FIG. 6 .

[0091] As an example, in step S141, a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma chemical vapor deposition process or a high aspect ratio process may be used to form a sacrificial layer 70 in the first through hole 60. The sacrificial layer 70 may include but is not limited to a polysilicon layer or a spin-on carbon layer (SOC), etc.

[0092] As an example, under the same etching gas, the etching selectivity ratio of the sacrificial layer 70 to the first dielectric layer 50 is greater than 1. For example, the etching selectivity ratio of the sacrificial layer 70 to the first dielectric layer 50 may be 1.5, 2.0, 2.5 or 3.0, etc. The etching selectivity ratio of the sacrificial layer 70 to the first dielectric layer 50 being greater than 1 can ensure that the etching rate of the sacrificial layer 70 is faster than the etching rate of the first dielectric layer 50 under the same etching conditions, thereby ensuring that the upper surface of the sacrificial layer 70 is higher than the upper surface of the retained first dielectric layer 50.

[0093] As an example, in step S142 , the sacrificial layer 70 located on the upper surface of the first dielectric layer 50 may be removed by using, but not limited to, a chemical mechanical planarization (CMP) process or an etching process.

[0094] In some embodiments, after step S14 and before step S15 , as shown in FIG. 7 , the method for preparing the semiconductor structure further includes: removing a portion of the first dielectric layer 50 so that the upper surface of the sacrificial layer 70 is higher than the upper surface of the retained first dielectric layer 50 .

[0095] For example, dry etching or wet etching may be used but is not limited to remove a portion of the first dielectric layer 50. Specifically, in this embodiment, wet etching is used to remove a portion of the first dielectric layer 50, and the etching solution is diluted hydrogen fluoride (HF).

[0096] As an example, please continue to refer to Figure 7. The height difference H between the upper surface of the sacrificial layer 70 and the upper surface of the retained first dielectric layer 50 is 1~50nm. For example, the height difference H between the upper surface of the sacrificial layer 70 and the upper surface of the retained first dielectric layer 50 can be 1nm, 10nm, 20nm, 30nm, 40nm or 50nm.

[0097] As an example, as shown in FIG9 , the longitudinal cross-section of the first through hole 60 is inverted trapezoidal. Since the upper surface of the sacrificial layer 70 is higher than the upper surface of the retained first dielectric layer 50, the width L1 of the top of the first through hole 60 is greater than the width of the portion of the sacrificial layer 70 flush with the upper surface of the retained first dielectric layer 50. This increases the pad area in contact between the first through hole 60 and the second through hole 90, and prevents the contact area from being reduced due to overlay offset when etching and developing the second through hole 90, thereby achieving a self-alignment effect.

[0098] As an example, the height difference between the upper surface of the sacrificial layer 70 and the upper surface of the retained first dielectric layer 50 may be 1-50 nm. For example, the height difference between the upper surface of the sacrificial layer 70 and the upper surface of the retained first dielectric layer 50 may be 1 nm, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm, etc.

[0099] The method for preparing the semiconductor structure provided in the embodiment of the present application removes part of the first dielectric layer 50 so that the upper surface of the sacrificial layer 70 is higher than the upper surface of the retained first dielectric layer 50, thereby increasing the pad area in contact with the first through hole 60 and the second through hole 90. This can prevent the contact area from being reduced due to overlay offset when etching the second through hole 90 and performing light development, thereby playing a role of self-alignment.

[0100] In step S15 , referring to step S15 in FIG. 1 and FIG. 8 , a second dielectric layer 80 is formed on the surface of the first dielectric layer 50 , and the second dielectric layer 80 covers the upper surface of the first dielectric layer 50 and the exposed sacrificial layer 70 .

[0101] As an example, the second dielectric layer 80 may be formed on the surface of the first dielectric layer 50 by using, but not limited to, a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma chemical vapor deposition process, or a high aspect ratio process. The second dielectric layer 80 may include, but not limited to, a borophosphosilicate glass layer, a high-density plasma layer, a high aspect ratio process film layer, or a material layer doped with different contents of boron (B) and phosphorus (P).

[0102] As an example, the material of the second dielectric layer 80 may be the same as that of the first dielectric layer 50 , or may be different from that of the first dielectric layer 50 .

[0103] As an example, the etching selectivity ratio of the second dielectric layer 80 to the first dielectric layer 50 is greater than or equal to 1: 1. For example, the etching selectivity ratio of the second dielectric layer 80 to the first dielectric layer 50 may be 1: 1, 2: 1, or 3: 1, etc.

[0104] As an example, the etching selectivity ratio of the second dielectric layer 80 to the first dielectric layer 50 is 1:1 to 5:1. For example, the etching selectivity ratio of the second dielectric layer 80 to the first dielectric layer 50 can be 1:1, 2:1, 3:1, 4:1 or 5:1. This is because in the wet etching process, the first through hole 60 and the second through hole 90 connected are pre-treated with a dilute hydrofluoric acid cleaning solution to ensure that the convex portion of the contact between the first through hole 60 and the second through hole 90 will be rounded, ensuring that the etched through hole area is smooth. The etching rate of the second dielectric layer 80 is greater than the etching rate of the first dielectric layer 50, which can ensure that the contact area of ​​the first through hole 60 and the second through hole 90 is the same, and at the same time, the contact interface between the through hole area, the first dielectric layer 50 and the second dielectric layer 80 is smooth, avoiding the phenomenon that the chemical cleaning agent will drill into the gap of the contact interface in the subsequent wet cleaning process and cause serious side etching.

[0105] In step S16 , referring to step S16 in FIG. 1 and FIG. 9 , a second through hole 90 is formed in the second dielectric layer 80 , and the second through hole 90 exposes the sacrificial layer 70 .

[0106] As an example, the second dielectric layer 80 can be etched using but not limited to photolithography and etching processes to form a second through hole 90. The width of the bottom of the second through hole 90 is L2 as shown in Figure 9. It should be noted that the width L2 of the bottom of the second through hole is smaller than the width L1 of the top of the first through hole.

[0107] In step S17 , referring to step S17 in FIG. 1 and FIGS. 10 to 11 , the sacrificial layer 70 is removed to form an etched through hole 110 .

[0108] As an example, the sacrificial layer 70 may be removed by, but not limited to, wet etching. Specifically, in this embodiment, the etching solution is a mixture of ammonia and water.

[0109] In another example, when the sacrificial layer 70 is a spin-on carbon layer, the sacrificial layer 70 may be removed by, but not limited to, an ashing process.

[0110] In some embodiments, after removing the sacrificial layer 70, the junction of the second through hole 90 and the first through hole 60 has a protrusion 100, as shown in Figure 10; after step S17, as shown in Figure 11, the method for preparing the semiconductor structure also includes: pre-treating the connected first through hole 60 and the second through hole 90 so that the protrusion 100 is rounded or removed to obtain an etched through hole 110.

[0111] As an example, a dilute hydrofluoric acid cleaning solution may be used to pre-treat the connected first through hole 60 and the second through hole 90 , so that the protrusion 100 is rounded or removed to obtain the etched through hole 110 .

[0112] The present application also provides a semiconductor structure, and the semiconductor structure in the present embodiment can be obtained by using the method for preparing the semiconductor structure shown in Figures 1 to 11. As shown in Figure 11, the semiconductor structure may include: a substrate 10; a first dielectric layer 50 located on the upper surface of the substrate 10; a second dielectric layer 80 located on the upper surface of the first dielectric layer 50; an etched through hole 110 penetrating the second dielectric layer 80 and extending into the first dielectric layer 50; and the etched through hole 110 is formed by a two-step etching process.

[0113] In the embodiment of the present application, an etched through hole is formed by a two-step through hole, which prevents the problem of the bottom of the through hole not being opened or the resistance of the wire in the through hole being too large due to the high aspect ratio and the micro-load effect of etching in the prior art. It has the advantages of ensuring that the bottom of the through hole is fully opened, reducing the resistance of the wire in the through hole, avoiding the formation of parasitic capacitance, and ensuring the performance of the device.

[0114] As an example, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a silicon germanium wafer; in the present embodiment, the substrate 10 is a silicon substrate.

[0115] As an example, please continue to refer to FIG. 11 , the substrate 10 may further include a shallow trench isolation structure 20 .

[0116] In another example, please continue to refer to FIG. 11 , the semiconductor structure may further include: a device structure 30 located on the upper surface of the substrate 10; a barrier layer 40 covers the upper surface of the substrate 10 and the device structure 30; in this embodiment, the device structure 30 may include a gate structure, and the gate structure may include a gate oxide layer 301, a gate conductive layer 302, and a sidewall 303; by way of example, the gate oxide layer 301 may include but is not limited to a silicon dioxide (SiO2) layer; the gate conductive layer 302 may include but is not limited to a doped polysilicon layer or a metal layer. By way of example, in this embodiment, the gate conductive layer 302 is a doped polysilicon layer. The barrier layer 40 may include but is not limited to a titanium nitride layer.

[0117] As an example, the first dielectric layer 50 may include but is not limited to a borophosphosilicate glass layer, a high-density plasma layer, or a high aspect ratio process film layer.

[0118] As an example, the material of the second dielectric layer 80 may be the same as that of the first dielectric layer 50 , or may be different from that of the first dielectric layer 50 .

[0119] As an example, the second dielectric layer 80 may include but is not limited to a borophosphosilicate glass layer, a high-density plasma layer, a high aspect ratio process film layer, or a material layer having a different boron and phosphorus doping content from the first dielectric layer 50 .

[0120] To summarize, in the semiconductor structure and preparation method thereof provided in the embodiments of the present application, an etched through hole is formed by a two-step through hole, and its unexpected effect is to prevent the problem of the bottom of the through hole not being opened or the resistance of the wire in the through hole being too large due to the high aspect ratio and the micro-load effect of etching in the prior art. It has the advantages of ensuring that the bottom of the through hole is fully opened, reducing the resistance of the wire in the through hole, avoiding the formation of parasitic capacitance, and ensuring the performance of the device.

[0121] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a first dielectric layer on the upper surface of the substrate; Forming first through holes distributed at intervals in the first dielectric layer; forming a sacrificial layer in the first through hole; forming a second dielectric layer on the surface of the first dielectric layer, wherein the second dielectric layer covers the upper surface of the first dielectric layer and the exposed sacrificial layer; forming a second through hole in the second dielectric layer, wherein the second through hole exposes the sacrificial layer; The sacrificial layer is removed to form an etched through hole.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Under the condition of the same etching gas, the etching selectivity ratio between the sacrificial layer and the first dielectric layer is greater than 1:

1.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: An etching selectivity ratio between the second dielectric layer and the first dielectric layer is greater than or equal to 1.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The etching selection ratio of the second dielectric layer to the first dielectric layer is 1:1-5:

1.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: After forming a sacrificial layer in the first through hole and before forming a second dielectric layer on the surface of the first dielectric layer, the method further includes: A portion of the first dielectric layer is removed so that an upper surface of the sacrificial layer is higher than an upper surface of the retained first dielectric layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The longitudinal cross-section of the first through hole is an inverted trapezoid.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that: The height difference between the upper surface of the sacrificial layer and the upper surface of the retained first dielectric layer is 1-50 nm.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that: The sacrificial layer is removed, and a convex portion is formed at the junction of the second through hole and the first through hole; After removing the sacrificial layer, the method further comprises: The first through hole and the second through hole that are connected are pre-processed so that the convex portion is rounded or removed to obtain the etched through hole.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The first through hole and the second through hole that are connected are pre-treated using a dilute hydrofluoric acid cleaning solution, so that the convex portion is rounded or removed to obtain the etched through hole.

10. A semiconductor structure, characterized in that: include: substrate; A first dielectric layer, located on the upper surface of the substrate; A second dielectric layer, located on an upper surface of the first dielectric layer; An etched through hole penetrates the second dielectric layer and extends into the first dielectric layer; the etched through hole is formed by a two-step etching process.

Images