Stacking device based on chip capacitor

Abstract

A stacking device based on chip capacitors comprises a functional circuit formed by stacking and vertically interconnecting the chip capacitors, and the functional circuit is connected with an external circuit through a bonding process. According to the device, the chip capacitor, the resistor and the bare chip are configured, the chip capacitor, the chip resistor and the semiconductor chip are vertically connected by means of lamination, and then the minimum device is formed by means of bonding, so that a traditional planar structure is changed into a three-dimensional structure, the size of the device is greatly reduced, and the size of the device is reduced. And meanwhile, distributed inductance and stray capacitance caused by a planar structure are reduced, and better performance and smaller size are achieved.

Description

Technical Field

[0001] The invention relates to a stacking device based on chip capacitors. Background Art

[0002] With the continuous development of semiconductor technology and packaging technology, the size of electronic products is getting smaller and smaller. However, since capacitors in semiconductors are limited by process and dielectric materials, it is difficult to directly integrate them through semiconductor technology. Therefore, ceramic capacitors are widely used in circuit applications to reduce product volume. Although the size of ceramic capacitors has been reduced from 0402 to 0201 and is still decreasing, due to its process, it is impossible to use stacking technology to vertically interconnect capacitors with different capacitance values ​​with resistors and chips, and the product size cannot be further reduced. Summary of the invention

[0003] The object of the present invention is to provide a stacked device based on chip capacitors, which can reduce the distributed inductance and stray capacitance caused by the planar structure and achieve miniaturization of the device.

[0004] To achieve the purpose of the present invention, a stacking device is provided herein, which includes a functional circuit formed by vertically interconnecting chip capacitor stacks, and the functional circuit is then connected to an external circuit through a bonding process.

[0005] In some embodiments, the device also includes a chip resistor and a semiconductor chip that are vertically interconnected with the chip capacitor stack to form a function, the back of the chip resistor is an insulating surface, the connection end is formed on the front side, and the semiconductor chip is a bare chip.

[0006] In some embodiments, the device uses a bonding or welding process to vertically interconnect the chip capacitors, the chip resistors, the semiconductor chips, the chip capacitors and the chip resistors, the chip capacitors and the semiconductor chip, or the chip resistors and the semiconductor chip.

[0007] The technical effects of the present invention are:

[0008] 1) This device configures chip capacitors, resistors and bare chips, vertically connects chip capacitors, chip resistors and semiconductor chips by stacking, and then forms a minimized device by bonding, turning the traditional planar structure into a three-dimensional structure, greatly reducing the size of the device, while reducing the distributed inductance and stray capacitance caused by the planar structure, and having better performance and smaller size.

[0009] 2) The vertical stacking of the device can not only further reduce the size of the device, but also ensure the effective stacking interconnection between chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are part of this application and are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but do not constitute an improper limitation of the present invention. Obviously, the drawings described below are only some embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0011] Figure 1 This is a distribution diagram of the chip capacitor tiling method described in the present invention;

[0012] Figure 2 The schematic diagram of the chip capacitor stacked with the chip resistor described in the present invention;

[0013] Figure 3 A schematic diagram of a chip capacitor stacked with semiconductor chips as described in the present invention;

[0014] Figure 4 A schematic diagram describing the stacking of chip capacitors, chip resistors, and semiconductor chips for the present invention;

[0015] Figure 5 A structural diagram of a stacking device formed by vertically stacking a chip capacitor, a chip resistor, and a semiconductor chip is described for the present invention;

[0016] Figure 6 A circuit diagram of an ideal oscillator circuit described for the present invention;

[0017] Figure 7 This is the circuit diagram of the actual oscillation circuit. DETAILED DESCRIPTION

[0018] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the invention will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0019] Chip capacitors are capacitors with upper and lower electrode structures made of ceramic substrates or semiconductor materials. This capacitor is suitable for reducing distributed parameters and is used for bonding upper and lower plate capacitors. This capacitor is different from traditional two-terminal capacitors and is connected in an upper and lower pole manner. Figure 1 Tiling method shown.

[0020] In order to further reduce the size of the circuit assembly, the stacked device uses bonding or welding technology to vertically connect chip capacitors or chip capacitors and semiconductor chips (bare chips) or multiple chip capacitors (including chip resistors) and multiple semiconductor chips, and other electrodes are connected to external circuits through bonding technology, thereby achieving minimized three-dimensional installation. Figure 2-5 .

[0021] The device has a maximum planar installation size for the bottom chip capacitor stack, and the remaining chip capacitors, chip resistors and semiconductor chips are stacked on the bottom chip capacitor to achieve electrical connection, forming a vertical stack interconnection, eliminating the planar structure, and eliminating the planar wiring size and wiring spacing, so that the circuit size is further reduced; the stacking to achieve interconnection reduces the line resistance and distributed inductance.

[0022] In the present disclosure, a chip capacitor stacked with a chip capacitor including a chip resistor is a vertically stacked interconnection between chip capacitors and chip capacitors (including chip resistors), and the surface electrodes are then connected to the outside by bonding; Figure 2 As shown, C1~Cn are chip capacitors (new capacitors with upper and lower electrode structures made of ceramic substrates or semiconductor materials), Rn is a chip resistor (a resistor with back insulation made of thick film, thin film or semiconductor technology and a front side bonding process), C1 and C2 or C1 and Cn, Rn are vertically stacked by bonding or welding process, and the bottom of the stacked device can be connected to other substrates such as PCB, thick film, thin film, DBC, ceramic, semiconductor material, etc. by bonding or welding, and the top is connected by bonding process ( Figure 5 As shown), the product can be miniaturized.

[0023] Chip capacitor stacking chip capacitors contain chip resistors, with C1 as the bottom layer, and C2 to Cn (including Rn) bonded or welded on C1 to form an upper and lower layer stacking method. On this basis, taking C2 as an example, Cx or Rx is continued to be stacked through bonding or welding processes, and so on. It can be stacked from a single simple stack to a more complex multiple stacking. When stacking, the size of the next layer of devices must be larger than the size of the previous layer.

[0024] The chip capacitor stacked semiconductor chip is vertically stacked and interconnected between the chip capacitor and the semiconductor chip, and the surface electrodes are connected to the outside by bonding; Figure 3 As shown, C1~Cn are chip capacitors (new capacitors with upper and lower electrode structures made of ceramic substrate or semiconductor material), V1~Vn are semiconductor chips (the figure takes triode as an example, but is not limited to triode, and the semiconductor chip is a bare chip), C1 and V1~Vn (which can be one chip or multiple chips) or C1~Cn and V1 or C1~Cn and V1~Vn are vertically stacked by bonding or welding process, and the bottom of the stacked device can be connected to other substrates such as PCB, thick film, thin film, DBC, ceramic, semiconductor material, etc. by bonding or welding, and the top is connected by bonding process ( Figure 5 As shown), the product can be miniaturized.

[0025] Chip capacitors stack semiconductor chips, with C1 as the bottom layer, and V1~Vn glued or welded on C1 to form an upper and lower stacking method, which is the simplest stacking method; with C1 as the bottom layer, Cx and Vx glued or welded on C1 to form the first stacking, and then Cn or Vn glued or welded on the basis of Cx to form a multi-layer stack. When stacking, the size of the next layer of devices must be larger than the size of the previous layer.

[0026] The chip capacitors, chip resistors, and semiconductor chips are stacked with each other by vertically stacking and interconnecting the chip capacitors, chip resistors, and semiconductor chips, and the surface electrodes are then connected to the outside by bonding; Figure 4 As shown, C1~Cn are chip capacitors (new capacitors with upper and lower electrode structures made of ceramic substrates or semiconductor materials), Rn is a chip resistor (a resistor with back insulation made of thick film, thin film or semiconductor technology and front bonding process), V1~Vn are semiconductor chips (the figure takes triode as an example, but is not limited to triode), C1~Cn, Rn and V1~Vn are vertically stacked by bonding or welding process (the number of chip capacitors, chip resistors and semiconductor chips and the stacking method can be freely combined), and the bottom of the stacked device can be connected to other substrates such as PCB, thick film, thin film, DBC, ceramics, semiconductor materials, etc. by bonding or welding, and the top is connected by bonding process ( Figure 5 As shown), the product can be miniaturized.

[0027] Chip capacitors, chip resistors, and semiconductor chips are stacked with C1 as the bottom layer. Cx, Rx, and Vx are bonded or welded on C1 to form the first stack. Cm, Rm, and Vm are stacked on the basis of Cx by bonding or welding to form the mth stack. Cn, Rn, and Vn are stacked on the basis of Cm by bonding or welding to form the nth stack. Each time C, R, and V are stacked, they can be one or more free combinations. When stacking, the size of the next layer of devices must be larger than the size of the previous layer.

[0028] This stacked device transforms the original planar structure into a vertical structure, minimizing the device and minimizing the impact of distributed inductance and stray capacitance. The chip capacitors, chip resistors and semiconductor chips in this device can be built into any functional circuit, such as a bridge drive circuit, an oscillation circuit, a switching circuit, etc. Since the line resistance and distributed inductance are reduced, the functional circuit formed has stable performance and low EMI. The functional circuit built by this device needs to be connected to the external circuit by bonding. Figure 6In the oscillation circuit shown in the figure, the base of the transistor Q1, the end of the inductor L connected to the capacitor C1, and the emitter of the transistor Q1 need to be brought out by bonding, and electrically connected to the external bias circuit (for providing a bias signal to the base), the power supply (for providing a bias signal to the collector), and the circuit ground respectively; Figure 6 The figure shows an ideal oscillation circuit. However, if a planar layout is used and the components are connected by wires or traces on a printed circuit board, more line resistance will be generated, resulting in an actual oscillation circuit such as Figure 7 As shown in the figure (Rx is the line resistance), by using the device to build an oscillation circuit, the line circuit and distributed inductance can be effectively reduced, the oscillation circuit can be closer to the ideal oscillation circuit, the performance of the oscillation circuit can be improved, and interference can be reduced.

[0029] The present disclosure has been described by the above-mentioned relevant embodiments, but the above-mentioned embodiments are only examples for implementing the present disclosure. It must be pointed out that the disclosed embodiments do not limit the scope of the present disclosure. On the contrary, changes and modifications made without departing from the spirit and scope of the present disclosure are all within the scope of patent protection of the present disclosure.

Claims

1. A stacking device based on chip capacitors, characterized in that: The device comprises a functional circuit formed by vertically interconnecting chip capacitor stacks, and the functional circuit is then connected to an external circuit through a bonding process.

2. The chip capacitor stacking device according to claim 1, characterized in that: It also includes a chip resistor and a semiconductor chip that are vertically interconnected with the chip capacitor stack to form a function. The back of the chip resistor is an insulating surface, and the connection end is formed on the front side. The semiconductor chip is a bare chip.

3. The chip capacitor stacking device according to claim 2, characterized in that: Adhesion or welding technology is used to vertically interconnect the chip capacitors, the chip resistors, the semiconductor chips, the chip capacitors and the chip resistors, the chip capacitors and the semiconductor chip, or the chip resistors and the semiconductor chip.

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