Multi-chip packaging body and preparation method thereof

Abstract

The invention discloses a multi-chip packaging body and a preparation method thereof. The multi-chip packaging body comprises a first plastic packaging plate, a second plastic packaging plate and a third plastic packaging plate which are sequentially stacked and arranged in an attached mode. A first chip is installed in the first plastic packaging plate. A target connecting piece is arranged in the second plastic package plate piece, and one end of the target connecting piece is connected with the drain electrode of the first chip; a second chip is installed in the third plastic package plate, and the drain electrode of the second chip is connected with the end, away from the first chip, of the target connecting piece. Through the mode, the connection path between the first chip and the second chip can be shortened, the signal transmission delay can be effectively reduced, the signal transmission efficiency is improved, the parasitic inductance and resistance of the multi-chip packaging body are effectively reduced, and the overall performance of the multi-chip packaging body is improved.

Description

Technical Field

[0001] The present application is applied to the technical field of chip packaging, in particular to a multi-chip package and a preparation method thereof. Background Art

[0002] Chip packaging is the shell used to install semiconductor integrated circuit chips. It plays the role of placing, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance. It is also a bridge to communicate the internal world of the chip with the external circuit.

[0003] Existing multi-chip packages mostly use traditional wire bonding. Although this technology provides reliable electrical connections, it also has some limitations.

[0004] Due to the presence of leads, there is a delay in signal transmission, which has an adverse effect on applications that require high-speed signal transmission. Summary of the invention

[0005] The present application provides a multi-chip package and a preparation method thereof to solve the problem of signal transmission delay in chip packaging.

[0006] In order to solve the above technical problems, the present application provides a method for preparing a multi-chip package, including: a first plastic packaging panel, a second plastic packaging panel and a third plastic packaging panel that are stacked and bonded in sequence: a first chip is installed in the first plastic packaging panel; a target connector is arranged in the second plastic packaging panel, and one end of the target connector is connected to the drain of the first chip; a second chip is installed in the third plastic packaging panel, and the drain of the second chip is connected to an end of the target connector away from the first chip.

[0007] In some embodiments, the first plastic sealing panel includes a first chip, a conductive substrate, a first plastic sealing layer and a plurality of first connecting members; a mounting groove is provided on the conductive substrate, and the first chip is installed in the mounting groove; a chip conductive layer is provided on the side of the first chip close to the second plastic sealing panel, and a substrate conductive layer is provided on the side of the conductive substrate close to the second plastic sealing panel; the first plastic sealing layer plastic seals the side of the conductive substrate away from the second plastic sealing panel, wraps the first chip and fills the mounting groove; a plurality of first connecting members are provided in the first plastic sealing layer, one end of each first connecting member is connected to the first chip, and the other end of each first connecting member extends from the side of the first plastic sealing layer away from the second plastic sealing panel until it is connected to the conductive substrate.

[0008] In some embodiments, the third plastic packaging panel includes a second chip, a third plastic packaging layer and multiple second connectors; the third plastic packaging layer and the second chip are bonded to the side of the second plastic packaging panel away from the first plastic packaging panel, and the third plastic packaging layer wraps the second chip; the second connectors are arranged in the third plastic packaging layer, one end of each second connector is connected to the second chip, and the other end of each second connector extends from the side of the third plastic packaging layer away from the second plastic packaging panel until it is connected to the target connector.

[0009] In some embodiments, the second plastic encapsulation panel includes a second plastic encapsulation layer, in which a plurality of target connectors are arranged; the target connectors include a first target connector and a second target connector; the opposite ends of the first target connector are respectively connected to the drain of the first chip and the drain of the second chip, and the opposite ends of the second target connector are respectively connected to the substrate conductive layer and the corresponding second connector.

[0010] In some embodiments, a first solder resist layer and a second solder resist layer are respectively provided on opposite sides of the multi-chip package; the first solder resist layer covers a side of the third plastic sealing panel away from the second plastic sealing panel, and the second solder resist layer partially covers a side of the first plastic sealing panel away from the third plastic sealing panel to expose multiple first connecting parts.

[0011] In order to solve the above-mentioned technical problems, the present application provides a method for preparing a multi-chip package for preparing a multi-chip package of any of the above-mentioned embodiments, including: obtaining a first plastic sealing panel; a first chip is installed in the first plastic sealing panel; a second plastic sealing panel is prepared by bonding on one side of the first plastic sealing panel; a target connector is provided in the second plastic sealing panel, and one end of the target connector is connected to the drain of the first chip; a third plastic sealing panel is prepared by bonding on the side of the second plastic sealing panel away from the first plastic sealing panel to obtain a multi-chip package, wherein the drain of the second chip in the third plastic sealing panel is connected to one end of the target connector away from the first chip.

[0012] In some embodiments, obtaining a first plastic encapsulation panel includes: obtaining a conductive substrate and preparing a mounting groove on one side of the conductive substrate; installing a first chip in the mounting groove, wherein a drain of the first chip is arranged in a direction away from a target side of the conductive substrate; and plastic encapsulating the target side of the conductive substrate to plastic encapsulate the first chip and fill the mounting groove.

[0013] In some embodiments, a second plastic-sealed plate is prepared by bonding on one side of a first plastic-sealed plate, including: etching a side of a conductive substrate away from a target side to form a chip conductive layer and a substrate conductive layer; wherein the chip conductive layer is bonded to the first chip, and the substrate conductive layer is bonded to the conductive substrate; plastic-sealing the side of the first plastic-sealed plate away from the target side to obtain a second plastic-sealed plate; drilling a side of the second plastic-sealed plate away from the first plastic-sealed plate to obtain a plurality of first blind holes respectively exposing the chip conductive layer and the substrate conductive layer; electroplating and etching in sequence on a side of the second plastic-sealed plate away from the first plastic-sealed plate to form a plurality of target connectors corresponding to the plurality of first blind holes, wherein the target connectors include a first target connector connecting the chip conductive layer and a second target connector connecting the substrate conductive layer.

[0014] In some embodiments, a third plastic sealing board is prepared by laminating on a side of the second plastic sealing board away from the first plastic sealing board to obtain a multi-chip package, including: laminating and installing a second chip on a side of the first target connector away from the first plastic sealing board, and connecting the drain of the second chip to the first target connector; plastic sealing the side of the second plastic sealing board away from the first plastic sealing board to obtain a third plastic sealing board; drilling the side of the third plastic sealing board away from the second plastic sealing board to obtain a plurality of third blind holes that respectively expose the second chip and the second target connector; electroplating and etching the side of the third plastic sealing board away from the second plastic sealing board in sequence to form a plurality of second connectors based on the plurality of third blind holes to obtain a multi-chip package.

[0015] In some embodiments, drilling is performed on the second plastic sealing plate to obtain a plurality of first blind holes respectively exposing the conductive layer and the conductive substrate, and also includes: drilling on the side of the first plastic sealing plate away from the second plastic sealing plate to obtain a plurality of second blind holes respectively exposing the first chip and the conductive substrate; electroplating and etching are performed on the side of the second plastic sealing plate away from the first plastic sealing plate in sequence to form a plurality of target connectors based on the plurality of first blind holes, including: electroplating on the side of the first plastic sealing plate away from the second plastic sealing plate to fill the plurality of second blind holes to form a target electroplating layer; electroplating and etching are performed on the side of the third plastic sealing plate away from the second plastic sealing plate in sequence to form a plurality of second connectors based on the plurality of third blind holes, and also includes: etching the target electroplating layer to form a plurality of first connectors to lead out the signal of the first chip.

[0016] In order to solve the above technical problems, the multi-chip package of the present application makes the connection path between the first chip and the second chip a target connection part, and the relatively short path can effectively reduce the signal transmission delay, improve the signal transmission efficiency, and effectively reduce the parasitic inductance and resistance of the multi-chip package, thereby improving the overall performance of the multi-chip package. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flow chart of an embodiment of a method for preparing a multi-chip package provided by the present application;

[0018] Figure 2 is a schematic flow chart of another embodiment of the method for preparing a multi-chip package provided by the present application;

[0019] Figure 3 yes Figure 2 A schematic diagram of the structure of the upper half of the preparation process in the embodiment;

[0020] Figure 4 yes Figure 2 A schematic diagram of the structure of the second half of the preparation process in the embodiment;

[0021] Figure 5 is a structural schematic diagram of an embodiment of a multi-chip package provided by the present application;

[0022] Figure 6 is a structural schematic diagram of another embodiment of a multi-chip package provided by the present application;

[0023] Figure 7 yes Figure 6 A circuit schematic diagram of a multi-chip package in an embodiment. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0025] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0026] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0027] See also Figure 1 , Figure 1 It is a schematic flow chart of an embodiment of a method for preparing a multi-chip package provided in the present application.

[0028] Step S11: obtaining a first plastic-sealed plate; a first chip is installed in the first plastic-sealed plate.

[0029] The first chip of the present embodiment may include a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and the first chip is plastic-sealed by a first plastic-sealing board.

[0030] Step S12: preparing a second plastic-sealed plate by laminating one side of the first plastic-sealed plate; a target connector is disposed in the second plastic-sealed plate, and one end of the target connector is connected to the drain of the first chip.

[0031] A second plastic sealing panel is prepared by laminating one side of the first plastic sealing panel, so that the second plastic sealing panel is laminating one side of the first plastic sealing panel.

[0032] The number of target connectors in the second plastic-sealed panel may include but is not limited to 5, 8, 10, 15 or 20, etc., and may be specifically set based on actual connection requirements.

[0033] One end of some target connecting members is connected to the drain of the first chip to lead out the drain of the first chip.

[0034] Step S13: preparing a third plastic encapsulation board by laminating the side of the second plastic encapsulation board away from the first plastic encapsulation board to obtain a multi-chip package, wherein the drain of the second chip in the third plastic encapsulation board is connected to the end of the target connector away from the first chip.

[0035] A second chip is mounted on a side of the second plastic-sealed plate away from the first plastic-sealed plate, and plastic-sealed to prepare a third plastic-sealed plate, thereby forming a multi-chip package in which the first plastic-sealed plate, the second plastic-sealed plate and the third plastic-sealed plate are sequentially stacked and bonded.

[0036] The second chip may include a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

[0037] The drain of the second chip in the third plastic packaging board is connected to the end of the corresponding target connector away from the first chip, that is, the target connector in the second plastic packaging board connects the drain of the first chip with the drain of the second chip, so that the first chip and the second chip share the drain, and the connection path between the first chip and the second chip is the target connector, which is relatively short, can effectively reduce signal transmission delay, improve signal transmission efficiency, and effectively reduce the parasitic inductance and resistance of the multi-chip package, thereby improving the overall performance of the multi-chip package.

[0038] Through the above method, the preparation method of the multi-chip package of this embodiment is obtained by obtaining a first plastic sealing plate; a first chip is installed in the first plastic sealing plate; a second plastic sealing plate is prepared by bonding on one side of the first plastic sealing plate; a plurality of target connectors are arranged in the second plastic sealing plate, and one end of some of the target connectors is connected to the drain of the first chip; a third plastic sealing plate is prepared by bonding on the side of the second plastic sealing plate away from the first plastic sealing plate to obtain a multi-chip package, wherein the drain of the second chip in the third plastic sealing plate is connected to the end of the target connector away from the first chip, so that the first chip and the second chip are drain-connected through the target connector, so that the connection path between the first chip and the second chip is the target connector, which is relatively short, can effectively reduce signal transmission delay, improve signal transmission efficiency, and effectively reduce the parasitic inductance and resistance of the multi-chip package, thereby improving the overall performance of the multi-chip package.

[0039] See also Figure 2-4 , Figure 2 is a flow chart of another embodiment of the method for preparing a multi-chip package provided by the present application, Figure 3 yes Figure 2 A schematic diagram of the structure of the upper half of the preparation process in the embodiment. Figure 4 yes Figure 2 A schematic diagram of the structure of the second half of the preparation process in the embodiment.

[0040] Step S21: Obtain a conductive substrate and prepare a mounting groove on a target side of the conductive substrate.

[0041] The conductive substrate may be a metal substrate, and specifically may include but is not limited to a copper substrate, an iron substrate, a silver substrate, an aluminum substrate, a nickel substrate or an alloy substrate.

[0042] The thickness of the conductive substrate may be greater than 100um, and may specifically include but is not limited to 100um, 110um, 130um, 150um, 200um, 250um or 300um, etc. In addition to achieving electrical functions, the conductive substrate within this thickness range can also improve the structural rigidity of the multi-chip package and improve the overall stability of the multi-chip package.

[0043] A mounting groove is prepared on the target side of the conductive substrate. The mounting groove can be a through groove or a blind groove, which is specifically set based on actual conditions. The mounting groove can be prepared by depth control, etching or laser ablation, etc., which are not limited here.

[0044] Step S22: installing the first chip in the installation groove, wherein the drain of the first chip is arranged in a direction away from the target side of the conductive substrate.

[0045] In a specific application scenario, when the mounting groove is a blind groove, the first chip can be directly mounted at the bottom of the mounting groove. The drain of the first chip is arranged in a direction away from the target side, that is, the drain of the first chip fits the bottom of the mounting groove.

[0046] In a specific application scenario, when the mounting groove is a through groove, a temporary bonding layer is set on the conductive substrate away from the target side of the whole board, and the first chip is installed in the mounting groove from the target side until the drain of the first chip contacts the temporary bonding layer. The first chip is installed into the conductive substrate from the target side. That is, the target side is the installation side of the first chip.

[0047] Step S23: plastic-encapsulating the target side of the conductive substrate to plastic-encapsulate the first chip and fill the mounting groove.

[0048] The target side of the conductive substrate is plastic-encapsulated to fill the mounting groove, thereby plastic-encapsulating the first chip.

[0049] In a specific application scenario, when the mounting groove is a blind groove, the target side of the conductive substrate can be directly plastic-sealed to plastic-seale the first chip and fill the mounting groove. In a specific application scenario, when the mounting groove is a through groove, the target side of the conductive substrate away from the temporary bonding layer is plastic-sealed to plastic-seale the first chip and fill the mounting groove.

[0050] Please read further Figure 3 In Figure 3 a, Figure 3 a Take the installation groove as a through groove as an example for explanation.

[0051] The conductive substrate 110 is provided with a mounting groove 112, and a first chip 120 is installed in the mounting groove 112. A temporary bonding layer 101 is laminated on one side of the conductive substrate 110, and a first plastic sealing layer 131 is laminated on the target side 105 of the conductive substrate 110. The first plastic sealing layer 131 fills the mounting groove 112 and wraps the first chip 120. The first metal layer 102 can also be laminated on the side of the first plastic sealing layer 131 away from the conductive substrate 110 for pressure-bonding during plastic sealing and to facilitate the subsequent metal attachment of electroplating.

[0052] When the mounting groove is a blind groove, the plastic sealing method is similar to that of the present embodiment and will not be described in detail.

[0053] Step S24: etching the side of the conductive substrate away from the target side to form a chip conductive layer and a substrate conductive layer.

[0054] In a specific application scenario, when the mounting groove is a blind groove, this step can directly etch the side of the conductive substrate away from the target side to form a chip conductive layer and a substrate conductive layer.

[0055] In a specific application scenario, when the mounting slot is a through slot, this step first removes the temporary bonding layer on one side of the conductive substrate, and electroplates the side of the conductive substrate to form an electroplating layer, and then etches the side to etch the electroplating layer to form a chip conductive layer and a substrate conductive layer.

[0056] Please read further Figure 3 In Figure 3 b, Figure 3 b in Figure 3 On the basis of a, the temporary bonding layer 101 on one side of the conductive substrate 110 is removed, and an electroplating layer is formed on the side of the conductive substrate 110, and finally the side is etched to etch the electroplating layer to form a chip conductive layer 104 and a substrate conductive layer 103. The chip conductive layer 104 is laminated with the first chip 120, specifically, laminated with the drain of the first chip 120, and the substrate conductive layer 103 is laminated with the conductive substrate 110.

[0057] Step S25: plastic-sealing the side of the first plastic-sealed panel away from the target side to obtain a second plastic-sealed panel.

[0058] Please read further Figure 3 In Figure 3 c, Figure 3 c Figure 3 b, plastic-sealing is performed on a side of the first plastic-sealed panel 111 away from the target side 105 to obtain a second plastic-sealed panel 132 .

[0059] A second metal layer 106 may be further provided on a side of the second plastic sealing plate 132 away from the first plastic sealing plate 111 to provide a pressing force during plastic sealing and facilitate metal attachment during subsequent electroplating.

[0060] The plastic packaging layer of the second plastic packaging plate 132 fills up the gap between the chip conductive layer 104 and the substrate conductive layer 103 .

[0061] Step S26: drilling holes on a side of the second plastic-sealed plate away from the first plastic-sealed plate to obtain a plurality of first blind holes that expose the conductive layer of the chip and the conductive layer of the substrate respectively.

[0062] Please read further Figure 3 In Figure 3 d, Figure 3 d in Figure 3 c, the second plastic package plate 132 is drilled to obtain a plurality of first blind holes 141 respectively exposing the chip conductive layer 104 and the substrate conductive layer 103. That is, some of the first blind holes 141 expose the chip conductive layer 104, and the other first blind holes 141 expose the substrate conductive layer 103.

[0063] The multiple drillings in this embodiment can be performed by mechanical depth control or laser ablation.

[0064] In this step, holes can also be drilled on one side of the first plastic encapsulation plate 111 away from the second plastic encapsulation plate 132 to obtain a plurality of second blind holes 142 that respectively expose the first chip 120 and the conductive substrate 110. That is, some of the second blind holes 142 expose the first chip 120, and the other part of the second blind holes 142 expose the conductive substrate 110.

[0065] The number of the first blind holes 141 and the second blind holes 142 is set based on actual needs.

[0066] Step S27: electroplating and etching are performed sequentially on a side of the second plastic encapsulation plate away from the first plastic encapsulation plate to form a plurality of target connectors corresponding to the plurality of first blind holes, wherein the target connectors include a first target connector connected to the conductive layer of the chip and a second target connector connected to the conductive layer of the substrate.

[0067] Please read further Figure 3 In Figure 3 e, Figure 3 e Figure 3 d, electroplating and etching are performed in sequence on a side of the second plastic encapsulation plate 132 away from the first plastic encapsulation plate 111 to form a plurality of target connectors 160 based on the plurality of first blind holes 141 .

[0068] Specifically, the side of the second plastic-sealed plate 132 away from the first plastic-sealed plate 111 is firstly electroplated to fill all the first blind holes 141 and cover the side of the second plastic-sealed plate 132 away from the first plastic-sealed plate 111. Then, the electroplating layer on the side of the second plastic-sealed plate 132 away from the first plastic-sealed plate 111 is etched to form a plurality of target connectors 160.

[0069] The target connection member 160 includes a first target connection member 161 connected to the chip conductive layer 104 and a second target connection member 162 connected to the substrate conductive layer 103 .

[0070] One end of the first target connector 161 is connected to the chip conductive layer 140 , and the other end is exposed outside the second plastic package board 132 ; one end of the second target connector 162 is connected to the substrate conductive layer 103 , and the other end is exposed outside the second plastic package board 132 .

[0071] In this step, the side of the first plastic encapsulation board 111 away from the second plastic encapsulation board 132 may also be electroplated to fill the plurality of second blind holes 142 to form a target electroplating layer 150. The target electroplating layer 150 also covers the side of the first plastic encapsulation board 111 away from the second plastic encapsulation board 132.

[0072] Step S28: mounting a second chip on a side of the first target connector away from the first plastic-sealed plate, and connecting the drain of the second chip to the first target connector; and plastic-sealing the side of the second plastic-sealed plate away from the first plastic-sealed plate to obtain a third plastic-sealed plate.

[0073] Please read further Figure 4 In Figure 4 a, Figure 4 a Figure 3 e, the second chip 170 is mounted on the side of the first target connector 161 away from the first plastic-sealed panel 111, and the drain of the second chip 170 is connected to the first target connector 161; the side of the second plastic-sealed panel 132 away from the first plastic-sealed panel 111 is plastic-sealed to obtain a third plastic-sealed panel 180.

[0074] The third plastic packaging panel 180 is disposed in contact with a side of the second plastic packaging panel 132 away from the first plastic packaging panel 111 , and wraps the second chip 170 .

[0075] After being installed, the second chip 170 is arranged symmetrically with the first chip 120 , one being positive and the other being negative, and the structural stress on the second chip 170 is also greatly reduced, thereby improving the reliability of the multi-chip package.

[0076] Step S29: drilling holes on a side of the third plastic-sealed plate away from the second plastic-sealed plate to obtain a plurality of third blind holes that respectively expose the second chip and the second target connector; electroplating and etching are performed in sequence on the side of the third plastic-sealed plate away from the second plastic-sealed plate to form a plurality of second connectors based on the plurality of third blind holes to obtain a multi-chip package.

[0077] Please read further Figure 4 In Figure 4 b, Figure 4 b in Figure 4 On the basis of a, a third plastic encapsulation plate 180 is drilled on a side away from the second plastic encapsulation plate 132 to obtain a plurality of third blind holes 183 that respectively expose the second chip 170 and the second target connector 162. That is, some of the third blind holes 183 expose the second chip 170, and another part of the third blind holes 183 expose the third blind holes 183.

[0078] The drilling may be performed by mechanical depth control or laser ablation, which is not limited here.

[0079] Please read further Figure 4 In Figure 4 c, Figure 4 c Figure 4 b, electroplating and etching are performed in sequence on a side of the third plastic encapsulation board 180 away from the second plastic encapsulation board 132 to form a plurality of second connectors 190 based on a plurality of third blind holes 183 to obtain a multi-chip package.

[0080] First, the side of the third plastic sealing panel 180 away from the second plastic sealing panel 132 is electroplated to fill the third blind hole 183 and cover the side of the third plastic sealing panel 180 away from the second plastic sealing panel 132 with the entire panel. Then, the electroplating layer on the side of the third plastic sealing panel 180 away from the second plastic sealing panel 132 is etched to form a plurality of second connectors 190.

[0081] One end of each second connector 190 is connected to the second chip 170 , and the other end of each second connector 190 extends from a side of the third plastic encapsulation board 180 away from the second plastic encapsulation board 132 to connect to the second target connector 162 .

[0082] In the above etching step, the target electroplating layer 150 of the first plastic package plate 111 is also etched to form a plurality of first connectors 151 to lead out the signal of the first chip 120. That is, double-sided etching simultaneously prepares the first connectors 151 and the second connectors 190, thereby improving the preparation efficiency.

[0083] In a specific application scenario, solder mask and surface coating can be performed on the opposite sides of the plate, respectively, so as to form a first solder mask layer (not shown) on the side of the third plastic-sealed plate 180 away from the first plastic-sealed plate 111, the first solder mask layer covers the side of the third plastic-sealed plate 180 away from the first plastic-sealed plate 111, and a second solder mask layer (not shown) is formed on the side of the first plastic-sealed plate 111 away from the third plastic-sealed plate 180, the second solder mask layer partially covers the side of the first plastic-sealed plate 111 away from the third plastic-sealed plate 180, so as to expose multiple first connectors 151 and realize external connection. The solder mask layer is used to electrically protect the surface of the multi-chip package. Among them, a semi-cured sheet can also be pressed between the first solder mask layer and the third plastic-sealed plate 180, so as to further improve the structural rigidity of the multi-chip package by using the semi-cured sheet, which is beneficial to the structural stability of the multi-chip package.

[0084] Through the above steps, the preparation method of the multi-chip package of this embodiment realizes one positive and one negative packaging of two chips, and the two chips share the same drain level, and are connected through the target connector. When the horizontal size of the multi-chip package remains unchanged, the chips have high compatibility and a short relative path, which can effectively reduce signal transmission delay, improve signal transmission efficiency, and effectively reduce the parasitic inductance and resistance of the multi-chip package, thereby improving the overall performance of the multi-chip package. The symmetrically arranged multi-chip package of this embodiment can reduce the structural stress caused by structural asymmetry, reduce the warping of the board, and improve the structural reliability, thereby improving the reliability of the multi-chip package. The first plastic-encapsulated board, the second plastic-encapsulated board, and the third plastic-encapsulated board are connected through the target connector, which can also reduce the delamination problem between the plastic-encapsulated boards and improve the structural reliability of the multi-chip package.

[0085] See also Figure 5 , Figure 5 1 is a schematic diagram of the structure of an embodiment of a multi-chip package provided by the present application. The multi-chip package of this embodiment can be prepared by the method for preparing the multi-chip package of any of the above embodiments.

[0086] The multi-chip package 200 of the present embodiment includes a first plastic packaging board 210 , a second plastic packaging board 220 , and a third plastic packaging board 230 which are sequentially stacked and bonded.

[0087] A first chip 211 is installed in the first plastic encapsulation board 210, a plurality of target connectors 221 are arranged in the second plastic encapsulation board 220, one end of the target connector 221 is connected to the drain of the first chip 211, a second chip 231 is installed in the third plastic encapsulation board 230, and the drain of the second chip 231 is connected to one end of the target connector 221 away from the first chip 211. That is, the drain of the first chip 211, the target connector 221 and the drain of the second chip 231 are connected in sequence, so that the connection path between the first chip 211 and the second chip 231 is the target connector 221, which is relatively short and can effectively reduce the signal transmission delay.

[0088] Through the above structure, the multi-chip package of this embodiment makes the connection path between the first chip and the second chip a target connection part, and the relative path is short, which can effectively reduce the signal transmission delay, improve the signal transmission efficiency, and effectively reduce the parasitic inductance and resistance of the multi-chip package, thereby improving the overall performance of the multi-chip package.

[0089] See also Figure 6 , Figure 6 1 is a schematic diagram of the structure of another embodiment of the multi-chip package provided by the present application. The multi-chip package of this embodiment can be prepared by the method for preparing the multi-chip package of any of the above embodiments.

[0090] The multi-chip package 300 of the present embodiment includes a first plastic packaging board 310 , a second plastic packaging board 320 , and a third plastic packaging board 330 which are sequentially stacked and bonded.

[0091] A first chip 311 is installed in the first plastic encapsulation board 310, a plurality of target connectors 321 are arranged in the second plastic encapsulation board 320, one end of the target connector 321 is connected to the drain of the first chip 311, a second chip 331 is installed in the third plastic encapsulation board 330, and the drain of the second chip 331 is connected to one end of the target connector 321 away from the first chip 311. That is, the drain of the first chip 311, the target connector 321 and the drain of the second chip 331 are connected in sequence, so that the connection path between the first chip 311 and the second chip 331 is the target connector 321, which is relatively short and can effectively reduce the signal transmission delay.

[0092] In some embodiments, the first plastic encapsulation plate 310 includes a first chip 311 , a conductive substrate 312 , a first plastic encapsulation layer 315 , and a plurality of first connectors 341 .

[0093] The conductive substrate 312 is provided with a mounting groove 316, and the first chip 311 is mounted in the mounting groove 316. The thickness of the first chip 311 may be slightly smaller than the thickness of the conductive substrate 312, that is, the thickness of the first chip 311 is 95%-100% of the thickness of the conductive substrate 312, so that during the plastic packaging and pressing process, the conductive substrate 312 is used for support, the stress on the first chip 311 is reduced, and the stability of the first chip 311 is improved.

[0094] A chip conductive layer 314 is bonded to one side of the first chip 311 close to the second plastic packaging board 320 , and a substrate conductive layer 313 is bonded to one side of the conductive substrate 312 close to the second plastic packaging board 320 .

[0095] The first plastic layer 315 plasticizes the target side 301 of the conductive substrate 312, wraps the first chip 311 and fills the mounting groove 316; the target side 301 is the side of the conductive substrate 312 away from the second plastic plate 320, and is also the entrance side for mounting the first chip 311.

[0096] A plurality of first connectors 341 are disposed in the first plastic packaging layer 315 , one end of each first connector 341 is connected to the first chip 311 , and the other end of each first connector 341 extends from a side of the first plastic packaging layer 315 away from the second plastic packaging plate 320 to connect to the conductive substrate 312 .

[0097] In a specific application scenario, one end of a first connector 341 is connected to the gate of the first chip 311 through a second blind hole (not marked in the figure) of the first chip 311, and the other end of the first connector 341 extends from the side of the first plastic encapsulation layer 315 away from the second plastic encapsulation plate 320 until it is connected to the corresponding conductive substrate 312 through another second blind hole; one end of a first connector 341 is connected to the source of the first chip 311 through a second blind hole (not marked in the figure) of the first chip 311, and the other end of the first connector 341 extends from the side of the first plastic encapsulation layer 315 away from the second plastic encapsulation plate 320 until it is connected to the corresponding conductive substrate 312 through another second blind hole. The gate and source of the first chip 311 are both arranged opposite to the drain, so that the drain is connected to the drain of the second chip 331, and the gate and source are connected to the first connector 341.

[0098] A portion of the first connection member 341 located on a side of the first plastic packaging layer 315 away from the second plastic packaging board 320 is exposed outside the multi-chip package 300 to lead out chip signals.

[0099] In some embodiments, the third plastic encapsulation plate 330 includes a second chip 331 , a third plastic encapsulation layer 343 and a plurality of second connecting members 332 .

[0100] The third plastic packaging layer 343 and the second chip 331 are laminated on a side of the second plastic packaging panel 320 away from the first plastic packaging panel 310, and the third plastic packaging layer 343 wraps the second chip 331; the second chip 331 is specifically laminated on a side of the target connector 321 away from the first plastic packaging panel 310 to be connected to the target connector 321.

[0101] The second chip 331 and the first chip 311 are symmetrically arranged relative to the second plastic packaging board 320 .

[0102] The second connectors 332 are disposed in the third plastic encapsulation layer 343 , one end of each second connector 332 is connected to the second chip 331 , and the other end of each second connector 332 extends from a side of the third plastic encapsulation layer 343 away from the second plastic encapsulation plate 320 to connect to the target connector 321 .

[0103] The first connection member 341 , the second connection member 332 and the target connection member 321 are arranged so that a plurality of heat sinks are arranged in the multi-chip package 300 to improve the heat dissipation efficiency of the multi-chip package 300 .

[0104] In a specific application scenario, one end of a second connector 332 is connected to the gate of the second chip 331 through a third blind hole (not marked in the figure) of the second chip 331, and the other end of the second connector 332 extends from the side of the third plastic encapsulation layer 343 away from the second plastic encapsulation plate 320 until it is connected to the corresponding target connector 321 through another third blind hole; one end of a second connector 332 is connected to the source of the second chip 331 through a third blind hole (not marked in the figure) of the second chip 331, and the other end of the second connector 332 extends from the side of the third plastic encapsulation layer 343 away from the second plastic encapsulation plate 320 until it is connected to the corresponding target connector 321 through another third blind hole. The gate and source of the second chip 331 are both arranged opposite to the drain, so that the drain is connected to the drain of the first chip 311, and the gate and source are connected to the second connector 332.

[0105] In some embodiments, the second plastic encapsulation plate 320 includes a second plastic encapsulation layer 342, and a plurality of target connectors 321 are disposed in the second plastic encapsulation layer 342; the target connector 321 includes a first target connector 322 and a second target connector 323; the opposite ends of the first target connector 322 are respectively connected to the drain of the first chip 311 and the drain of the second chip 331, and the opposite ends of the second target connector 323 are respectively connected to the substrate conductive layer 313 and the corresponding second connector 332. The number of the first target connector 322 and the second target connector 323 is set based on actual needs and is not limited.

[0106] The first plastic encapsulation layer 315 , the second plastic encapsulation layer 342 and the third plastic encapsulation layer 343 may include one or more insulating materials such as epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), ceramic-based materials, etc.

[0107] The first chip 311 and the second chip 331 are fixedly connected by welding through a target connector 321 prepared through a blind hole in the second plastic encapsulation plate 320, thereby avoiding direct contact between the first plastic encapsulation layer 315 and the third plastic encapsulation layer 343 and improving the bonding strength between different encapsulation materials.

[0108] In a specific application scenario, the gate and source of the first chip 311 are respectively led out through the corresponding first connector 341; the source of the first chip 311 is connected to the source of the second chip 331 through the first target connector 322; and the gate and source of the second chip 331 are led out through the second connector 332, the second target connector 323, the substrate conductive layer 313, the conductive substrate 312 and the first connector 341 in turn, thereby realizing the circuit connection of the multi-chip package 300.

[0109] See also Figure 7 , Figure 7 yes Figure 6 A circuit schematic diagram of a multi-chip package in an embodiment.

[0110] The circuit principle of the multi-chip package 300 is shown in the figure. The first chip 311 and the second chip 331 share a drain.

[0111] In some embodiments, a first solder resist layer 350 and a second solder resist layer 360 are respectively provided on opposite sides of the multi-chip package; the first solder resist layer 350 covers the side of the third plastic sealing panel 330 away from the second plastic sealing panel 320, and the second solder resist layer 360 partially covers the side of the first plastic sealing panel 310 away from the third plastic sealing panel 330 to expose multiple first connecting parts 341.

[0112] The first solder resist layer 350 and the second solder resist layer 360 are used to electrically protect the multi-chip package 300 .

[0113] Through the above structure, the multi-chip package of this embodiment realizes one positive and one negative package of two chips, and the two chips share the same drain level, and the connection is realized through the target connector. When the horizontal size of the multi-chip package remains unchanged, the chip compatibility is high, and the relative path is short, which can effectively reduce the signal transmission delay, improve the signal transmission efficiency, and effectively reduce the parasitic inductance and resistance of the multi-chip package, and improve the overall performance of the multi-chip package; and the symmetrically arranged multi-chip package of this embodiment can reduce the structural stress caused by structural asymmetry, reduce the warping of the board, and improve the structural reliability, thereby improving the reliability of the multi-chip package. The first plastic sealing board, the second plastic sealing board, and the third plastic sealing board are connected through the target connector, which can also reduce the delamination problem between the plastic sealing boards and improve the structural reliability of the multi-chip package. And the arrangement of the first connector and the second connector on the opposite sides of the board increases the heat dissipation area of ​​the multi-chip package and improves the heat dissipation efficiency of the multi-chip package.

[0114] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A multi-chip package, characterized in that: The multi-chip package comprises a first plastic sealing plate, a second plastic sealing plate and a third plastic sealing plate which are stacked and bonded in sequence: A first chip is installed in the first plastic-sealed plate; A target connector is disposed in the second plastic sealing plate, and one end of the target connector is connected to the drain of the first chip; A second chip is installed in the third plastic-sealed plate, and a drain of the second chip is connected to an end of the target connector away from the first chip.

2. The multi-chip package according to claim 1, wherein: The first plastic encapsulation plate comprises a first chip, a conductive substrate, a first plastic encapsulation layer and a plurality of first connecting members; The conductive substrate is provided with a mounting groove, and the first chip is mounted in the mounting groove; a chip conductive layer is bonded to a side of the first chip close to the second plastic sealing plate, and a substrate conductive layer is bonded to a side of the conductive substrate close to the second plastic sealing plate; The first plastic sealing layer plastic seals the side of the conductive substrate away from the second plastic sealing plate, wraps the first chip and fills the mounting groove; A plurality of first connectors are arranged in the first plastic packaging layer, one end of each of the first connectors is connected to the first chip, and the other end of each of the first connectors extends from a side of the first plastic packaging layer away from the second plastic packaging plate until it is connected to the conductive substrate.

3. The multi-chip package according to claim 2, wherein: The third plastic sealing plate comprises a second chip, a third plastic sealing layer and a plurality of second connecting members; The third plastic sealing layer is bonded with the second chip and arranged on a side of the second plastic sealing plate away from the first plastic sealing plate, and the third plastic sealing layer wraps the second chip; The second connector is disposed in the third plastic packaging layer, one end of each second connector is connected to the second chip, and the other end of each second connector extends from a side of the third plastic packaging layer away from the second plastic packaging plate until connected to the target connector.

4. The multi-chip package according to claim 3, wherein: The second plastic sealing plate comprises a second plastic sealing layer, and a plurality of target connecting members are arranged in the second plastic sealing layer; the target connecting members comprise a first target connecting member and a second target connecting member; Two opposite ends of the first target connection member are respectively connected to the drain of the first chip and the drain of the second chip, and two opposite ends of the second target connection member are respectively connected to the substrate conductive layer and the corresponding second connection member.

5. The multi-chip package according to claim 1, wherein: The first solder resist layer and the second solder resist layer are respectively provided on the opposite sides of the multi-chip package; the first solder resist layer covers the side of the third plastic sealing panel away from the second plastic sealing panel, and the second solder resist layer partially covers the side of the first plastic sealing panel away from the third plastic sealing panel to expose the multiple first connecting parts of the first plastic sealing panel.

6. A method for preparing a multi-chip package, characterized in that: The method for preparing the multi-chip package is used to prepare the multi-chip package according to any one of claims 1 to 5, comprising: A first plastic-sealed plate is obtained; a first chip is installed in the first plastic-sealed plate; A second plastic-sealed plate is prepared by laminating one side of the first plastic-sealed plate; a target connector is arranged in the second plastic-sealed plate, and one end of the target connector is connected to the drain of the first chip; A third plastic encapsulation board is prepared by laminating the side of the second plastic encapsulation board away from the first plastic encapsulation board to obtain a multi-chip package, wherein the drain of the second chip in the third plastic encapsulation board is connected to an end of the target connector away from the first chip.

7. The method for preparing a multi-chip package according to claim 6, wherein: The step of obtaining the first plastic-sealed plate comprises: Acquire a conductive substrate, and prepare a mounting groove on a target side of the conductive substrate; Mounting the first chip in the mounting groove, wherein the drain of the first chip is arranged in a direction away from the target side of the conductive substrate; The target side of the conductive substrate is plastic-sealed to plastic-seale the first chip and fill the mounting groove.

8. The method for preparing a multi-chip package according to claim 7, wherein: The step of laminating the second plastic-sealed plate on one side of the first plastic-sealed plate comprises: Etching a side of the conductive substrate away from the target side to form a chip conductive layer and a substrate conductive layer; wherein the chip conductive layer is bonded to the first chip, and the substrate conductive layer is bonded to the conductive substrate; Plastic-sealing a side of the first plastic-sealed panel away from the target side to obtain a second plastic-sealed panel; Drilling holes on a side of the second plastic-sealed plate away from the first plastic-sealed plate to obtain a plurality of first blind holes that expose the chip conductive layer and the substrate conductive layer respectively; The side of the second plastic encapsulation plate away from the first plastic encapsulation plate is electroplated and etched in sequence to form a plurality of target connectors corresponding to the plurality of the first blind holes, wherein the target connectors include a first target connector connected to the chip conductive layer and a second target connector connected to the substrate conductive layer.

9. The method for preparing a multi-chip package according to claim 8, wherein: The method of preparing a third plastic sealing plate by laminating the side of the second plastic sealing plate away from the first plastic sealing plate to obtain a multi-chip package includes: A second chip is mounted on a side of the first target connection member away from the first plastic package plate, and a drain of the second chip is connected to the first target connection member; Plastic-sealing the side of the second plastic-sealed panel away from the first plastic-sealed panel to obtain a third plastic-sealed panel; Drilling a hole on a side of the third plastic-sealed plate away from the second plastic-sealed plate to obtain a plurality of third blind holes that expose the second chip and the second target connector respectively; The side of the third plastic encapsulation plate away from the second plastic encapsulation plate is electroplated and etched in sequence to form a plurality of second connectors based on the plurality of third blind holes to obtain a multi-chip package.

10. The method for preparing a multi-chip package according to claim 9, wherein: The drilling of the second plastic-sealed plate to obtain a plurality of first blind holes respectively exposing the conductive layer and the conductive substrate further comprises: Drilling holes on a side of the first plastic-sealed plate away from the second plastic-sealed plate to obtain a plurality of second blind holes that expose the first chip and the conductive substrate respectively; The step of sequentially electroplating and etching a side of the second plastic-encapsulated plate away from the first plastic-encapsulated plate to form a plurality of the target connectors based on the plurality of the first blind holes comprises: Electroplating a side of the first plastic-sealed plate away from the second plastic-sealed plate to fill the plurality of second blind holes to form a target electroplating layer; The method of sequentially electroplating and etching a side of the third plastic-sealed plate away from the second plastic-sealed plate to form a plurality of second connectors based on the plurality of third blind holes further comprises: The target electroplating layer is etched to form a plurality of first connecting members to lead out the signal of the first chip.

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