Vertical cavity surface emitting type laser chip with epitaxial structure grown on p-type substrate

Abstract

The invention provides a vertical cavity surface emitting type laser chip with an epitaxial structure grown on a p-type substrate. Different from a vertical cavity surface emitting type laser chip with an epitaxial structure grown on an n-type substrate in the prior art, the vertical cavity surface emitting type laser chip disclosed by the invention can be subjected to follow-up processing, a heterogeneous substrate made of a high-heat-dissipation-speed material is used for bonding, an original p-type substrate can be removed, and the yield of the vertical cavity surface emitting type laser chip is improved. Therefore, the vertical cavity surface emitting type laser chip can effectively dissipate heat under high-power operation, and stability and reliability reduction caused by slow heat dissipation of the assembly can be avoided.

Description

Technical Field

[0001] The present invention relates to a vertical cavity surface emitting laser chip, and more particularly to a vertical cavity surface emitting laser chip with an epitaxial structure grown on a p-type substrate, wherein the vertical cavity surface emitting laser chip can be bonded with other heterogeneous substrates to remove the original p-type substrate to improve heat dissipation performance. Background Art

[0002] Laser chips are currently used in many technical fields, such as optical communications, material processing, displays, automotive lighting, dermatology, surgery, and three-dimensional sensing in LiDAR. Common laser chips are roughly divided into edge-emitting laser chips and surface-emitting laser chips. Edge-emitting laser chips can have a smaller laser emission angle, that is, the laser divergence angle is smaller. However, the laser emission angle of surface-emitting laser chips is larger. In general use, it is hoped that the laser chip's laser is concentrated, that is, the laser emission angle cannot be too large.

[0003] After the chip process is completed, the edge-emitting laser chip must be split into core strips and end-face coated. This process is complex and time-consuming and is the key to affecting the process yield. Since the surface-emitting laser chip does not use the natural fracture surface of the crystal as a reflective surface, it does not need to use splitting or end-face coating, which can save considerable process time and avoid affecting the process yield. Therefore, the industry still uses surface-emitting laser chips more frequently. Although the laser emission angle of edge-emitting laser chips is smaller, many applications still use surface-emitting laser chips due to process yield and manufacturing cost issues.

[0004] Please refer to Figure 1 , Figure 1 Schematic cross-sectional view of a VCSEL chip of the prior art. The VCSEL chip 1 is grown on an n-type substrate 101 and thus includes an n-type electrode 100, an n-type substrate 101, an n-type buffer layer 102, an n-type distributed Bragg reflector 103, an n-type cladding layer 104, a quantum well layer 105, a p-type cladding layer 106, a first p-type distributed Bragg reflector 107, an oxide layer 108, a second p-type distributed Bragg reflector 109 and a p-type electrode 110.

[0005] An n-type buffer layer 102 is formed on an n-type substrate 101 , an n-type distributed Bragg reflection layer 103 is formed on the n-type buffer layer 102 , an n-type cap layer 104 is formed on the n-type distributed Bragg reflection layer 103 , a quantum well layer 105 is formed on the n-type cap layer 104 , a p-type cap layer 106 is formed on the quantum well layer 105 , and a first p-type distributed Bragg reflection layer 107 is formed on the p-type cap layer 106 .

[0006] The oxide layer 108 is formed on the first p-type distributed Bragg reflector layer 107, and the oxide layer 108 is provided with a slot 111 to expose a portion of the first p-type distributed Bragg reflector layer 107, so that light can be emitted from the vertical cavity surface emitting laser chip 1. The second p-type distributed Bragg reflector layer 109 is formed on the oxide layer 108. Finally, the p-type electrode 110 is formed on the second p-type distributed Bragg reflector layer 109 and is located outside the slot 111 on the horizontal projection plane, and the n-type electrode 100 is formed under the n-type substrate 101.

[0007] The n-type substrate 101 is a substrate made of gallium arsenide material, and the substrate made of gallium arsenide material is doped to form the n-type substrate 101. The thickness of the n-type substrate 101 is 100 to 120 microns (including the two end values ​​of 100 microns and 120 microns) to support the entire vertical cavity surface emitting laser chip 1. However, the thermal conductivity of gallium arsenide is 46W / m·K, so for a vertical cavity surface emitting laser chip 1 with a power of more than 2 watts, it is easy to affect the stability and reliability of the component during operation due to insufficient heat dissipation. Summary of the invention

[0008] In view of this, the inventor, with the help of his rich professional knowledge and years of practical experience, has improved a vertical cavity surface emitting laser chip, thereby providing a vertical cavity surface emitting laser chip grown on a p-type substrate. After obtaining the vertical cavity surface emitting laser chip grown on a p-type substrate, the technical problem solved is that the original p-type substrate can be replaced by bonding other heterogeneous substrates with better heat dissipation, thereby improving the technical problem of the prior art that the stability and reliability of the components are reduced due to insufficient heat dissipation.

[0009] The technical means adopted by the present invention are described as follows.

[0010] In order to achieve the above-mentioned purpose of the present invention, the present invention provides a vertical cavity surface emitting laser chip with an epitaxial structure grown on a p-type substrate, wherein the vertical cavity surface emitting laser chip includes an epitaxial structure grown on the p-type substrate. The epitaxial structure includes the p-type substrate, an etching stop layer, a p-type buffer layer, a p-type distributed Bragg reflector layer, an oxide layer, a p-type cap layer, a quantum well layer and an n-type distributed Bragg reflector layer in order from bottom to top, wherein the oxide layer is provided with a slot to expose a portion of the p-type distributed Bragg reflector layer.

[0011] According to the above-mentioned VCSEL chip, the VCSEL chip further comprises: a p-type electrode located under the p-type substrate; and an n-type electrode located on the n-type distributed Bragg reflector.

[0012] According to the above-mentioned VCSEL chip, the epitaxial structure of the VCSEL chip further includes: an active layer located above the oxide layer and below the p-type cover layer, a portion of the active layer faces the exposed portion of the p-type distributed Bragg reflector.

[0013] According to the above-mentioned VCSEL chip, the epitaxial structure of the VCSEL chip further includes: an n-type cladding layer located above the quantum well layer and below the n-type distributed Bragg reflection layer.

[0014] According to the vertical cavity surface emitting laser chip, the thickness of the etching stop layer is 200 to 600 angstroms. The sum of the thicknesses of the p-type buffer layer and the p-type distributed Bragg reflection layer is 0.34 micrometers (μm), the thickness of the oxide layer is 0.02 micrometers (μm), the thickness of the quantum well layer is 0.27 micrometers (μm), and the thickness of the n-type distributed Bragg reflection layer is 0.35 micrometers (μm).

[0015] In order to achieve the aforementioned purpose of the present invention, the present invention provides a vertical cavity surface emitting laser chip with an epitaxial structure grown on a p-type substrate, wherein the vertical cavity surface emitting laser chip comprises: a vertical cavity surface emitting laser chip in which the p-type substrate is replaced by a bonded heterogeneous substrate after a bonding process is performed on the epitaxial structure grown on the p-type substrate, the vertical cavity surface emitting laser chip comprises the heterogeneous substrate, a p-type buffer layer, a p-type distributed Bragg reflection layer, an oxide layer, a p-type cap layer, a quantum well layer and an n-type distributed Bragg reflection layer in order from bottom to top, wherein the oxide layer is provided with a slot to expose a portion of the p-type distributed Bragg reflection layer, and the epitaxial structure grown on the p-type substrate is etched.

[0016] According to the above-mentioned vertical cavity surface emitting laser chip, the vertical cavity surface emitting laser chip further includes: a p-type electrode located under the heterogeneous substrate; and an n-type electrode located on the n-type distributed Bragg reflection layer.

[0017] According to the above-mentioned VCSEL chip, the epitaxial structure of the VCSEL chip further includes: an active layer located above the oxide layer and below the p-type cover layer, a portion of the active layer faces the exposed portion of the p-type distributed Bragg reflector.

[0018] According to the above-mentioned vertical cavity surface emitting laser chip, the epitaxial structure of the vertical cavity surface emitting laser chip further includes: an n-type capping layer located above the quantum well layer and below the n-type distributed Bragg reflection layer; and another p-type electrode located above the heterogeneous substrate and below the p-type buffer layer.

[0019] According to the above-mentioned vertical cavity surface emitting laser chip, the sum of the thicknesses of the p-type buffer layer and the p-type distributed Bragg reflection layer is 0.34 micrometers (μm), the thickness of the oxide layer is 0.02 micrometers (μm), the thickness of the quantum well layer is 0.27 micrometers (μm), and the thickness of the n-type distributed Bragg reflection layer is 0.35 micrometers (μm).

[0020] Thus, the technical effect produced by the present invention is as follows: the substrate of the VCSEL chip of the present invention is a p-type substrate. In addition to being able to directly form a p-type electrode for use, it can also be bonded through subsequent processes to replace the original p-type substrate with a bonded heterogeneous substrate to enhance the usability and application range of the VCSEL chip. For example, the heterogeneous substrate is selected from a material with a high heat dissipation rate (for example, aluminum nitride or molybdenum). BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 : Schematic cross-sectional view of a vertical cavity surface emitting laser chip in the prior art.

[0022] Figure 2 : A schematic cross-sectional view of a vertical cavity surface emitting laser chip according to an embodiment of the present invention.

[0023] Figure 3 : A schematic cross-sectional view of a vertical cavity surface emitting laser chip according to another embodiment of the present invention.

[0024] Description of the figure number:

[0025] (Prior Art)

[0026] 1: Vertical Cavity Surface Emitting Laser Chip

[0027] 100: n-type electrode

[0028] 101: n-type substrate

[0029] 102: n-type buffer layer

[0030] 103: n-type distributed Bragg reflector

[0031] 104: n-type cladding layer

[0032] 105: Quantum Well Layer

[0033] 106: p-type cladding layer

[0034] 107: The first p-type distributed Bragg reflector

[0035] 108: Oxide layer

[0036] 109: Second p-type distributed Bragg reflection layer

[0037] 110: p-type electrode

[0038] 111: Slot

[0039] (The present invention)

[0040] 2.2': Vertical Cavity Surface Emitting Laser Chip

[0041] 200, 214, 215: p-type electrodes

[0042] 201: p-type substrate

[0043] 202: Etch stop layer

[0044] 203: p-type buffer layer

[0045] 204: p-type distributed Bragg reflector

[0046] 205: Oxide layer

[0047] 206: Active layer

[0048] 207: p-type cover layer

[0049] 208: Quantum Well Layer

[0050] 209: n-type cladding layer

[0051] 210: n-type distributed Bragg reflector

[0052] 211: n-type electrode

[0053] 212: Slot

[0054] 213: Heterogeneous substrate. DETAILED DESCRIPTION

[0055] The present invention provides a vertical cavity surface emitting laser chip with an epitaxial structure grown on a p-type substrate. Different from the prior art vertical cavity surface emitting laser chip with an epitaxial structure grown on an n-type substrate, the vertical cavity surface emitting laser chip of the present invention can be processed later, and a heterogeneous substrate made of a material with a high heat dissipation rate (for example, aluminum nitride or molybdenum) can be used for bonding, and the original p-type substrate can be removed, so that the vertical cavity surface emitting laser chip can effectively dissipate heat under high-power operation, avoiding the stability and reliability of the component being reduced due to slow heat dissipation.

[0056] Since the epitaxial structure is grown on a p-type substrate, a p-type electrode is disposed under the p-type substrate, and on the p-type substrate, there are an etching stop layer, a p-type buffer layer, a p-type distributed Bragg reflector layer, an oxide layer, an active layer, a p-type cover layer, a quantum well layer, an n-type cover layer, an n-type distributed Bragg reflector layer and an n-type electrode in order from bottom to top, wherein the oxide layer is formed with slots, and the slots expose the p-type distributed Bragg reflector layer so that the active layer faces the p-type distributed Bragg reflector layer. When the p-type electrode and the n-type electrode present a voltage greater than the junction threshold, light is generated through the action of the active layer, the p-type cover layer, the quantum well layer and the n-type cover layer, and part of the generated light is reflected through the slots, and the other part of the generated light is directly emitted upward.

[0057] Simply put, a VCSEL chip with an epitaxial structure grown on a p-type substrate can emit light just like a VCSEL chip with an epitaxial structure grown on a p-type substrate. However, a VCSEL chip with an epitaxial structure grown on a p-type substrate can undergo an additional bonding process. By bonding a foreign substrate to a p-type substrate and then removing the p-type substrate, a VCSEL chip with a specific function can be effectively implemented. For example, to increase heat dissipation capacity, a foreign substrate made of a material with a high heat dissipation rate can be selected.

[0058] See also Figure 2 , Figure 2 2 is a schematic cross-sectional view of a vertical cavity surface emitting laser chip according to an embodiment of the present invention. The vertical cavity surface emitting laser chip 2 comprises a p-type electrode 200, a p-type substrate 201, an etch stop layer 202, a p-type buffer layer 203, a p-type distributed Bragg reflector 204, an oxide layer 205, an active layer 206, a p-type cap layer 207, a quantum well layer 208, an n-type cap layer 209, an n-type distributed Bragg reflector 210 and an n-type electrode 211, wherein the epitaxial structure grown on the p-type substrate 201 comprises the p-type substrate 201, the etch stop layer 202, the p-type buffer layer 203, the p-type distributed Bragg reflector 204, the oxide layer 205, the active layer 206, the p-type cap layer 207, the quantum well layer 208, the n-type cap layer 209 and the n-type distributed Bragg reflector 210.

[0059] A p-type electrode 200 is formed under a p-type substrate 201, an etch stop layer 202 is formed on the p-type substrate 201, a p-type buffer layer 203 is formed on the etch stop layer 202, a p-type distributed Bragg reflector 204 is formed on the p-type buffer layer 203, an oxide layer 205 is formed on the p-type distributed Bragg reflector 204, an active layer 206 is formed on the oxide layer 205, a p-type cap layer 207 is formed on the active layer 206, a quantum well layer 208 is formed on the p-type cap layer 207, an n-type cap layer 209 is formed on the quantum well layer 208, an n-type distributed Bragg reflector 210 is formed on the n-type cap layer 209, and an n-type electrode 211 is formed on the n-type distributed Bragg reflector 210.

[0060] The oxide layer 205 is provided with a slot 212 to expose a portion of the p-type distributed Bragg reflector 204, and the active layer 206 faces the exposed portion of the p-type distributed Bragg reflector 204, so that light is provided to penetrate the p-type distributed Bragg reflector 204 and then undergo light reflection resonance, wherein the thickness of the oxide layer 205 is 0.02 micrometers (μm). The n-type electrode 211 also exposes a portion of the n-type distributed Bragg reflector 210, and the exposed portion of the n-type distributed Bragg reflector 210 also corresponds to the slot 212, so that light can be emitted from the vertical cavity surface emitting laser chip 2.

[0061] The p-type electrode 200 can be made of a conductive material, such as gold, silver, copper, aluminum gallium arsenide (AlxGaAs), or indium tin oxide (ITO), where x is related to the refractive index and conductivity. The shape of the p-type electrode 200 can be a rectangular column. The p-type substrate 201 can be made of sapphire or aluminum gallium arsenide (AlxGaAs), where x is related to the refractive index and conductivity. For the p-type substrate 201 and the p-type electrode 200, x is different. When the p-type substrate 201 is made of aluminum gallium arsenide (AlxGaAs), it is doped with a concentration of 3×10 18 The electric hole.

[0062] The etching stop layer 202 is made of p-type indium gallium phosphide (InGaP) with a thickness of 200 to 600 angstroms. And it is doped with a concentration of 3×10 18 Up to 6×10 18 The p-type buffer layer 203 is made of aluminum gallium arsenide (AlxGaAs), where x is related to the refractive index and conductivity, and the p-type buffer layer 203 is made of a rectangular column.

[0063] The p-type distributed Bragg reflector 204 is made of AlxGaAs material. The p-type distributed Bragg reflector 204 is composed of multiple AlxGaAs layers. In the multiple AlxGaAs layers, x is not the same, so as to form a p-type distributed Bragg reflector. One part (lower half) of the p-type distributed Bragg reflector 204 is in the shape of a rectangular column, and the other part (upper half) of the p-type distributed Bragg reflector 204 is in the shape of a circular column. The sum of the thicknesses of the p-type buffer layer 203 and the p-type distributed Bragg reflector 204 is 0.34 micrometers (μm).

[0064] The oxide layer 205 is made of an oxide of gallium aluminum arsenide (AlxGaAs). The active layer 206 is made of an electroluminescent material. The p-type cover layer 207 is made of gallium aluminum arsenide (AlxGaAs) material. The quantum well layer 208 is made of a plurality of gallium aluminum arsenide (AlxGaAs) layers, in which x is not all the same, so as to generate a quantum well, so that the electroluminescence effect is better. The n-type cover layer 209 is made of gallium aluminum arsenide (AlxGaAs) material. The thickness of the quantum well layer 208 is 0.27 micrometers (μm).

[0065] The n-type distributed Bragg reflector 210 is made of AlxGaAs material. The n-type distributed Bragg reflector 210 is composed of multiple AlxGaAs layers. In the multiple AlxGaAs layers, x is not the same, so as to form an n-type distributed Bragg reflector. The thickness of the n-type distributed Bragg reflector 210 is 0.35 micrometers (μm). The n-type electrode 211 can be made of a conductive material, such as gold, silver, copper, AlxGaAs or indium tin oxide (ITO), where the selection of x is related to the refractive index and conductivity.

[0066] The active layer 206, the p-type cladding layer 207, the quantum well layer 208, the n-type cladding layer 209 and the n-type distributed Bragg reflector 210 are in the shape of rectangular columns, and the n-type electrode 211 is in the shape of a closed ring, such as a circular ring, and the shape of the slot 212 may correspond to the shape of the n-type electrode 211. In addition, it should be noted that the n-type cladding layer 209 and the active layer 206 are not essential components in the present invention, because the quantum well layer 208 itself is an electroluminescent material, and the function of the n-type cladding layer 209 may also be replaced by an aluminum gallium arsenide (AlxGaAs) layer of the n-type distributed Bragg reflector 210.

[0067] Next, please refer to Figure 3 , Figure 3 FIG. 1 is a schematic cross-sectional view of a vertical cavity surface emitting laser chip according to another embodiment of the present invention. Figure 2The vertical cavity surface emitting laser chip 2 of the present invention uses a foreign substrate 213 to replace the p-type substrate 201. Specifically, the vertical cavity surface emitting laser chip 2 without forming the p-type electrode 200 is subjected to a bonding process to realize the vertical cavity surface emitting laser chip 2'. The p-type substrate 201 of the vertical cavity surface emitting laser chip 2 without forming the p-type electrode 200 is removed (by etching, at most only the p-type substrate 201 and the etching stop layer 202 are etched away), and a p-type electrode 215 is formed under the p-type buffer layer 203. Then, the foreign substrate 213 is bonded under the p-type electrode 215, and finally the p-type electrode 214 is formed under the foreign substrate 213. The foreign substrate 213 can be made of a material with a high heat dissipation rate. Incidentally, in one of the embodiments, the p-type electrode 215 may not be provided.

[0068] It can be seen from the above implementation description that the VCSEL chip of the present invention can be used directly as a VCSEL chip compared with the prior art and products after the epitaxial structure of the VCSEL chip forms a p-type electrode. Furthermore, the epitaxial structure of the VCSEL chip can be used without forming a p-type electrode first, but by using a heterogeneous substrate to replace the p-type substrate through a bonding process, and then forming a bottom p-type electrode. In this way, the usability and application breadth of the VCSEL chip can be increased according to the selected heterogeneous substrate material. For example, the heterogeneous substrate can be made of a material with a high heat dissipation rate to increase the operating wattage of the VCSEL chip, or, when operating at the same high wattage, it can have higher product stability and reliability.

Claims

1. A vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate, characterized in that: The vertical cavity surface emitting laser chip comprises: The epitaxial structure grown on the p-type substrate (201) comprises, from bottom to top, the p-type substrate (201), an etching stop layer (202), a p-type buffer layer (203), a p-type distributed Bragg reflection layer (204), an oxide layer (205), a p-type cap layer (207), a quantum well layer (208) and an n-type distributed Bragg reflection layer (210), wherein the oxide layer (205) is provided with a slot (212) to expose a portion of the p-type distributed Bragg reflection layer (204).

2. The vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate as claimed in claim 1, characterized in that: The vertical cavity surface emitting laser chip further comprises: A p-type electrode (200) is located below the p-type substrate (201); and an n-type electrode (211) is located above the n-type distributed Bragg reflection layer (210).

3. The vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate as claimed in claim 2, characterized in that: The epitaxial structure of the vertical cavity surface emitting laser chip further comprises: An active layer (206) is located on the oxide layer (205) and below the p-type cover layer (207), and a portion of the active layer (206) faces the exposed portion of the p-type distributed Bragg reflector layer (204).

4. The vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate as claimed in claim 3, characterized in that: The epitaxial structure of the vertical cavity surface emitting laser chip further comprises: The n-type capping layer (209) is located above the quantum well layer (208) and below the n-type distributed Bragg reflection layer (210).

5. The vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate as claimed in claim 4, characterized in that: The thickness of the etching stop layer (202) is 200 to 600 angstroms, the sum of the thicknesses of the p-type buffer layer (203) and the p-type distributed Bragg reflection layer (204) is 0.34 microns, the thickness of the oxide layer (205) is 0.02 microns, the thickness of the quantum well layer (208) is 0.27 microns, and the thickness of the n-type distributed Bragg reflection layer (210) is 0.35 microns.

6. A vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate, characterized in that: The vertical cavity surface emitting laser chip comprises: A vertical cavity surface emitting laser chip is produced by subjecting an epitaxial structure grown on the p-type substrate (201) to a bonding process, wherein the p-type substrate (201) is replaced by a bonded foreign substrate (213). The vertical cavity surface emitting laser chip comprises, from bottom to top, the foreign substrate (213), a p-type buffer layer (203), a p-type distributed Bragg reflection layer (204), an oxide layer (205), a p-type cap layer (207), a quantum well layer (208) and an n-type distributed Bragg reflection layer (210), wherein the oxide layer (205) is provided with a slot (212) to expose a portion of the p-type distributed Bragg reflection layer (204), and the epitaxial structure grown on the p-type substrate (201) is etched.

7. The vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate as claimed in claim 6, characterized in that: The vertical cavity surface emitting laser chip further comprises: A p-type electrode (214) located below the foreign substrate (213); and An n-type electrode (211) is located on the n-type distributed Bragg reflection layer (210).

8. The vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate as claimed in claim 7, characterized in that: The epitaxial structure of the vertical cavity surface emitting laser chip further comprises: An active layer (206) is located on the oxide layer (205) and below the p-type cover layer (207), and a portion of the active layer (206) faces the exposed portion of the p-type distributed Bragg reflector layer (204).

9. The vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate as claimed in claim 8, characterized in that: The epitaxial structure of the vertical cavity surface emitting laser chip further comprises: An n-type capping layer (209) is located above the quantum well layer (208) and below the n-type distributed Bragg reflection layer (210); and Another p-type electrode (215) is located on the foreign substrate (213) and below the p-type buffer layer (203).

10. The vertical cavity surface emitting laser chip having an epitaxial structure grown on a p-type substrate as claimed in claim 9, characterized in that: The sum of the thicknesses of the p-type buffer layer (203) and the p-type distributed Bragg reflection layer (204) is 0.34 micrometers, the thickness of the oxide layer (205) is 0.02 micrometers, the thickness of the quantum well layer (208) is 0.27 micrometers, and the thickness of the n-type distributed Bragg reflection layer (210) is 0.35 micrometers.

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