Multi-port radio frequency transmit-receive switch synthesis module

Abstract

The invention discloses a multi-port radio frequency transmit-receive switch synthesis module, which belongs to the technical field of communication and comprises a combiner CMB1, a combiner CMB2, a switch matrix SW1, a switch matrix SW2, a switch matrix SW3, change-over switches TRS1 to TRS2, a power interface POW, a transmitting signal port, a transmit-receive selection control interface and a channel selection control interface. The technical problems of receiving and transmitting switching and synthesis of multi-channel signals are solved, a receiving and transmitting conversion function, a synthesis network and a switch assembly are integrated, signals of branches can be received by double ports, the signals can be single-path signals or two-path synthesis signals, use of instruments such as a signal source and a frequency spectrograph can be reduced, the test cost is saved, the test efficiency is improved, and the test cost is reduced. According to the invention, the system has good expansion capability, can be expanded to more ports, can significantly shorten the test time, and achieves the cooperative control of multiple devices through TTL signals, RS422 and other hardware interfaces.

Description

Technical Field

[0001] The invention belongs to the field of communication technology, and in particular relates to a multi-port radio frequency transceiver switch synthesis module. Background Art

[0002] In modern wireless communication systems, the transmission and reception of RF channels usually rely on separate signal sources and spectrum analyzers. Especially when performing transmission and reception tests on multiple channels, a large number of instruments and equipment (such as signal sources and spectrum analyzers) are required. This requirement increases costs and reduces test efficiency.

[0003] In order to improve the flexibility and economy of testing, switch matrices are introduced into the test system. Traditional switch matrices are usually unidirectional and can only control the transmission of signals from input ports to multiple output ports. They cannot meet the complex test requirements of time-sharing switching of transceivers and synthesis of multi-channel signals. The existing technology lacks the synthesis of multi-port RF signals, transceiver switching, and efficient signal transmission processing mechanism. Summary of the invention

[0004] The purpose of the present invention is to provide a multi-port radio frequency transceiver switch synthesis module, which solves the technical problems of transceiver switching and synthesis of multi-channel signals.

[0005] To achieve the above object, the present invention adopts the following technical solution: A multi-port radio frequency transceiver switch synthesis module comprises a combiner CMB1, a combiner CMB2, a switch matrix SW1, a switch matrix SW2, a switch matrix SW3, a conversion switch TRS1, a conversion switch TRS2, a conversion switch TRS3, a conversion switch TRS4, ​​a conversion switch TRS5, a conversion switch TRS6, a conversion switch TRS7, a conversion switch TRS8, a conversion switch TRS9, a conversion switch TRS10, a conversion switch TRS11, a conversion switch TRS12, a power interface POW, a transmission signal port, a transceiver selection control interface and a channel selection control interface, wherein the conversion switches TRS1 to TRS6 are respectively connected to 6 signal receiving ports of the switch matrix SW2, i.e., an A1 end to an A6 end, and the conversion switches TRS7 to TRS12 are respectively connected to 6 signal receiving ports of the switch matrix SW3, i.e., an A7 end to an A12 end; One branch signal output end of the switch matrix SW2 is connected to the combiner CMB1, and another branch signal output end is connected to a signal input end of the switch matrix SW1; One branch signal output end of the switch matrix SW3 is connected to the combiner CMB2, and another branch signal output end is connected to another signal input end of the switch matrix SW1; The two signal output terminals of the switch matrix SW1 are connected to the combiner CMB1 and the combiner CMB2 respectively; The transfer switches TRS1 to TRS12 are all connected to the transmission signal port, i.e., the JL_in terminal, and the transfer switches TRS1 to TRS12 are respectively connected to 12 branch signal ports, i.e., the CH1 terminal to the CH12 terminal; The output end of the combiner CMB1 is connected to the first signal output end, namely, the CH_A end, and the output end of the combiner CMB2 is connected to the second signal output port, namely, the CH_B end; The power interface POW is connected to an external power supply, and supplies power to the combiner CMB1, the combiner CMB2, the switch matrix SW1, the switch matrix SW2, the switch matrix SW3, and the transfer switches TRS1 to TRS12.

[0006] Preferably, the TX end of the conversion switch TRS1 to the TX end of the conversion switch TRS12 are both connected to the JL_in end; The RX end of the transfer switch TRS1 to the RX end of the transfer switch TRS6 are respectively connected to the A1 end to the A6 end of the switch matrix SW2; The RX end of the transfer switch TRS7 to the RX end of the transfer switch TRS12 are respectively connected to the A7 end to the A12 end of the switch matrix SW3; The ANT end of the conversion switch TRS1 to the ANT end of the conversion switch TRS12 are connected to the CH1 end to the CH12 end respectively.

[0007] Preferably, the two signal input terminals of the switch matrix SW1 are terminals 2 and 3 of the switch matrix SW1, and the two signal output terminals of the switch matrix SW1 are terminals 1 and 4 of the switch matrix SW1; The two branch signal output ends of the switch matrix SW2 are the FL_A end and the FL_B end of the switch matrix SW2, the FL_A end is connected to the IN1 end of the combiner CMB1, and the FL_B end is connected to the 2 end of the switch matrix SW1; The two branch signal output terminals of the switch matrix SW3 are respectively the FL_C terminal and the FL_D terminal of the switch matrix SW2, the FL_C terminal is connected to the 3 terminal of the switch matrix SW1, and the FL_D terminal is connected to the IN2 terminal of the combiner CMB2; Terminal 1 of the switch matrix SW1 is connected to terminal IN2 of the combiner CMB1, and terminal 4 is connected to terminal IN1 of the combiner CMB2.

[0008] Preferably, the switch matrix SW1 includes switches SW1_1, SW1_2, SW1_3 and SW1_4, the COM pin of switch SW1_1 is connected to the two terminals, the P1 pin is connected to the P1 pin of switch SW1_4, and the P2 pin is connected to the P1 pin of switch SW1_3; The COM pin of the switch SW1_2 is connected to the three terminals, the P1 pin is connected to the P2 pin of the switch SW1_4, and the P2 pin is connected to the P2 pin of the switch SW1_3; The COM pin of the switch SW1_3 is connected to the 4 terminals; The COM pin of the switch SW1_4 is connected to the 1 terminal.

[0009] Preferably, the switch SW1_1, the switch SW1_2, the switch SW1_3 and the switch SW1_4 are all single-pole double-throw switches.

[0010] Preferably, the switch matrix SW2 includes switches S1, S2, S3, S4, S5, S6, S7, S8, S9 and S10, the COM pin of switch S9 is connected to the FL_A terminal, the P1 pin is connected to the P4 pin of switch S1, the P2 pin is connected to the P4 pin of switch S2, the P3 pin is connected to the P4 pin of switch S3, and the P4 pin is connected to the COM pin of switch S8; The P1 pin of switch S10 is connected to the COM pin of switch S7, the P2 pin is connected to the P1 pin of switch S4, the P3 pin is connected to the P1 pin of switch S5, the P4 pin is connected to the P1 pin of switch S6, and the COM pin is connected to the FL_B terminal; The P2 pin, P3 pin and P4 pin of the switch S7 are connected to the P3 pin of the switch S1, the P3 pin of the switch S2 and the P3 pin of the switch S3 respectively; The P1 pin, P2 pin and P3 pin of the switch S8 are connected to the P2 pin of the switch S4, the P2 pin of the switch S5 and the P2 pin of the switch S6 respectively; The COM pin of switch S1 is connected to the A1 terminal, the COM pin of switch S2 is connected to the A2 terminal, the COM pin of switch S3 is connected to the A3 terminal, the COM pin of switch S4 is connected to the A4 terminal, the COM pin of switch S5 is connected to the A5 terminal, and the COM pin of switch S6 is connected to the A6 terminal; The P1 pin of switch S7, the P4 pin of switch S8, the P2 pin and the P1 pin of switch S1, the P2 pin and the P1 pin of switch S2, the P2 pin and the P1 pin of switch S3, the P4 pin and the P3 pin of switch S4, the P4 pin and the P3 pin of switch S5, and the P4 pin and the P3 pin of switch S6 are all connected to an external load; The switch matrix SW3 includes switches S11, S12, S13, S14, S15, S16, S17, S18, S19 and S20, wherein the COM pin of the switch S19 is connected to the FL_C terminal, the P1 pin is connected to the P4 pin of the switch S11, the P2 pin is connected to the P4 pin of the switch S12, the P3 pin is connected to the P4 pin of the switch S13, and the P4 pin is connected to the COM pin of the switch S18; The P1 pin of the switch S20 is connected to the COM pin of the switch S17, the P2 pin is connected to the P1 pin of the switch S14, the P3 pin is connected to the P1 pin of the switch S15, the P4 pin is connected to the P1 pin of the switch S16, and the COM pin is connected to the FL_D terminal; The P2 pin, P3 pin and P4 pin of the switch S17 are connected to the P3 pin of the switch S11, the P3 pin of the switch S12 and the P3 pin of the switch S13 respectively; The P1 pin, P2 pin and P3 pin of the switch S18 are connected to the P2 pin of the switch S14, the P2 pin of the switch S15 and the P2 pin of the switch S16 respectively; The COM pin of switch S11 is connected to the A7 terminal, the COM pin of switch S12 is connected to the A8 terminal, the COM pin of switch S13 is connected to the A9 terminal, the COM pin of switch S14 is connected to the A10 terminal, the COM pin of switch S15 is connected to the A11 terminal, and the COM pin of switch S16 is connected to the A12 terminal; Pin P1 of switch S17, pin P4 of switch S18, pin P2 and pin P1 of switch S11, pin P2 and pin P1 of switch S2, pin P2 and pin P1 of switch S13, pin P4 and pin P3 of switch S14, pin P4 and pin P3 of switch S15, and pin P4 and pin P3 of switch S16 are all connected to external loads.

[0011] Preferably, the switch S1, the switch S2, the switch S3, the switch S4, the switch S5, the switch S6, the switch S7, the switch S8, the switch S9, the switch S10, the switch S11, the switch S12, the switch S13, the switch S14, the switch S15, the switch S16, the switch S17, the switch S18, the switch S19 and the switch S20 are all single-pole four-throw switches.

[0012] The multi-port RF transceiver switch synthesis module described in the present invention solves the technical problems of transceiver switching and synthesis of multi-channel signals, and integrates transceiver conversion functions, synthesis networks, and switch components on the basis of traditional unidirectional matrix switches. The dual ports can receive branch signals, which can be single-channel signals or two-channel synthetic signals, so as to meet the test requirements of different scenarios, reduce the use of instruments such as signal sources and spectrum analyzers, save test costs, improve test efficiency, and have good expansion capabilities. By adding switch modules and channels, it can be expanded to more ports to meet more complex test requirements, has the potential for further optimization and simplification, can significantly shorten the test time, and realize the coordinated control of multiple devices through hardware interfaces such as TTL signals and RS422. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic block diagram of the present invention; Figure 2It is a schematic block diagram of the switch matrix SW1 of the present invention; Figure 3 It is a schematic block diagram of the switch matrix SW2 of the present invention; Figure 4 It is a schematic block diagram of the switch matrix SW3 of the present invention; Figure 5 It is a single-channel output state combination diagram of the switch matrix SW2 of the present invention; Figure 6 It is a dual-channel output state combination diagram of the switch matrix SW2 of the present invention; Figure 7 It is a schematic diagram of the present invention in which the main route A has 30 combinations and the main route B has 30 combinations; Figure 8 The main route A of the present invention has 36 combinations, and the state of the main route B is adjusted according to the selection of the main route A. DETAILED DESCRIPTION

[0014] like Figure 1-Figure 8 A multi-port RF transceiver switch synthesis module shown includes a combiner CMB1, a combiner CMB2, a switch matrix SW1, a switch matrix SW2, a switch matrix SW3, a conversion switch TRS1, a conversion switch TRS2, a conversion switch TRS3, a conversion switch TRS4, ​​a conversion switch TRS5, a conversion switch TRS6, a conversion switch TRS7, a conversion switch TRS8, a conversion switch TRS9, a conversion switch TRS10, a conversion switch TRS11, a conversion switch TRS12, a power interface POW, a transmission signal port, a transceiver selection control interface and a channel selection control interface.

[0015] The transmit / receive selection control interface is used to control the module's transmit / receive state. This interface should be connected in parallel with the module's internal control circuit and is responsible for switching the transmit and receive modes. It switches to the transmit state at a high level and switches to the receive state at a low level.

[0016] The channel selection control interface is used to select the specific signal transmission path and decide which branch signals are synthesized into the main channel A (output by the CH_A terminal) or the main channel B (output by the CH_B terminal) in the receiving state. It should be connected in parallel with each SP2T / SP4T switch to control the switching state of each switch through the change of high and low levels.

[0017] The conversion switches TRS1 to TRS6 are respectively connected to the six signal receiving ports of the switch matrix SW2, i.e., the A1 terminal to the A6 terminal, and the conversion switches TRS7 to TRS12 are respectively connected to the six signal receiving ports of the switch matrix SW3, i.e., the A7 terminal to the A12 terminal; The TX end of the switching switch TRS1 to the TX end of the switching switch TRS12 are both connected to the JL_in end; The RX end of the transfer switch TRS1 to the RX end of the transfer switch TRS6 are respectively connected to the A1 end to the A6 end of the switch matrix SW2; The RX end of the transfer switch TRS7 to the RX end of the transfer switch TRS12 are respectively connected to the A7 end to the A12 end of the switch matrix SW3; The ANT end of the conversion switch TRS1 to the ANT end of the conversion switch TRS12 are connected to the CH1 end to the CH12 end respectively.

[0018] One branch signal output end of the switch matrix SW2 is connected to the combiner CMB1, and another branch signal output end is connected to a signal input end of the switch matrix SW1; One branch signal output end of the switch matrix SW3 is connected to the combiner CMB2, and another branch signal output end is connected to another signal input end of the switch matrix SW1; The two signal output terminals of the switch matrix SW1 are connected to the combiner CMB1 and the combiner CMB2 respectively; The two signal input terminals of the switch matrix SW1 are terminal 2 and terminal 3 of the switch matrix SW1, and the two signal output terminals of the switch matrix SW1 are terminal 1 and terminal 4 of the switch matrix SW1; The two branch signal output ends of the switch matrix SW2 are the FL_A end and the FL_B end of the switch matrix SW2, the FL_A end is connected to the IN1 end of the combiner CMB1, and the FL_B end is connected to the 2 end of the switch matrix SW1; The switch matrix SW2 includes switches S1, S2, S3, S4, S5, S6, S7, S8, S9 and S10, wherein the COM pin of switch S9 is connected to the FL_A terminal, the P1 pin is connected to the P4 pin of switch S1, the P2 pin is connected to the P4 pin of switch S2, the P3 pin is connected to the P4 pin of switch S3, and the P4 pin is connected to the COM pin of switch S8; The P1 pin of switch S10 is connected to the COM pin of switch S7, the P2 pin is connected to the P1 pin of switch S4, the P3 pin is connected to the P1 pin of switch S5, the P4 pin is connected to the P1 pin of switch S6, and the COM pin is connected to the FL_B terminal; The P2 pin, P3 pin and P4 pin of the switch S7 are connected to the P3 pin of the switch S1, the P3 pin of the switch S2 and the P3 pin of the switch S3 respectively; The P1 pin, P2 pin and P3 pin of the switch S8 are connected to the P2 pin of the switch S4, the P2 pin of the switch S5 and the P2 pin of the switch S6 respectively; The COM pin of switch S1 is connected to the A1 terminal, the COM pin of switch S2 is connected to the A2 terminal, the COM pin of switch S3 is connected to the A3 terminal, the COM pin of switch S4 is connected to the A4 terminal, the COM pin of switch S5 is connected to the A5 terminal, and the COM pin of switch S6 is connected to the A6 terminal; Pin P1 of switch S7, pin P4 of switch S8, pin P2 and pin P1 of switch S1, pin P2 and pin P1 of switch S2, pin P2 and pin P1 of switch S3, pin P4 and pin P3 of switch S4, pin P4 and pin P3 of switch S5, and pin P4 and pin P3 of switch S6 are all connected to external loads.

[0019] The two branch signal output terminals of the switch matrix SW3 are respectively the FL_C terminal and the FL_D terminal of the switch matrix SW2, the FL_C terminal is connected to the 3 terminal of the switch matrix SW1, and the FL_D terminal is connected to the IN2 terminal of the combiner CMB2; The switch matrix SW3 includes switches S11, S12, S13, S14, S15, S16, S17, S18, S19 and S20, wherein the COM pin of the switch S19 is connected to the FL_C terminal, the P1 pin is connected to the P4 pin of the switch S11, the P2 pin is connected to the P4 pin of the switch S12, the P3 pin is connected to the P4 pin of the switch S13, and the P4 pin is connected to the COM pin of the switch S18; The P1 pin of the switch S20 is connected to the COM pin of the switch S17, the P2 pin is connected to the P1 pin of the switch S14, the P3 pin is connected to the P1 pin of the switch S15, the P4 pin is connected to the P1 pin of the switch S16, and the COM pin is connected to the FL_D terminal; The P2 pin, P3 pin and P4 pin of the switch S17 are connected to the P3 pin of the switch S11, the P3 pin of the switch S12 and the P3 pin of the switch S13 respectively; The P1 pin, P2 pin and P3 pin of the switch S18 are connected to the P2 pin of the switch S14, the P2 pin of the switch S15 and the P2 pin of the switch S16 respectively; The COM pin of switch S11 is connected to the A7 terminal, the COM pin of switch S12 is connected to the A8 terminal, the COM pin of switch S13 is connected to the A9 terminal, the COM pin of switch S14 is connected to the A10 terminal, the COM pin of switch S15 is connected to the A11 terminal, and the COM pin of switch S16 is connected to the A12 terminal; Pin P1 of switch S17, pin P4 of switch S18, pin P2 and pin P1 of switch S11, pin P2 and pin P1 of switch S2, pin P2 and pin P1 of switch S13, pin P4 and pin P3 of switch S14, pin P4 and pin P3 of switch S15, and pin P4 and pin P3 of switch S16 are all connected to external loads.

[0020] Terminal 1 of the switch matrix SW1 is connected to terminal IN2 of the combiner CMB1, and terminal 4 is connected to terminal IN1 of the combiner CMB2.

[0021] The switch matrix SW1 includes switches SW1_1, SW1_2, SW1_3 and SW1_4, the COM pin of the switch SW1_1 is connected to the two terminals, the P1 pin is connected to the P1 pin of the switch SW1_4, and the P2 pin is connected to the P1 pin of the switch SW1_3; The COM pin of the switch SW1_2 is connected to the three terminals, the P1 pin is connected to the P2 pin of the switch SW1_4, and the P2 pin is connected to the P2 pin of the switch SW1_3; The COM pin of the switch SW1_3 is connected to the 4 terminals; The COM pin of the switch SW1_4 is connected to the 1 terminal.

[0022] The switch SW1_1 , the switch SW1_2 , the switch SW1_3 , and the switch SW1_4 are all single-pole double-throw switches.

[0023] The transfer switches TRS1 to TRS12 are all connected to the transmission signal port, i.e., the JL_in terminal, and the transfer switches TRS1 to TRS12 are respectively connected to 12 branch signal ports, i.e., the CH1 terminal to the CH12 terminal; The output end of the combiner CMB1 is connected to the first signal output end, namely, the CH_A end, and the output end of the combiner CMB2 is connected to the second signal output port, namely, the CH_B end; The power interface POW is connected to an external power supply, and supplies power to the combiner CMB1, the combiner CMB2, the switch matrix SW1, the switch matrix SW2, the switch matrix SW3, and the transfer switches TRS1 to TRS12.

[0024] The switch S1, the switch S2, the switch S3, the switch S4, the switch S5, the switch S6, the switch S7, the switch S8, the switch S9, the switch S10, the switch S11, the switch S12, the switch S13, the switch S14, the switch S15, the switch S16, the switch S17, the switch S18, the switch S19 and the switch S20 are all single-pole four-throw switches.

[0025] The present invention is based on switch matrix technology, and realizes the transceiver switching and signal synthesis of radio frequency signals by combining multiple transceiver conversion switches and switch matrices. Specifically, the module includes 12 branches (CH1 end to CH12 end), 2 2-6 switch modules (switch matrix SW2 and switch matrix SW3), 1 SP2T switch combination (switch matrix SW1), 2 combining units (combiner CMB1 and combiner CMB2) and multiple transceiver conversion switches (conversion switch TRS1 to conversion switch TRS12 power supply).

[0026] The working process is as follows: Transmitting state: When the transmit / receive selection control interface is at a high level, the excitation signal is input from the transmit signal port, and then evenly distributed to the 12 branch ports through the power division network for transmission. The switch matrix switches the signal path to ensure that each branch can correctly send signals to the device under test (DUT).

[0027] Receiving state: When the transmit / receive selection control interface is at a low level, the receiving end is turned on. By selecting different signal paths through the channel selection control interface, the receiving signals of the 12 branch ports can be synthesized and output to the main channel A and the main channel B. The main channel A is synthesized and output by the A1 and A2 signals, and the main channel B is synthesized and output by the B1 and B2 signals. Each combiner unit is responsible for combining multiple signals into a single signal output.

[0028] In this embodiment, combiner CMB1, combiner CMB2, switch matrix SW1, switch matrix SW2, switch matrix SW3, conversion switch TRS1, conversion switch TRS2, conversion switch TRS3, conversion switch TRS4, ​​conversion switch TRS5, conversion switch TRS6, conversion switch TRS7, conversion switch TRS8, conversion switch TRS9, conversion switch TRS10, conversion switch TRS11, conversion switch TRS12, power interface POW, transmission signal port, transceiver selection control interface and channel selection control interface are all arranged on the same PCB board or in the same module.

[0029] In this embodiment, the switch matrix of the multi-port RF transceiver switch synthesis module is controlled by the driver board, and the serial port is connected to the host computer. The control instructions sent by the host computer are converted into TTL signals by the driver board to drive each switch. The internal SP4T switch (single-pole four-throw switch) and SP2T switch (single-pole double-throw switch) are responsible for selecting the transmission path of the signal to achieve the function of dual-channel signal output or single-channel signal output. When dual-channel output is required, the present invention supports selecting two signals from multiple branches and synthesizing them into main path A and main path B, further improving the test efficiency and flexibility.

[0030] In this embodiment, when outputting a single signal, only one of the switch matrix SW2 branch A (output by FL_A) or branch B (output by FL_B) has a signal output. The signal of branch A or branch B is one of the branches 1 (input and output by A1 terminal) to branch 6 (input and output by A6 terminal), with a total of 12 cases, such as branch 1 / branch 2, branch 1 / branch 3, branch 1 / branch 4, branch 6 / branch 1, branch 6 / branch 2, branch 6 / branch 3, etc. If branch A or branch B is not required to output a signal, the corresponding SP4T can be connected to the load port.

[0031] Similarly, C (output by FL_C) or branch D (output by FL_D).

[0032] When outputting dual-channel signals, the signals of branch A / branch B are selected from any two of branches 1 to 6, with a total of 30 situations.

[0033] Similarly, the circuit principle and function of the switch matrix SW3 are the same as those of the switch matrix SW2.

[0034] The switch matrix SW1 is composed of 4 SP2T switches (switch SW1_1 to switch SW1_4), and its function is to switch the signals of branch B and branch C to terminals 1 and 4 of the switch matrix SW1 through the control channel.

[0035] Combiner CMB1 combines the signal of branch A and the signal of end 1 of switch matrix SW1 and outputs them to port A of main path. Combiner CMB2 combines the signal of end 4 of switch matrix SW1 and the signal of branch D and outputs them to port B of main path.

[0036] In this embodiment, the external power supply connected to POW is a 5V power supply, and the transmit / receive selection control interface outputs a 5V TTL signal, a high level selects transmission, and a low level selects reception.

[0037] The channel selection control interface outputs a 5V TTL signal, and its control logic is as follows: When the level is high: any two of branch 1, branch 2, branch 3, branch 4, branch 5, and branch 6 are combined into the main path A; any two of branch 7, branch 8, branch 9, branch 10, branch 11, and branch 12 are combined into the main path B; When the level is low: select any one of branch 1, branch 2, branch 3, branch 4, branch 5, and branch 6 and any one of branch 7, branch 8, branch 9, branch 10, branch 11, and branch 12 to combine them into the main road A; remove the one output to the main road A from branch 1, branch 2, branch 3, branch 4, branch 5, and branch 6, and select any one of the other 5 roads and remove the one output to the main road A from branch 7, branch 8, branch 9, branch 10, branch 11, and branch 12, and select any one of the other 5 roads; combine these two roads into the main road B.

[0038] The working state of the feedback output is high level is normal, low level is faulty.

[0039] When used specifically, the working process is as follows: When the transmit / receive conversion control signal is high, the module is in the transmitting state, and the transmitting excitation signal is evenly distributed to 12 branch interfaces, and the transmitting excitation signal is amplified.

[0040] When the transmit / receive conversion control signal is low, the module is in the receiving state. According to the channel selection control signal, the signals input from the 12 branch interfaces are synthesized into 2 outputs and amplified: Control the internal SP4T switch (S1 to S10) to select any one of branches 1 to 6 to output from branch A or branch A does not output a signal (the switch is connected to the load).

[0041] Control the internal SP4T switch (S1 to S10) to select any one of branches 1 to 6 to output from branch B or branch B does not output a signal (the switch is connected to the load).

[0042] Control the internal SP4T switch (S11 to S20) to select any one of branches 7 to 12 to output from branch C or branch C does not output the signal (the switch is connected to the load). Branch 7 to branch 12 are input and output through CH7 to CH12 respectively.

[0043] Control the internal SP4T switch (S11 to S20) to select any one of branches 7 to 12 to output from branch D or branch D does not output a signal (the switch is connected to the load).

[0044] The branch B and branch C signals need to pass through two stages of SP2T (switch SW1_1 to switch SW1_4) to reach the combiner. Channel selection is performed by controlling the SP2T switch (switch SW1_1 to switch SW1_4).

[0045] When the channel selection control signal is high, the branch B signal passes through the SP2T switch SW1_1 and the SP2T switch SW1_3 and is output to the 1 terminal; the branch C signal passes through the SP2T switch SW1_2 and the SP2T switch SW1_4 and is output to the 4 terminal. When the channel selection control signal is low, the branch C signal passes through the SP2T switch SW1_2 and the SP2T switch SW1_3 and is output to the 1 terminal; the branch B signal passes through the SP2T switch SW1_1 and the SP2T switch SW1_4 and is output to the 4 terminal.

[0046] When the receiving channel selection control signal is high, any two signals input from the interface of branch 1 to branch 6 are selected, and the outputs are the signal output from the FL_A terminal and the signal output from the 1 terminal respectively. These two signals are combined into the main path A. Any two signals input from the interface of branch 7 to branch 12 are selected, and the outputs are the signal output from the 4 terminal and the signal output from the FL_D terminal respectively. These two signals are combined into the main path B.

[0047] When the receiving channel selection control signal is low, any one of the input signals from branch 1 to branch 6 is selected, and the output signal is the signal output by FL_A. Any one of the input signals from branch 7 to branch 12 is selected, and the output signal is the signal output by terminal 1. These two signals are combined to main channel A.

[0048] The signal input from the interface of branch 1 to branch 6 is removed from the signal output from output FL_A. One of the other five channels is selected at random, and the output signal is the signal output from terminal 4. The signal input from the interface of branch 7 to branch 12 is removed from the signal output from output 1. One of the other five channels is selected at random, and the output signal is the signal output from terminal FL_D. These two signals are combined into the main channel B.

[0049] In this embodiment, the working status of the module can also be fed back through the low-frequency connector interface, and a front panel is provided, and the working status of the module is displayed through the LED lights on the panel.

[0050] In this embodiment, combiners CMB1 and CMB2 use mini's DC to 18GHz power divider, model EP2RKU+, which is a packaged chip. In the DC to 4GHz frequency band, the insertion loss is 3.2dB, the minimum isolation is 8dB, the maximum phase imbalance difference is 4°, and the maximum amplitude imbalance difference is 0.3dB. In the 4GHz to 18GHz frequency band, the insertion loss is 3.3dB, the minimum isolation is 14dB, the phase imbalance difference is 14°, and the amplitude imbalance difference is 0.4dB.

[0051] SP4T selected Hittite's DC to 20GHz switch, model HMC641LP4E, which is a packaged chip. It has a DC to 20GHz frequency band, an insertion loss of 3dB, and a minimum isolation of 30dB.

[0052] SP2T selected Hittite's DC to 20GHz switch, model HMC547LP3E, which is a packaged chip. It has a DC to 20GHz frequency band, an insertion loss of 2dB, and a minimum isolation of 33dB.

[0053] The power divider used in the power division network for transceiver conversion is EP2RKU+, and the transceiver conversion switch used is HMC547LP3E.

[0054] The multi-port RF transceiver switch synthesis module described in the present invention solves the technical problems of transceiver switching and synthesis of multi-channel signals, and integrates transceiver conversion functions, synthesis networks, and switch components on the basis of traditional unidirectional matrix switches. The dual ports can receive branch signals, which can be single-channel signals or two-channel synthetic signals, so as to meet the test requirements of different scenarios, reduce the use of instruments such as signal sources and spectrum analyzers, save test costs, improve test efficiency, and have good expansion capabilities. By adding switch modules and channels, it can be expanded to more ports to meet more complex test requirements, has the potential for further optimization and simplification, can significantly shorten the test time, and realize the coordinated control of multiple devices through hardware interfaces such as TTL signals and RS422.

Claims

1. A multi-port radio frequency transceiver switch synthesis module, characterized in that: It includes a combiner CMB1, a combiner CMB2, a switch matrix SW1, a switch matrix SW2, a switch matrix SW3, a conversion switch TRS1, a conversion switch TRS2, a conversion switch TRS3, a conversion switch TRS4, ​​a conversion switch TRS5, a conversion switch TRS6, a conversion switch TRS7, a conversion switch TRS8, a conversion switch TRS9, a conversion switch TRS10, a conversion switch TRS11, a conversion switch TRS12, a power interface POW, a transmission signal port, a transceiver selection control interface and a channel selection control interface, wherein the conversion switches TRS1 to TRS6 are respectively connected to 6 signal receiving ports of the switch matrix SW2, i.e., end A1 to end A6, and the conversion switches TRS7 to TRS12 are respectively connected to 6 signal receiving ports of the switch matrix SW3, i.e., end A7 to end A12; One branch signal output end of the switch matrix SW2 is connected to the combiner CMB1, and another branch signal output end is connected to a signal input end of the switch matrix SW1; The switch matrix SW2 is used to select the synthesis path of the received signal to the CH_A terminal; One branch signal output end of the switch matrix SW3 is connected to the combiner CMB2, and another branch signal output end is connected to another signal input end of the switch matrix SW1; The switch matrix SW3 is used to select the synthesis path of the received signal to the CH_B terminal; The two signal output terminals of the switch matrix SW1 are connected to the combiner CMB1 and the combiner CMB2 respectively; The transfer switches TRS1 to TRS12 are all connected to the transmission signal port, i.e., the JL_in terminal, and the transfer switches TRS1 to TRS12 are respectively connected to 12 branch signal ports, i.e., the CH1 terminal to the CH12 terminal; The output end of the combiner CMB1 is connected to the first signal output end, namely, the CH_A end, and the output end of the combiner CMB2 is connected to the second signal output port, namely, the CH_B end; The power interface POW is connected to an external power supply, and supplies power to the combiner CMB1, the combiner CMB2, the switch matrix SW1, the switch matrix SW2, the switch matrix SW3, and the transfer switches TRS1 to TRS12.

2. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 1, characterized in that: The TX end of the switching switch TRS1 to the TX end of the switching switch TRS12 are both connected to the JL_in end; The RX end of the transfer switch TRS1 to the RX end of the transfer switch TRS6 are respectively connected to the A1 end to the A6 end of the switch matrix SW2; The RX end of the transfer switch TRS7 to the RX end of the transfer switch TRS12 are respectively connected to the A7 end to the A12 end of the switch matrix SW3; The ANT end of the conversion switch TRS1 to the ANT end of the conversion switch TRS12 are connected to the CH1 end to the CH12 end respectively.

3. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 2, characterized in that: The two signal input terminals of the switch matrix SW1 are terminal 2 and terminal 3 of the switch matrix SW1, and the two signal output terminals of the switch matrix SW1 are terminal 1 and terminal 4 of the switch matrix SW1; The two branch signal output ends of the switch matrix SW2 are the FL_A end and the FL_B end of the switch matrix SW2, the FL_A end is connected to the IN1 end of the combiner CMB1, and the FL_B end is connected to the 2 end of the switch matrix SW1; The two branch signal output terminals of the switch matrix SW3 are respectively the FL_C terminal and the FL_D terminal of the switch matrix SW2, the FL_C terminal is connected to the 3 terminal of the switch matrix SW1, and the FL_D terminal is connected to the IN2 terminal of the combiner CMB2; Terminal 1 of the switch matrix SW1 is connected to terminal IN2 of the combiner CMB1, and terminal 4 is connected to terminal IN1 of the combiner CMB2.

4. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 3, characterized in that: The switch matrix SW1 includes switches SW1_1, SW1_2, SW1_3 and SW1_4, the COM pin of the switch SW1_1 is connected to the two terminals, the P1 pin is connected to the P1 pin of the switch SW1_4, and the P2 pin is connected to the P1 pin of the switch SW1_3; The COM pin of the switch SW1_2 is connected to the three terminals, the P1 pin is connected to the P2 pin of the switch SW1_4, and the P2 pin is connected to the P2 pin of the switch SW1_3; The COM pin of the switch SW1_3 is connected to the 4 terminals; The COM pin of the switch SW1_4 is connected to the 1 terminal.

5. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 4, characterized in that: The switch SW1_1 , the switch SW1_2 , the switch SW1_3 , and the switch SW1_4 are all single-pole double-throw switches.

6. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 4, characterized in that: The switch matrix SW2 includes switches S1, S2, S3, S4, S5, S6, S7, S8, S9 and S10, wherein the COM pin of switch S9 is connected to the FL_A terminal, the P1 pin is connected to the P4 pin of switch S1, the P2 pin is connected to the P4 pin of switch S2, the P3 pin is connected to the P4 pin of switch S3, and the P4 pin is connected to the COM pin of switch S8; The P1 pin of switch S10 is connected to the COM pin of switch S7, the P2 pin is connected to the P1 pin of switch S4, the P3 pin is connected to the P1 pin of switch S5, the P4 pin is connected to the P1 pin of switch S6, and the COM pin is connected to the FL_B terminal; The P2 pin, P3 pin and P4 pin of the switch S7 are connected to the P3 pin of the switch S1, the P3 pin of the switch S2 and the P3 pin of the switch S3 respectively; The P1 pin, P2 pin and P3 pin of the switch S8 are connected to the P2 pin of the switch S4, the P2 pin of the switch S5 and the P2 pin of the switch S6 respectively; The COM pin of switch S1 is connected to the A1 terminal, the COM pin of switch S2 is connected to the A2 terminal, the COM pin of switch S3 is connected to the A3 terminal, the COM pin of switch S4 is connected to the A4 terminal, the COM pin of switch S5 is connected to the A5 terminal, and the COM pin of switch S6 is connected to the A6 terminal; The P1 pin of switch S7, the P4 pin of switch S8, the P2 pin and the P1 pin of switch S1, the P2 pin and the P1 pin of switch S2, the P2 pin and the P1 pin of switch S3, the P4 pin and the P3 pin of switch S4, the P4 pin and the P3 pin of switch S5, and the P4 pin and the P3 pin of switch S6 are all connected to an external load; The switch matrix SW3 includes switches S11, S12, S13, S14, S15, S16, S17, S18, S19 and S20, wherein the COM pin of the switch S19 is connected to the FL_C terminal, the P1 pin is connected to the P4 pin of the switch S11, the P2 pin is connected to the P4 pin of the switch S12, the P3 pin is connected to the P4 pin of the switch S13, and the P4 pin is connected to the COM pin of the switch S18; The P1 pin of the switch S20 is connected to the COM pin of the switch S17, the P2 pin is connected to the P1 pin of the switch S14, the P3 pin is connected to the P1 pin of the switch S15, the P4 pin is connected to the P1 pin of the switch S16, and the COM pin is connected to the FL_D terminal; The P2 pin, the P3 pin and the P4 pin of the switch S17 are connected to the P3 pin of the switch S11, the P3 pin of the switch S12 and the P3 pin of the switch S13 respectively; The P1 pin, P2 pin and P3 pin of the switch S18 are connected to the P2 pin of the switch S14, the P2 pin of the switch S15 and the P2 pin of the switch S16 respectively; The COM pin of switch S11 is connected to the A7 terminal, the COM pin of switch S12 is connected to the A8 terminal, the COM pin of switch S13 is connected to the A9 terminal, the COM pin of switch S14 is connected to the A10 terminal, the COM pin of switch S15 is connected to the A11 terminal, and the COM pin of switch S16 is connected to the A12 terminal; Pin P1 of switch S17, pin P4 of switch S18, pin P2 and pin P1 of switch S11, pin P2 and pin P1 of switch S2, pin P2 and pin P1 of switch S13, pin P4 and pin P3 of switch S14, pin P4 and pin P3 of switch S15, and pin P4 and pin P3 of switch S16 are all connected to external loads.

7. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 6, characterized in that: The switch S1, the switch S2, the switch S3, the switch S4, the switch S5, the switch S6, the switch S7, the switch S8, the switch S9, the switch S10, the switch S11, the switch S12, the switch S13, the switch S14, the switch S15, the switch S16, the switch S17, the switch S18, the switch S19 and the switch S20 are all single-pole four-throw switches.

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