Clock synchronization method and device based on DPU, electronic equipment and computer storage medium

Abstract

The embodiment of the invention provides a DPU-based clock synchronization method and device, electronic equipment and a computer storage medium. The method is applied to a first media access controller of a DPU network card, and comprises the following steps: in response to a received first clock synchronization message, obtaining a first timestamp for sending the first clock synchronization message to a slave server; sending the first timestamp to the first CPU; in response to receiving a second clock synchronization message sent by the first CPU, sending the second clock synchronization message to a slave server; in response to a third clock synchronization message sent from the server, obtaining a fourth timestamp when the third clock synchronization message is received; and in response to a fourth clock synchronization message sent by the first CPU, sending the fourth clock synchronization message to the slave server. According to the invention, the timestamp of the clock synchronization message is obtained through the first media access controller, the waiting delay time of the clock synchronization message in the DPU is effectively eliminated, and the clock synchronization precision is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a clock synchronization method, device, electronic device and computer storage medium based on DPU. Background Art

[0002] In a server cluster, when different servers communicate through network cards, clock synchronization is required to ensure the accuracy of data processing.

[0003] In the existing clock synchronization method, the CPU of the master server usually obtains the timestamp, and then sends the clock synchronization message with the timestamp to the network card, which then sends it to the network card of the slave server.

[0004] However, when the CPU of the master server sends the clock synchronization message with a timestamp to the slave server through the network card, the clock synchronization message will remain in the network card for a delay time waiting to be sent, but the slave server cannot know the delay time of the master server sending the clock synchronization message, which will cause a large time error when the slave server performs clock synchronization based on the timestamp of the clock synchronization message. Summary of the invention

[0005] In view of this, an embodiment of the present application provides a DPU-based clock synchronization solution to at least partially solve the above problems.

[0006] According to a first aspect of an embodiment of the present application, a clock synchronization method based on a DPU is provided, which is applied to a first media access controller of a DPU network card, wherein the first media access controller is arranged in the DPU of a master server, and the method comprises:

[0007] In response to a received first clock synchronization message, obtaining a first timestamp for sending the first clock synchronization message to the slave server, wherein the first clock synchronization message is sent by a first CPU, and the first CPU is set in the master server;

[0008] Sending the first timestamp to the first CPU;

[0009] In response to receiving a second clock synchronization message including the first timestamp sent by the first CPU, sending the second clock synchronization message to the slave server;

[0010] In response to the third clock synchronization message sent from the server, acquiring a fourth timestamp of receiving the third clock synchronization message;

[0011] In response to the fourth clock synchronization message including the fourth timestamp sent by the first CPU, the fourth clock synchronization message is sent to the slave server, and the first timestamp and the fourth timestamp are used by the slave server to synchronize the clock to the clock of the master server.

[0012] In some embodiments, in response to the received first clock synchronization message, obtaining a first timestamp of sending the first clock synchronization message to the slave server, wherein the first clock synchronization message is sent by the first CPU, includes:

[0013] In response to receiving a first clock synchronization message sent by the CPU, acquiring a sending time of a byte of the first clock synchronization message;

[0014] The sending time of the byte is determined as the first timestamp.

[0015] In some embodiments, in response to the third clock synchronization message sent from the server, acquiring a fourth timestamp of receiving the third clock synchronization message includes:

[0016] In response to the third clock synchronization message sent from the server, acquiring a receiving time of a byte received from the third clock synchronization message;

[0017] The reception time of the byte is determined as the fourth timestamp.

[0018] According to a second aspect of an embodiment of the present application, a clock synchronization method based on a DPU is provided, which is applied to a second media access controller of a DPU network card, wherein the second media access controller is arranged in the DPU of a slave server, and the method comprises:

[0019] In response to a received second clock synchronization message including a first timestamp, acquiring a second timestamp of the received second clock message, wherein the second clock synchronization message including the first timestamp is sent by the master server;

[0020] In response to a third clock synchronization message sent by a second CPU, acquiring a third timestamp for sending the third clock synchronization message to the master server, wherein the second CPU is arranged on the slave server;

[0021] Receiving a fourth clock synchronization message including a fourth timestamp sent by the main server;

[0022] The second clock synchronization message including the first timestamp, the fourth clock synchronization message including the fourth timestamp, the second timestamp and the third timestamp are sent to the second CPU, so that the second CPU synchronizes the clock of the slave server to the clock of the master server according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp.

[0023] In some embodiments, in response to receiving the second clock synchronization message including the first timestamp, obtaining the second timestamp of receiving the second clock message includes:

[0024] In response to receiving a second clock synchronization message including a first timestamp sent by the master server, acquiring a receiving time of a byte of the second clock synchronization message including the first timestamp;

[0025] The receiving time of the byte of the second clock synchronization message including the first timestamp is determined as the second timestamp.

[0026] In some embodiments, in response to the third clock synchronization message sent by the second CPU, obtaining a third timestamp of sending the third clock synchronization message to the master server includes:

[0027] In response to a third clock synchronization message sent by the second CPU, acquiring a sending time of bytes of the third clock message;

[0028] The sending time of the bytes of the third clock message is determined as the third timestamp.

[0029] According to a third aspect of an embodiment of the present application, a clock synchronization method based on a DPU is provided, which is applied to a first media access controller of a DPU network card, wherein the first media access controller is arranged in the DPU of a master server, and the method comprises:

[0030] In response to a received first clock synchronization message, obtaining a first timestamp of receiving the first clock synchronization message, wherein the first clock synchronization message is sent by a first CPU, and the first CPU is set in the master server;

[0031] Generate a second clock synchronization message including the first timestamp according to the first timestamp and the first time message;

[0032] Sending the second clock synchronization message to the slave server;

[0033] In response to the third clock synchronization message sent from the server, acquiring a fourth timestamp of receiving the third clock synchronization message;

[0034] In response to the fourth clock synchronization message including the fourth timestamp sent by the first CPU, the fourth clock synchronization message is sent to the slave server, and the first timestamp and the fourth timestamp are used by the slave server to synchronize the clock to the clock of the master server.

[0035] According to a fourth aspect of an embodiment of the present application, a clock synchronization device based on a DPU is provided, which is applied to a first media access controller of a DPU network card, wherein the first media access controller is arranged in the DPU of a master server, and the device comprises:

[0036] A first acquisition module, configured to acquire, in response to a received first clock synchronization message, a first timestamp for sending the first clock synchronization message to a slave server, wherein the first clock synchronization message is sent by a first CPU, and the first CPU is arranged on the master server;

[0037] A first sending module, configured to send the first timestamp to the CPU;

[0038] a second sending module, configured to send the second clock synchronization message to the slave server in response to receiving a second clock synchronization message including the first timestamp sent by the CPU;

[0039] A second acquisition module, configured to acquire, in response to the third clock synchronization message sent from the server, a fourth timestamp of receiving the third clock synchronization message;

[0040] The third sending module is used to send the fourth clock synchronization message to the slave server in response to the fourth clock synchronization message including the fourth timestamp sent by the first CPU, and the first timestamp and the fourth timestamp are used for the slave server to synchronize the clock to the clock of the master server.

[0041] According to the fifth aspect of the embodiment of the present application, there is provided an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform operations corresponding to the aforementioned DPU-based clock synchronization method.

[0042] According to a fourth aspect of an embodiment of the present application, a computer storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the DPU-based clock synchronization method as described above is implemented.

[0043] According to the DPU-based clock synchronization solution provided in the embodiment of the present application, when the first media access controller receives the clock synchronization message sent by the first CPU and sends the clock synchronization message to the slave server, it obtains the first timestamp of the sent clock synchronization message and sends the first timestamp to the first CPU, and further sends the second clock synchronization message to the slave server. Furthermore, when the first media access controller receives the third clock synchronization message, it obtains the fourth timestamp of the third clock synchronization message, and finally sends the fourth clock synchronization message including the fourth timestamp to the slave server, so that the slave server synchronizes the clock with the clock of the master server. In the embodiment of the present application, the first media access controller can obtain the timestamp of the clock synchronization message when receiving or sending the clock synchronization message, which effectively eliminates the delay time of the clock synchronization message waiting in the DPU, and then the slave server can accurately synchronize the clock according to the timestamp obtained by the first media access controller, thereby improving the accuracy of clock synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0045] Figure 1 A schematic diagram of clock synchronization in the prior art provided in an embodiment of the present application;

[0046] Figure 2 is a flowchart of a clock synchronization method based on a DPU according to an embodiment of the present application;

[0047] Figure 3 is a flowchart of a clock synchronization method based on a DPU according to an embodiment of the present application;

[0048] Figure 4 is a flowchart of a clock synchronization method based on a DPU according to an embodiment of the present application;

[0049] Figure 5 is an interactive schematic diagram of a DPU-based clock synchronization method according to another embodiment of the present application;

[0050] Figure 6 A schematic diagram of the structure of a slave server according to an embodiment of the present application;

[0051] Figure 7 is a structural block diagram of a clock synchronization device based on a DPU according to an embodiment of the present application;

[0052] Figure 8 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the embodiments of the present application should fall within the scope of protection of the embodiments of the present application.

[0054] In a server cluster, when different servers communicate through network cards, clock synchronization is required to ensure the accuracy of data processing. Figure 1 As shown, it is a schematic diagram of clock synchronization in the prior art provided by an embodiment of the present application, wherein the main server includes a first CPU and a network card. When the first CPU of the main server needs to perform clock synchronization, the first CPU obtains the timestamp of the clock synchronization message when generating the clock synchronization message. Further, the first CPU sends the clock synchronization message including the timestamp to the network card, and the network card sends the clock synchronization message including the timestamp to the slave server. However, in the process of the first CPU sending the clock synchronization message including the timestamp to the network card, there will be path time. If the clock synchronization message including the timestamp needs to wait to be sent in the network card, there will be a delay time. However, the slave server cannot know the above path time and delay time. When the slave server performs clock synchronization, it still uses the timestamp obtained by the first CPU, which will result in low accuracy of the slave server using the timestamp obtained by the first CPU for clock synchronization.

[0055] To solve the above problems, the embodiment of the present application provides a clock synchronization method based on a DPU (Data Processing Unit), which is applied to a first media access controller of a DPU network card. The first media access controller is set in the DPU of a master server. The specific steps are as follows: Figure 2 As shown, the method includes:

[0056] S201: In response to a received first clock synchronization message, a first media access controller obtains a first timestamp for sending the first clock synchronization message to a slave server.

[0057] In an embodiment of the present application, during the periodic clock synchronization process, the first CPU of the main server generates a first clock synchronization message and sends the first clock synchronization message to the first media access controller (MAC) of the main server DPU. When the first media access controller receives the first clock synchronization message and sends the first clock synchronization message to the slave server, the first media access controller obtains the first timestamp of sending the first clock synchronization message, thereby determining the time of sending the first time synchronization message.

[0058] S202: The first media access controller sends a first timestamp to the first CPU.

[0059] In an embodiment of the present application, after the first media access controller obtains the first timestamp of the first clock synchronization message, the first media access controller sends the first timestamp of the first clock synchronization message to the first CPU of the main server, so that the first CPU of the main server uses the first timestamp to generate a second clock synchronization message including the first timestamp.

[0060] S203: In response to receiving the second clock synchronization message including the first timestamp sent by the first CPU, the first media access controller sends the second clock synchronization message to the slave server.

[0061] In an embodiment of the present application, after receiving the first timestamp, the first CPU of the main server generates a second clock synchronization message including the first timestamp based on the first timestamp, and sends the second clock synchronization message including the first timestamp to the first media access controller. After receiving the second clock synchronization message including the first timestamp, the first media access controller responds to the second clock synchronization message including the first timestamp and sends the second clock synchronization message including the first timestamp to the slave server, so that the slave server can obtain the first timestamp.

[0062] S204: The first media access controller obtains a fourth timestamp of receiving the third clock synchronization message in response to the third clock synchronization message sent from the server.

[0063] In an embodiment of the present application, after receiving the second clock synchronization message including the first timestamp, the slave server generates a third clock synchronization message and sends the third clock synchronization message to the first media access controller. After receiving the third clock synchronization message, the first media access controller obtains a fourth timestamp of receiving the third clock synchronization message. Further, the first media access controller sends the fourth timestamp to the first CPU of the main server, so that the first CPU of the main server generates a fourth clock message including the fourth timestamp using the fourth timestamp.

[0064] S205: The first media access controller sends a fourth clock synchronization message to the slave server in response to the fourth clock synchronization message including a fourth timestamp sent by the first CPU.

[0065] In an embodiment of the present application, after the first CPU of the main server generates a fourth clock message including the fourth timestamp using the fourth timestamp, the first CPU sends the fourth clock message including the fourth timestamp to the first media access controller. After receiving the fourth clock message including the fourth timestamp, the first media access controller responds to the fourth clock message including the fourth timestamp and sends the fourth clock message including the fourth timestamp to the slave server, so that the slave server obtains the fourth timestamp, so that the slave server can synchronize its clock with the clock of the main server using the first timestamp and the fourth timestamp.

[0066] The clock synchronization method based on DPU in the embodiment of the present application is that when the first media access controller receives the clock synchronization message sent by the first CPU and sends the clock synchronization message to the slave server, it obtains the first timestamp of the sent clock synchronization message, and sends the first timestamp to the first CPU, and further sends the second clock synchronization message to the slave server. Furthermore, when the first media access controller receives the third clock synchronization message, it obtains the fourth timestamp of the third clock synchronization message, and finally sends the fourth clock synchronization message including the fourth timestamp to the slave server, so that the slave server synchronizes the clock with the clock of the master server. In the embodiment of the present application, the first media access controller can obtain the timestamp of the clock synchronization message when receiving or sending the clock synchronization message, which effectively eliminates the delay time of the clock synchronization message waiting in the DPU, and then the slave server can accurately perform clock synchronization according to the timestamp obtained by the first media access controller, thereby improving the accuracy of clock synchronization.

[0067] Further, in response to the received first clock synchronization message, acquiring a first timestamp for sending the first clock synchronization message to the slave server in the embodiment of the present application may include the following steps:

[0068] S2011: In response to receiving a first clock synchronization message sent by a CPU, the first media access controller obtains a sending time of bytes of the first clock synchronization message.

[0069] In the embodiment of the present application, after receiving the first clock synchronization message sent by the first CPU, the first media access controller obtains the sending time of the bytes while sending the first clock message to the slave server byte by byte.

[0070] In an example, the first media access controller may obtain the sending time of the first byte of the first clock message when sending the first clock message to the slave server byte by byte.

[0071] S2022: The first media access controller determines the sending time of the byte as a first timestamp.

[0072] In the embodiment of the present application, the first media access controller determines the obtained sending time of the byte as the first timestamp after the sending time of the byte.

[0073] In an example, the first media access controller can obtain the sending time of the first byte of the first clock message when sending the first clock message to the slave server byte by byte, and determine the sending time of the first byte of the first clock message as the first timestamp.

[0074] In one example, the clock acquired by the first media access controller may be generated by a phase-locked loop.

[0075] The first media access controller of the embodiment of the present application can accurately determine the sending time of the first clock message by obtaining the first timestamp in the process of sending the first clock message byte, thereby effectively eliminating the delay time of the clock synchronization message waiting in the DPU, so that the slave server can accurately perform clock synchronization according to the timestamp obtained by the first media access controller, thereby improving the clock synchronization accuracy.

[0076] Further, in response to the third clock synchronization message sent from the server, acquiring a fourth timestamp of receiving the third clock synchronization message in the embodiment of the present application may include the following steps:

[0077] S2041: The first media access controller obtains a receiving time of a byte received from the third clock synchronization message in response to the third clock synchronization message sent from the server.

[0078] In the embodiment of the present application, when the first media access controller receives the third clock message sent from the server, the first media access controller obtains the receiving time of the third clock synchronization message byte.

[0079] In an example, during the process of receiving the third clock synchronization message, the first media access controller may obtain the receiving time of the first byte of the third clock message, and further obtain the receiving time of the third clock message.

[0080] S2042: The first media access controller determines the receiving time of the byte as a fourth timestamp.

[0081] In the embodiment of the present application, after acquiring the receiving time of the byte of the third clock message, the first media access controller determines the receiving time of the byte of the third clock synchronization message as the fourth timestamp.

[0082] In an example, during the process of receiving the third clock synchronization message, the first media access controller may obtain the receiving time of the first byte of the third clock message, and determine the receiving time of the first byte of the third clock message as the fourth timestamp.

[0083] The first media access controller of the embodiment of the present application can accurately determine the reception time of the third clock message by obtaining the fourth timestamp during the process of receiving the third clock message byte, thereby effectively eliminating the delay time of the clock synchronization message waiting in the DPU, so that the slave server can accurately perform clock synchronization according to the timestamp obtained by the first media access controller, thereby improving the clock synchronization accuracy.

[0084] Furthermore, the embodiment of the present application provides a clock synchronization method based on a DPU, which is applied to a second media access controller of a DPU network card, and the second media access controller is set in the DPU of a slave server. The specific steps are: Figure 3 As shown, including:

[0085] S301: In response to a received second clock synchronization message including a first timestamp, a second media access controller obtains a second timestamp of a received second clock synchronization message.

[0086] In an embodiment of the present application, when the first media access controller sends a second clock synchronization message including a first timestamp to a slave server, the first media access controller first sends the second clock synchronization message including the first timestamp to the second media access controller in the DPU of the slave server. In the process of receiving the second clock synchronization message including the first timestamp, the second media access controller obtains the receiving time of the second clock message, determines the receiving time of the second clock message as the second timestamp, and simultaneously sends the second clock synchronization message including the first timestamp to the second CPU of the slave server.

[0087] S302: The second media access controller obtains a third timestamp of sending the third clock synchronization message to the primary server in response to the third clock synchronization message sent by the second CPU.

[0088] In an embodiment of the present application, during the clock synchronization process, after the second CPU of the slave server receives the second clock synchronization message including the first timestamp, the second CPU generates a third clock synchronization message and sends the third clock synchronization message to the second media access controller. After the second media access controller receives the third clock synchronization message and sends the third clock synchronization message to the first media access controller, the second media access controller obtains the time of sending the third clock synchronization message, and then determines the third timestamp of sending the third clock synchronization message.

[0089] S303: The second media access controller receives a fourth clock synchronization message including a fourth timestamp sent by the primary server.

[0090] In the embodiment of the present application, the second media access controller receives a fourth clock synchronization message including a fourth timestamp sent by the first media access controller of the primary server.

[0091] S304: The second media access controller sends a second clock synchronization message including the first timestamp, a fourth clock synchronization message including the fourth timestamp, the second timestamp, and the third timestamp to the second CPU.

[0092] In an embodiment of the present application, after receiving the fourth clock synchronization message including the fourth timestamp, the second media access control sends the received first timestamp second clock synchronization message, the fourth clock synchronization message including the fourth timestamp, and the obtained second timestamp and third timestamp to the second CPU, so that the second CPU calculates the clock offset between the slave server clock and the master server clock according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp, and the second CPU adjusts the clock of the slave server according to the calculation result to complete the clock synchronization.

[0093] In one example, the clock skew is calculated according to the following formula:

[0094] Calculate the average path delay De l ay:

[0095] De l ay=[(t4-t1)-(t3-t2)] / 2;

[0096] After deformation: t2 = t1 + Del ay + Offset = t1 + [(t4 - t1) - (t3 - t2)] / 2 + Offset;

[0097] Finally: clock offset Offset: Offset = [(t2-t1)+(t3-t4)] / 2.

[0098] The embodiment of the present application obtains the second timestamp and the third timestamp through the second media access controller, and can accurately obtain the sending or receiving time of the clock synchronization message when receiving or sending the clock synchronization message, thereby effectively eliminating the delay time of the clock synchronization message waiting in the DPU, so that the slave server can accurately perform clock synchronization according to the timestamp obtained from the second media access controller, thereby improving the clock synchronization accuracy.

[0099] Further, in response to the received second clock synchronization message including the first timestamp, acquiring the second timestamp of the received second clock message in the embodiment of the present application may include the following steps:

[0100] S3011: In response to receiving a second clock synchronization message including a first timestamp sent by a primary server, the second media access controller obtains a receiving time of bytes of the second clock synchronization message including the first timestamp.

[0101] In an embodiment of the present application, the main server sends a second clock synchronization message including a first timestamp to the second media access controller through the first media access controller. In the process of receiving the second clock synchronization message including the first timestamp, the second media access controller obtains the reception time of the bytes of the second clock synchronization message including the first timestamp, thereby determining the reception time of the bytes of the second clock synchronization message.

[0102] S3012: The second media access controller determines a receiving time of a byte of a second clock synchronization message including the first timestamp as a second timestamp.

[0103] In the embodiment of the present application, after the second media access controller obtains the receiving time of the byte of the second clock synchronization message including the first timestamp, the second media access controller determines the receiving time as the second timestamp.

[0104] In one example, when the second media access controller determines the reception time of the bytes of the second clock synchronization message including the first timestamp, the second media access controller can obtain the reception time of the first byte of the second clock synchronization message and determine the reception time of the first byte of the second clock synchronization message as the second timestamp.

[0105] The second media access controller in the embodiment of the present application can accurately determine the reception time of the second clock message by obtaining the second timestamp during the process of receiving the second clock message bytes, thereby effectively eliminating the delay time of the clock synchronization message waiting in the DPU, so that the slave server can accurately perform clock synchronization according to the timestamp obtained by the second media access controller, thereby improving the clock synchronization accuracy.

[0106] Further, in response to the third clock synchronization message sent by the second CPU, acquiring a third timestamp for sending the third clock synchronization message to the main server in the embodiment of the present application may include the following steps:

[0107] S3021: The second media access controller obtains the sending time of bytes of the third clock message in response to the third clock synchronization message sent by the second CPU.

[0108] In the embodiment of the present application, when the second media access controller sends the third clock message to the main server, the second media access controller obtains the sending time of the bytes of the third clock synchronization message, and then determines the sending time of the bytes of the third clock message.

[0109] In one example, when the second media access controller sends the third clock message to the main server, the second media access controller can obtain the sending time of the first byte of the third clock synchronization message, and then determine the sending time of the first byte of the third clock synchronization message as the sending time of the third clock message.

[0110] S3022: The second media access controller determines the sending time of the bytes of the third clock message as a third timestamp.

[0111] In the embodiment of the present application, after acquiring the sending time of the bytes of the third clock message, the second media access controller determines the sending time of the bytes of the third clock message as the third timestamp.

[0112] The second media access controller in the embodiment of the present application can accurately determine the sending time of the third clock message by obtaining the third timestamp in the process of sending the third clock message byte, thereby effectively eliminating the delay time of the clock synchronization message waiting in the DPU, so that the slave server can accurately perform clock synchronization according to the timestamp obtained by the first media access controller, thereby improving the clock synchronization accuracy.

[0113] Furthermore, the embodiment of the present application provides a clock synchronization method based on a DPU, which is applied to a first media access controller of a DPU network card, and the first media access controller is set in the DPU of the main server. The specific steps are as follows: Figure 4 As shown, including:

[0114] S401: In response to a received first clock synchronization message, a first media access controller obtains a first timestamp of the received first clock synchronization message.

[0115] In the embodiment of the present application, this step is the same as step S201 and will not be described in detail here.

[0116] S402: The first media access controller generates a second clock synchronization message including the first timestamp according to the first timestamp and the first time message.

[0117] In an embodiment of the present application, the first media access controller receives the first clock synchronization message, and after obtaining the first timestamp of the received first clock synchronization message, the first media access controller inserts the first timestamp into the first clock synchronization message, thereby generating a first clock synchronization message including the first timestamp.

[0118] S403: The first media access controller sends a second clock synchronization message to the slave server.

[0119] In the embodiment of the present application, this step is the same as step S203 and will not be described in detail here.

[0120] S404: In response to the third clock synchronization message sent from the server, obtain a fourth timestamp of receiving the third clock synchronization message.

[0121] In the embodiment of the present application, this step is the same as step S204 and will not be described in detail here.

[0122] 405 . In response to the fourth clock synchronization message including the fourth timestamp sent by the first CPU, the first media access controller sends the fourth clock synchronization message to the slave server.

[0123] In the embodiment of the present application, this step is the same as step S205 and will not be described in detail here.

[0124] Furthermore, the present application embodiment provides another clock synchronization method based on DPU, see Figure 5 As shown, including:

[0125] The first CPU of the master server (Master) sends a first clock synchronization message (Sync) to the first media access controller of the DPU, and the first media access controller sends the first clock synchronization message to the second media access controller of the slave server (Sl ave) DPU. During the sending process, the sending time of the first byte of the first clock message is determined as the first timestamp, and the first timestamp is sent to the first CPU. The first CPU generates a second clock synchronization message (Fo ll ow_Up) including the first timestamp according to the first timestamp, and sends the second clock synchronization message including the first timestamp to the first media access controller. The first media access controller sends the second clock synchronization message including the first timestamp to the second media access controller.

[0126] When receiving the second clock synchronization message including the first timestamp, the second media access controller obtains the reception time of the first byte of the second clock synchronization message including the first timestamp, and determines the reception time of the first byte of the second clock synchronization message including the first timestamp as the second timestamp, and simultaneously sends the second clock synchronization message including the first timestamp and the second timestamp to the second CPU of the slave server, the second CPU generates a third clock synchronization message, and sends the third clock synchronization message to the second media access controller, and in the process of receiving the third clock synchronization message, the second media access controller determines the third timestamp according to the reception time of the first byte of the third clock synchronization message, and the second media access controller simultaneously sends the third timestamp to the second CPU.

[0127] During the process of receiving the third clock synchronization message, the first media access controller obtains the reception time of the first byte of the third clock synchronization message, determines the reception time of the first byte of the third clock synchronization message as the fourth timestamp, and sends the fourth timestamp and the third clock synchronization message to the first CPU. The first CPU generates a fourth clock synchronization message including the fourth timestamp according to the fourth timestamp, and sends the fourth clock synchronization message including the fourth timestamp to the first media access controller. The first media access controller sends the fourth clock synchronization message including the fourth timestamp to the second media access controller.

[0128] The second media access controller sends the received fourth clock synchronization message including the fourth timestamp to the second CPU, and then the second CPU can synchronize the clock of the slave server with the clock of the master server according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp.

[0129] For further information, see Figure 6 As shown, it is a structural diagram of the slave server of an embodiment of the present application. When the second CPU performs time synchronization, it first calculates the clock offset according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp to adjust the clock of the slave server based on the clock offset. After the adjustment is completed, the adjusted clock is sent to the register. At the same time, the second CPU sends a clock adjustment signal to the hardware adjustment module. The hardware adjustment module reads the current clock in the register in response to the clock adjustment signal, thereby synchronizing the clock of the slave server with the clock of the master server.

[0130] In one example, when the second media access controller obtains the timestamp, the second media access controller obtains the time in the register through the hard time adjustment module, thereby determining the timestamp.

[0131] Furthermore, the embodiment of the present application provides a clock synchronization device based on a DPU, which is applied to a first media access controller of a DPU network card, and the first media access controller is arranged in the DPU of the main server, specifically as follows: Figure 7 As shown, the device comprises:

[0132] A first acquisition module 701 is used to acquire a first timestamp of sending the first clock synchronization message to the slave server in response to a received first clock synchronization message, wherein the first clock synchronization message is sent by a first CPU, and the first CPU is set in the master server;

[0133] The first sending module 702 is configured to send the first timestamp to the CPU.

[0134] The second sending module 703 is configured to send the second clock synchronization message to the slave server in response to receiving the second clock synchronization message including the first timestamp sent by the CPU.

[0135] A second acquisition module 704, configured to acquire, in response to a third clock synchronization message sent from the server, a fourth timestamp of receiving the third clock synchronization message;

[0136] The third sending module 705 is used to send the fourth clock synchronization message to the slave server in response to the fourth clock synchronization message including the fourth timestamp sent by the first CPU, and the first timestamp and the fourth timestamp are used for the slave server to synchronize the clock to the clock of the master server.

[0137] The DPU-based clock synchronization device of this embodiment is used to implement the corresponding DPU-based clock synchronization method in the aforementioned multiple method embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be described in detail here. In addition, the functional implementation of each module in the deadlock processing device of this embodiment can refer to the description of the corresponding parts in the aforementioned method embodiments, which will not be described in detail here.

[0138] Reference Figure 8 , shows a schematic diagram of the structure of an electronic device according to an embodiment of the present application. The specific embodiment of the present application does not limit the specific implementation of the electronic device.

[0139] like Figure 8 As shown, the electronic device may include: a processor (processor) 802, a communication interface (Communications Interface) 804, a memory (memory) 806, and a communication bus 808.

[0140] in:

[0141] The processor 802 , the communication interface 804 , and the memory 806 communicate with each other via a communication bus 808 .

[0142] The communication interface 804 is used to communicate with other electronic devices or servers.

[0143] The processor 802 is used to execute the program 810, and specifically can execute the relevant steps in the above-mentioned DPU-based clock synchronization method embodiment.

[0144] Specifically, the program 810 may include program codes, which include computer operation instructions.

[0145] The processor 802 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs; or may be processors of different types, such as one or more CPUs and one or more ASICs.

[0146] The memory 806 is used to store the program 810. The memory 806 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory.

[0147] The program 810 may be specifically configured to enable the processor 802 to perform the following operations:

[0148] In an optional implementation, the program 810 is also used to enable the processor 802 to implement each step in the program 810. The specific implementation can refer to the corresponding steps and corresponding descriptions in the units in the above-mentioned DPU-based clock synchronization method embodiment, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described devices and modules can refer to the corresponding process description in the above-mentioned method embodiment, which will not be repeated here.

[0149] An embodiment of the present application also provides a computer program product, including computer instructions, which instruct a computing device to perform operations corresponding to any DPU-based clock synchronization method in the above-mentioned multiple method embodiments.

[0150] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.

[0151] The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor or programmable or dedicated hardware (such as an AS IC or FPGA). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the DPU-based clock synchronization method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the DPU-based clock synchronization method shown herein, the execution of the code converts the general-purpose computer into a dedicated computer for executing the DPU-based clock synchronization method shown herein.

[0152] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

[0153] The above implementation methods are only used to illustrate the embodiments of the present application, and are not limitations on the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present application. The scope of patent protection of the embodiments of the present application should be limited by the claims.

Claims

1. A clock synchronization method based on DPU, characterized in that: A first media access controller applied to a DPU network card, wherein the first media access controller is arranged in the DPU of a master server, and the method comprises: In response to a received first clock synchronization message, obtaining a first timestamp for sending the first clock synchronization message to the slave server, wherein the first clock synchronization message is sent by a first CPU, and the first CPU is set in the master server; Sending the first timestamp to the first CPU; In response to receiving a second clock synchronization message including the first timestamp sent by the first CPU, sending the second clock synchronization message to the slave server; In response to the third clock synchronization message sent from the server, acquiring a fourth timestamp of receiving the third clock synchronization message; In response to the fourth clock synchronization message including the fourth timestamp sent by the first CPU, the fourth clock synchronization message is sent to the slave server, and the first timestamp and the fourth timestamp are used by the slave server to synchronize the clock to the clock of the master server.

2. The method according to claim 1, characterized in that The step of acquiring, in response to the received first clock synchronization message, a first timestamp for sending the first clock synchronization message to the slave server comprises: In response to receiving a first clock synchronization message sent by the first CPU, obtaining a sending time of a byte of the first clock synchronization message; The sending time of the byte is determined as the first timestamp.

3. The method according to claim 1, characterized in that: The step of acquiring, in response to the third clock synchronization message sent from the server, a fourth timestamp of receiving the third clock synchronization message comprises: In response to the third clock synchronization message sent from the server, acquiring a receiving time when bytes of the third clock synchronization message are received; The reception time of the byte is determined as the fourth timestamp.

4. A clock synchronization method based on DPU, characterized in that: A second media access controller applied to a DPU network card, wherein the second media access controller is arranged in the DPU of a slave server, and the method comprises: In response to a received second clock synchronization message including a first timestamp, acquiring a second timestamp of the received second clock message, wherein the second clock synchronization message including the first timestamp is sent by the master server; In response to a third clock synchronization message sent by a second CPU, acquiring a third timestamp for sending the third clock synchronization message to the master server, wherein the second CPU is arranged on the slave server; Receiving a fourth clock synchronization message including a fourth timestamp sent by the main server; The second clock synchronization message including the first timestamp, the fourth clock synchronization message including the fourth timestamp, the second timestamp and the third timestamp are sent to the second CPU, so that the second CPU synchronizes the clock of the slave server to the clock of the master server according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp.

5. The method according to claim 4, characterized in that The step of acquiring, in response to the received second clock synchronization message including the first timestamp, a second timestamp of receiving the second clock message comprises: In response to receiving a second clock synchronization message including a first timestamp sent by the master server, acquiring a receiving time of a byte of the second clock synchronization message including the first timestamp; The receiving time of the byte of the second clock synchronization message including the first timestamp is determined as the second timestamp.

6. The method according to claim 4, characterized in that The step of acquiring, in response to the third clock synchronization message sent by the second CPU, a third timestamp of sending the third clock synchronization message to the master server comprises: In response to a third clock synchronization message sent by the second CPU, acquiring a sending time of bytes of the third clock message; The sending time of the bytes of the third clock message is determined as the third timestamp.

7. A clock synchronization method based on DPU, characterized in that: A first media access controller applied to a DPU network card, wherein the first media access controller is arranged in the DPU of a master server, and the method comprises: In response to a received first clock synchronization message, obtaining a first timestamp of receiving the first clock synchronization message, wherein the first clock synchronization message is sent by a first CPU, and the first CPU is set in the master server; Generate a second clock synchronization message including the first timestamp according to the first timestamp and the first time message; Sending the second clock synchronization message to the slave server; In response to the third clock synchronization message sent from the server, acquiring a fourth timestamp of receiving the third clock synchronization message; In response to the fourth clock synchronization message including the fourth timestamp sent by the first CPU, the fourth clock synchronization message is sent to the slave server, and the first timestamp and the fourth timestamp are used by the slave server to synchronize the clock to the clock of the master server.

8. A clock synchronization device based on DPU, characterized in that: A first media access controller applied to a DPU network card, wherein the first media access controller is arranged in the DPU of the main server, and the device comprises: A first acquisition module, configured to acquire, in response to a received first clock synchronization message, a first timestamp for sending the first clock synchronization message to a slave server, wherein the first clock synchronization message is sent by a first CPU, and the first CPU is arranged on the master server; A first sending module, configured to send the first timestamp to the CPU; a second sending module, configured to send the second clock synchronization message to the slave server in response to receiving a second clock synchronization message including the first timestamp sent by the CPU; A second acquisition module, configured to acquire, in response to the third clock synchronization message sent from the server, a fourth timestamp of receiving the third clock synchronization message; The third sending module is used to send the fourth clock synchronization message to the slave server in response to the fourth clock synchronization message including the fourth timestamp sent by the first CPU, and the first timestamp and the fourth timestamp are used for the slave server to synchronize the clock to the clock of the master server.

9. An electronic device, comprising: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform operations corresponding to the DPU-based clock synchronization method as described in any one of claims 1-7.

10. A computer program product, comprising computer instructions, wherein the computer instructions instruct a computing device to perform operations corresponding to the DPU-based clock synchronization method as described in any one of claims 1 to 7.

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