Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the isolation structure is located in the substrate; the control gate structure is positioned on the substrate at the side part of the isolation structure; the selection grid electrode is located on the isolation structure; the source-drain doped region is positioned in the substrate on two sides of the control gate structure; and the programming dielectric layer is located at the top of the selection grid. The semiconductor structure provided by the embodiment of the invention is provided with a selection gate located on an isolation structure, source-drain doped regions located in a substrate at two sides of a control gate structure are electrically connected with the selection gate, and a programming dielectric layer is located at the top of the selection gate; as the substrate region between the isolation structures is the active region, the selection gate is arranged on the isolation structures, so that the area of the semiconductor structure is reduced, and the occupied area of the device is further reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] One Time Programmable (OTP) memory based on antifuse structure is widely used due to its advantages such as high stability and compatibility with CMOS (Complementary Metal Oxide Semiconductor) process. Currently, the demand for one-time programmable storage is increasing. One-time programmable memory is usually composed of one-time programmable storage unit and peripheral circuit. At present, most of the antifuse one-time programmable memory based on CMOS process uses two field effect transistors in series. The one-time programmable memory produced can write the code into the memory in the form of coding, and program it by applying high voltage to the selected unit to break down the gate dielectric layer in the one-time programmable memory.

[0003] At present, one-time programmable memory devices occupy too large an area. In order to reduce chip costs, the area requirements for one-time programmable memories are getting higher and higher. Therefore, it is necessary to develop a one-time programmable memory with a smaller area to reduce the area of ​​the device. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce the area of ​​the semiconductor structure while ensuring that the semiconductor structure can operate normally.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; an isolation structure located in the substrate; a control gate structure located on the substrate on the side of the isolation structure; a selection gate located on the isolation structure; source-drain doped regions located in the substrate on both sides of the control gate structure; a programming dielectric layer located on top of the selection gate; wherein the source-drain doped regions of the control gate structure close to one side of the selection gate are electrically connected to the selection gate.

[0006] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, in which an isolation structure is formed; forming a control gate structure on the substrate on the side of the isolation structure; forming a selection gate on the isolation structure; forming source-drain doped regions in the substrate on both sides of the control gate structure; forming a programming dielectric layer on top of the selection gate; and electrically connecting the source-drain doped regions of the control gate structure close to the selection gate side to the selection gate.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] The semiconductor structure provided by the embodiment of the present invention has a selection gate located on an isolation structure, a source-drain doped region of a control gate structure close to the selection gate is electrically connected to the selection gate, and a programming dielectric layer is located on the top of the selection gate; since the substrate area between the isolation structures is an active area (active area, AA), the selection gate is set on the isolation structure, which is beneficial to saving the area of ​​the active area, so that the area of ​​the semiconductor structure is reduced, and thus the occupied area of ​​the device is reduced. In addition, the programming dielectric layer is located on the top of the selection gate, so that programming is performed by breakdown of the programming dielectric layer. At the same time, the source-drain doped region of the control gate structure close to the selection gate is electrically connected to the selection gate, so that the path current can flow to the source-drain doped region located on the side of the control gate structure away from the selection gate via the selection gate and the source-drain doped region, thereby ensuring that the semiconductor structure can operate normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of a semiconductor structure;

[0010] Figure 2 A schematic diagram showing an embodiment of a semiconductor structure of the present invention is shown;

[0011] Figures 3 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] As can be seen from the background technology, the one-time programmable memory occupies too large an area, and it is very important to reduce the device area.

[0013] Now, we will analyze the reasons why one-time programmable memory occupies too large an area by combining a semiconductor structure. Figure 1 , Figure 1 It is a schematic diagram of a semiconductor structure.

[0014] The semiconductor structure includes: a substrate 10; an isolation structure 20, which is located in the substrate 10; a first gate structure 40, which is located on the substrate 10 and includes a first dielectric layer 42 and a first gate 41 located on the first dielectric layer 42; a second gate structure 90, which is located on the substrate 10 and includes a second dielectric layer 92 and a second gate 91 located on the second dielectric layer 92; a source-drain doped region 30, which is located in the substrate 10 on both sides of the first gate structure 40 and the second gate structure 90; a bit line (BL) plug 70, which is located at the top of the source-drain doped region 30 on the side of the second gate structure 90 away from the first gate structure 40 and is electrically connected to the source-drain doped region 30; a word line (WL) plug 60, which is located at the top of the second gate structure 90 and is electrically connected to the second gate structure 90; and a source line (SL) plug 50, which is located at the top of the first gate structure 40 and is electrically connected to the first gate structure 40.

[0015] However, since the first gate structure 40 and the second gate structure 90 are both located in the active region, the one-time programmable memory occupies too large an area.

[0016] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including a substrate; an isolation structure located in the substrate; a control gate structure located on the substrate on the side of the isolation structure; a selection gate located on the isolation structure; source and drain doped regions located in the substrate on both sides of the control gate structure; and a programming dielectric layer located on top of the selection gate; wherein the source and drain doped regions of the control gate structure close to one side of the selection gate are electrically connected to the selection gate.

[0017] The semiconductor structure provided by the embodiment of the present invention has a selection gate located on an isolation structure, a source-drain doped region of a control gate structure close to the selection gate is electrically connected to the selection gate, and a programming dielectric layer is located on the top of the selection gate; since the substrate area between the isolation structures is an active area, the selection gate is arranged on the isolation structure, which is beneficial to saving the area of ​​the active area, so that the area of ​​the semiconductor structure is reduced, and thus the occupied area of ​​the device is reduced. In addition, the programming dielectric layer is located on the top of the selection gate, so that programming is performed by breakdown of the programming dielectric layer. At the same time, the source-drain doped region of the control gate structure close to the selection gate is electrically connected to the selection gate, so that the path current can flow through the selection gate and the source-drain doped region to the source-drain doped region located on the side of the control gate structure away from the selection gate, thereby ensuring that the semiconductor structure can operate normally.

[0018] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0019] Figure 2 It is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0020] refer to Figure 2 In this embodiment, the semiconductor structure includes: a substrate 100; an isolation structure 200, located in the substrate 100; a control gate structure 400, located on the substrate 100 at the side of the isolation structure 200; a selection gate 1000, located on the isolation structure 200; a source-drain doped region 300, located in the substrate 100 on both sides of the control gate structure 400; a programming dielectric layer 900, located on the top of the selection gate 1000; wherein the source-drain doped region 300 of the control gate structure 400 close to the selection gate 1000 is electrically connected to the selection gate 1000.

[0021] The substrate 100 is used to provide a process platform for forming the semiconductor structure. In this embodiment, the semiconductor structure is a one-time programmable memory.

[0022] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may also be a material suitable for process requirements or easy to integrate.

[0023] The isolation structure 200 is used to isolate adjacent devices.

[0024] In this embodiment, the material of the isolation structure 200 is an insulating material, and the insulating material includes silicon oxide. The isolation structure 200 is a shallow trench isolation (STI), so that the isolation structure 200 has a good isolation effect.

[0025] The control gate structure 400 is located on the substrate 100 on the side of the isolation structure 200, and includes a gate dielectric layer 402 and a control gate 401 located on the gate dielectric layer 402; the control gate structure 400 and the source-drain doped regions 300 located on both sides thereof constitute a switch control transistor, and the switch control transistor realizes the passage with the selection gate 1000 by controlling the conduction of the channel below it, thereby realizing programming by breaking down the programming dielectric layer 900 through high voltage.

[0026] The gate dielectric layer 402 is a gate dielectric layer for isolating the control gate 401 and the channel thereunder. As an example, the material of the gate dielectric layer 402 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0027] The selection gate 1000 is connected in series with the switch control transistor, and the selection gate 1000 is used to select the switch control transistor to be programmed and to be read.

[0028] In this embodiment, the selection gate 1000 is located on the isolation structure 200. Since the substrate 100 area between the isolation structures 200 is an active area, the selection gate 1000 is set on the isolation structure 200, which is beneficial to saving the area of ​​the active area, reducing the area of ​​the semiconductor structure, and further reducing the occupied area of ​​the device.

[0029] It should be noted that the projection of the selection gate 1000 on the isolation structure 200 is located inside the isolation structure 200 .

[0030] When the semiconductor structure is working, after the programming dielectric layer 900 is broken down, the path current can flow to the source-drain doped region 300 located on the side of the control gate structure 400 away from the selection gate 1000 through the selection gate 1000 and the source-drain doped region 300 on the side of the control gate structure 400 away from the selection gate 1000. Since the thickness of the isolation structure 200 is usually greater than the thickness of the gate dielectric layer, when a high voltage is applied to the programming dielectric layer 900 formed on the top of the selection gate 1000, the isolation structure 200 is not easily broken down, thereby reducing the probability of affecting the preset flow direction of the current due to the breakdown of the dielectric material at the bottom of the selection gate 1000.

[0031] In this embodiment, the material of the control gate 401 includes polysilicon or metal, and the material of the selection gate 1000 includes polysilicon or metal.

[0032] It should be noted that the semiconductor structure further includes: a gate spacer (not shown), which is located on the sidewalls of the control gate 401 and the sidewalls of the selection gate 1000 .

[0033] The gate sidewall is used to define the formation position of the source-drain doping region 300 , and is also used to protect the control gate 401 and the selection gate 1000 .

[0034] The gate sidewall spacer may be a single-layer structure or a stacked structure, and the material of the gate sidewall spacer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the gate sidewall spacer is a single-layer structure, and the material of the gate sidewall spacer is silicon nitride.

[0035] The source-drain doped region 300 is used to form a source region or a drain region of a device.

[0036] The conductivity type of the doped ions in the source-drain doping region 300 is the same as the channel conductivity type of the corresponding device. As an example, when the formed device is an N-type field effect transistor device, the doped ions in the source-drain doping region 300 are N-type doped ions, and the N-type doped ions include P ions, As ions, or Sb ions; when the formed device is a P-type field effect transistor device, the doped ions in the source-drain doping region 300 are P-type doped ions, and the P-type doped ions include B ions, Ga ions, or In ions.

[0037] In this embodiment, the selection gate 1000 is disposed adjacent to a source-drain doping region 300 in the switch control transistor close to one side of the selection gate 1000. Specifically, the source-drain doping region is also located in the substrate 100 on both sides of the selection gate 1000, and the adjacent control gate structure 400 and the selection gate 1000 share the source-drain doping region 300.

[0038] The selection gate 1000 is disposed adjacent to the source-drain doping region 300 of the switch control transistor close to the selection gate 1000, which effectively reduces the distance between the source-drain doping region 300 of the control gate structure 400 close to the selection gate 1000 and the selection gate 1000, thereby reducing the difficulty of electrically connecting the source-drain doping region 300 of the control gate structure 400 close to the selection gate 1000 and the selection gate 1000. For example, when a shared plug is used to realize the electrical connection between the two, the line width of the shared plug is smaller, which is conducive to reducing the difficulty of forming the shared plug.

[0039] Source and drain doping regions are also formed in the substrate 100 on both sides of the selection gate 1000, which is beneficial to improving the stability of the process.

[0040] In this embodiment, the source-drain doped regions 300 are formed by ion implantation.

[0041] The programming dielectric layer 900 is located on the top of the selection gate 1000 , and the one-time programmable memory is programmed by breaking through the programming dielectric layer 900 .

[0042] In this embodiment, the selection gate 1000 is located on the isolation structure 200, that is, the selection gate 1000 and the substrate 100 are isolated by the isolation structure 200. Therefore, in order to ensure that the semiconductor structure can work normally, the programming dielectric layer 900 is set on the top of the selection gate 1000, so that programming is performed by the breakdown of the programming dielectric layer 900. Specifically, once the programming dielectric layer 900 breaks down, the path current can flow through the selection gate 1000 and the source-drain doped region 300 to the source-drain doped region 300 located on the side of the control gate structure 400 away from the selection gate 1000.

[0043] In this embodiment, the programming dielectric layer 900 also extends to cover the sidewall of the selection gate 1000 facing away from the control gate structure 400 .

[0044] The programming dielectric layer 900 is usually formed by a deposition process and a patterning process. Therefore, the programming dielectric layer 900 also extends to cover the side wall of the selection gate 1000 facing away from the control gate structure 400, which is beneficial to increase the process window of the patterning process and reduce the difficulty of the patterning process.

[0045] Specifically, the programming dielectric layer 900 extends to cover the gate spacer on the sidewall of the selection gate 1000 facing away from the control gate structure 400 .

[0046] The material of the programming dielectric layer 900 includes one or more of silicon oxide and silicon nitride. Silicon oxide and silicon nitride are highly compatible with existing processes.

[0047] In this embodiment, the programming dielectric layer 900 includes a residual metal silicide barrier (SAB) layer, that is, a residual portion after the metal silicide barrier layer is patterned. In other embodiments, the programming dielectric layer may also be formed separately.

[0048] The process for forming the semiconductor structure includes a metal silicide process, and the metal silicide barrier layer is used to shield the area where the metal silicide layer does not need to be formed. Therefore, using the remaining metal silicide barrier layer as the programming dielectric layer 900 is beneficial to simplify the complexity of forming the programming dielectric layer 900, and is beneficial to improving manufacturing efficiency and saving process costs.

[0049] As an example, the programming dielectric layer 900 is a residual metal silicide barrier layer, therefore, the programming dielectric layer 900 includes a bottom dielectric layer 901 and a top dielectric layer 902 covering the bottom dielectric layer 901, wherein the material of the top dielectric layer 902 is silicon nitride, and the material of the bottom dielectric layer 901 is silicon oxide.

[0050] The material of the bottom dielectric layer 901 is silicon oxide, which can also play a role of stress buffering, which is beneficial to improving the adhesion between the top dielectric layer 902 and the selection gate 1000 .

[0051] As an example, the programming dielectric layer 900 is made by an atomic layer deposition process, which improves the conformal coverage capability of the programming dielectric layer 900 .

[0052] In this embodiment, the source-drain doped region 300 of the control gate structure 400 close to the selection gate 1000 (that is, the source-drain doped region 300 close to the selection gate 1000 in the switch control transistor) is electrically connected to the selection gate 1000. Therefore, the path current can flow through the selection gate 1000 and the source-drain doped region 300 to the source-drain doped region 300 located on the side of the control gate structure 400 away from the selection gate 1000, thereby ensuring that the semiconductor structure can work normally (for example, the control gate structure 400 confirms the state of the OTP unit by reading the path current between the selection gate 1000 and the source-drain doped region 300 on the side of the control gate structure 400 away from the selection gate 1000).

[0053] Specifically, the semiconductor structure also includes: a shared plug 1100, which is located on the selection gate 1000 exposed by the programming dielectric layer 900 and the source-drain doped region 300 of the control gate structure 400 close to the selection gate side, and the shared plug 1100 electrically connects the selection gate 1000 and the source-drain doped region 300 of the control gate 400 structure close to the selection gate 1000 side.

[0054] The shared plug 1100 is used to electrically connect the selection gate 1000 and the source-drain doped region 300 of the control gate structure 400 close to the selection gate 1000, thereby reducing the complexity of electrical connection between the source-drain doped region 300 of the control gate structure 400 close to the selection gate 1000 and the selection gate 1000.

[0055] The material of the shared plug 1100 includes metal, for example, one or more of tungsten, cobalt and ruthenium. Tungsten, cobalt and ruthenium have good conductivity, which is conducive to improving the electrical connection performance between the shared plug 1100 and the selection gate 1000 and the source-drain doping region 300.

[0056] In this embodiment, along a direction perpendicular to the sidewall of the selection gate 1000 , an overlapping width W1 between the shared plug 1100 and the selection gate 1000 is at least 60 nanometers, and an overlapping width W2 between the shared plug 1100 and the source / drain doped region 300 is at least 60 nanometers.

[0057] Along the direction perpendicular to the side wall of the selection gate 1000, the overlapping width W1 of the shared plug 1100 and the selection gate 1000, as well as the overlapping width W2 of the shared plug 1100 and the source-drain doped region 300 should not be too small, otherwise, due to the influence of alignment error, it is easy to cause poor contact between the shared plug 1100 and the selection gate 1000 or the source-drain doped region 300, thereby affecting the normal operation of the device.

[0058] In this embodiment, the semiconductor structure further includes: a metal silicide layer 800 located between the bottom of the shared plug 1100 and the select gate 1000 , and between the bottom of the shared plug 1100 and the source-drain doped region 300 .

[0059] The metal silicide layer 800 can effectively reduce the contact resistance between the shared plug 1100 and the selection gate 1000 , and the contact resistance between the shared plug 1100 and the source-drain doped region 300 , thereby improving the electrical connection performance of the selection gate 1000 , the shared plug 1100 and the source-drain doped region 300 .

[0060] In this embodiment, the semiconductor structure further includes: a bit line plug 700, which is located at the top of the source-drain doped region 300 on the side of the control gate structure 400 away from the selection gate 1000 and is electrically connected to the source-drain doped region 300 at the bottom; a word line plug 600, which is located at the top of the control gate structure 400 and is electrically connected to the control gate structure 400; and a source line plug 500, which is located on the programming dielectric layer 900 and is connected to the programming dielectric layer 900.

[0061] In this embodiment, the source line plug 500 is connected to the programming dielectric layer 900 , so that a voltage is applied to the programming dielectric layer 900 through the source line plug 500 to achieve breakdown of the programming dielectric layer 900 .

[0062] The bit line plug 700 is electrically connected to the source-drain doped region 300 at the bottom thereof, and the word line plug 600 is electrically connected to the control gate structure 400, so as to apply electrical signals required for normal operation of the device to the source-drain doped region 300 and the control gate structure 400 away from the select gate 1000.

[0063] For the definition of the materials of the bit line plug 700 , the word line plug 600 and the source line plug 500 , reference may be made to the aforementioned description of the shared plug 1100 , which will not be repeated here.

[0064] In one embodiment, the bit line plug 700 , the word line plug 600 , the source line plug 500 and the shared plug 1100 are formed in the same step, and therefore, the bit line plug 700 , the word line plug 600 , the source line plug 500 and the shared plug 1100 are made of the same material.

[0065] It should be noted that the semiconductor structure also includes: a third dielectric layer (not shown), which is located on the substrate 100 and covers the control gate structure 400, the selection gate 1000, the source and drain doped regions 300, the programming dielectric layer 900 and the metal silicide layer 800; accordingly, the bit line plug 700, the word line plug 600, the source line plug 500 and the shared plug 1100 are all located in the third dielectric layer.

[0066] The third dielectric layer is used to achieve electrical isolation among the bit line plug 700 , the word line plug 600 , the source line plug 500 and the shared plug 1100 .

[0067] As an example, the material of the third dielectric layer is silicon oxide. It is understandable that in other embodiments, the material of the third dielectric layer may also be an insulating material.

[0068] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0069] refer to Figure 3 , providing a substrate 110, on which an isolation structure 210 is formed.

[0070] The substrate 110 is used to provide a process platform for subsequent processes.

[0071] In this embodiment, the material of the substrate 110 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may also be a material suitable for process requirements or easy to integrate.

[0072] The isolation structure 210 is used to isolate adjacent devices.

[0073] In this embodiment, the isolation structure 210 is made of insulating material, including silicon oxide. The isolation structure 210 is shallow trench isolation, and the shallow trench isolation technology uses a recessed trench structure, so that the isolation structure 210 has a good isolation effect.

[0074] Continue to refer Figure 3, a control gate structure 410 is formed on the substrate 110 at the side of the isolation structure 210 , including a gate dielectric layer 404 and a control gate 403 located on the gate dielectric layer 404 ; and a selection gate 2000 is formed on the isolation structure 210 .

[0075] The control gate structure 410 and the source-drain doped regions 310 in the substrate on both sides thereof constitute a switch control transistor. The switch control transistor realizes the passage with the selection gate 2000 by controlling the conduction of the channel below it, thereby realizing programming by breaking down the programming dielectric layer 910 through high voltage.

[0076] The selection gate 2000 is used to select the switch control transistor to be programmed and read.

[0077] The selection gate 2000 is located on the isolation structure 210, so that the occupation of the active area can be effectively reduced, so that the area of ​​the semiconductor structure is reduced, and further the occupied area of ​​the device is reduced.

[0078] It should be noted that, a programming dielectric layer is subsequently formed on the top of the selection gate 2000, and the source-drain doping region of the control gate structure 410 close to the selection gate 2000 is electrically connected to the selection gate 2000. The projection of the selection gate 2000 on the isolation structure 210 is located inside the isolation structure 210. Since the thickness of the isolation structure 210 is usually larger than the thickness of the gate dielectric layer, when a high voltage is applied to the programming dielectric layer formed on the top of the selection gate 2000, the isolation structure 210 is not easily broken down, thereby reducing the probability of affecting the preset flow direction of the current due to the breakdown of the dielectric material at the bottom of the selection gate 2000.

[0079] In this embodiment, the material of the control gate 403 includes polysilicon or metal, and the material of the selection gate 2000 includes polysilicon or metal.

[0080] In this embodiment, the control gate 403 and the selection gate 2000 are formed in the same step, thereby reducing the modification of the existing process and reducing the process complexity. Accordingly, the control gate 403 and the selection gate 2000 are made of the same material.

[0081] The gate dielectric layer 404 is a gate dielectric layer for isolating the control gate 403 and the channel thereunder. As an example, the material of the gate dielectric layer 404 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0082] It should be noted that after forming the control gate 403 and the selection gate 2000 , the process further includes: forming gate spacers (not shown) on the sidewalls of the control gate 403 and the selection gate 2000 .

[0083] The gate sidewall is used to subsequently define the formation position of the source and drain doping regions, and is also used to protect the control gate 403 and the selection gate 2000 in subsequent processes.

[0084] The gate sidewall spacer may be a single-layer structure or a stacked structure, and the material of the gate sidewall spacer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the gate sidewall spacer is a single-layer structure, and the material of the gate sidewall spacer is silicon nitride.

[0085] refer to Figure 4 , source and drain doped regions are formed in the substrate 110 on both sides of the control gate structure 410 .

[0086] The source-drain doped region 310 is used to form a source region or a drain region of a device.

[0087] The doping ions in the source-drain doping region 310 are determined by the corresponding device type. The doping of an N-type field effect transistor device is N-type doping with electrons as the majority carriers, and the doping of a P-type field effect transistor device is P-type doping with holes as the majority carriers.

[0088] In this embodiment, the selection gate 2000 is disposed adjacent to the source-drain doped region 310 in the switch control transistor close to one side of the selection gate 2000. Specifically, in the step of forming the source-drain doped region 310 in the substrate 110 on both sides of the control gate structure 410, the source-drain doped region 310 is also formed in the substrate 110 on both sides of the selection gate 2000, and the control gate structure 410 and the selection gate 2000 share the source-drain doped region 310.

[0089] The selection gate 2000 is disposed adjacent to the source-drain doping region 310 of the switch control transistor close to the selection gate 2000, which effectively reduces the distance between the source-drain doping region 310 of the control gate structure 410 close to the selection gate 2000 and the selection gate 2000, thereby reducing the difficulty of electrically connecting the source-drain doping region 310 of the control gate structure 410 close to the selection gate 2000 and the selection gate 2000. For example, when a shared plug is used to realize the electrical connection between the two, the line width of the shared plug is smaller, which is conducive to reducing the difficulty of forming the shared plug.

[0090] In this embodiment, the source-drain doping region 310 is formed by an ion implantation process.

[0091] Combined with reference Figure 5 and Figure 6 , a programming dielectric layer 910 is formed on the top of the selection gate 2000 .

[0092] The programming dielectric layer 910 is located on the top of the selection gate 2000 , and the one-time programmable memory is programmed by breaking down the programming dielectric layer 910 .

[0093] In this embodiment, the selection gate 2000 is located on the isolation structure 310, that is, the selection gate 2000 and the substrate 110 are isolated by the isolation structure 310. Therefore, in order to ensure that the semiconductor structure can work normally, the programming dielectric layer 910 is set on the top of the selection gate 2000, so that programming is performed by the breakdown of the programming dielectric layer 910. Specifically, once the programming dielectric layer 910 breaks down, the path current can flow through the selection gate 2000 and the source-drain doped region 310 to the source-drain doped region 310 located on the side of the control gate structure 410 away from the selection gate 2000.

[0094] The material of the programming dielectric layer 910 includes one or more of silicon oxide and silicon nitride. Silicon oxide and silicon nitride are highly compatible with existing processes.

[0095] In this embodiment, the step of forming a programming dielectric layer 910 on the top of the selection gate 2000 includes: forming a metal silicide blocking layer covering the isolation structure 210, the control gate structure 410, the selection gate 2000 and the source and drain doping regions 310; patterning the metal silicide blocking layer, retaining the remaining metal silicide blocking layer located on the top of the selection gate 2000, and the remaining metal silicide blocking layer serving as the programming dielectric layer 910.

[0096] The metal silicide barrier layer is used to shield the area where the metal silicide layer does not need to be formed. Therefore, using the remaining metal silicide barrier layer as the programming dielectric layer 910 is beneficial to simplify the complexity of forming the programming dielectric layer 910, and is beneficial to improving manufacturing efficiency and saving process costs.

[0097] In the present embodiment, in the step of forming a metal silicide barrier layer covering the isolation structure 210, the control gate structure 410, the selection gate 2000 and the source-drain doping region 310, the metal silicide barrier layer is an ONO (oxide-nitride-oxide) structure, that is, it includes a silicon oxide layer, a silicon nitride layer and another silicon oxide layer stacked in sequence from bottom to top.

[0098] It should be noted that in the process of graphing the metal silicide barrier layer, the silicon oxide layer on the top layer is removed. Therefore, the programming dielectric layer 910 includes a bottom dielectric layer 903 and a top dielectric layer 904 covering the bottom dielectric layer 903, wherein the material of the top dielectric layer 904 is silicon nitride and the material of the bottom dielectric layer 903 is silicon oxide.

[0099] The material of the bottom dielectric layer 903 is silicon oxide, which can also play a role of stress buffering, which is beneficial to improving the adhesion between the top dielectric layer 904 and the selection gate 2000 .

[0100] In this embodiment, in the step of forming a metal silicide barrier layer covering the isolation structure 210, the control gate structure 410, the selection gate 2000 and the source-drain doping region 310, the metal silicide barrier layer is made by an atomic layer deposition process, which improves the conformal coverage capability of the programming dielectric layer 910.

[0101] In other embodiments, the programming dielectric layer may also be formed separately.

[0102] In this embodiment, the programming dielectric layer 910 also extends to cover the sidewall of the selection gate 2000 facing away from the control gate structure 410 .

[0103] The programming dielectric layer 910 is formed by a deposition process and a patterning process. Therefore, the programming dielectric layer 910 also extends to cover the side wall of the selection gate 2000 facing away from the control gate structure 410, which is beneficial to increase the process window of the patterning process and reduce the difficulty of the patterning process.

[0104] Specifically, the programming dielectric layer 910 extends to cover the gate spacer on the sidewall of the selection gate 2000 facing away from the control gate structure 410 .

[0105] Combined with reference Figure 6 and Figure 7 , so that the source-drain doped region 310 on the side of the control gate structure 410 close to the selection gate 2000 is electrically connected to the selection gate 2000.

[0106] In this embodiment, the source-drain doped region 310 of the control gate structure 410 close to the selection gate 2000 is electrically connected to the selection gate 2000. Therefore, the path current can flow through the selection gate 2000 and the source-drain doped region 310 to the source-drain doped region 310 located on the side of the control gate structure 410 away from the selection gate 2000, thereby ensuring that the semiconductor structure can work normally (for example, the control gate structure 410 confirms the state of the OTP unit by reading the path current between the selection gate 2000 and the source-drain doped region 310 on the side of the control gate structure 410 away from the selection gate 2000).

[0107] Specifically, after forming the programming dielectric layer 910, the semiconductor structure forming method further includes: forming a shared plug 1200 located on the selection gate 2000 exposed by the programming dielectric layer 910 and the source-drain doped region 310 of the control gate structure 410 close to the selection gate 2000, wherein the shared plug 1200 is used to electrically connect the selection gate 2000 and the source-drain doped region 310 of the control gate structure 410 close to the selection gate 2000.

[0108] The shared plug 1200 is used to electrically connect the select gate 2000 and the source-drain doped region 310 of the control gate structure 410 close to the select gate 2000, thereby reducing the complexity of achieving electrical connection between the select gate 2000 and the source-drain doped region 310 of the control gate structure 410 close to the select gate 2000.

[0109] The material of the shared plug 1200 includes metal, for example, one or more of tungsten, cobalt and ruthenium. Tungsten, cobalt and ruthenium have good conductivity, which is conducive to improving the electrical connection performance between the shared plug 1200 and the selection gate 2000 and the source and drain doping region 310.

[0110] In this embodiment, along a direction perpendicular to the sidewall of the selection gate 2000 , an overlapping width W1 between the shared plug 1200 and the selection gate 2000 is at least 60 nanometers, and an overlapping width W2 between the shared plug 1200 and the source / drain doped region 310 is at least 60 nanometers.

[0111] Along the direction perpendicular to the side wall of the selection gate 2000, the overlapping width W1 of the shared plug 1200 and the selection gate 2000, as well as the overlapping width W2 of the shared plug 1200 and the source-drain doped region 310 should not be too small, otherwise, due to the influence of alignment error, it is easy to cause poor contact between the shared plug 1200 and the selection gate 2000 or the source-drain doped region 310, thereby affecting the normal operation of the device.

[0112] Combined with reference Figure 6 It should be noted that, before forming the shared plug 1200, the forming method further includes: forming a metal silicide layer 810 on the selection gate 2000 and the source-drain doped region 310 exposed by the programming dielectric layer 910; accordingly, Figure 7 As shown, in the step of forming the shared plug 1200 , the shared plug 1200 is connected to the metal silicide layer 810 .

[0113] The metal silicide layer 810 can effectively reduce the contact resistance between the shared plug 1200 and the selection gate 2000 , and the contact resistance between the shared plug 1200 and the source-drain doped region 310 , thereby improving the electrical connection performance of the selection gate 2000 , the shared plug 1200 and the source-drain doped region 310 .

[0114] Continue to refer Figure 7 The formation method further includes: forming a bit line plug 710 on the top of the source-drain doped region 310 on the side of the control gate structure 410 away from the selection gate 2000, and the bit line plug 710 is electrically connected to the source-drain doped region 310 at the bottom; forming a word line plug 610 on the top of the control gate 410, and the word line plug 610 is electrically connected to the control gate 410; forming a source line plug 510 on the programming dielectric layer 910, and the source line plug 510 is connected to the programming dielectric layer 910.

[0115] In this embodiment, the source line plug 510 is connected to the programming dielectric layer 910 , and a voltage is applied to the programming dielectric layer 910 through the source line plug 510 to achieve breakdown of the programming dielectric layer 910 .

[0116] The bit line plug 710 is electrically connected to the source-drain doped region 310 at the bottom thereof, and the word line plug 610 is electrically connected to the control gate structure 410, thereby applying electrical signals required for normal operation of the device to the source-drain doped region 310 and the control gate structure 410 away from the select gate 2000.

[0117] In this embodiment, the bit line plug 700 , the word line plug 600 , the source line plug 500 and the shared plug 1100 are formed in the same step, so the bit line plug 700 , the word line plug 600 , the source line plug 500 and the shared plug 1100 are made of the same material.

[0118] It should be noted that, before forming the bit line plug 700, the word line plug 600, the source line plug 500 and the shared plug 1100, the method for forming the semiconductor structure further includes: forming a third dielectric layer (not shown) on the substrate 110, the third dielectric layer covering the control gate structure 410, the selection gate 2000, the source and drain doped regions 310, the programming dielectric layer 910 and the metal silicide layer 810; accordingly, the bit line plug 710, the word line plug 610, the source line plug 510 and the shared plug 1200 are all formed in the third dielectric layer.

[0119] Specifically, after forming a bit line opening, a word line opening, a source line opening and a shared opening in the third dielectric layer, a conductive material is filled in the bit line opening, the word line opening, the source line opening and the shared opening to respectively form a bit line plug 700 located in the bit line opening, a word line plug 600 located in the word line opening, a source line plug 500 located in the source line opening, and a shared plug 1100 located in the shared opening.

[0120] The third dielectric layer is used to achieve electrical isolation among the bit line plug 710 , the word line plug 610 , the source line plug 510 and the shared plug 1200 .

[0121] As an example, the material of the third dielectric layer is silicon oxide. It is understandable that in other embodiments, the material of the third dielectric layer may also be an insulating material.

[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; an isolation structure, located in the substrate; a control gate structure located on the substrate at a side of the isolation structure; A select gate located on the isolation structure; Source and drain doped regions are located in the substrate on both sides of the control gate structure; A programming dielectric layer, located on top of the selection gate; Wherein, the source-drain doped region of the control gate structure close to the select gate is electrically connected to the select gate.

2. The semiconductor structure according to claim 1, wherein: The material of the control gate includes polysilicon or metal, and the material of the select gate includes polysilicon or metal.

3. The semiconductor structure according to claim 1, wherein: The semiconductor structure also includes: a shared plug located on the select gate exposed by the programming dielectric layer and the source-drain doped region of the control gate structure close to the select gate, the shared plug electrically connecting the select gate and the source-drain doped region of the control gate structure close to the select gate.

4. The semiconductor structure according to claim 3, characterized in that The material of the shared plug includes one or more of tungsten, cobalt and ruthenium.

5. The semiconductor structure according to claim 3, wherein: The semiconductor structure further includes: a metal silicide layer located between the bottom of the shared plug and the selection gate, and between the bottom of the shared plug and the source and drain doping regions.

6. The semiconductor structure according to claim 3, characterized in that Along a direction perpendicular to the sidewall of the selection gate, an overlapping width between the shared plug and the selection gate is at least 60 nanometers, and an overlapping width between the shared plug and the source-drain doped region is at least 60 nanometers.

7. The semiconductor structure according to claim 1, wherein: The programming dielectric layer also extends to cover the sidewall of the selection gate facing away from the control gate structure.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The source-drain doping regions are also located in the substrate at both sides of the selection gate, and the control gate structure and the selection gate share the source-drain doping regions.

9. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The programming dielectric layer includes a residual metal silicide barrier layer.

10. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The material of the programming dielectric layer includes one or more of silicon oxide and silicon nitride.

11. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The semiconductor structure further includes a source line plug located on the programming dielectric layer and connected to the programming dielectric layer.

12. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The semiconductor structure further comprises: a bit line plug, which is located at the top of the source-drain doped region on the side of the control gate structure away from the selection gate and is electrically connected to the source-drain doped region at the bottom; The word line plug is located on the top of the control gate structure and is electrically connected to the control gate structure.

13. A method for forming a semiconductor structure, characterized in that: include: providing a substrate having an isolation structure formed therein; forming a control gate structure on the substrate at a side of the isolation structure; forming a select gate on the isolation structure; forming source-drain doped regions in the substrate on both sides of the control gate structure; forming a programming dielectric layer on top of the select gate; The source-drain doped region of the control gate structure close to the selection gate is electrically connected to the selection gate.

14. The method for forming a semiconductor structure according to claim 13, wherein: After forming the programming dielectric layer, the formation method further includes: forming a shared plug located on the selection gate exposed by the programming dielectric layer and the source and drain doped region of the control gate structure close to the selection gate side, wherein the shared plug electrically connects the selection gate and the source and drain doped region of the control gate structure close to the selection gate side.

15. The method for forming a semiconductor structure according to claim 14, wherein: Before forming the shared plug, the forming method further comprises: forming a metal silicide layer on the selection gate and the source-drain doped region exposed by the programming dielectric layer; In the step of forming the shared plug, the shared plug is connected to the metal silicide layer.

16. The method for forming a semiconductor structure according to claim 14, wherein: In the step of forming the shared plug, along a direction perpendicular to the sidewall of the selection gate, an overlapping width between the shared plug and the selection gate is at least 60 nanometers, and an overlapping width between the shared plug and the source and drain doping regions is at least 60 nanometers.

17. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming a programming dielectric layer on the top of the selection gate, the programming dielectric layer also extends to cover the side wall of the selection gate facing away from the control gate structure.

18. The method for forming a semiconductor structure according to any one of claims 13 to 17, wherein: The step of forming a programming dielectric layer on top of the selection gate includes: forming a metal silicide barrier layer covering the isolation structure, the control gate structure, the selection gate and the source and drain doping regions; The metal silicide barrier layer is patterned to retain a remaining metal silicide barrier layer on the top of the selection gate, wherein the remaining metal silicide barrier layer serves as a programming dielectric layer.

19. The method for forming a semiconductor structure according to any one of claims 13 to 17, wherein: The forming method further comprises: forming a source line plug on the programming dielectric layer, wherein the source line plug is connected to the programming dielectric layer.

20. The method for forming a semiconductor structure according to any one of claims 13 to 17, wherein: In the step of forming source-drain doped regions in the substrate on both sides of the control gate structure, the source-drain doped regions are also formed in the substrate on both sides of the selection gate, and the control gate structure and the selection gate share the source-drain doped regions.

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