Trim table optimization method, write command processing method and storage device

Abstract

The invention relates to a Trim table optimization method, a write command processing method and a storage device. In the embodiment of the invention, the mapping relation between the logical address LBA number and the bit is determined, and then the Trim table is constructed by utilizing the mapping relation, so that each item of the Trim table records the bit mapping of the continuous logical address LBA range, namely, a plurality of LBAs are mapped to the same bit, and compared with the bit mapping that each item of the existing Trim table records one LBA, the bit mapping of each item of the existing Trim table records one LBA, namely, the bit mapping of each item of the existing Trim table is more accurate. Different LBAs are mapped to different bits, the size of the Trim table is reduced, the Trim table can be directly stored in a power-down mode, extra recording and power-on recovery during operation are not needed, and therefore the recording and power-on recovery process during operation can be simplified.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of storage technology, and in particular to a Trim table optimization method, a write command processing method, and a storage device. Background Art

[0002] The Trim command is also called the Dataset Management command in the Non-Volatile Memory express (NVMe) specification. Its function is to inform the Solid State Disk (SSD) in advance which data is invalid, so that the SSD can perceive and perform garbage collection (GC) in advance to minimize the impact of background commands on the host's read and write commands. The Trim command is a command to deallocate data, that is, to delete or erase data. The L2P table is a mapping table with continuous addresses stored in the SSD memory, which is used to represent the mapping relationship between the logical address (Logical Block Address, LBA) and the physical address (Physical Block Address, PBA). The host accesses the data on the SSD through the L2P table. As the capacity of the SSD increases, the L2P table also increases. The DDR size occupied by the L2P table is about 1 / 1000 of the SSD capacity. For example, the L2P table size in a 1T solid-state drive is 1G. When the SSD receives a large-scale Trim command from the Host, directly adjusting the L2P table consumes a huge amount of time and DDR bandwidth, thus affecting the performance of Host IO (Input Output).

[0003] In order to reduce the impact on Host IO performance, a Trim table is added in the prior art to represent bit (BIT) mapping of a logical address (LBA), that is, each LBA corresponds to a BIT. Figure 1 This is a schematic diagram of a Trim table. Each item in the Trim table records the BIT mapping of an LBA. The BIT is 1 or 0. A BIT of 1 indicates that the corresponding LBA is the LBA to be processed by the Trim command; a BIT of 0 indicates that the LBA space has been allocated. The size of the Trim table is 1 / 32 of the L2P table. In the processing of a large range of Trim commands, the BIT corresponding to the LBA to be processed by the Trim command can be directly set to 1, indicating that the LBA corresponding to the BIT is the LBA to be processed by the Trim command, so as to reduce DDR access and the performance impact on Host IO. When the LBA is rewritten by the Host, the Bit corresponding to the LBA needs to be cleared.

[0004] However, the Trim table takes up a lot of DDR space. For example, in a 4T SSD, the Trim table takes up about 100MiB of space. And since hundreds of megabytes of data cannot be directly flushed to the NAND flash memory when the power is off, the Trim table cannot be saved directly when the power is off, and additional runtime recording and power-on recovery are required. Summary of the invention

[0005] At least one embodiment of the present disclosure provides a Trim table optimization method, a write command processing method and a storage device to solve the problem that the Trim table cannot be directly saved when power is off and requires additional runtime recording and power-on recovery.

[0006] In a first aspect, an embodiment of the present disclosure provides a Trim table optimization method, the method comprising:

[0007] Determine the mapping relationship between the number of logical address LBAs and the bit position, where multiple LBAs are mapped to one bit position;

[0008] A Trim table is constructed, where each entry of the Trim table records a bit mapping of a continuous logical address LBA range, wherein the number of LBAs corresponding to the continuous logical address LBA range is the number of LBAs indicated by the mapping relationship.

[0009] In some embodiments, determining the mapping relationship between the number of logical address LBAs and the bit position includes:

[0010] Based on the maximum amount of data saved after power failure, the mapping relationship between the number of logical address LBAs and the bit position is determined.

[0011] In some embodiments, based on the maximum amount of data saved when power is off, determining the mapping relationship between the number of logical address LBAs and the bit position includes:

[0012] Determine the maximum number of logical addresses LBA corresponding to the maximum amount of data saved when power is off;

[0013] A mapping relationship between the number of logical address LBAs and the bit position is determined, and the number of logical address LBAs indicated in the mapping relationship is greater than or equal to the maximum number of logical address LBAs.

[0014] In a second aspect, an embodiment of the present disclosure provides a method for processing a Trim command, the method comprising:

[0015] Determine the starting LBA and length in the Trim command;

[0016] Based on the continuous LBA range, the starting LBA and the length of each item record in the Trim table, the LBA range to be processed by the Trim command is divided into a plurality of sub-ranges;

[0017] For each sub-range, modify the LBA mapping corresponding to the sub-range in the L2P table to an invalid value or modify the bit mapping corresponding to the sub-range in the Trim table to 1.

[0018] In some embodiments, based on the continuous LBA range, the starting LBA and the length of each entry record in the Trim table, the LBA range to be processed by the Trim command is divided into a plurality of sub-ranges, including:

[0019] Based on the starting LBA and the length, determine the LBA range to be processed by the Trim command;

[0020] Based on the continuous LBA range of each item record in the Trim table, the LBA range to be processed by the Trim command is divided into a first non-aligned range, an aligned range, and a second non-aligned range.

[0021] In some embodiments, for each sub-range, modifying the LBA mapping corresponding to the sub-range in the L2P table to an invalid value or modifying the bit mapping corresponding to the sub-range in the Trim table to 1 includes:

[0022] For the first non-aligned range, modify the LBA mapping corresponding to the first non-aligned range in the L2P table to an invalid value;

[0023] Alternatively, for the alignment range, modify the bit mapping corresponding to the alignment range in the Trim table to 1;

[0024] Alternatively, for the second non-aligned range, the LBA mapping corresponding to the second non-aligned range in the L2P table is modified to an invalid value.

[0025] In a third aspect, an embodiment of the present disclosure provides a method for processing a read command, wherein the method is applied to SSD firmware, and includes:

[0026] The SSD firmware receives the read command sent by the host;

[0027] The SSD firmware sends a Trim table query instruction to the SSD hardware. The Trim table query instruction carries the LBA in the read command.

[0028] The SSD firmware receives the bit mapping of the LBA sent by the SSD hardware in the Trim table;

[0029] The SSD firmware determines the return data based on the bit map and sends the return data to the host.

[0030] In some embodiments, the SSD firmware determines the return data based on the bitmap, including:

[0031] If the bitmap is 1, the SSD firmware determines that the returned data is invalid data;

[0032] If the bit map is not 1, the SSD firmware determines that the returned data is the actual data stored in the LBA in the read command.

[0033] In some embodiments, if the bitmap is not 1, the SSD firmware determines that the returned data is the actual data stored in the LBA in the read command, including:

[0034] If the bit mapping is not 1, the SSD firmware sends an L2P table query instruction to the SSD hardware, and the L2P table query instruction carries the LBA in the read command; the SSD firmware receives the PBA corresponding to the LBA sent by the SSD hardware; the SSD firmware obtains the actual data stored in the LBA in the read command from the PBA.

[0035] In a fourth aspect, an embodiment of the present disclosure provides a method for processing a read command, wherein the method is applied to SSD hardware, and the method includes:

[0036] The SSD hardware receives the Trim table query instruction sent by the SSD firmware, and the Trim table query instruction carries the LBA in the read command;

[0037] The SSD hardware queries the Trim table for the bit mapping corresponding to the LBA in the read command;

[0038] The SSD hardware sends the SSD firmware a bit map of the LBA in the read command corresponding to the Trim table.

[0039] In some embodiments, the method for processing a read command further includes:

[0040] The SSD hardware receives the L2P table query instruction sent by the SSD firmware, and the L2P table query instruction carries the LBA in the read command;

[0041] The SSD hardware looks up the PBA corresponding to the LBA in the read command in the L2P table;

[0042] The SSD hardware sends the PBA corresponding to the LBA in the read command to the SSD firmware.

[0043] In a fifth aspect, an embodiment of the present disclosure provides a method for processing a write command, wherein the method is applied to SSD firmware, and the method includes:

[0044] The SSD firmware receives the write command sent by the host;

[0045] The SSD firmware sends a Trim table query instruction to the SSD hardware. The Trim table query instruction carries the LBA in the write command.

[0046] The SSD firmware receives the bit mapping of the LBA sent by the SSD hardware in the Trim table;

[0047] The SSD firmware starts the preset write process based on the bit map or starts the preset write process after modifying the L2P table and the Trim table.

[0048] In some embodiments, the SSD firmware starts a preset write process based on the bit map or starts a preset write process after modifying the L2P table and the Trim table, including:

[0049] If the bitmap is not 1, the SSD firmware starts the preset write process;

[0050] Alternatively, if the bit map is 1, the SSD firmware determines all LBAs corresponding to the bit map; the SSD firmware instructs the SSD hardware to asynchronously modify the L2P table and the Trim table; and the SSD firmware starts a preset write process after receiving a modification completion indication sent by the SSD hardware.

[0051] In some embodiments, the SSD firmware instructs the SSD hardware to asynchronously modify the L2P table and the Trim table, including:

[0052] The SSD firmware sends a modification instruction to the SSD hardware, and the modification instruction carries all LBAs and bit maps corresponding to the bit map.

[0053] In some embodiments, a bit mapping table corresponding to the Trim table is maintained in the SSD firmware, wherein multiple bits in the Trim table correspond to a bit in the bit mapping table; after the SSD firmware receives the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware, the method for processing the write command further includes:

[0054] If the bitmap is 1, the SSD firmware queries the bitmap table for the bit corresponding to the bitmap;

[0055] If the bit corresponding to the bitmap is 0, the SSD firmware sets the bit corresponding to the bitmap in the bitmap table to 1;

[0056] After the SSD firmware receives the modification completion indication sent by the SSD hardware, the SSD firmware sets the corresponding bit of the bit mapping in the bit mapping table to 0.

[0057] In some embodiments, after the SSD firmware searches the bit mapping table for the bit corresponding to the bit mapping, the method for processing the write command further includes:

[0058] If the bit corresponding to the bit map is 1, the SSD firmware sends a Trim table query instruction to the SSD hardware, and the Trim table query instruction carries the LBA in the write command;

[0059] The SSD firmware receives a second bit map corresponding to the LBA sent by the SSD hardware;

[0060] If the second bitmap is 1, the SSD firmware searches the bitmap table for the bit corresponding to the second bitmap;

[0061] If the bit corresponding to the second bit mapping is 1, the SSD firmware sends the Trim table query instruction to the SSD hardware again; if the bit corresponding to the second bit mapping is 0, the SSD firmware sets the bit corresponding to the second bit mapping in the bit mapping table to 1, and after the SSD firmware receives the modification completion indication sent by the SSD hardware, the SSD firmware sets the bit corresponding to the second bit mapping in the bit mapping table to 0.

[0062] In some embodiments, the bit mapping table is a Trim Hash table, and M bits in the Trim table correspond to one bit in the Trim Hash table.

[0063] In a sixth aspect, an embodiment of the present disclosure provides a method for processing a write command, wherein the method is applied to SSD hardware, and the method includes:

[0064] The SSD hardware receives the Trim table query instruction sent by the SSD firmware, and the Trim table query instruction carries the LBA in the write command;

[0065] The SSD hardware queries the Trim table for the bit mapping corresponding to the LBA in the write command;

[0066] The SSD hardware sends the SSD firmware a bit map of the LBA in the write command corresponding to the Trim table.

[0067] In some embodiments, the method for processing a write command further includes:

[0068] The SSD hardware receives a modification instruction sent by the SSD firmware, where the modification instruction carries all LBAs and bit maps corresponding to the bit map;

[0069] The SSD hardware modifies the PBAs corresponding to all LBAs corresponding to the bitmap in the L2P table to invalid values, and modifies the bitmap to 0 in the Trim table;

[0070] The SSD hardware sends a modification completion indication to the SSD firmware.

[0071] In a seventh aspect, an embodiment of the present disclosure provides a Trim table optimization device, the device comprising:

[0072] A determination unit, used to determine a mapping relationship between the number of logical address LBAs and bits, where the mapping relationship is that multiple LBAs are mapped to one bit;

[0073] The construction unit is used to construct a Trim table, each entry of the Trim table records a bit mapping of a continuous logical address LBA range, wherein the number of LBAs corresponding to the continuous logical address LBA range is the number of LBAs indicated by the mapping relationship.

[0074] In an eighth aspect, an embodiment of the present disclosure provides a Trim command processing device, the device comprising:

[0075] A determination unit, used to determine the starting LBA and length in the Trim command;

[0076] A division unit, for dividing the LBA range to be processed by the Trim command into a plurality of sub-ranges based on the continuous LBA range, the starting LBA and the length of each item record in the Trim table;

[0077] The modification unit is used to modify the LBA mapping corresponding to the sub-range in the L2P table to an invalid value or modify the bit mapping corresponding to the sub-range in the Trim table to 1 for each sub-range.

[0078] In a ninth aspect, an embodiment of the present disclosure provides a read command processing device, which is applied to SSD firmware, and includes:

[0079] A first receiving unit, used for receiving a read command sent by a host;

[0080] A sending unit, used to send a Trim table query instruction to the SSD hardware, where the Trim table query instruction carries the LBA in the read command;

[0081] The second receiving unit is used to receive the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware;

[0082] The determination unit is used to determine the return data based on the bit map and send the return data to the host.

[0083] In a tenth aspect, an embodiment of the present disclosure provides a read command processing device, which is applied to SSD hardware, and includes:

[0084] A receiving unit, used for receiving a Trim table query instruction sent by the SSD firmware, where the Trim table query instruction carries the LBA in the read command;

[0085] A query unit, used to query the Trim table for a bit mapping corresponding to the LBA in the read command in the Trim table;

[0086] The sending unit is used to send the bit mapping corresponding to the LBA in the Trim table in the read command to the SSD firmware.

[0087] In an eleventh aspect, an embodiment of the present disclosure provides a write command processing device, which is applied to SSD firmware, and includes:

[0088] A first receiving unit, used for receiving a write command sent by a host;

[0089] A sending unit, used to send a Trim table query instruction to the SSD hardware, where the Trim table query instruction carries the LBA in the write command;

[0090] The second receiving unit is used to receive the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware;

[0091] The start unit is used to start the preset write process based on the bit map or to start the preset write process after modifying the L2P table and the Trim table.

[0092] In a twelfth aspect, an embodiment of the present disclosure provides a write command processing device, which is applied to SSD hardware, and includes:

[0093] A receiving unit, used for receiving a Trim table query instruction sent by the SSD firmware, where the Trim table query instruction carries the LBA in the write command;

[0094] A query unit, used to query the Trim table for a bit mapping corresponding to the LBA in the write command;

[0095] The sending unit is used to send the bit mapping corresponding to the LBA in the Trim table in the write command to the SSD firmware.

[0096] In the thirteenth aspect, the embodiment of the present disclosure further proposes a storage device, which includes: a control component and an NVM chip, the control component executes the steps of any Trim table optimization method according to the first aspect or the steps of any Trim command processing method according to the second aspect.

[0097] In the fourteenth aspect, the embodiment of the present disclosure also proposes a storage device, which includes: a control component and an NVM chip, the control component includes SSD firmware and SSD hardware; the SSD firmware executes the steps of the processing method of any read command in the third aspect or the steps of the processing method of any write command in the fifth aspect; the SSD hardware executes the steps of the processing method of any read command in the fourth aspect or the steps of the processing method of any write command in the sixth aspect.

[0098] In the fifteenth aspect, an embodiment of the present disclosure also proposes an electronic device, which includes a memory, a processor, and a computer program stored on the memory, wherein the processor executes the computer program to implement the steps of any Trim table optimization method in the first aspect or the steps of any Trim command processing method in the second aspect or the steps of any read command processing method in the third aspect or the steps of any write command processing method in the fifth aspect or the steps of any read command processing method in the fourth aspect or the steps of any write command processing method in the sixth aspect.

[0099] In the sixteenth aspect, the embodiment of the present disclosure also proposes a computer-readable storage medium, wherein the computer-readable storage medium stores a program or instruction, and the program or instruction enables the computer to execute the steps of any Trim table optimization method in the first aspect, or the steps of any Trim command processing method in the second aspect, or the steps of any read command processing method in the third aspect, or the steps of any write command processing method in the fifth aspect, or the steps of any read command processing method in the fourth aspect, or the steps of any write command processing method in the sixth aspect.

[0100] In the seventeenth aspect, the embodiments of the present disclosure also provide a computer program product, wherein the computer program product includes a computer program, the computer program is stored in a computer-readable storage medium, at least one processor of a computer reads and executes the computer program from the computer-readable storage medium, so that the computer executes the steps of any Trim table optimization method of the first aspect or the steps of any Trim command processing method of the second aspect or the steps of any read command processing method of the third aspect or the steps of any write command processing method of the fifth aspect or the steps of any read command processing method of the fourth aspect or the steps of any write command processing method of the sixth aspect.

[0101] It can be seen that in at least one embodiment of the present disclosure, by determining the mapping relationship between the number of logical address LBAs and the bit positions, and then using the mapping relationship to construct a Trim table, each item in the Trim table records the bit mapping of a continuous logical address LBA range, that is, multiple LBAs are mapped to the same bit position. Compared with the existing Trim table in which each item records the bit mapping of one LBA, that is, different LBAs are mapped to different bit positions, this embodiment reduces the size of the Trim table, so that the Trim table can be directly saved when power is off, without the need for additional runtime recording and power-on recovery, thereby simplifying the runtime recording and power-on recovery process. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and a person skilled in the art can also obtain other drawings based on these drawings.

[0103] Figure 1 A schematic diagram of a Trim table;

[0104] Figure 2 A flow chart of a Trim table optimization method provided in an embodiment of the present disclosure;

[0105] Figure 3 A schematic diagram of a mapping relationship between an L2P table and a Trim table provided in an embodiment of the present disclosure;

[0106] Figure 4 A flow chart of a method for processing a Trim command provided in an embodiment of the present disclosure;

[0107] Figure 5 An operation diagram of a Trim command provided in an embodiment of the present disclosure;

[0108] Figure 6 A schematic diagram of a processing flow when a host read command hits a Trim logical address provided by an embodiment of the present disclosure;

[0109] Figure 7 A schematic diagram of a processing flow when a host write command hits a Trim logical address provided by an embodiment of the present disclosure;

[0110] Figure 8 A method for processing a read command provided in an embodiment of the present disclosure;

[0111] Fig. 9 A method for processing a read command provided in an embodiment of the present disclosure;

[0112] Fig.10 A method for processing a write command provided in an embodiment of the present disclosure;

[0113] Fig.11 A method for processing a write command provided in an embodiment of the present disclosure;

[0114] Fig.12 A schematic diagram of a process of asynchronous hardware acceleration provided by an embodiment of the present disclosure;

[0115] Fig.13 A schematic diagram of a mapping relationship between a Trim table and a Trim Hash table provided in an embodiment of the present disclosure;

[0116] Fig.14 A schematic diagram of a process of asynchronous hardware acceleration based on Trim Hash table provided in an embodiment of the present disclosure;

[0117] Fig.15 A schematic diagram of a Trim table optimization device provided in an embodiment of the present disclosure;

[0118] Fig.16 A schematic diagram of a Trim command processing device provided in an embodiment of the present disclosure;

[0119] Fig.17 A schematic diagram of a read command processing device provided in an embodiment of the present disclosure;

[0120] Fig.18 A schematic diagram of a read command processing device provided in an embodiment of the present disclosure;

[0121] Fig.19 A schematic diagram of a write command processing device provided in an embodiment of the present disclosure;

[0122] Fig. 20 A schematic diagram of a write command processing device provided in an embodiment of the present disclosure;

[0123] Fig.21 An exemplary block diagram of an electronic device provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0124] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0125] In the relevant embodiments of the present disclosure, when the host reads a certain LBA, the SSD needs to first check the BIT corresponding to the LBA in the Trim table. If the BIT is 1, the SSD returns all 0 data to the host; if the BIT is 0, the SSD checks the L2P table to obtain the physical address (PBA) corresponding to the LBA, and then reads the actual data stored in the PBA and returns the actual data to the host. In other words, only one LBA corresponds to one BIT, which requires a large storage space of the Trim table, which is not easy to save and restore after a power failure.

[0126] Figure 2A flow chart of a Trim table optimization method provided for an embodiment of the present disclosure is provided, wherein the executor of the Trim table optimization method is an electronic device, and the electronic device includes but is not limited to storage devices (such as solid-state drives SSDs, flash memory devices, etc.), smart phones, PDAs, tablet computers, wearable devices with display screens, desktop computers, laptop computers, all-in-one machines, smart home devices, servers, etc., wherein the server can be an independent server or a cluster of multiple servers, including servers built locally and servers set up in the cloud.

[0127] like Figure 2 As shown, the Trim table optimization method includes step 201 and step 202:

[0128] In step 201, a mapping relationship between the number of logical addresses LBA and bits is determined.

[0129] The mapping relationship is that multiple LBAs are mapped to one bit.

[0130] In step 202, a Trim table is constructed, and each entry of the Trim table records the bit mapping of a continuous logical address LBA range, wherein the number of LBAs corresponding to the continuous logical address LBA range is the number of LBAs indicated by the mapping relationship.

[0131] In this embodiment, the mapping relationship between the number of logical address LBAs and the bit positions is determined, and then the mapping relationship is used to construct a Trim table, so that each item in the Trim table records the bit mapping of a continuous logical address LBA range, that is, multiple LBAs are mapped to the same bit position. Compared with the existing Trim table in which each item records the bit mapping of one LBA, that is, different LBAs are mapped to different bit positions, this embodiment reduces the size of the Trim table. Since the data volume of the optimized Trim table is small enough, the Trim table can be directly saved when the power is off, without the need for additional runtime recording and power-on recovery, thereby simplifying the runtime recording and power-on recovery process.

[0132] In some embodiments, determining the mapping relationship between the number of logical address LBAs and the bit positions in step 201 includes: determining the mapping relationship between the number of logical address LBAs and the bit positions based on the maximum amount of data that can be saved upon power failure.

[0133] In this embodiment, since the mapping relationship between the number of LBAs and the bit positions determines the size of the Trim table constructed in step 202, in order to enable the size of the Trim table constructed in step 202 to be directly saved when power is off, this embodiment determines the mapping relationship between the number of LBAs and the bit positions based on the maximum amount of data that can be saved when power is off.

[0134] In some embodiments, based on the maximum amount of data saved when power is off, determining the mapping relationship between the number of logical address LBAs and the bit position includes the following steps 1 and 2:

[0135] Step 1: Determine the maximum number of logical addresses LBA corresponding to the maximum amount of data saved when power is off.

[0136] Step 2: Determine a mapping relationship between the number of logical address LBAs and the bit position, where the number of logical address LBAs indicated in the mapping relationship is greater than or equal to the maximum number of logical address LBAs.

[0137] For example, the maximum number of LBAs corresponding to the maximum amount of data saved when power is off is N, and the mapping relationship between the number of LBAs and the bit position is determined as N LBAs mapping to the same bit position. Figure 3 A schematic diagram of a mapping relationship between an L2P table and a Trim table provided in an embodiment of the present disclosure. Figure 3 In the example, N LBAs in the L2P table are mapped to the same bit in the Trim table, and the size of the Trim table is reduced to 1 / N of the existing Trim table size. When N=1024, the size of the Trim table can be reduced to 1 / 1024 of the existing Trim table size. Not only does it save DDR space, but this size can also be directly flushed to NAND when power is off, simplifying the recording and power-on recovery process during operation.

[0138] Figure 4 The present invention provides a flow chart of a method for processing a Trim command, wherein the execution subject of the method is an electronic device, and the electronic device includes a storage device (such as a solid state drive SSD, a flash memory device, etc.). Figure 4 As shown, the processing method of the Trim command includes but is not limited to steps 401 to 403:

[0139] In step 401, the starting LBA and length in the Trim command are determined.

[0140] In step 402, based on the continuous LBA range, the starting LBA and the length of each entry record in the Trim table, the LBA range to be processed by the Trim command is divided into a plurality of sub-ranges.

[0141] In step 403, for each sub-range, the LBA mapping corresponding to the sub-range in the L2P table is modified to an invalid value or the bit mapping corresponding to the sub-range in the Trim table is modified to 1.

[0142] In this embodiment, after receiving the Trim command sent by the host, the SSD firmware checks the starting LBA and length (LEN) in the Trim command, and can determine the LBA range to be processed by the Trim command based on the starting LBA and length, and then divide the LBA range to be processed by the Trim command into multiple sub-ranges. For each sub-range, modify the L2P table or the Trim table.

[0143] In some embodiments, step 402 divides the LBA range to be processed by the Trim command into multiple sub-ranges based on the continuous LBA range, the starting LBA and the length of each item record in the Trim table, including the following steps 1 and 2:

[0144] Step 1: Based on the starting LBA and length, determine the LBA range to be processed by the Trim command.

[0145] Step 2: Based on the continuous LBA range of each item record in the Trim table, the LBA range to be processed by the Trim command is divided into a first non-aligned range, an aligned range and a second non-aligned range.

[0146] For example, Figure 5 A schematic diagram of the operation of a Trim command provided in an embodiment of the present disclosure, in Figure 5 In the example, the LBA range to be processed by the Trim command is LBA1 to LBA 2N+1. The N LBAs in the L2P table are mapped to the same bit in the Trim table. The Trim table is as follows: Figure 3 As shown, therefore, the LBA range to be processed by the Trim command is divided into a first non-aligned range (i.e., a head non-aligned range), an aligned range (i.e., an LBA range corresponding to a certain bit in the Trim table) and a second non-aligned range (i.e., a tail non-aligned range). Among them, the head non-aligned range is LBA1 to LBA N-1, the aligned range is LBA N to LBA 2N-1, and the tail non-aligned range is LBA 2N and LBA 2N+1.

[0147] In some embodiments, in step 403, for each sub-range, modifying the LBA mapping corresponding to the sub-range in the L2P table to an invalid value or modifying the bit mapping corresponding to the sub-range in the Trim table to 1 includes:

[0148] For the first unaligned range, modify the LBA mapping corresponding to the first unaligned range in the L2P table to an invalid value; or, for the aligned range, modify the bit mapping corresponding to the aligned range in the Trim table to 1; or, for the second unaligned range, modify the LBA mapping corresponding to the second unaligned range in the L2P table to an invalid value.

[0149] For example, in Figure 5In the example, the first non-aligned range (that is, the head non-aligned range) is LBA1 to LBAN-1, and the LBA mapping corresponding to the first non-aligned range in the L2P table is modified to an invalid value, for example, the value in a specific DDR address is modified directly by the CPU or by hardware asynchronously. The second non-aligned range (that is, the tail non-aligned range) is LBA 2N and LBA 2N+1, and the LBA mapping corresponding to the second non-aligned range in the L2P table is modified to an invalid value, for example, the value in a specific DDR address is modified directly by the CPU or by hardware asynchronously. The alignment range is LBA N to LBA 2N-1, and the bit mapping corresponding to the alignment range in the Trim table is modified to 1, indicating that the LBA corresponding to the alignment range is subjected to a Trim operation (that is, the data stored in the LBA is deallocated).

[0150] Figure 6 A schematic diagram of a processing flow when a host read command hits a Trimmed logical address is provided in an embodiment of the present disclosure, and the execution subject of the processing flow is a solid state drive SSD. Figure 6 In the Trim table, each bit corresponds to N LBAs. The host reads LBA X; after receiving the read command, the SSD determines LBA X in the read command, and then checks whether the bit mapping corresponding to LBA X in the Trim table (i.e., Bit X / N, where X / N means X is rounded to N, and each bit in the Trim table corresponds to N LBAs) is 1; if it is 1, it means that LBA X is Trim, and the SSD directly returns invalid data (such as all-zero data) to the host; if it is not 1, it means that LBA X has been assigned a PBA, and the SSD searches for the PBA corresponding to LBA X in the L2P table, and then obtains the actual data from the PBA and returns the actual data to the host.

[0151] Figure 7 A schematic diagram of a processing flow when a host write command hits a Trim logical address provided by an embodiment of the present disclosure, wherein the execution subject of the processing flow is a solid state drive SSD. Figure 7In the Trim table, each bit corresponds to N LBAs. The host writes LBA X; after receiving the write command, the SSD determines the LBA X in the write command, and then checks whether the bit mapping corresponding to LBA X in the Trim table (i.e., Bit X / N, where X / N represents X rounded to N, and each bit in the Trim table corresponds to N LBAs) is 1; if it is not 1, it means that LBA X has been assigned a PBA, and the SSD starts the preset write process, which is the existing write process and will not be described in detail; if it is 1, it means that LBA X is Trim, and the SSD first determines all LBAs corresponding to the bit mapping corresponding to LBA X (i.e., Bit X / N), and then modifies the PBAs corresponding to all LBAs corresponding to Bit X / N in the L2P table to invalid values ​​(INVALID), and then modifies BitX / N in the Trim table to 0, and then starts the preset write process.

[0152] exist Figure 7 In the method of SSD directly accessing DDR through CPU, the following operations need to be performed in sequence: check the bit mapping corresponding to LBA X in the Trim table, modify the LBA mapping of all LBAs corresponding to Bit X / N in the L2P table to invalid values, and modify Bit X / N in the Trim table to 0. However, when N becomes larger, the time for CPU to operate DDR will also be longer, thus affecting the write operation of LBA that does not belong to Bit X / N and increasing the delay of the write operation.

[0153] Figure 8 A method for processing a read command is provided in an embodiment of the present disclosure. The method is applied to SSD firmware. In this embodiment, the solid state drive SSD includes SSD firmware and SSD hardware, wherein the SSD hardware is a hardware module in the SSD controller. Figure 8 As shown, the processing method of the read command includes but is not limited to steps 801 to 804:

[0154] In step 801, the SSD firmware receives a read command sent by a host.

[0155] In step 802, the SSD firmware sends a Trim table query instruction to the SSD hardware, and the Trim table query instruction carries the LBA in the read command.

[0156] In step 803, the SSD firmware receives the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware.

[0157] In step 804, the SSD firmware determines the return data based on the bit map and sends the return data to the host.

[0158] In this embodiment, the SSD firmware and SSD hardware inside the SSD cooperate with each other. When the SSD firmware receives a read command, it sends a Trim table query instruction to the SSD hardware, and the SSD hardware executes the Trim table query operation, while the SSD firmware can receive the next read command without waiting for feedback from the SSD hardware, thereby realizing asynchronous processing of read commands inside the SSD, increasing the concurrency of the SSD in processing read commands, and reducing read operation delays.

[0159] In some embodiments, in step 804, the SSD firmware determines the return data based on the bit map, including steps (1) and (2):

[0160] Step (1): If the bit mapping is 1, the SSD firmware determines that the returned data is invalid data.

[0161] In this embodiment, the SSD firmware determines that the LBA in the read command is Trim based on the bit mapping being 1, and the SSD firmware directly returns invalid data (eg, all-zero data) to the host.

[0162] Step (2): If the bit mapping is not 1, the SSD firmware determines that the returned data is the actual data stored in the LBA in the read command.

[0163] In this embodiment, the SSD firmware determines that the LBA in the read command has been assigned a PBA based on the bit mapping not being 1, and the SSD firmware returns the actual data stored in the LBA in the read command as return data to the host.

[0164] In some embodiments, if the bit mapping is not 1 in step (2), the SSD firmware determines that the returned data is the actual data stored in the LBA in the read command, including:

[0165] If the bit mapping is not 1, the SSD firmware sends an L2P table query instruction to the SSD hardware, and the L2P table query instruction carries the LBA in the read command; the SSD firmware receives the PBA corresponding to the LBA sent by the SSD hardware; the SSD firmware obtains the actual data stored in the LBA in the read command from the PBA.

[0166] Fig. 9 A method for processing a read command is provided in an embodiment of the present disclosure. The method is applied to SSD hardware. In this embodiment, the solid state drive SSD includes SSD firmware and SSD hardware. Fig. 9 As shown, the processing method of the read command includes but is not limited to steps 901 to 903:

[0167] In step 901, the SSD hardware receives a Trim table query instruction sent by the SSD firmware, where the Trim table query instruction carries the LBA in the read command.

[0168] In step 902, the SSD hardware searches the Trim table for a bit map corresponding to the LBA in the read command.

[0169] In step 903, the SSD hardware sends the bit mapping corresponding to the LBA in the read command in the Trim table to the SSD firmware.

[0170] In this embodiment, the Trim table query instruction is an instruction generated by the SSD firmware after receiving the read command sent by the host. After the SSD hardware receives the Trim table query instruction sent by the SSD firmware, it queries the Trim table for the bit mapping corresponding to the LBA in the read command in the Trim table, wherein if the bit mapping is 1, it means that the LBA in the read command is Trim; if the bit mapping is not 1, it means that the LBA in the read command has been assigned a PBA. The SSD hardware sends the bit mapping corresponding to the LBA in the read command in the Trim table to the SSD firmware, so that the SSD firmware determines the return data to be returned to the host based on the bit mapping. Asynchronous processing of read commands is realized within the SSD, the concurrency of the SSD in processing read commands is increased, and the delay of read operations is reduced.

[0171] In some embodiments, the SSD hardware receives an L2P table query instruction sent by the SSD firmware, the L2P table query instruction carries the LBA in the read command; the SSD hardware searches the L2P table for a PBA corresponding to the LBA in the read command; the SSD hardware sends the PBA corresponding to the LBA in the read command to the SSD firmware.

[0172] In this embodiment, the L2P table query instruction is an instruction generated by the SSD firmware based on the fact that the bit mapping of the LBA in the read command is not 1 (indicating that the LBA has been assigned a PBA). After the SSD hardware receives the L2P table query instruction sent by the SSD firmware, it queries the PBA corresponding to the LBA in the read command in the L2P table, and then sends the PBA corresponding to the LBA in the read command to the SSD firmware, so that the SSD firmware obtains the actual data from the PBA and returns the actual data to the host. Asynchronous processing of read commands is realized within the SSD, the concurrency of the SSD processing read commands is increased, and the delay of read operations is reduced.

[0173] Fig.10 A method for processing a write command provided in an embodiment of the present disclosure is applied to SSD firmware. In this embodiment, the solid state drive SSD includes SSD firmware and SSD hardware. Fig.10 As shown, the processing method of the write command includes but is not limited to steps 1001 to 1004:

[0174] In step 1001, the SSD firmware receives a write command sent by a host.

[0175] In step 1002, the SSD firmware sends a Trim table query instruction to the SSD hardware, and the Trim table query instruction carries the LBA in the write command.

[0176] In step 1003, the SSD firmware receives the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware.

[0177] In step 1004, the SSD firmware starts the preset write process based on the bit map or starts the preset write process after modifying the L2P table and the Trim table.

[0178] In this embodiment, the SSD firmware and SSD hardware inside the SSD cooperate with each other. When the SSD firmware receives a write command, it sends a Trim table query instruction to the SSD hardware, and the SSD hardware executes the Trim table query operation. In addition, the SSD hardware completes the modification operations of the L2P table and the Trim table, and the SSD firmware can receive the next write command without waiting for feedback from the SSD hardware, thereby realizing asynchronous processing of write commands inside the SSD, increasing the concurrency of the SSD in processing write commands, and reducing write operation delays.

[0179] In some embodiments, in step 1004, the SSD firmware starts the preset write process based on the bit map or starts the preset write process after modifying the L2P table and the Trim table, including step (1) and step (2):

[0180] Step (1): If the bit mapping is not 1, the SSD firmware starts the preset write process.

[0181] In this embodiment, the SSD firmware determines that the LBA in the write command has been allocated with a PBA based on the bit mapping not being 1, and the SSD firmware directly starts the preset write process.

[0182] Step (2), if the bit mapping is 1, the SSD firmware determines all LBAs corresponding to the bit mapping; the SSD firmware instructs the SSD hardware to asynchronously modify the L2P table and the Trim table; the SSD firmware starts the preset write process after receiving the modification completion indication sent by the SSD hardware.

[0183] The SSD firmware instructs the SSD hardware to asynchronously modify the L2P table and the Trim table, including: the SSD firmware sends a modification instruction to the SSD hardware, and the modification instruction carries all LBAs and bit maps corresponding to the bit map.

[0184] In this embodiment, the SSD firmware determines that the LBA in the write command is Trim based on the bit mapping being 1. The SSD firmware first determines the bit mapping corresponding to the LBA in the write command in the Trim table (for example, Figure 7 All LBAs corresponding to Bit X / N in Figure 7The SSD firmware starts the preset write process after the SSD hardware completes the modification of the L2P table and the Trim table.

[0185] Fig.11 A method for processing a write command is provided in an embodiment of the present disclosure. The method is applied to SSD hardware. In this embodiment, the solid state drive SSD includes SSD firmware and SSD hardware, such as Fig.11 As shown, the method for processing the write command includes but is not limited to steps 1101 to 1103:

[0186] In step 1101, the SSD hardware receives a Trim table query instruction sent by the SSD firmware, where the Trim table query instruction carries the LBA in the write command.

[0187] In step 1102, the SSD hardware searches the Trim table for a bit map corresponding to the LBA in the write command.

[0188] In step 1103, the SSD hardware sends the bit mapping corresponding to the LBA in the write command in the Trim table to the SSD firmware.

[0189] In this embodiment, the Trim table query instruction is an instruction generated by the SSD firmware after receiving the write command sent by the host. After the SSD hardware receives the Trim table query instruction sent by the SSD firmware, it queries the Trim table for the bit mapping corresponding to the LBA in the write command in the Trim table, wherein if the bit mapping is 1, it indicates that the LBA in the write command is Trim; if the bit mapping is not 1, it indicates that the LBA in the write command has been assigned a PBA. The SSD hardware sends the bit mapping corresponding to the LBA in the write command in the Trim table to the SSD firmware, so that the SSD firmware starts the preset write process based on the bit mapping or starts the preset write process after modifying the L2P table and the Trim table. Asynchronous processing of write commands is realized within the SSD, the concurrency of the SSD in processing write commands is increased, and the delay of write operations is reduced.

[0190] In some embodiments, the SSD hardware receives a modification instruction sent by the SSD firmware, the modification instruction carries all LBAs and bit maps corresponding to the bit map; the SSD hardware modifies the PBAs corresponding to all LBAs corresponding to the bit map in the L2P table to invalid values, and modifies the bit map to 0 in the Trim table; the SSD hardware sends a modification completion indication to the SSD firmware.

[0191] In this embodiment, the modification instruction is an instruction generated by the SSD firmware based on the bit mapping of the LBA in the write command being 1 (indicating that the LBA is Trim). After the SSD hardware receives the modification instruction sent by the SSD firmware, it changes the bit mapping (for example Figure 7 All LBAs corresponding to Bit X / N in Figure 7 The corresponding PBA in the L2P table is modified to an invalid value (INVALID), and then Bit X / N in the Trim table is modified to 0, and a modification completion indication is sent to the SSD firmware. After the SSD firmware receives the modification completion indication sent by the SSD hardware, it starts the preset write process. Asynchronous processing of write commands is realized in the SSD, the concurrency of the SSD processing write commands is increased, and the read operation delay is reduced.

[0192] based on Fig.10 and Fig.11 The processing method of the write command disclosed in the related embodiment, Fig.12 A schematic diagram of a process flow of asynchronous hardware acceleration provided by an embodiment of the present disclosure, in Fig.12 In the write command processing flow, the following steps 1 to 8 are included:

[0193] 1. When the host writes: LBA X, the SSD firmware receives the write command sent by the host and sends a read command to the SSD hardware to read Bit X / N in the Trim table, that is, sends a Trim table query instruction to the SSD hardware;

[0194] 2. After the SSD hardware receives the Trim table query instruction, the SSD hardware queries the Trim table for the bit mapping (i.e., Bit X / N) corresponding to the LBA in the write command in the Trim table. That is, the SSD hardware reads Bit X / N in the Trim table and returns the obtained Bit X / N to the SSD firmware;

[0195] 3. The SSD firmware determines whether the Trim Bit (i.e., bit mapping) is 1. If it is 1, it goes to step 4; if it is not 1, it starts the preset write process;

[0196] 4. The SSD firmware sends a modification instruction to the SSD hardware. The modification instruction carries all LBAs and bit mappings corresponding to the Trim Bit (that is, the bit mapping). That is, the SSD firmware initiates a modification to the SSD hardware to modify the L2P table mapping corresponding to the Trim Bit (that is, all LBAs corresponding to the Trim Bit) to an invalid value, and modifies the Trim Bit to 0 in the Trim table.

[0197] 5. After receiving the modification instruction, the SSD hardware will modify all LBAs (such as Figure 7 The corresponding PBA in the L2P table is modified to an invalid value (INVALID), and then Bit X / N in the Trim table is modified to 0;

[0198] 6. The SSD hardware sends a CPL message to the SSD firmware to notify the SSD firmware that the modification is completed, wherein the CPL message is a message in which the target device sends a completion indication to the source device after the source device (i.e., the SSD firmware in this embodiment) sends an IO request (i.e., a modification instruction) to the target device (i.e., the SSD hardware in this embodiment);

[0199] 7. The SSD firmware receives a modification completion indication (i.e., a CPL message) from the SSD hardware and determines that both the Trim table and the L2P table have been modified;

[0200] 8. The SSD firmware starts the preset write process.

[0201] In summary, this method maps N logical addresses LBA to one bit, which can reduce the size of the Trim table and solve the problem of DDR and power-off recovery during power-off. By setting the L2P table mapping to an invalid value during the write process and clearing the record in the Trim table, as asynchronous concurrent processing, delays can be avoided.

[0202] However, using Fig.12 The asynchronous method shown may cause a problem: Assuming that LBAX and LBAX+1 correspond to the same bit mapping in the Trim table (i.e., Bit X / N), when the SSD firmware sends the Trim table query instruction of LBAX and the Trim table query instruction of LBAX+1 to the SSD hardware successively, the SSD firmware may receive BitX / N as 1 at the same time, indicating that LBAX and LBAX+1 are Trim. At this time, the SSD firmware will send two modification instructions to the SSD hardware. Not only will it cause a waste of bandwidth, but it may also cause the write during the period to be overwritten by Trim, causing silent errors. Silent Data Corruption refers to the storage system providing corrupted data to the application without issuing any warning. For example, due to media damage, a bad block appears in the disk. When the application reads the block, it will read erroneous data.

[0203] In order to solve the silent error, in some embodiments, a bit mapping table corresponding to the Trim table is maintained in the SSD firmware, wherein multiple bits in the Trim table correspond to one bit in the bit mapping table. For example, the bit mapping table corresponding to the Trim table is a Trim Hash table, and M bits in the Trim table correspond to one bit in the Trim Hash table. The Trim Hash table can be constructed by storing the value obtained by taking the modulus of the bit in the Trim table to M in the Trim Hash table, such as Fig.13 The specific calculation formula is as follows:

[0204] Trim_Hash_BitIdx=Trim_Bit_Idx%M

[0205] Among them, Trim_Hash_BitIdx represents the bit index in the Trim Hash table, Trim_Bit_Idx represents the bit index in the Trim table, % is the modulus operator, and M is a positive integer.

[0206] It can be seen that since the size of the Trim Hash table is 1 / M of the Trim table size, M can be adjusted so that the Trim Hash table can be stored in the SRAM of the SSD firmware to speed up the access efficiency of the Trim Hash table.

[0207] In some embodiments, after the SSD firmware receives the bit mapping corresponding to the LBA of the write command sent by the SSD hardware in the Trim table, if the bit mapping is 1, indicating that the LBA of the write command is Trim, the SSD firmware Fig.13 The SSD firmware queries the Trim Hash table in the bit mapping for the bit corresponding to the bit mapping; if the bit corresponding to the bit mapping is 0 (that is, the value of the bit is 0, but the index of the non-bit is 0), the SSD firmware sets the bit corresponding to the bit mapping in the bit mapping table to 1; after the SSD firmware receives the modification completion indication sent by the SSD hardware, the SSD firmware sets the bit corresponding to the bit mapping in the bit mapping table to 0.

[0208] In some embodiments, the SSD firmware specifies a bitmap table (e.g. Fig.13After querying the bit corresponding to the bit mapping in the Trim Hash table in the SSD, if the bit corresponding to the bit mapping is 1, the SSD firmware sends a Trim table query instruction to the SSD hardware, and the Trim table query instruction carries the LBA in the write command; the SSD firmware receives the second bit mapping corresponding to the LBA sent by the SSD hardware; if the second bit mapping is 1, the SSD firmware queries the bit corresponding to the second bit mapping in the bit mapping table; if the bit corresponding to the second bit mapping is 1, the SSD firmware sends the Trim table query instruction to the SSD hardware again; if the bit corresponding to the second bit mapping is 0, the SSD firmware sets the bit corresponding to the second bit mapping in the bit mapping table to 1, and after the SSD firmware receives the modification completion indication sent by the SSD hardware, the SSD firmware sets the bit corresponding to the second bit mapping in the bit mapping table to 0.

[0209] In some embodiments, the bit mapping table is a Trim Hash table, and M bits in the Trim table correspond to one bit in the Trim Hash table.

[0210] It can be seen that in this embodiment, when the SSD firmware receives a write command for a certain LBA, if it is found that the bit mapping corresponding to the LBA in the Trim table is 1 and the bit mapping corresponding to the Trim Hash table (recorded as Trim Hash Bit) is 1, it means that the SSD hardware is currently executing the modification instructions corresponding to other LBAs, and there is no need to send the modification instructions again. Therefore, the SSD firmware sends the Trim table query instruction at a preset time interval until the Trim Hash Bit of the aforementioned LBA is 0, indicating that the modification instructions corresponding to other LBAs have been executed. Then, the SSD firmware sends the modification instruction for the aforementioned LBA to the SSD hardware. Avoid silent errors, ensure that the bits in the Trim table (recorded as Trim Bit) will not be modified repeatedly, and maintain sufficient concurrency.

[0211] exist Fig.12 On the basis of Fig.14 A schematic diagram of a process of asynchronous hardware acceleration based on Trim Hash table provided in an embodiment of the present disclosure. Fig.14 As shown, the write command processing flow includes steps 1 to 11:

[0212] 1. When the host writes: LBA X, the SSD firmware receives the write command sent by the host and sends a read instruction to the SSD hardware to read Bit X / N in the Trim table, that is, to send a Trim table query instruction to the SSD hardware;

[0213] 2. After the SSD hardware receives the Trim table query instruction, the SSD hardware queries the Trim table for the bit mapping (i.e., Bit X / N) corresponding to the LBA in the write command in the Trim table. That is, the SSD hardware reads Bit X / N in the Trim table and returns the obtained Bit X / N to the SSD firmware;

[0214] 3. The SSD firmware determines whether the Trim Bit (i.e., bit mapping) is 1. If it is 1, it goes to step 4; if it is not 1, it starts the preset write process;

[0215] 4. The SSD firmware determines whether the bit corresponding to the Trim Bit in the Trim Hash table (recorded as Trim Hash Bit) is 1; if it is 1, go to step 1; if not 1, go to step 5;

[0216] 5. SSD firmware changes Trim Hash Bit to 1;

[0217] 6. The SSD firmware sends a modification instruction to the SSD hardware. The modification instruction carries all LBAs and bit mappings corresponding to the Trim Bit (that is, the bit mapping). That is, the SSD firmware initiates a modification to the SSD hardware to modify the L2P table mapping corresponding to the Trim Bit (that is, all LBAs corresponding to the Trim Bit) to an invalid value, and modifies the Trim Bit to 0 in the Trim table.

[0218] 7. After receiving the modification instruction, the SSD hardware will modify all LBAs (such as Figure 7 The corresponding PBA in the L2P table is modified to an invalid value (INVALID), and then Bit X / N in the Trim table is modified to 0;

[0219] 8. The SSD hardware sends a CPL message to the SSD firmware to notify the SSD firmware that the modification is completed. The CPL message is a message in which the target device sends a completion indication to the source device after the source device (i.e., the SSD firmware in this embodiment) sends an IO request (i.e., a modification instruction) to the target device (i.e., the SSD hardware in this embodiment);

[0220] 9. The SSD firmware receives a modification completion indication (i.e., CPL message) from the SSD hardware and determines that both the Trim table and the L2P table have been modified;

[0221] 10. SSD firmware changes Trim Hash Bit to 0;

[0222] 11. The SSD firmware starts the preset write process.

[0223] In summary, this method maps N logical addresses LBA to one bit, which can reduce the size of the Trim table and solve the problem of DDR and power-off recovery during power-off. By setting the L2P table mapping to an invalid value during the write process and clearing the record in the Trim table, as asynchronous concurrent processing, delays can be avoided. It can further solve the timing problem caused by asynchronous modification of the Trim table, reduce silent errors, and maintain sufficient concurrency.

[0224] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all described as a series of action combinations, but those skilled in the art can understand that the embodiments of the present disclosure are not limited by the described action sequence, because according to the embodiments of the present disclosure, some steps can be performed in other sequences or simultaneously. In addition, those skilled in the art can understand that the embodiments described in the specification are all optional embodiments.

[0225] Fig.15 Schematic diagram of a Trim table optimization device provided in an embodiment of the present disclosure. The Trim table optimization device can execute the processing flow provided in each embodiment of the Trim table optimization method, such as Fig.15 As shown, the Trim table optimization device includes but is not limited to: a determination unit 1501 and a construction unit 1502. The functions of each unit are described as follows:

[0226] The determining unit 1501 is used to determine the mapping relationship between the number of logical address LBAs and bits, where the mapping relationship is that multiple LBAs are mapped to one bit;

[0227] The construction unit 1502 is used to construct a Trim table, each entry of the Trim table records a bit mapping of a continuous logical address LBA range, wherein the number of LBAs corresponding to the continuous logical address LBA range is the number of LBAs indicated by the mapping relationship.

[0228] In some embodiments, the determination unit 1501 is used to determine the mapping relationship between the number of logical address LBAs and the bit positions based on the maximum amount of data saved when power is off.

[0229] In some embodiments, the determining unit 1501 is configured to:

[0230] Determine the maximum number of logical addresses LBA corresponding to the maximum amount of data saved when power is off;

[0231] A mapping relationship between the number of logical address LBAs and the bit position is determined, and the number of logical address LBAs indicated in the mapping relationship is greater than or equal to the maximum number of logical address LBAs.

[0232] Fig.16Schematic diagram of a Trim command processing device provided in an embodiment of the present disclosure. The Trim command processing device can execute the processing flow provided in each embodiment of the Trim command processing method, such as Fig.16 As shown, the processing device of the Trim command includes but is not limited to: a determination unit 1601, a division unit 1602 and a modification unit 1603. The functions of each unit are described as follows:

[0233] Determining unit 1601, used to determine the starting LBA and length in the Trim command;

[0234] A division unit 1602 is used to divide the LBA range to be processed by the Trim command into multiple sub-ranges based on the continuous LBA range, the starting LBA and the length of each item record in the Trim table;

[0235] The modifying unit 1603 is used to modify the LBA mapping corresponding to the sub-range in the L2P table to an invalid value or modify the bit mapping corresponding to the sub-range in the Trim table to 1 for each sub-range.

[0236] In some embodiments, the partitioning unit 1602 is used to:

[0237] Based on the starting LBA and the length, determine the LBA range to be processed by the Trim command;

[0238] Based on the continuous LBA range of each item record in the Trim table, the LBA range to be processed by the Trim command is divided into a first non-aligned range, an aligned range, and a second non-aligned range.

[0239] In some embodiments, the modifying unit 1603 is used to:

[0240] For the first non-aligned range, modify the LBA mapping corresponding to the first non-aligned range in the L2P table to an invalid value;

[0241] Alternatively, for the alignment range, modify the bit mapping corresponding to the alignment range in the Trim table to 1;

[0242] Alternatively, for the second non-aligned range, the LBA mapping corresponding to the second non-aligned range in the L2P table is modified to an invalid value.

[0243] Fig.17 Schematic diagram of a read command processing device provided in an embodiment of the present disclosure, the read command processing device is applied to SSD firmware, such as Fig.17 As shown, the read command processing device includes: a first receiving unit 1701, a sending unit 1702, a second receiving unit 1703 and a determining unit 1704. The functions of each unit are described as follows:

[0244] The first receiving unit 1701 is used to receive a read command sent by a host;

[0245] The sending unit 1702 is used to send a Trim table query instruction to the SSD hardware, where the Trim table query instruction carries the LBA in the read command;

[0246] The second receiving unit 1703 is used to receive the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware;

[0247] The determination unit 1704 is configured to determine the return data based on the bit map, and send the return data to the host.

[0248] In some embodiments, the determining unit 1704 determines the return data based on the bit map, including:

[0249] If the bit map is 1, the returned data is determined to be invalid data;

[0250] If the bit map is not 1, it is determined that the returned data is the actual data stored in the LBA in the read command.

[0251] In some embodiments, the determining unit 1704 determines that the returned data is the actual data stored in the LBA in the read command, including:

[0252] Send an L2P table query instruction to the SSD hardware, the L2P table query instruction carrying the LBA in the read command; receive the PBA corresponding to the LBA sent by the SSD hardware; and obtain the actual data stored in the LBA in the read command from the PBA.

[0253] Fig.18 Schematic diagram of a read command processing device provided in an embodiment of the present disclosure, the read command processing device is applied to SSD hardware, such as Fig.18 As shown, the read command processing device includes: a receiving unit 1801, a query unit 1802 and a sending unit 1803. The functions of each unit are described as follows:

[0254] The receiving unit 1801 is used to receive a Trim table query instruction sent by the SSD firmware, where the Trim table query instruction carries the LBA in the read command;

[0255] A query unit 1802 is used to query the Trim table for a bit mapping corresponding to the LBA in the read command in the Trim table;

[0256] The sending unit 1803 is used to send the bit mapping corresponding to the LBA in the Trim table in the read command to the SSD firmware.

[0257] In some embodiments, the receiving unit 1801 is further configured to receive an L2P table query instruction sent by the SSD firmware, where the L2P table query instruction carries the LBA in the read command;

[0258] The query unit 1802 is also used to search the PBA corresponding to the LBA in the read command in the L2P table;

[0259] The sending unit 1803 is further configured to send the PBA corresponding to the LBA in the read command to the SSD firmware.

[0260] Fig.19 Schematic diagram of a write command processing device provided in an embodiment of the present disclosure, the write command processing device is applied to SSD firmware, such as Fig.19 As shown, the write command processing device includes: a first receiving unit 1901, a sending unit 1902, a second receiving unit 1903 and a starting unit 1904. The functions of each unit are described as follows:

[0261] The first receiving unit 1901 is used to receive a write command sent by a host;

[0262] A sending unit 1902 is used to send a Trim table query instruction to the SSD hardware, where the Trim table query instruction carries the LBA in the write command;

[0263] The second receiving unit 1903 is used to receive the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware;

[0264] The starting unit 1904 is used to start the preset write process based on the bit map or start the preset write process after modifying the L2P table and the Trim table.

[0265] In some embodiments, the startup unit 1904 is used to:

[0266] If the bitmap is not 1, the preset write process is started;

[0267] Alternatively, if the bit mapping is 1, all LBAs corresponding to the bit mapping are determined; a modification instruction is sent to the SSD hardware, the modification instruction carries all LBAs and bit mappings corresponding to the bit mapping; and the preset write process is started after receiving the modification completion indication sent by the SSD hardware.

[0268] In some embodiments, a bit mapping table corresponding to the Trim table is maintained in the SSD firmware, wherein a plurality of bits in the Trim table correspond to a bit in the bit mapping table; and the write command processing device further comprises:

[0269] The processing unit is configured to query the bit corresponding to the bit mapping in the bit mapping table after the second receiving unit 1903 receives the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware, if the bit mapping is 1; if the bit corresponding to the bit mapping is 0, the SSD firmware sets the bit corresponding to the bit mapping in the bit mapping table to 1;

[0270] The processing unit is further configured to set the corresponding bit in the bit mapping table to 0 after the starting unit 1904 receives the modification completion indication sent by the SSD hardware.

[0271] In some embodiments, the processing unit is also used to query the bit corresponding to the bit mapping in the bit mapping table, and if the bit corresponding to the bit mapping is 1, send a Trim table query instruction to the SSD hardware, the Trim table query instruction carries the LBA in the write command; receive a second bit mapping corresponding to the LBA sent by the SSD hardware; if the second bit mapping is 1, query the bit corresponding to the second bit mapping in the bit mapping table; if the bit corresponding to the second bit mapping is 1, send the Trim table query instruction to the SSD hardware again; if the bit corresponding to the second bit mapping is 0, set the corresponding bit of the second bit mapping in the bit mapping table to 1, and after the start unit 1904 receives the modification completion indication sent by the SSD hardware, the processing unit sets the corresponding bit of the second bit mapping in the bit mapping table to 0.

[0272] In some embodiments, the bit mapping table is a Trim Hash table, and M bits in the Trim table correspond to one bit in the Trim Hash table.

[0273] Fig. 20 Schematic diagram of a write command processing device provided in an embodiment of the present disclosure, the write command processing device is applied to SSD hardware, such as Fig. 20 As shown, the write command processing device includes: a receiving unit 2001, a query unit 2002 and a sending unit 2003. The functions of each unit are described as follows:

[0274] The receiving unit 2001 is used to receive a Trim table query instruction sent by the SSD firmware, where the Trim table query instruction carries the LBA in the write command;

[0275] A query unit 2002 is used to query the Trim table for a bit mapping corresponding to the LBA in the write command in the Trim table;

[0276] The sending unit 2003 is used to send the bit mapping corresponding to the LBA in the Trim table in the write command to the SSD firmware.

[0277] In some embodiments, the receiving unit 2001 is further used to receive a modification instruction sent by the SSD firmware, where the modification instruction carries all LBAs and bit maps corresponding to the bit map;

[0278] The write command processing device further includes a modification unit, which is used to modify the PBAs corresponding to all LBAs corresponding to the bit mapping in the L2P table to invalid values, and to modify the bit mapping to 0 in the Trim table;

[0279] The sending unit 2003 is further configured to send a modification completion indication to the SSD firmware.

[0280] For details of the apparatus disclosed in the above embodiments, reference may be made to the corresponding method embodiments, and will not be described again to avoid repetition.

[0281] In an embodiment of the present disclosure, a storage device (or solid-state storage device, etc.) is provided, including: a control component and an NVM (Non-Volatile Memory) chip, and the control component executes the steps of the Trim table optimization method or the steps of the Trim command processing method in any of the above method embodiments.

[0282] In an embodiment of the present disclosure, a storage device (or solid-state storage device, etc.) is provided, including: a control component and an NVM chip, the control component includes SSD firmware and SSD hardware; the SSD firmware executes the steps of the read command processing method or the steps of the write command processing method in any of the above method embodiments in which the SSD firmware is the execution subject; the SSD hardware executes the steps of the read command processing method or the steps of the write command processing method in any of the above method embodiments in which the SSD hardware is the execution subject.

[0283] Fig.21 is an exemplary block diagram of an electronic device provided by an embodiment of the present disclosure. Fig.21 As shown, the electronic device includes: a memory 2101, a processor 2102, and a computer program stored in the memory 2101. It can be understood that the memory 2101 in this embodiment can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories.

[0284] In some embodiments, the memory 2101 stores the following elements, executable modules or data structures, or a subset thereof, or an extended set thereof: an operating system and application programs.

[0285] Among them, the operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., which are used to implement various basic tasks and process hardware-based tasks. The application program includes various application programs, such as a media player (Media Player), a browser (Browser), etc., which are used to implement various application tasks. The program that implements the steps of the Trim table optimization method or the steps of the Trim command processing method or the steps of the read command processing method or the steps of the write command processing method provided in the embodiment of the present disclosure can be included in the application program.

[0286] In the embodiment of the present disclosure, at least one processor 2102 calls a program or instruction stored in at least one memory 2101, specifically, a program or instruction stored in an application program, and at least one processor 2102 is used to execute the steps of the Trim table optimization method or the steps of the Trim command processing method or the steps of the read command processing method or the steps of the write command processing method provided in the embodiment of the present disclosure.

[0287] The steps of the Trim table optimization method or the steps of the Trim command processing method or the steps of the read command processing method or the steps of the write command processing method provided in the embodiment of the present disclosure can be applied to the processor 2102, or implemented by the processor 2102. The processor 2102 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 2102 or an instruction in the form of software. The above-mentioned processor 2102 can be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0288] The steps of the Trim table optimization method or the steps of the Trim command processing method or the steps of the read command processing method or the steps of the write command processing method provided in the embodiment of the present disclosure can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 2101, and the processor 2102 reads the information in the memory 2101 and completes the steps of the method in combination with its hardware.

[0289] The disclosed embodiment also proposes a computer-readable storage medium, wherein the computer-readable storage medium stores a program or instruction, wherein the program or instruction enables a computer to execute the steps of a Trim table optimization method or a Trim command processing method or a read command processing method or a write command processing method, which will not be described here in order to avoid repeated description. The computer-readable storage medium may be a non-transitory computer-readable storage medium.

[0290] The embodiment of the present disclosure also proposes a computer program product, which includes a computer program, which is stored in a computer-readable storage medium, and the computer-readable storage medium may be a non-transitory computer-readable storage medium. At least one processor of a computer reads and executes the computer program from the computer-readable storage medium, so that the computer executes the steps of the Trim table optimization method or the steps of the Trim command processing method or the steps of the read command processing method or the steps of the write command processing method. To avoid repeated description, it will not be repeated here.

[0291] The above-described device or equipment embodiments are merely illustrative, wherein the unit modules described as separate components may or may not be physically separated, and the components displayed as module units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0292] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution can be essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute various embodiments or certain parts of the embodiments.

[0293] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A Trim table optimization method, the method comprising: Determine a mapping relationship between the number of logical address LBAs and bits, where multiple LBAs are mapped to one bit; A Trim table is constructed, wherein each entry of the Trim table records a bit mapping of a continuous logical address LBA range, wherein the number of LBAs corresponding to the continuous logical address LBA range is the number of LBAs indicated by the mapping relationship.

2. The method according to claim 1, wherein: The determining of the mapping relationship between the number of logical address LBAs and the bit position includes: Based on the maximum amount of data saved after power failure, the mapping relationship between the number of logical address LBAs and the bit position is determined.

3. The method according to claim 2, wherein: The determining of the mapping relationship between the number of logical address LBAs and the bit positions based on the maximum amount of data saved upon power failure includes: Determine the maximum number of logical addresses LBA corresponding to the maximum amount of data saved when power is off; A mapping relationship between the number of logical address LBAs and the bit position is determined, wherein the number of logical address LBAs indicated in the mapping relationship is greater than or equal to the maximum number of the logical address LBAs.

4. A method for processing a Trim command, processing a Trim command based on the Trim table according to any one of claims 1 to 3, the method comprising: Determine the starting LBA and length in the Trim command; Based on the continuous LBA range, the starting LBA and the length of each item record in the Trim table, the LBA range to be processed by the Trim command is divided into a plurality of sub-ranges; For each of the sub-ranges, the LBA mapping corresponding to the sub-range in the L2P table is modified to an invalid value or the bit mapping corresponding to the sub-range in the Trim table is modified to 1.

5. The method according to claim 4, wherein: The LBA range to be processed by the Trim command is divided into a plurality of sub-ranges based on the continuous LBA range of each item record in the Trim table, the starting LBA and the length, including: Based on the starting LBA and the length, determining the LBA range to be processed by the Trim command; Based on the continuous LBA range of each item record in the Trim table, the LBA range to be processed by the Trim command is divided into a first non-aligned range, an aligned range, and a second non-aligned range.

6. The method according to claim 5, wherein: The step of modifying, for each of the sub-ranges, the LBA mapping corresponding to the sub-range in the L2P table to an invalid value or modifying the bit mapping corresponding to the sub-range in the Trim table to 1 includes: For the first non-aligned range, modify the LBA mapping corresponding to the first non-aligned range in the L2P table to an invalid value; Alternatively, for the alignment range, modify the bit mapping corresponding to the alignment range in the Trim table to 1; Alternatively, for the second non-aligned range, modify the LBA mapping corresponding to the second non-aligned range in the L2P table to an invalid value.

7. A method for processing a read command, wherein: Applied to SSD firmware, processing a read command based on the Trim table according to any one of claims 1 to 3, the method comprising: The SSD firmware receives a read command sent by the host; The SSD firmware sends a Trim table query instruction to the SSD hardware, wherein the Trim table query instruction carries the LBA in the read command; The SSD firmware receives the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware; The SSD firmware determines return data based on the bit map and sends the return data to the host.

8. A method for processing a read command, wherein: Applied to SSD hardware, the method for processing a read command based on the Trim table according to any one of claims 1 to 3 comprises: The SSD hardware receives a Trim table query instruction sent by the SSD firmware, where the Trim table query instruction carries the LBA in the read command; The SSD hardware queries the Trim table for a bit mapping corresponding to the LBA in the read command in the Trim table; The SSD hardware sends a bit map corresponding to the LBA in the read command in the Trim table to the SSD firmware.

9. A method for processing a write command, wherein: Applied to SSD firmware, the method for processing a write command based on the Trim table according to any one of claims 1 to 3 comprises: The SSD firmware receives a write command sent by the host; The SSD firmware sends a Trim table query instruction to the SSD hardware, where the Trim table query instruction carries the LBA in the write command; The SSD firmware receives the bit mapping corresponding to the LBA in the Trim table sent by the SSD hardware; The SSD firmware starts a preset write process based on the bit map or starts a preset write process after modifying the L2P table and the Trim table.

10. A storage device, wherein: include: A control component and an NVM chip, wherein the control component executes the steps of the Trim table optimization method according to any one of claims 1 to 3 or the steps of the Trim command processing method according to any one of claims 4 to 6.

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