Chip and hardware error repair system
By setting up interfaces and input signal switching units in the chip function module, and using hardware repair networks for signal repair, the problem of hardware errors found in integrated circuits after chipping is solved, and the normal operation and cost saving of the chip are achieved.
Patent Information
- Application Number
- CN202411260517.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-01-03
AI Technical Summary
In integrated circuit design, hardware errors are often found in the post-disc phase as design complexity increases, resulting in chip designers facing limited solutions, firmware or software cannot avoid hardware errors, resulting in the need to modify the light mask to reflow again films, causing high additional costs.
Design a chip hardware error repair system, by setting the first interface and the second interface in the functional module, using the hardware repair network for signal transmission and repair, avoiding the need for adjustment of firmware or software, and allowing occurrence in key functional modules Repair when hardware errors are not required to redistribute.
The normal operation of the chip is achieved, avoiding the modification of the firmware or software process and lighting mask by greatly adjusting the firmware or software process and lighting mask, significantly saving costs, and improving the reliability and repair efficiency of the chip.
Smart Images
Figure CN119250006A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a chip and hardware error repair system. Background Art
[0002] In the integrated circuit design process, most hardware errors can be discovered and repaired through mature verification methods. However, as the design complexity increases, the test space and test complexity also increase greatly, which leads to some hardware errors being discovered only in the sample test stage after tape-out, or even after mass production and large-scale use. When hardware errors are discovered in the post-tapeout stage, the solutions left for chip designers are often very limited. One way is to rely on firmware or software processes to avoid triggering hardware errors, but often firmware or software processes cannot avoid the hardware errors. Under the premise that the firmware and software cannot avoid the hardware errors, designers need to analyze and make trade-offs to decide whether to shut down the module with the hardware error. If the hardware error occurs in a key functional module that cannot be shut down, and the firmware or software process cannot avoid triggering the hardware error, the chip design company often needs to work with the chip manufacturing factory to modify the light mask to varying degrees for re-tapeout, but this method requires millions or even tens of millions of additional expenses. Summary of the invention
[0003] The purpose of the embodiments of the present application is to provide a chip and hardware error repair system to solve the above problems.
[0004] An embodiment of the present application provides a chip, which includes: a functional module and a first on-chip network; the functional module includes: a first interface, the output end of the first interface is connected to the first on-chip network, and is used to transmit the upstream and downstream module signals to the hardware repair network through the first on-chip network in an enabled state, so that the hardware repair network can perform signal repair; the upstream and downstream module signals include signals output by the upstream module of the functional module to the functional module, or signals fed back by the downstream module of the functional module to the functional module; a second interface, the input end of the second interface is connected to the first on-chip network, and is used to receive the repair signal transmitted from the hardware repair network through the first on-chip network in an enabled state; an input signal switching unit, the first input port of the input signal switching unit is respectively connected to the signal output end of the upstream module of the functional module and the signal feedback end of the downstream module of the functional module, the second input port of the input signal switching unit is connected to the output end of the second interface, and the output end of the input signal switching unit is connected to the internal functional circuit of the functional module.
[0005] In the above implementation scheme, by setting the first interface, the second interface and the input signal switching unit in the functional module of the chip, when there is a hardware error in the functional module, the first interface can be used to transmit the upstream and downstream module signals of the functional module to the hardware repair network outside the chip for processing, and the second interface can be used to receive the repair signal of the hardware repair network so that the functional module related to the functional module with the hardware error can obtain the correct repair signal after repair, thereby ensuring the normal use of the chip. Compared with relying on firmware or software processes to avoid triggering hardware errors, this scheme no longer requires a significant adjustment of the firmware or software process. Under the premise that the firmware and software cannot avoid the hardware error, since it is allowed to use the hardware repair network outside the chip for repair, the designer does not need to decide whether to shut down the functional module with the hardware error. At the same time, because it is also allowed to use the hardware repair network outside the chip for repair, even if the hardware error occurs in a key functional module that cannot be shut down, and the firmware or software process cannot avoid triggering the hardware error, it is not necessary to modify the light mask for re-stripping, which can save costs to a great extent.
[0006] Furthermore, the second interface is also used to receive upstream and downstream module signals from the hardware repair network through the first on-chip network in an enabled state; the internal functional circuit includes a data trigger, and the data trigger is used to transmit data backward according to the timing of the internal functional circuit; the second interface is configured to: when there is a hardware error in the functional module, send the repair signal to the corresponding data trigger; the input signal switching unit is configured to: when there is no hardware error in the functional module, connect the first input port and the output end of the input signal switching unit; when there is a hardware error in the functional module, connect the second input port and the output end of the input signal switching unit to output the upstream and downstream module signals from the second interface to the internal functional circuit, so as to trigger the data trigger to transmit the received signal backward according to the timing of the internal functional circuit.
[0007] It can be understood that in any functional module, the transmission of its signal is through a data trigger (such as a D trigger) and is gradually transmitted to other functional modules with the clock beat. In the above implementation scheme, the second interface is configured to receive the upstream and downstream module signals transmitted from the hardware repair network through the first on-chip network in an enabled state, and the second interface is configured to send the repair signal to the corresponding data trigger when there is a hardware error in the functional module, and the input signal switching unit is configured to input the upstream and downstream module signals transmitted from the hardware repair network to the internal functional circuit when there is a hardware error in the functional module. In this way, since the upstream and downstream module signals and the repair signal input into the internal functional circuit are both transmitted from the hardware repair network, the upstream and downstream module signals and the repair signal input into the internal functional circuit can be synchronized in timing, so that the upstream and downstream module signals entering the internal functional circuit can trigger each data trigger normally according to the timing of the internal functional circuit, so that each data trigger can send the repair signal to the relevant functional module normally according to the timing of the internal functional circuit, so that the entire chip can operate normally, and the effect of repairing the functional module with hardware errors is achieved.
[0008] Furthermore, the functional module also includes a selector, and each data trigger corresponds to a selector; for any one of the data triggers: the data input port of the data trigger is connected to the output end of the corresponding selector; the first input end of the selector is connected to the output end of the preceding device of the data trigger in the internal functional circuit, and the second input end of the selector is connected to the second interface; wherein: the selector is configured to: when there is no hardware error in the functional module, connect the first input end of the selector to the data input port of the data trigger; when there is a hardware error in the functional module, connect the second input end of the selector to the data input port of the data trigger.
[0009] In the above implementation scheme, a selector is set for each data trigger, and one input end of the selector is connected to the output end of the previous device of the data trigger in the internal functional circuit, the other input end of the selector is connected to the second interface, the output end of the selector is connected to the data input port of the corresponding data trigger, and the selector is configured as follows: when there is no hardware error in the functional module, the first input end of the selector is connected to the data input port of the data trigger; when there is a hardware error in the functional module, the second input end of the selector is connected to the data input port of the data trigger. In this way, the control of whether the data required to be transmitted by the data trigger is a repair signal or a signal of the internal functional circuit can be realized by controlling the selector. When there is no hardware error in the functional module, the first input end of the selector is connected to the output end, so that the functional module works normally and outputs the signal generated by the normal operation of the internal functional circuit. When there is a hardware error in the functional module, the second input end of the selector is connected to the output end to realize the transmission of the repair signal, so that the chip works normally and the functional module is repaired.
[0010] Furthermore, the functional module also includes a selector, and each data trigger corresponds to a selector; for any one of the data triggers: the data input port of the data trigger is connected to the output end of the corresponding selector; the first input end of the selector is connected to the output end of the preceding device of the data trigger in the internal functional circuit, and the second input end of the selector is connected to the second interface; wherein: the selector is configured to: when there is no hardware error in the functional module, connect the first input end of the selector to the data input port of the data trigger; when there is a hardware error in the functional module and the data trigger connected to the selector belongs to the error circuit that causes the hardware error, connect the second input end of the selector to the data input port of the data trigger; when there is a hardware error in the functional module, but the data trigger connected to the selector does not belong to the error circuit that causes the hardware error, connect the first input end of the selector to the data input port of the data trigger.
[0011] In the above implementation scheme, a selector is set for each data trigger, and one input end of the selector is connected to the output end of the previous device of the data trigger in the internal functional circuit, the other input end of the selector is connected to the second interface, the output end of the selector is connected to the data input port of the corresponding data trigger, and the selector is configured as follows: when there is no hardware error in the functional module, the first input end of the selector is connected to the data input port of the data trigger; when there is a hardware error in the functional module and the data trigger connected to the selector belongs to the error circuit causing the hardware error, the second input end of the selector is connected to the data input port of the data trigger; when there is a hardware error in the functional module, but the data trigger connected to the selector does not belong to the error circuit causing the hardware error, the first input end of the selector is connected to the data input port of the data trigger. In this way, by controlling the selector, it is possible to control whether the data required to be transmitted by the data trigger is a repair signal or a signal of the internal functional circuit. When there is no hardware error in the functional module, the first input end of the selector is connected to the output end, so that the functional module works normally and outputs the signal generated by the normal operation of the internal functional circuit. In the case of a hardware error in a functional module, the first input and output ends of some selectors that do not belong to the error circuit that caused the hardware error are still turned on, while the second input and output ends of some selectors that belong to the error circuit that caused the hardware error are turned on. In this way, only the signal repair is performed on the error circuit that caused the hardware error, and the normal circuit that did not cause the hardware error can still output the correct signal normally. The transmission of the repair signal can also be achieved, so that the chip works normally and the functional module is repaired. And for the hardware repair network outside the chip, only the repair circuit of the error circuit can be configured, and the complexity of the repair circuit can be lower and the area can be smaller, which is conducive to reducing the area of the hardware repair network.
[0012] Furthermore, the first on-chip network is a network on chip dedicated to connecting the first interface, the second interface and the hardware repair network.
[0013] In the above implementation scheme, the signal interaction in the hardware error repair process is carried out by adopting an on-chip network dedicated to the first interface and the second interface connected to the hardware repair network. In this way, the signals that need to interact with the external hardware repair network will not interfere with the signals between normal functional modules in the chip, thereby improving the reliability of the repaired chip.
[0014] Furthermore, the chip further includes a first P2P interface, and the first on-chip network is connected to the hardware repair network via the first P2P interface.
[0015] In the above implementation scheme, a P2P interface is used to interact with the external hardware repair network, and a single P2P interface can reach a rate of tens of GByte / s or even hundreds of GByte / s. Therefore, the use of a P2P interface can better match the data bandwidth within the chip and meet the signal transmission requirements. At the same time, the protocol used by the P2P interface can be customized, which is also convenient for chip manufacturers to design and modify the upper-layer software of the chip, thereby facilitating the use of the chip after hardware repair.
[0016] Furthermore, each of the functional modules is assigned a unique identifier; the first on-chip network is configured to: upon receiving the upstream and downstream module signals transmitted from the first interface of any functional module, transmit the upstream and downstream module signals and the unique identifier of the functional module to the hardware repair network in order.
[0017] In the above implementation scheme, by assigning a unique identifier to each functional module, when transmitting the upstream and downstream module signals from the first interface of any functional module to the hardware repair network, the unique identifier of the functional module is transmitted together, so that the hardware repair network can accurately know which functional module's corresponding repair circuit the corresponding upstream and downstream module signals should be handed over to, thereby ensuring that the upstream and downstream module signals can be correctly processed. At the same time, by performing sequence-preserving transmission of the upstream and downstream module signals and the unique identifier of the functional module together, signal confusion during the transmission process can be avoided, and the reliability of the repair can be improved.
[0018] Furthermore, the first on-chip network is specifically configured as follows: upon receiving the upstream and downstream module signals transmitted from the first interface of any functional module, each piece of data in the upstream and downstream module signals is sequentially marked, and an end tag is marked on the last piece of data in the upstream and downstream module signals; and the marked upstream and downstream module signals and the unique identifier of the functional module are transmitted to the hardware repair network.
[0019] In the above implementation scheme, each data in the upstream and downstream module signals is marked in sequence, and the end tag is marked on the last data in the upstream and downstream module signals. In this way, after the hardware repair network receives each data, the upstream and downstream module signals can be accurately restored based on the tags, avoiding signal confusion during transmission and improving the reliability of repair.
[0020] An embodiment of the present application also provides a hardware error repair system, comprising: any one of the aforementioned chips; and a hardware repair network connected to a first on-chip network of the chip.
[0021] In the above implementation scheme, the hardware repair network is used to process the upstream and downstream module signals that need to be processed by the functional module with hardware errors in the chip. After obtaining the correct signal (i.e., the repair signal), it is transmitted back to the chip, which can realize the repair of the hardware error and ensure the normal use of the chip. Compared with relying on firmware or software processes to avoid triggering hardware errors, the system no longer needs to significantly adjust the firmware or software processes. Under the premise that the firmware and software cannot avoid the hardware error, since the off-chip hardware repair network is used for repair, the designer does not need to decide whether to shut down the functional module with the hardware error. At the same time, because the off-chip hardware repair network is used for repair, even if the hardware error occurs in a key functional module that cannot be shut down, and the firmware or software process cannot avoid triggering the hardware error, there is no need to modify the light mask for re-flow, which can save costs to a great extent.
[0022] Furthermore, the hardware repair network includes: a repair circuit for repairing a functional module with hardware errors in the chip; and a second on-chip network connected to the chip and the repair circuit, respectively.
[0023] Furthermore, the hardware repair network further includes a second P2P interface, and the second on-chip network is connected to the chip via the second P2P interface.
[0024] In the above implementation scheme, the P2P interface is used to interact with the chip, and a single P2P interface can reach a rate of tens of GByte / s or even hundreds of GByte / s. Therefore, the P2P interface can better match the internal data bandwidth of the chip and meet the signal transmission requirements. At the same time, the protocol used by the P2P interface can be customized, which is also convenient for chip manufacturers to design and modify the upper-layer software of the chip, thereby facilitating the subsequent use of the chip after hardware repair.
[0025] Furthermore, the second on-chip network is configured to: upon receiving the upstream and downstream module signals and the unique identifier transmitted from the chip, distribute the upstream and downstream module signals to the repair circuit corresponding to the unique identifier.
[0026] In the above implementation, through the configuration of the unique identifier, the hardware repair network can accurately know to which repair circuit the received upstream and downstream module signals should be handed over, thereby ensuring that the upstream and downstream module signals can be correctly processed.
[0027] Furthermore, the second on-chip network is specifically configured to: restore the upstream and downstream module signals according to the sequence of each received data; and distribute the upstream and downstream module signals to the repair circuit corresponding to the unique identifier.
[0028] In the above implementation scheme, the upstream and downstream module signals can be accurately restored based on the markings of each received data, thereby avoiding signal confusion during the transmission process and improving the reliability of repair.
[0029] Furthermore, the second on-chip network is configured to: upon receiving the upstream and downstream module signals and the repair signal from any repair circuit, transmit the upstream and downstream module signals, the repair signal and the unique identifier corresponding to the repair circuit to the chip in order.
[0030] In the above implementation scheme, when receiving the upstream and downstream module signals and the repair signal from any repair circuit, the upstream and downstream module signals, the repair signal and the unique identifier corresponding to the repair circuit are transmitted to the chip in order, so that the chip can accurately know which functional module the corresponding upstream and downstream module signals should be handed over to, thereby ensuring that the signal can be correctly received. At the same time, by transmitting the upstream and downstream module signals, the repair signal and the unique identifier of the functional module in order, signal confusion during the transmission process can be avoided, and the reliability of the repair can be improved.
[0031] Furthermore, the second on-chip network is specifically configured as follows: when receiving the upstream and downstream module signals and the repair signal transmitted by any repair circuit, each data in the upstream and downstream module signals and the repair signal is marked in sequence, and an end tag is marked on the last data in the upstream and downstream module signals and the repair signal; the marked upstream and downstream module signals, the repair signal and the unique identifier of the functional module are transmitted to the chip.
[0032] In the above implementation scheme, each data in the upstream and downstream module signals is marked in sequence, and an end tag is marked on the last data in the upstream and downstream module signals. In this way, after the chip receives each data, the upstream and downstream module signals can be accurately restored based on the tags, avoiding signal confusion during transmission and improving the reliability of repair. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0034] Figure 1 A schematic diagram of the structure of a chip provided in an embodiment of the present application;
[0035] Figure 2A basic structural diagram of a functional module provided in an embodiment of the present application;
[0036] Figure 3 A schematic diagram of a specific functional module provided in an embodiment of the present application;
[0037] Figure 4 A schematic diagram of the basic structure of a hardware error repair system provided in an embodiment of the present application;
[0038] Figure 5 A schematic diagram of the structure of a specific hardware error repair system provided in an embodiment of the present application;
[0039] Figure 6 A flowchart of a repair process provided in an embodiment of the present application. DETAILED DESCRIPTION
[0040] In order to be able to understand the features and technical contents of the embodiments of the present application in more detail, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0041] The terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.
[0042] Unless otherwise stated, the term "plurality" means two or more.
[0043] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.
[0044] A chip is provided in the embodiment of the present application, which can be seen in Figure 1 As shown, the chip includes multiple functional modules and a first on-chip network.
[0045] In the embodiments of the present application, a functional module refers to a collection of circuits in a chip that implement a certain function, such as a convolution operation circuit that implements a convolution operation, a multiplication operation circuit that implements a multiplication operation, and so on.
[0046] In the embodiments of the present application, Figure 2 As shown, each functional module may include a first interface, a second interface and an input signal switching unit.
[0047] The output end of the first interface is connected to the first on-chip network, and is used to transmit upstream and downstream module signals to the hardware repair network through the first on-chip network in an enabled state, so that the hardware repair network can perform signal repair.
[0048] The input end of the second interface is connected to the first on-chip network, and is used to receive the repair signal transmitted from the hardware repair network through the first on-chip network when in an enabled state.
[0049] An input signal switching unit, wherein the first input port of the input signal switching unit is respectively connected to the signal output end of the upstream module of the functional module and the signal feedback end of the downstream module of the functional module, the second input port of the input signal switching unit is connected to the output end of the second interface, and the output end of the input signal switching unit is connected to the internal functional circuit of the functional module.
[0050] It should be noted that, in the application embodiment, the upstream and downstream module signals include the signals output by the upstream module of the functional module to the functional module, or the signals fed back by the downstream module of the functional module to the functional module. In the application embodiment, the repair signal refers to the correct signal generated after the hardware repair network correctly processes the upstream and downstream module signals.
[0051] In a feasible implementation of the application embodiment, when the above chip has a hardware problem and needs to be connected to a hardware repair network for repair, the repair can be achieved in the following manner:
[0052] The input signal switching unit can be configured as follows: when there is no hardware error in the functional module to which the functional module is connected, the first input port and the output end of the input signal switching unit are connected; when there is a hardware error in the functional module to which the functional module is connected, the second input port and the output end of the input signal switching unit are connected; when there is a hardware error in the functional module itself, the connection between the input port and the output end is closed.
[0053] In this way, the function module with hardware errors can pass the upstream and downstream module signals to the hardware repair network for processing through the first interface, and the function module no longer processes the upstream and downstream module signals. The function module connected to the function module can conduct the second input port and the output end of the input signal switching unit when it needs to receive the signal from the function module, so as to receive the repair signal from the hardware repair network through the second interface. That is, the effect of replacing the function module with hardware errors with the hardware repair network is achieved, and the hardware errors are repaired.
[0054] Exemplarily, assuming that there is a hardware error in function module 0, the first interface of function module 0 is enabled to transmit the upstream and downstream module signals to the hardware repair network for processing, and the input signal switching unit of function module 0 is configured to no longer input the upstream and downstream module signals to the internal functional circuit of function module 0. Assuming that function module 1 is a function module connected to function module 0, the second interface of function module 1 can be controlled to be enabled, and the input signal switching unit of function module 1 can be configured to conduct the second input port with the output end of the input signal switching unit, and the repair signal obtained by the hardware repair network is input to the internal functional circuit of function module 1 for processing.
[0055] In another feasible implementation of the application embodiment, when the above chip has a hardware problem and needs to be connected to a hardware repair network for repair, it can also be repaired in the following way:
[0056] The second interface is also configured to receive upstream and downstream module signals from the hardware repair network through the first on-chip network in an enabled state. That is, the hardware repair network simultaneously feeds back upstream and downstream module signals and repair signals, and since both the upstream and downstream module signals and the repair signals are fed back by the hardware repair network, the upstream and downstream module signals and the repair signals are synchronized.
[0057] Because in any functional module, the signal is transmitted through a data trigger (such as a D trigger, but not limited to) and gradually transmitted to other functional modules with the clock beat. That is, for any functional module, its internal functional circuit (that is, the various logic circuits that implement specific functions) includes a data trigger, and the data trigger is used to transmit the data backward according to the timing of the internal functional circuit. Therefore, the second interface can also be configured as: in the case of a hardware error in the functional module, the repair signal is sent to the corresponding data trigger; the input signal switching unit is configured as: in the case of no hardware error in the functional module, the first input port and the output end of the input signal switching unit are connected; in the case of a hardware error in the functional module, the second input port and the output end of the input signal switching unit are connected, so as to output the upstream and downstream module signals transmitted from the second interface to the internal functional circuit, so as to trigger the data trigger according to the timing of the internal functional circuit to transmit the received signal backward.
[0058] For example, assuming that there is a hardware error in functional module 0, the first interface and the second interface of functional module 0 are started, and the input signal switching unit is configured to connect the second input port and the output end of the input signal switching unit (that is, connect the second interface of functional module 0 and the internal functional circuit). At this time, the upstream and downstream module signals synchronized with the repair signal enter the internal functional circuit and are executed according to the inherent logic of the internal functional circuit, thereby triggering the data trigger for data transmission according to the specified timing requirements, and then continuing to transmit the repair signal backward according to the specified timing, so as to transmit the correct signal to the downstream functional module or feedback to the upstream functional module, thereby realizing the repair of the hardware error.
[0059] In this feasible implementation mode, if Figure 3 As shown, the function module may also include a selector, and each data trigger corresponds to a selector. For any data trigger: the data input port of the data trigger is connected to the output end of the corresponding selector; the first input end of the selector is connected to the output end of the previous device of the data trigger in the internal function circuit, and the second input end of the selector is connected to the second interface.
[0060] In an exemplary embodiment, the selector can be configured to: when there is no hardware error in the functional module, connect the first input terminal of the selector to the data input port of the data trigger; when there is a hardware error in the functional module, connect the second input terminal of the selector to the data input port of the data trigger.
[0061] For example, Figure 3 The functional module shown has a hardware error, the first interface and the second interface of the functional module are started, the second interface and the internal functional circuit of the functional module are turned on, and the second input end of all selectors in the functional module is turned on with the data input port of the data trigger (that is, the repair signal is input to the data input port of the data trigger). When the upstream and downstream module signals synchronized with the repair signal enter the internal functional circuit, they are executed according to the inherent logic of the internal functional circuit, thereby triggering the data trigger according to the specified timing requirements, and the trigger transmits the repair signal that is about to be connected backward, and finally transmits the correct signal to the downstream functional module or feeds back to the upstream functional module, so as to achieve the repair of the hardware error.
[0062] In another exemplary scheme, the selector can be configured as follows: when there is no hardware error in the functional module, the first input terminal of the selector is connected to the data input port of the data trigger; when there is a hardware error in the functional module and the data trigger connected to the selector belongs to the error circuit that causes the hardware error, the second input terminal of the selector is connected to the data input port of the data trigger; when there is a hardware error in the functional module, but the data trigger connected to the selector does not belong to the error circuit that causes the hardware error, the first input terminal of the selector is connected to the data input port of the data trigger.
[0063] For example, Figure 3 As shown, there is a hardware error in a part of the circuit in the functional module. Figure 3 In the figure, the circuit is marked as an error circuit, and there is a normal circuit besides it. Then the first interface and the second interface of the functional module are started, the second interface and the internal functional circuit of the functional module are turned on, and the selectors a and b in the functional module are turned on the first input end and the data input port of the data trigger (that is, the signal generated by the normal circuit continues to be input to the data input port of the data trigger), and the selectors c and d in the functional module are turned on the second input end and the data input port of the data trigger (that is, the repair signal is input to the data input port of the data trigger). When the upstream and downstream module signals synchronized with the repair signal enter the internal functional circuit, they are executed according to the inherent logic of the internal functional circuit, thereby triggering the data trigger according to the specified timing requirements, and the data trigger is about to transmit the connected signal backward. Since the signal output by the error circuit is covered and becomes the correct repair signal, the correct signal will eventually be transmitted to the downstream functional module or fed back to the upstream functional module to achieve the repair of the hardware error.
[0064] In the embodiment of the present application, the selector directly connected to the output end of the error circuit may be used as the selector belonging to the error circuit causing the hardware error.
[0065] In the embodiment of the present application, in order to clarify to which data trigger each repair signal should be sent, each data trigger can be numbered in advance, or each selector can be numbered. Correspondingly, in the repair circuit corresponding to the functional module, the repair signal output by the repair circuit is also numbered according to the same numbering logic, so that the second interface can distribute the repair signal to the data trigger based on the numbering.
[0066] It is understandable that for a chip, an on-chip network needs to be set up in it to meet the instruction distribution and data interaction requirements when the chip is operating normally. Then, in a feasible implementation, the first on-chip system that implements the information interaction between the chip and the hardware repair network in the embodiment of the present application can be directly implemented using the on-chip network in the chip that is used to meet the instruction distribution and data interaction requirements when the chip is operating normally.
[0067] In other implementations, in addition to the on-chip network used to meet the instruction distribution and data interaction requirements of the chip during normal operation, a separate on-chip network dedicated to the first interface, the second interface and the hardware repair network can be set up to specifically interact with the chip and the hardware repair network. In this way, by using the dedicated first interface, the second interface and the hardware repair network to transmit upstream and downstream signals and repair signals, the signals that need to interact with the external hardware repair network and the signals between normal functional modules in the chip will not interfere with each other, thereby improving the reliability of the repaired chip.
[0068] In the embodiments of the present application, Figure 1 As shown, the chip may also include a first P2P interface, and the first on-chip network is connected to the hardware repair network through the first P2P interface. In an embodiment of the present application, the protocol adopted by the first P2P interface may be customized, so as to facilitate the chip design manufacturer to design and modify the upper-layer software, and to facilitate the adjustment of the number of the first P2P interface, so as to facilitate the use of the chip after the hardware repair. In addition, by adopting the P2P interface to interact with the external hardware repair network for signal, since a single P2P interface can reach a rate of tens of GByte / s or even hundreds of GByte / s, the use of the P2P interface can better match the data bandwidth within the chip and meet the signal transmission requirements.
[0069] In addition, in the embodiment of the present application, the interface on the chip for interacting with the hardware repair network can also be implemented using a standard interface such as USB (Universal Serial Bus), and the upper-layer software only needs to be configured according to the standard protocol used by the standard interface.
[0070] In the embodiment of the present application, it is considered that there may be a situation where multiple functional modules have hardware errors. Then, in this case, a corresponding repair circuit needs to be configured for each functional module with hardware errors in the hardware repair network. Then, in order to allow the upstream and downstream module signals sent by the functional module to be received and processed by the corresponding repair circuit, and to allow the repair signal returned by the repair circuit, or the returned repair signal and the upstream and downstream module signals to be received by the corresponding functional module, a unique identifier can be assigned to each functional module.
[0071] Accordingly, the first on-chip network can be configured to: upon receiving the upstream and downstream module signals transmitted from the first interface of any functional module, the upstream and downstream module signals and the unique identifier of the functional module are transmitted to the hardware repair network in an order-preserving manner. In this way, by assigning a unique identifier to each functional module, when transmitting the upstream and downstream module signals transmitted from the first interface of any functional module to the hardware repair network, the unique identifier of the functional module is transmitted together, so that the hardware repair network can accurately know which functional module's corresponding repair circuit the corresponding upstream and downstream module signals should be handed over to, thereby ensuring that the upstream and downstream module signals can be correctly processed. At the same time, by transmitting the upstream and downstream module signals and the unique identifier of the functional module in an order-preserving manner, signal confusion during the transmission process can be avoided, and the reliability of the repair can be improved.
[0072] In an embodiment of the present application, in order to achieve order-preserving transmission, an optional implementation method is: configuring the first on-chip network to: when receiving the upstream and downstream module signals transmitted from the first interface of any functional module, mark each data in the upstream and downstream module signals in sequence, and mark the last data in the upstream and downstream module signals with an end tag; transmit the subsequent upstream and downstream module signals and the unique identifier of the functional module to the hardware repair network.
[0073] For example, if there are 6 data in the upstream and downstream module signals, they can be marked as A, B, C, D, A, E in sequence. The end tag E represents the end tag of the data stream. When the hardware repair network receives the data stream, it reassembles the data stream in the order of A, B, C, D, A, E to obtain the upstream and downstream module signals.
[0074] In the embodiment of the present application, the marked label may be transmitted only on the on-chip network and the P2P interface.
[0075] Based on the same inventive concept, a hardware error repair system is also provided in the embodiment of the present application, see Figure 4 As shown, it includes a chip with a hardware error and a hardware repair network, and the hardware repair network is connected to the first on-chip network of the chip. The structure of the chip can refer to the above description of the embodiment of the present application.
[0076] In the embodiments of the present application, Figure 5 As shown, the hardware repair network includes a repair circuit and a second on-chip network. The repair circuit is used to repair functional modules with hardware errors in the chip. The second on-chip network is connected to the chip and the repair circuit respectively.
[0077] It can be understood that in the embodiment of the present application, each functional module in the chip with a hardware error needs to be provided with a corresponding repair circuit. The repair circuit can be a correct functional circuit that can fully implement all functions of the corresponding functional module. Figure 3 The chip shown is configured as follows: when there is no hardware error in the functional module, the first input terminal of the selector is connected to the data input port of the data trigger; when there is a hardware error in the functional module and the data trigger connected to the selector belongs to the error circuit that causes the hardware error, the second input terminal of the selector is connected to the data input port of the data trigger; when there is a hardware error in the functional module but the data trigger connected to the selector does not belong to the error circuit that causes the hardware error, the first input terminal of the selector is connected to the data input port of the data trigger. The repair circuit can also be the correct circuit corresponding to the error circuit in the corresponding functional module.
[0078] In the embodiments of the present application, Figure 5 As shown, the hardware repair network also includes a second P2P interface, and the second on-chip network is connected to the chip via the second P2P interface.
[0079] Alternatively, the interface on the hardware repair network for interacting with the chip may also be implemented using a standard interface such as USB, and subsequently only the upper-layer software needs to be configured according to the standard protocol used by the standard interface.
[0080] It can be understood that in the embodiment of the present application, the types of interfaces used to realize the interaction between the two parties on the chip and the hardware repair network are consistent. For example, if a P2P interface is used on the chip, a P2P interface is also used on the hardware repair network. In addition, the number of interfaces used to realize the interaction between the two parties on the chip and the hardware repair network should match. For example, the number of interfaces used to realize the interaction between the two parties on the chip and the hardware repair network are 4 each.
[0081] In the embodiment of the present application, the hardware repair network can adopt but is not limited to PAL (Programming Array Logic), GAL (Generic Array Logic), CPLD (Complex Programmable Logic Device), FPGA (Field-Programmable Gate Array), etc.
[0082] In the embodiments of the present application, the chip may be, but is not limited to, a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, an AI (Artificial Intelligence) chip, an MCU (Microcontroller Unit), a GPGPU (General-Purpose Computing On Graphics Processing Unit) chip, or the like.
[0083] In some optional implementations of the embodiments of the present application, when the upstream and downstream module signals transmitted from the chip carry a unique identifier, the second on-chip network can be configured to: upon receiving the upstream and downstream module signals and the unique identifier transmitted from the chip, assign the upstream and downstream module signals to the repair circuit corresponding to the unique identifier. It can be understood that at this time, the repair circuit corresponding to each functional module can be assigned a unique identifier consistent with the corresponding functional module.
[0084] In an embodiment of the present application, when the upstream and downstream module signals transmitted from the chip are marked, the second on-chip network can be specifically configured as follows: restore the upstream and downstream module signals in the order of the received data, and assign the restored upstream and downstream module signals to the repair circuit corresponding to the unique identifier.
[0085] For example, after receiving 6 data items marked in the order of A, B, C, D, A, and E, the second on-chip network reassembles the data in the order of A, B, C, D, A, and E to obtain the upstream and downstream module signals. Among them, the position of the data with the same mark during reassembly can be determined according to the order in which they are received. In the above example, there are two data items marked as A, so the data received first is placed in the first place, and the data received second is placed in the fifth place.
[0086] In an embodiment of the present application, the second on-chip network can be configured to: upon receiving upstream and downstream module signals and repair signals from any repair circuit, transmit the upstream and downstream module signals, repair signals and the unique identifier corresponding to the repair circuit to the chip in order.
[0087] Optionally, the second on-chip network can be specifically configured as follows: when receiving the upstream and downstream module signals or repair signals from any repair circuit, each data in the upstream and downstream module signals and the repair signal is marked in sequence, and an end tag is marked on the last data in the upstream and downstream module signals and the repair signal; the marked upstream and downstream module signals, the repair signal and the unique identifier of the functional module are transmitted to the chip.
[0088] Accordingly, the first on-chip network may be configured to restore upstream and downstream module signals and repair signals according to the sequence of each received data, and assign the restored upstream and downstream module signals and repair signals to the functional module corresponding to the unique identifier.
[0089] In the embodiment of the present application, the entire repair process can be found in Figure 6 As shown, including:
[0090] S601: Determine the functional module with hardware error in the chip through debugging and other means.
[0091] S602: Configure a hardware repair network and connect it to the chip to form a hardware error repair system. The hardware repair network includes a repair circuit corresponding to the functional module with hardware error.
[0092] S603: Configure the functional module with hardware errors in the chip.
[0093] It includes enabling the first interface and the second interface of the functional module, controlling the selection of the input signal switching unit, etc.
[0094] S604: Run the chip program to complete hardware error repair.
[0095] Based on the solution provided by the embodiment of the present application, by presetting the first interface, the second interface and the input signal switching unit in each functional module within the chip, the chip can repair the hardware error by accessing the hardware repair network outside the chip. Compared with relying on firmware or software processes to avoid triggering hardware errors, this solution no longer requires a substantial adjustment of the firmware or software process. Under the premise that the firmware and software cannot avoid the hardware error, since it is allowed to use the hardware repair network outside the chip for repair, the designer does not need to decide whether to shut down the functional module with the hardware error. At the same time, because it is also allowed to use the hardware repair network outside the chip for repair, even if the hardware error occurs in a critical functional module that cannot be shut down, and the firmware or software process cannot avoid triggering the hardware error, there is no need to modify the light mask for re-flowing, which can save costs to a great extent.
[0096] In the present application, the various embodiments and implementation modes provided above can be freely combined to obtain new embodiments without conflict.
[0097] In the embodiments provided in the present application, it should be understood that the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some communication interface, device or unit, which may be electrical, mechanical or other forms.
[0098] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0099] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip, characterized in that: The chip includes a functional module and a first on-chip network; the functional module includes: a first interface, wherein an output end of the first interface is connected to the first on-chip network, and is used to transmit the upstream and downstream module signals to the hardware repair network through the first on-chip network in an enabled state, so that the hardware repair network can perform signal repair; the upstream and downstream module signals include signals output by the upstream module of the functional module to the functional module, or signals fed back by the downstream module of the functional module to the functional module; a second interface, wherein an input end of the second interface is connected to the first on-chip network, and is used to receive a repair signal transmitted from the hardware repair network through the first on-chip network in an enabled state; An input signal switching unit, wherein the first input port of the input signal switching unit is respectively connected to the signal output end of the upstream module of the functional module and the signal feedback end of the downstream module of the functional module, the second input port of the input signal switching unit is connected to the output end of the second interface, and the output end of the input signal switching unit is connected to the internal functional circuit of the functional module.
2. The chip according to claim 1, characterized in that: The second interface is also used to receive upstream and downstream module signals from the hardware repair network through the first on-chip network when in an enabled state; The internal functional circuit includes a data trigger, and the data trigger is used to transmit data backward according to the timing of the internal functional circuit; The second interface is configured to: when there is a hardware error in the functional module, send the repair signal to the corresponding data trigger; The input signal switching unit is configured to: conduct the first input port and the output end of the input signal switching unit when there is no hardware error in the functional module; In the event that a hardware error occurs in the functional module, the second input port and the output end of the input signal switching unit are turned on to output the upstream and downstream module signals from the second interface to the internal functional circuit, so as to trigger the data trigger to transmit the received signal backward according to the timing of the internal functional circuit.
3. The chip according to claim 2, characterized in that: The functional module also includes a selector, and each data trigger corresponds to a selector; For any of the data triggers: The data input port of the data trigger is connected to the output end of the corresponding selector; the first input end of the selector is connected to the output end of the preceding device of the data trigger in the internal functional circuit, and the second input end of the selector is connected to the second interface; Wherein: the selector is configured to: when there is no hardware error in the functional module, connect the first input end of the selector and the data input port of the data trigger; when there is a hardware error in the functional module, connect the second input end of the selector and the data input port of the data trigger.
4. The chip according to claim 2, characterized in that: The functional module also includes a selector, and each data trigger corresponds to a selector; For any of the data triggers: The data input port of the data trigger is connected to the output end of the corresponding selector; the first input end of the selector is connected to the output end of the preceding device of the data trigger in the internal functional circuit, and the second input end of the selector is connected to the second interface; Wherein: the selector is configured as: In the case that there is no hardware error in the functional module, connecting the first input end of the selector and the data input port of the data trigger; When there is a hardware error in the functional module and the data trigger connected to the selector belongs to the error circuit that causes the hardware error, the second input end of the selector and the data input port of the data trigger are turned on; when there is a hardware error in the functional module, but the data trigger connected to the selector does not belong to the error circuit that causes the hardware error, the first input end of the selector and the data input port of the data trigger are turned on.
5. The chip according to any one of claims 1 to 4, characterized in that: The first on-chip network is a network on chip dedicated to connecting the first interface, the second interface, and the hardware repair network.
6. The chip according to any one of claims 1 to 4, characterized in that: The chip further includes a first P2P interface, and the first on-chip network is connected to the hardware repair network via the first P2P interface.
7. The chip according to any one of claims 1 to 4, characterized in that: Each of the functional modules is assigned a unique identifier; The first on-chip network is configured to: upon receiving the upstream and downstream module signals transmitted from the first interface of any functional module, transmit the upstream and downstream module signals together with the unique identifier of the functional module to the hardware repair network in an order-preserving manner.
8. The chip according to claim 7, characterized in that: The first on-chip network is specifically configured as follows: When the upstream and downstream module signals are received from the first interface of any functional module, each data in the upstream and downstream module signals is marked in sequence, and an end tag is marked on the last data in the upstream and downstream module signals; the marked upstream and downstream module signals and the unique identifier of the functional module are transmitted to the hardware repair network.
9. A hardware error repair system, characterized in that: include: The chip according to any one of claims 1 to 8; A hardware repair network is connected to the first on-chip network of the chip.
10. The hardware error recovery system according to claim 9, characterized in that: The hardware repair network includes: A repair circuit, used for repairing a functional module having a hardware error in the chip; The second on-chip network is connected to the chip and the repair circuit respectively.
11. The hardware error recovery system according to claim 10, characterized in that: The hardware repair network further includes a second P2P interface, and the second on-chip network is connected to the chip via the second P2P interface.
12. The hardware error recovery system according to claim 10, characterized in that: The second on-chip network is configured to: upon receiving the upstream and downstream module signals and the unique identifier transmitted from the chip, distribute the upstream and downstream module signals to the repair circuit corresponding to the unique identifier.
13. The hardware error recovery system according to claim 12, characterized in that: The second on-chip network is specifically configured to: restore the upstream and downstream module signals according to the sequence of each received data; and distribute the upstream and downstream module signals to the repair circuit corresponding to the unique identifier.
14. The hardware error repair system according to any one of claims 10 to 13, characterized in that: The second network on chip is configured as: When the upstream and downstream module signals and the repair signal are received from any repair circuit, the upstream and downstream module signals, the repair signal and the unique identifier corresponding to the repair circuit are transmitted to the chip together in order.
15. The hardware error recovery system according to claim 14, characterized in that: The second network on chip is specifically configured as follows: When the upstream and downstream module signals and the repair signal are received from any repair circuit, each data in the upstream and downstream module signals and the repair signal is marked in sequence, and an end tag is marked on the last data in the upstream and downstream module signals and the repair signal; the marked upstream and downstream module signals, the repair signal and the unique identifier of the functional module are transmitted to the chip.