Silicon substrate gallium nitride semiconductor wafer and preparation method and application thereof

Abstract

The invention discloses a silicon substrate gallium nitride semiconductor wafer and a preparation method and application thereof, and relates to the technical field of semiconductor materials. The silicon substrate gallium nitride semiconductor wafer is composed of a silicon single crystal substrate, a silicon carbide single crystal thin film barrier layer, an ultrathin porous titanium nitride weak bonding decoupling layer, an aluminum nitride single crystal thin film nucleating layer template layer and a gallium nitride single crystal thin film quality improving layer which are stacked in sequence. According to the invention, the pore size and the pore density in the ultrathin porous titanium nitride weak bonding decoupling layer are regulated and controlled, so that the weak bonding decoupling effect of the aluminum nitride single crystal film nucleating layer template layer on the ultrathin porous titanium nitride weak bonding decoupling layer is regulated and controlled; therefore, large mismatch stress regulation and control and crack-free thickness improvement of the silicon substrate gallium nitride material are realized, and material crystallization quality and preparation efficiency are improved. The silicon substrate gallium nitride semiconductor wafer can be applied to development and production of gallium nitride-based power electronic devices, microwave radio frequency devices and optoelectronic devices.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor materials, and in particular to a silicon substrate gallium nitride semiconductor wafer and a preparation method and application thereof. Background Art

[0002] The silicon (Si) single crystal substrate has a cubic diamond crystal structure with a lattice constant of 0.5341 nm, an in-plane lattice constant of 0.383 nm and an in-plane thermal expansion coefficient of 3.59×10 -6 K -1 Gallium nitride (GaN) has a hexagonal wurtzite crystal structure, with lattice constants a = 0.31885nm, c = 0.5185nm, and a-axis thermal expansion coefficient of 5.59×10 -6 K -1 , c-axis thermal expansion coefficient is 3.17×10 -6 K -1 . Using silicon single crystal substrates to prepare and grow gallium nitride (GaN) will result in relatively large lattice mismatch (mismatch -16.9%) and thermal mismatch (mismatch 56%), and the problems of interface reaction and interface component interdiffusion are also very prominent. In particular, when using conventional high-temperature (such as above 1000°C) low-pressure metal organic chemical vapor deposition (MOCVD) process for preparation and growth, a large number of silicon (Si) atoms produced by high-temperature decomposition on the surface of the silicon (Si) substrate diffuse into the gallium nitride (GaN) epitaxial layer, causing n-type heavy doping with uncontrollable doping concentration. The upward diffusion of dislocations along the line will also form silicon (Si) spots and leakage channels, making it difficult to improve the voltage resistance performance of silicon (Si) substrate gallium nitride (GaN) power electronic devices. In order to overcome the typical large mismatch heteroepitaxial growth problem of GaN on silicon (Si) substrate, an aluminum nitride (AlN) single crystal film with a thickness of at least 100 nm is usually prepared on a large-size silicon single crystal substrate as a barrier layer and a buffer layer, and then a multi-layer aluminum gallium nitride (AlGaN) single crystal film or a multi-period aluminum nitride / gallium nitride (AlN / GaN) superlattice is inserted to form a large mismatch stress regulation structure to regulate the large mismatch stress and inhibit the upward extension of line dislocations. However, it is still difficult to increase the crack-free thickness of the GaN single crystal film quality improvement layer to more than 5 μm and reduce the dislocation density to 1×10 8 cm -2 Below. Among them, aluminum nitride (AlN) has a hexagonal wurtzite structure, lattice constant a = 0.3112nm, c = 0.4882nm; a-axis thermal expansion coefficient is 4.15×10 -6 K -1 , c-axis thermal expansion coefficient is 5.27×10 -6 K -1. Aluminum nitride (AlN) single crystal thin film is commonly used as a barrier layer. Due to the presence of a large number of grain boundaries and line dislocations in the aluminum nitride single crystal thin film, the effect of blocking silicon (Si) diffusion is limited. In addition, the effect of regulating large mismatch stress by introducing multi-layer thin aluminum gallium nitride (AlGaN) or multi-period AlN / GaN superlattice will be weakened as the size of the silicon (Si) substrate increases. The larger the size of the silicon (Si) substrate, the smaller the crack-free thickness of the gallium nitride (GaN) epitaxial layer. The thickness of the aluminum gallium nitride (AlGaN) or the number of periods of the multi-period AlN / GaN superlattice have to be greatly increased, which greatly reduces the growth efficiency of the preparation of large-size silicon substrate gallium nitride epitaxial wafer materials. This is also one of the reasons why the crack-free thickness of the gallium nitride (GaN) epitaxial layer on 6-inch and 8-inch silicon substrates is difficult to increase to more than 5μm and the production capacity is difficult to increase. Therefore, it is necessary to design a new silicon (Si) substrate gallium nitride (GaN) large mismatch stress control structure to more effectively block silicon diffusion and achieve the crystal quality, crack-free thickness and material preparation efficiency of silicon substrate gallium nitride (GaN) epitaxial material. Summary of the invention

[0003] The technical problem to be solved by the present invention is that the large mismatch stress in the preparation and growth of silicon substrate gallium nitride materials is difficult to effectively regulate, and it is difficult to further improve the crystal quality, crack-free thickness and material preparation efficiency of silicon substrate gallium nitride materials. In order to more effectively block silicon diffusion and reduce the influence of large mismatch stress on the material preparation growth quality, a silicon substrate gallium nitride semiconductor wafer including a large mismatch stress regulation structure is provided.

[0004] In order to solve the above problems, the present invention proposes the following technical solutions:

[0005] In a first aspect, the present invention provides a silicon substrate gallium nitride semiconductor wafer, comprising:

[0006] A silicon single crystal substrate with a thickness of 500-1000 μm;

[0007] A silicon carbide single crystal thin film barrier layer with a thickness of 200-500 nm and a 3C-SiC structure, disposed on the silicon single crystal substrate;

[0008] An ultra-thin porous titanium nitride weakly bonded decoupling layer with a thickness of 10-30 nm, disposed on the silicon carbide single crystal thin film barrier layer;

[0009] A 500-1000nm thick aluminum nitride single crystal thin film nucleation layer template layer, disposed on the ultra-thin porous titanium nitride weakly bonded decoupling layer;

[0010] A gallium nitride single crystal film quality improvement layer with a thickness of not less than 5 μm is arranged on the aluminum nitride single crystal film nucleation layer template layer.

[0011] It can be understood that in the silicon substrate gallium nitride semiconductor wafer of the present invention, a large mismatch stress control structure is added between the silicon single crystal substrate and the gallium nitride epitaxial layer, and the large mismatch stress control structure is used to block silicon diffusion and reduce the influence of large mismatch stress on the growth quality of material preparation. In the present invention, the large mismatch stress control structure is composed of a silicon carbide single crystal film barrier layer, an ultra-thin porous titanium nitride weakly bonded decoupling layer, and an aluminum nitride single crystal film nucleation layer template layer stacked in sequence.

[0012] Furthermore, the size of the silicon single crystal substrate includes but is not limited to 1 inch, 2 inches, 4 inches, 6 inches, 8 inches, and 12 inches in diameter.

[0013] The gallium nitride single crystal film quality improvement layer has no cracks and a dislocation density not higher than 1×10 8 cm -2 .

[0014] Furthermore, the porosity of the ultra-thin porous titanium nitride weakly bonded decoupling layer is 35-75%.

[0015] Furthermore, the dislocation density of the aluminum nitride single crystal thin film nucleation layer template layer is not higher than 1×10 7 cm -2 And the surface roughness is not higher than 0.5nm.

[0016] In a second aspect, the present invention provides a method for preparing the silicon substrate gallium nitride semiconductor wafer according to the first aspect, comprising the following steps:

[0017] S1, preparing a silicon single crystal substrate, and performing high-temperature and high-vacuum baking on the surface of the silicon single crystal substrate to remove the remaining oxide layer and adsorbed impurities;

[0018] S2, forming a silicon carbide single crystal thin film barrier layer having a 3C-SiC structure on the silicon single crystal substrate;

[0019] S3, forming an ultra-thin indium titanium nitrogen single crystal thin film layer having a single preferred orientation in the C direction on the silicon carbide single crystal thin film barrier layer;

[0020] S4, forming an aluminum nitride single crystal thin film layer having a single preferred orientation in the C direction on the ultra-thin indium titanium nitride single crystal thin film layer having a single preferred orientation in the C direction;

[0021] S5, performing high-temperature high-vacuum annealing in a hydrogen atmosphere, so that the indium component in the ultra-thin indium titanium nitride single crystal thin film layer is completely thermally decomposed and precipitated from the grain gaps in the aluminum nitride single crystal thin film layer with a single preferred orientation in the C direction, to obtain the ultra-thin porous titanium nitride weakly bonded decoupling layer;

[0022] S6, performing high-temperature and high-vacuum annealing in an ammonia atmosphere, so that the grains in the aluminum nitride single crystal thin film layer having a single preferred orientation in the C direction are fused, combined and recrystallized to obtain the aluminum nitride single crystal thin film nucleation layer template layer;

[0023] S7, forming a gallium nitride single crystal thin film quality improvement layer on the aluminum nitride single crystal thin film nucleation layer template layer.

[0024] Furthermore, in step S5, the conditions for high temperature and high vacuum annealing in a hydrogen atmosphere are: hydrogen atmosphere pressure 30-50 Pa, annealing temperature 650-850° C., and high temperature and high vacuum annealing for 1.0-3.0 hours.

[0025] Furthermore, in step S6, the high temperature and high vacuum annealing conditions in the ammonia atmosphere are: ammonia atmosphere pressure 50-100 Pa, annealing temperature 1000-1200° C., and high temperature and high vacuum annealing for 1.0-5.0 hours.

[0026] The present invention also provides the silicon substrate gallium nitride semiconductor wafer, or the silicon substrate gallium nitride semiconductor wafer prepared by the method can be used to develop and produce gallium nitride-based power electronic devices, gallium nitride-based microwave radio frequency devices, gallium nitride-based light emitting diode devices, gallium nitride-based laser diode devices, and gallium nitride-based ultraviolet detection devices.

[0027] Compared with the prior art, the technical effects achieved by the present invention include:

[0028] The silicon substrate gallium nitride semiconductor wafer provided by the present invention is composed of a silicon single crystal substrate, a silicon carbide (3C-SiC) single crystal film barrier layer, an ultra-thin porous titanium nitride (TiN) weak bonding decoupling layer, an aluminum nitride (AlN) single crystal film nucleation layer template layer and a gallium nitride (GaN) single crystal film quality improvement layer stacked in sequence. Among them, the silicon carbide single crystal film barrier layer with a 3C-SiC structure is denser than the conventional aluminum nitride (AlN) single crystal film barrier layer, which can better block the thermal diffusion of silicon (Si) atoms generated by high temperature decomposition on the surface of the silicon (Si) substrate into the gallium nitride (GaN) epitaxial layer, and provide a good template for the subsequent single crystal preparation and growth of other structural layers; the a-axis thermal expansion coefficient of titanium nitride (TiN) is 9.5×10 -6 K -1, which is larger than silicon (Si), gallium nitride (GaN), aluminum nitride (AlN) and aluminum oxide (Al2O3). The ultra-thin porous titanium nitride weakly bonded decoupling layer of the present invention can more effectively coordinate the thermal stress generated during the large-scale cooling process, and is not affected by the expansion of the size of the silicon (Si) single crystal substrate; the aluminum nitride (AlN) single crystal film nucleation layer template layer of the present invention has a higher crystal quality than the conventional aluminum nitride (AlN) single crystal film barrier layer buffer layer and the multi-layer aluminum gallium nitride (AlGaN) single crystal film component gradient buffer layer, which can not only provide a single crystal film template with better crystal quality, but also more effectively reduce the lattice mismatch stress and dislocation density of the gallium nitride (GaN) single crystal film quality improvement layer; by regulating the thickness and porosity of the ultra-thin porous titanium nitride (TiN) weakly bonded decoupling layer, not only can the large mismatch stress and dislocation density of the gallium nitride (GaN) single crystal film quality improvement layer be reduced to a greater extent, but also the crack-free thickness and yield of the gallium nitride (GaN) single crystal film quality improvement layer can be greatly improved.

[0029] Furthermore, according to the method for preparing a silicon substrate gallium nitride semiconductor wafer of the present invention, the ultra-thin porous titanium nitride (TiN) weakly bonded decoupling layer is formed by a high-temperature high-vacuum annealing process of an ultra-thin single crystal layer of indium titanium nitride (InTiN) containing an indium (In) component in a hydrogen atmosphere to completely thermally decompose and precipitate the indium (In) component. Among them, the indium titanium nitride (InTiN) single crystal thin film material with a high content of indium (In) component has a strong polarity, and it is easy to realize the growth of a hexagonal crystal structure with a C-axis single preferred orientation single crystal with regular grain arrangement on the surface of a silicon carbide (3C-SiC) single crystal thin film barrier layer. Using the ultra-thin indium titanium nitride (InTiN) layer with a hexagonal crystal structure and a C-axis single preferred orientation single crystal as a template, the growth of a hexagonal crystal structure of aluminum nitride (AlN) with a hexagonal crystal structure and a C-axis single preferred orientation single crystal can also be realized. After high-temperature and high-vacuum annealing treatment in a hydrogen atmosphere, the indium (In) component in the ultra-thin indium titanium nitride (InTiN) single crystal layer will completely decompose and precipitate along the grain gaps of the upper aluminum nitride (AlN) single crystal film layer, thereby forming an ultra-thin porous titanium nitride (TiN) weakly bonded decoupling layer. The ultra-thin porous titanium nitride (TiN) weakly bonded decoupling layer can achieve weak bonding and decoupling between the aluminum nitride (AlN) single crystal thin film nucleation layer template layer thereon and the silicon (Si) substrate and silicon carbide (3C-SiC) single crystal thin film barrier layer at the bottom; the weakly bonded decoupled aluminum nitride (AlN) single crystal thin film nucleation layer template layer is then subjected to high temperature and high vacuum annealing treatment in an ammonia atmosphere. Only high temperature and high vacuum annealing treatment at 1000-1200°C is required to achieve grain fusion and merger in the aluminum nitride (AlN) single crystal thin film and then recrystallize to form an aluminum nitride (AlN) single crystal thin film nucleation layer template layer with higher crystal quality, which is lower than the recrystallization temperature (1400-1600°C) of aluminum nitride film on conventional sapphire substrate.

[0030] Furthermore, the structure of the silicon substrate gallium nitride semiconductor wafer provided by the present invention can realize the large mismatch stress regulation of silicon substrate gallium nitride. The "unsupported substrate" model design based on the flexible substrate is compared with the existing flexible substrate preparation technology, such as sacrificial layer bonding technology, ion implantation buried layer technology and few-layer two-dimensional material technology, etc., the weak bonding decoupling effect is difficult to control. The pore size and pore density in the film layer after high-temperature and high-vacuum annealing can be controlled by regulating the indium (In) component concentration and layer thickness in the ultra-thin indium titanium nitride (InTiN) film, thereby achieving the weak bonding decoupling effect regulation of the aluminum nitride (AlN) single crystal thin film nucleation layer template layer thereon. Ultra-thin porous titanium nitride (TiN) weakly bonded decoupling layers with different thicknesses, pore sizes and densities are designed and prepared on silicon (Si) single crystal substrates of different sizes, which can not only significantly improve the crystallization quality of the aluminum nitride (AlN) single crystal film nucleation layer and template layer thereon, but also significantly reduce the stress and dislocation density of the subsequent epitaxially grown thicker gallium nitride (GaN) single crystal film quality improvement layer, and significantly improve the crack-free thickness and material preparation growth efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0032] Figure 1 The schematic diagram of the structure of the silicon substrate gallium nitride semiconductor wafer of Example 1 of the present invention is shown in FIG. 100 is a silicon substrate, which is composed of a silicon single crystal substrate 101; 200 is a large mismatch stress control structure, which is composed of a silicon carbide single crystal film barrier layer 201, an ultra-thin porous titanium nitride weak bonding decoupling layer 202, and an aluminum nitride single crystal film nucleation layer template layer 203 stacked in sequence; and 300 is a gallium nitride epitaxial layer, which is composed of a gallium nitride single crystal film quality improvement layer 301.

[0033] Figure 2 This is a schematic diagram of the structure of forming an ultra-thin indium titanium nitride single crystal thin film layer and an aluminum nitride single crystal thin film layer having a single preferred orientation in the C direction on the silicon carbide single crystal thin film barrier layer 201 in the method for preparing a silicon substrate gallium nitride semiconductor wafer according to Example 1 of the present invention. Among them, 2021 is an ultra-thin indium titanium nitride single crystal thin film layer, and 2031 is an aluminum nitride single crystal thin film layer.

[0034] Figure 3This is a structural schematic diagram of the method for preparing a gallium nitride semiconductor wafer on a silicon substrate of Example 1 of the present invention, in which an ultra-thin porous titanium nitride weakly bonded decoupling layer 202 and an aluminum nitride single crystal thin film nucleation layer template layer 203 are formed on the silicon carbide single crystal thin film barrier layer 201 through high temperature and high vacuum annealing. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0037] It should also be understood that the terms used in this description of the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present invention. As used in the description of the embodiments of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms.

[0038] Example 1

[0039] This embodiment discloses a 6-inch silicon substrate gallium nitride semiconductor wafer, the structure of which is as follows: Figure 1 As shown. 100 is a silicon substrate, which is composed of a silicon single crystal substrate 101; 200 is a large mismatch stress control structure, which is composed of a silicon carbide single crystal film barrier layer 201, an ultra-thin porous titanium nitride weak bonding decoupling layer 202, and an aluminum nitride single crystal film nucleation layer template layer 203 stacked in sequence; 300 is a gallium nitride epitaxial layer, which is composed of a gallium nitride single crystal film quality improvement layer 301.

[0040] See also Figure 2 and Figure 3 The structure and preparation method of the silicon substrate gallium nitride semiconductor wafer of this embodiment are described as follows:

[0041] A 6-inch 1000 μm thick silicon single crystal substrate (101).

[0042] A 200nm thick silicon carbide single crystal thin film barrier layer (201) with a 3C-SiC structure is prepared on a 6-inch 1000μm thick silicon single crystal substrate (101) by using a 1100°C high temperature chemical vapor deposition (HTCVD) process.

[0043] A 30nm thick ultra-thin porous titanium nitride weak bonding decoupling layer (202) and a 500nm thick aluminum nitride single crystal film nucleation layer template layer (203). In this embodiment, the above structure is prepared by using a 650°C medium and high temperature plasma enhanced chemical vapor deposition (PECVD) process on a 200nm thick silicon carbide single crystal film barrier layer (101) to sequentially form an ultra-thin indium titanium nitride (InTiN) single crystal layer (2021) with a thickness of 30nm and an indium component atomic percentage concentration of 75% and a C-axis single preferred orientation and a 500nm thick aluminum nitride single crystal film layer (2031) with a C-axis single preferred orientation, and firstly annealing at a high temperature and high vacuum at a hydrogen atmosphere pressure of 30Pa and an annealing temperature of 900°C for 0.5 hours to completely thermally decompose the indium (In) component in the ultra-thin indium titanium nitride (InTiN) single crystal layer (2021) and form a silicon carbide single crystal film barrier layer (101). The aluminum nitride single crystal film layer (2031) is precipitated at the grain gaps and grain boundaries to form an ultra-thin porous titanium nitride weakly bonded decoupling layer (202); and then subjected to high-temperature high-vacuum annealing at an ammonia atmosphere pressure of 50 Pa and an annealing temperature of 1100° C. for 1 hour, so that the grains in the aluminum nitride single crystal film layer (2031) are merged, fused, and recrystallized to form an aluminum nitride single crystal film nucleation layer template layer (203); in this embodiment, the atomic percentage concentration of the indium (In) component in the ultra-thin indium titanium nitride (InTiN) single crystal layer (2021) is 75%, the porosity of the ultra-thin porous titanium nitride weakly bonded decoupling layer (202) is 75%, and the dislocation density of the aluminum nitride single crystal film nucleation layer template layer (203) is not higher than 1×10 7 cm -2 And the surface roughness is not higher than 0.5nm.

[0044] In other embodiments, a medium to high temperature plasma enhanced chemical vapor deposition (PECVD) process at 550-750°C can be used to sequentially form an ultra-thin indium titanium nitride (InTiN) single crystal layer (2021) having a single preferred orientation along the C axis and an aluminum nitride single crystal thin film layer having a single preferred orientation along the C axis.

[0045] A gallium nitride single crystal thin film quality improvement layer (301) without cracks and having a thickness of not less than 10 μm is prepared by a conventional 1050° C. high temperature metal organic chemical vapor deposition (MOCVD) process and grown on the above-mentioned 500 nm thick aluminum nitride single crystal thin film nucleation layer template layer (203); in this embodiment, the dislocation density of the gallium nitride single crystal thin film quality improvement layer (301) is not higher than 5×10 7 cm -2 .

[0046] The 6-inch silicon substrate gallium nitride semiconductor wafer prepared by the above embodiment can be used to develop and produce high-frequency and high-power gallium nitride-based microwave radio frequency devices.

[0047] Example 2

[0048] See also Figure 1-3 This embodiment provides an 8-inch silicon substrate gallium nitride semiconductor wafer. The structure of the 8-inch silicon substrate gallium nitride semiconductor wafer includes, from bottom to top:

[0049] An 8-inch 1500 μm thick silicon single crystal substrate (101);

[0050] A 300nm thick silicon carbide single crystal thin film barrier layer (201);

[0051] An ultra-thin porous titanium nitride weakly bonded decoupling layer (202) with a thickness of 20 nm;

[0052] A 1000nm thick aluminum nitride single crystal thin film nucleation layer template layer (203);

[0053] A gallium nitride single crystal thin film quality improvement layer (301) having a crack-free thickness of not less than 7 μm.

[0054] The method for preparing the above-mentioned 8-inch silicon substrate gallium nitride semiconductor wafer comprises the following steps:

[0055] S1. Prepare an 8-inch silicon single crystal substrate (101), and perform high-temperature high-vacuum baking on the surface of the 8-inch silicon single crystal substrate (101) in a hydrogen atmosphere pressure of 20 Pa and a substrate heating temperature of 1100° C. to remove the remaining oxide layer and adsorbed impurities.

[0056] S2. On the 8-inch silicon single crystal substrate (101), a low-energy ion beam deposition process is used at a medium-high temperature of 750-850° C. to form a silicon carbide single crystal thin film barrier layer (201) having a 3C-SiC structure. In this embodiment, a low-energy ion beam deposition process is used at a medium-high temperature of 750° C. to form a silicon carbide single crystal thin film barrier layer (201) having a 3C-SiC structure.

[0057] S3. On the silicon carbide single crystal thin film barrier layer (201), a pulsed DC magnetron sputtering process is used at a medium-high temperature of 550-750° C. to form an ultra-thin indium titanium nitrogen single crystal thin film layer (2121) having a single preferred orientation in the C direction. The atomic percentage concentration of the indium component in the ultra-thin indium titanium nitrogen single crystal layer (2121) in this embodiment is 65%. In this embodiment, a pulsed DC magnetron sputtering process is used at a medium-high temperature of 750° C. to form an ultra-thin indium titanium nitrogen single crystal thin film layer (2121) having a single preferred orientation in the C direction.

[0058] S4. On the ultra-thin indium titanium nitride single crystal thin film layer (2021) with a single preferred orientation in the C direction, a pulsed magnetron sputtering process is used at a medium-high temperature of 550-750°C to form an aluminum nitride single crystal thin film layer (2031) with a single preferred orientation in the C direction; this embodiment uses a pulsed magnetron sputtering process at a medium-high temperature of 750°C to form an aluminum nitride single crystal thin film layer (2031) with a single preferred orientation in the C direction.

[0059] S5. Perform high-temperature high-vacuum annealing for 1.0 hour under a hydrogen atmosphere pressure of 50 Pa and a high temperature of 850° C., so that the indium component in the ultra-thin indium titanium nitride single crystal thin film layer (2021) is completely thermally decomposed and precipitated from the grain gaps and grain boundaries in the aluminum nitride single crystal thin film layer (2031) with a single preferential orientation in the C direction, to obtain the ultra-thin porous titanium nitride weakly bonded decoupling layer (202). The porosity of the ultra-thin porous titanium nitride weakly bonded decoupling layer (202) in this embodiment is 65%.

[0060] S6. Perform high-temperature high-vacuum annealing for 2 hours at an ammonia atmosphere pressure of 100 Pa and a high temperature of 1150° C. to fuse and recrystallize the grains in the aluminum nitride single crystal thin film layer (2031) having a single preferred orientation in the C direction, thereby obtaining the aluminum nitride single crystal thin film nucleation layer template layer (203). In this embodiment, the dislocation density of the aluminum nitride single crystal thin film nucleation layer template layer (203) is not higher than 2×10 7 cm -2 And the surface roughness is not higher than 0.6nm.

[0061] S7. On the aluminum nitride single crystal thin film nucleation layer template layer (203), a gallium nitride single crystal thin film quality improvement layer (301) having a thickness of not less than 7 μm is prepared by a metal organic chemical vapor deposition process at a high temperature of 1050° C. In this embodiment, the gallium nitride single crystal thin film quality improvement layer (301) has no cracks and a dislocation density of not more than 6×10 7 cm -2 .

[0062] The 8-inch silicon substrate gallium nitride semiconductor wafer prepared by the above embodiment can be used to develop and produce gallium nitride-based power electronic devices with a withstand voltage of not less than 1200V.

[0063] The silicon substrate gallium nitride semiconductor wafer provided in the embodiment of the present invention uses a large mismatch stress control structure composed of a silicon carbide (3C-SiC) single crystal film barrier layer, an ultra-thin porous titanium nitride (TiN) weak bonding decoupling layer, and an aluminum nitride (AlN) single crystal film nucleation layer template layer to control the large mismatch stress of silicon substrate gallium nitride, which can not only further improve the crystallization quality, crack-free thickness and material preparation efficiency of silicon substrate gallium nitride materials, but also more effectively block silicon diffusion and reduce the influence of large mismatch stress on material preparation growth quality.

[0064] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0065] The above is a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A silicon substrate gallium nitride semiconductor wafer, characterized in that: include: A silicon single crystal substrate with a thickness of 500-1000 μm; A silicon carbide single crystal thin film barrier layer with a thickness of 200-500 nm and a 3C-SiC structure, disposed on the silicon single crystal substrate; An ultra-thin porous titanium nitride weakly bonded decoupling layer with a thickness of 10-30 nm, disposed on the silicon carbide single crystal thin film barrier layer; A 500-1000nm thick aluminum nitride single crystal thin film nucleation layer template layer, disposed on the ultra-thin porous titanium nitride weakly bonded decoupling layer; A gallium nitride single crystal film quality improvement layer with a thickness of not less than 5 μm is arranged on the aluminum nitride single crystal film nucleation layer template layer.

2. The silicon substrate gallium nitride semiconductor wafer according to claim 1, characterized in that: The size of the silicon single crystal substrate includes but is not limited to 1 inch, 2 inches, 4 inches, 6 inches, 8 inches, and 12 inches in diameter.

3. The silicon substrate gallium nitride semiconductor wafer according to claim 2, characterized in that: The gallium nitride single crystal film quality improvement layer has no cracks and a dislocation density not higher than 1×10 8 cm -2 .

4. The silicon substrate gallium nitride semiconductor wafer according to claim 1, characterized in that: The porosity of the ultra-thin porous titanium nitride weakly bonded decoupling layer is 35-75%.

5. The silicon substrate gallium nitride semiconductor wafer according to claim 1, characterized in that: The dislocation density of the aluminum nitride single crystal film nucleation layer template layer is not higher than 1×10 7 cm -2 And the surface roughness is not higher than 0.5nm.

6. A method for preparing a silicon substrate gallium nitride semiconductor wafer according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1, preparing a silicon single crystal substrate, and performing high-temperature and high-vacuum baking on the surface of the silicon single crystal substrate to remove the remaining oxide layer and adsorbed impurities; S2, forming a silicon carbide single crystal thin film barrier layer having a 3C-SiC structure on the silicon single crystal substrate; S3, forming an ultra-thin indium titanium nitrogen single crystal thin film layer having a single preferred orientation in the C direction on the silicon carbide single crystal thin film barrier layer; S4, forming an aluminum nitride single crystal thin film layer having a single preferred orientation in the C direction on the ultra-thin indium titanium nitride single crystal thin film layer having a single preferred orientation in the C direction; S5, performing high-temperature high-vacuum annealing in a hydrogen atmosphere, so that the indium component in the ultra-thin indium titanium nitride single crystal thin film layer is completely thermally decomposed and precipitated from the grain gaps in the aluminum nitride single crystal thin film layer with a single preferred orientation in the C direction, to obtain the ultra-thin porous titanium nitride weakly bonded decoupling layer; S6, performing high-temperature and high-vacuum annealing in an ammonia atmosphere, so that the grains in the aluminum nitride single crystal thin film layer having a single preferred orientation in the C direction are fused, combined and recrystallized to obtain the aluminum nitride single crystal thin film nucleation layer template layer; S7, forming a gallium nitride single crystal thin film quality improvement layer on the aluminum nitride single crystal thin film nucleation layer template layer.

7. The method for preparing the silicon substrate gallium nitride semiconductor wafer according to claim 6, characterized in that: In step S5, the high temperature and high vacuum annealing conditions in the hydrogen atmosphere are: hydrogen atmosphere pressure 30-50 Pa, annealing temperature 650-850° C., and high temperature and high vacuum annealing time 1.0-3.0 hours.

8. The method for preparing the silicon substrate gallium nitride semiconductor wafer according to claim 6, characterized in that: In step S6, the high temperature and high vacuum annealing conditions in the ammonia atmosphere are: ammonia atmosphere pressure 50-100 Pa, annealing temperature 1000-1200° C., and high temperature and high vacuum annealing time 1.0-5.0 hours.

9. The method for preparing the silicon substrate gallium nitride semiconductor wafer according to claim 6, characterized in that: The atomic percentage concentration of indium component in the ultra-thin indium titanium nitrogen single crystal film layer is 35-75%.

10. The silicon substrate gallium nitride semiconductor wafer as described in any one of claims 1 to 5, or the silicon substrate gallium nitride semiconductor wafer obtained by the method as described in any one of claims 6 to 9 can be used to develop and produce gallium nitride-based power electronic devices, gallium nitride-based microwave radio frequency devices, gallium nitride-based light emitting diode devices, gallium nitride-based laser diode devices, and gallium nitride-based ultraviolet detection devices.

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