Manufacturing method of semiconductor device, semiconductor device and memory system

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor device, the semiconductor device and a memory system thereof. The manufacturing method of the semiconductor device comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a semiconductor layer, a penetrating contact and a grid line gap structure, the penetrating contact and the grid line gap structure are located on the first side of the semiconductor layer, the penetrating contact and the grid line gap structure extend to the semiconductor layer in the first direction perpendicular to the semiconductor layer, and the semiconductor layer is provided with a protruding part; the lug boss is positioned on a second side, opposite to the first side, of the semiconductor layer and is at least partially aligned with the grid line gap structure; and etching the semiconductor layer from the second side to remove at least a portion of the protrusion and form an opening and an isolation trench exposing the through contact, at least a portion of the isolation trench being located between the protrusion and the opening on a plane perpendicular to the first direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, and a memory system. Background Art

[0002] In the manufacturing process of three-dimensional memory (e.g., 3D NAND memory), in order to meet the electrical performance and yield of the three-dimensional memory, complex process processing is usually required from the back side of the semiconductor layer, which increases the manufacturing difficulty and also increases the time and economic cost. Summary of the invention

[0003] The present application provides a method for manufacturing a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0004] Some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: providing a semiconductor structure, wherein the semiconductor structure includes a semiconductor layer and a through contact and a gate line gap structure located on a first side of the semiconductor layer, the through contact and the gate line gap structure extend to the semiconductor layer along a first direction perpendicular to the semiconductor layer, the semiconductor layer has a protrusion, the protrusion is located on a second side of the semiconductor layer opposite to the first side, and is at least partially aligned with the gate line gap structure; and etching the semiconductor layer from the second side to remove at least part of the protrusion and form an opening and an isolation groove exposing the through contact, wherein, on a plane perpendicular to the first direction, at least part of the isolation groove is located between the protrusion and the opening.

[0005] In some embodiments, etching the semiconductor layer from the second side to remove at least a portion of the protrusion and form an opening and an isolation trench exposing the through contact includes: forming a mask layer having a first pattern on the second side of the semiconductor layer, wherein the first pattern exposes the opening, the isolation trench, and the protrusion; and etching the semiconductor layer using the mask layer to remove at least a portion of the protrusion and form the opening and the isolation trench.

[0006] In some embodiments, a dimension of the opening is larger than a dimension of the through contact in a plane parallel to the semiconductor layer.

[0007] In some embodiments, the method further includes: forming an insulating layer on sidewalls of the opening and the isolation trench.

[0008] In some embodiments, the semiconductor structure further includes a stop layer covering a surface of the semiconductor layer on a second side, wherein etching the semiconductor layer from the second side to remove at least a portion of the protrusion and form an opening and an isolation groove exposing the through contact further includes: etching the stop layer from the second side to remove a portion of the stop layer covering the protrusion.

[0009] In some embodiments, the stop layer is an insulating material. After the insulating layer is formed on the side walls of the opening and the isolation trench, the method further includes: forming a metal layer filling the opening and the isolation trench and covering the surface of the stop layer; and removing a portion of the metal layer covering the surface of the stop layer to the stop layer, so that the retained metal layer is connected to the metal layer filling the opening.

[0010] In some embodiments, the gate line gap structure also extends along a second direction parallel to the semiconductor layer, and adjacent gate line gap structures in the third direction define a storage block, and the isolation trench is annular; on a plane perpendicular to the first direction, the isolation trench surrounds the storage block, and the opening is located outside the annular area defined by the isolation trench, and the third direction is perpendicular to the first direction and the second direction.

[0011] Some other embodiments of the present application provide a semiconductor device. The semiconductor device includes: a semiconductor layer; a through contact located on a first side of the semiconductor layer and extending in a first direction perpendicular to the semiconductor layer; a gate line gap structure located on a first side of the semiconductor layer and extending to the semiconductor layer in the first direction; a conductive contact that penetrates the semiconductor layer and is connected to the through contact; and an isolation structure that penetrates the semiconductor layer, and at least a portion of the isolation structure is located between the conductive contact and the gate line gap structure on a plane perpendicular to the first direction.

[0012] In some embodiments, the semiconductor layer has a first surface away from the gate line gap structure, and in the first direction, a distance between a portion of the first surface corresponding to the gate line gap structure and other portions of the first surface is less than

[0013] In some embodiments, the conductive contact includes a first metal portion and a first insulating layer located on an outer side wall of the first metal portion, the first metal portion being connected to the through contact; the isolation structure includes a second metal portion and a second insulating layer located on an outer side wall of the second metal portion.

[0014] In some embodiments, a dimension of the conductive contact is larger than a dimension of the through contact in a plane parallel to the semiconductor layer.

[0015] In some embodiments, the semiconductor device also includes: a stop layer, located on the first surface of the semiconductor layer and having an opening exposing a portion of the semiconductor layer corresponding to the gate line gap structure; and a metal wiring layer, located on a side of the stop layer away from the semiconductor layer, including a metal wire, the metal wire being connected to the conductive contact and the portion of the semiconductor layer corresponding to the gate line gap structure.

[0016] In some embodiments, the material of the stop layer includes silicon oxide, and the material of the metal wiring layer includes aluminum.

[0017] In some embodiments, the gate line gap structure also extends along a second direction parallel to the semiconductor layer, and adjacent gate line gap structures in a third direction define a storage block, and the isolation structure is annular; on a plane perpendicular to the first direction, the isolation structure surrounds the storage block, and the conductive contact is located outside the annular area defined by the isolation structure, and the third direction is perpendicular to the first direction and the second direction.

[0018] In some embodiments, the semiconductor device also includes: a stacking structure located on the second side of the semiconductor layer; and an insulating structure located on the first side of the semiconductor layer and arranged parallel to the stacking structure; wherein the gate line gap structure passes through the stacking structure, passes through the contact and passes through the insulating structure.

[0019] In some embodiments, the semiconductor device further includes: a channel structure penetrating the stacked structure and extending to the semiconductor layer.

[0020] In some embodiments, the semiconductor device further includes: a peripheral circuit structure connected to the channel structure at a side of the stack structure away from the semiconductor layer; wherein the through contact is connected to the peripheral circuit structure.

[0021] Some other embodiments of the present application provide a memory system, which includes: a three-dimensional memory including at least one semiconductor device as mentioned in any of the above embodiments; and a controller coupled to the three-dimensional memory and used to control the three-dimensional memory to store data.

[0022] According to at least one embodiment of the present application, the manufacturing method of the semiconductor device, the semiconductor device and the memory system provided by the present application form an opening and an isolation groove in a single lithography and etching process (i.e., using a mask), the opening can be used to lead out the through contact, and the isolation groove can be used to achieve electrical isolation between the lead-out structure of the through contact and the semiconductor layer used as a common source, and the raised portion on the second side of the semiconductor layer is used to remove at least a portion of the raised portion, which can avoid damage to, for example, the channel structure located on the first side of the semiconductor layer, and is conducive to improving the yield. At the same time, the surface of the semiconductor layer after at least a portion of the raised portion is removed is relatively flat, which is more friendly to the subsequent thin film deposition process on the surface of the semiconductor layer. In addition, it is conducive to reducing the difficulty and cost of manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0024] Figures 1A to 1F is a cross-sectional schematic diagram of a semiconductor device in a manufacturing process according to an exemplary embodiment of the present application;

[0025] Figure 2is a schematic flow chart of a method for manufacturing a semiconductor device according to another exemplary embodiment of the present application;

[0026] FIG. 3A to FIG. 3D according to Figure 2 A schematic cross-sectional view of a semiconductor device during the manufacturing process of the manufacturing method shown;

[0027] Figure 4 is based on Figure 2 A schematic top view of a semiconductor device formed by the manufacturing method shown;

[0028] Figure 5 yes Figure 3A A partial enlarged schematic diagram of region C is shown;

[0029] Figure 6 is a block diagram of a system having a memory system according to an exemplary embodiment of the present application; and

[0030] Fig. 7A and Figure 7B is a schematic diagram of a memory system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first side discussed in this application may also be referred to as the second side, and vice versa.

[0033] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0034] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0035] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0036] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0037] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0038] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0039] It should be noted that, in the following, the x-direction, y-direction, and z-direction in each figure show the spatial relationship of the components in the semiconductor device. For example, the z-direction is a first direction perpendicular to the semiconductor layer, and the x-direction and the y-direction are respectively a second direction and a third direction perpendicular to each other on a plane parallel to the semiconductor layer. The same concept will be used throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0040] Figures 1A to 1F FIG. 1 is a cross-sectional schematic diagram of a semiconductor device of an exemplary embodiment of the present application during the manufacturing process. Figure 1A and Figure 1BAs shown, in the intermediate structure of the semiconductor device (i.e., semiconductor structure 100a), the side of the semiconductor layer 111 where the stacked structure 121 is not provided can be referred to as the back side of the semiconductor layer 111. Optionally, the back side surface of the semiconductor layer 111 can have a stop layer 141. During the back side process of the semiconductor layer 111, the first mask layer 101 can be used to first remove the portion of the semiconductor layer 111 and the stop layer 141 corresponding to the through contact 131, so that the through contact 131 is exposed. The semiconductor layer 111 that is not removed can be used as a common source of the memory cell array. For example, the through contact 131 is electrically connected to the peripheral circuit structure 151.

[0041] Then, if Figure 1C As shown, an insulating material layer 191 may be formed on the back side of the semiconductor layer 111, and the insulating material layer 191 also fills the cavity formed by removing a portion of the semiconductor layer 111 in the previous step, so that the through contact 131 is covered by the insulating material layer 191. Figure 1D and Figure 1E As shown, the insulating material layer 191 is removed by using the second mask layer 102 to form a conductive contact hole (corresponding to the outer contour of the conductive contact 162) and a source contact hole (corresponding to the outer contour of the source contact 192), and a conductive material is filled in the conductive contact hole and the source contact hole to form the conductive contact 162 and the source contact 192. Subsequently, as shown in FIG. Figure 1F As shown, a metal wiring layer 181 is formed on a side of the insulating material layer 191 away from the semiconductor layer 111 .

[0042] In this embodiment, two photolithography and etching processes (i.e., using two masks) are used to electrically isolate the conductive contact 162 from the semiconductor layer 111 used as a common source, and to lead out the through contact 131 and the semiconductor layer 111 used as a common source. The process is relatively complicated and is not conducive to reducing manufacturing difficulty and cost.

[0043] Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to another exemplary embodiment of the present invention. Figure 2 As shown, a method 200 for manufacturing a semiconductor device (hereinafter referred to as manufacturing method 200 ) may include the following steps.

[0044] S210, providing a semiconductor structure, wherein the semiconductor structure includes a semiconductor layer and a through contact and gate line gap structure located on a first side of the semiconductor layer, the through contact and gate line gap structure extend to the semiconductor layer along a first direction perpendicular to the semiconductor layer, the semiconductor layer has a protrusion, the protrusion is located on a second side of the semiconductor layer opposite to the first side, and is at least partially aligned with the gate line gap structure.

[0045] S220, etching the semiconductor layer from the second side to remove at least part of the protrusion and form an opening exposing the through contact and an isolation trench, wherein, on a plane perpendicular to the first direction, at least part of the isolation trench is located between the protrusion and the opening.

[0046] According to the manufacturing method of the semiconductor device provided by this embodiment, an opening and an isolation groove are formed in one photolithography and etching process (i.e., using a mask), the opening can be used to lead out the through contact, and the isolation groove can be used to achieve electrical isolation between the lead-out structure of the through contact and the semiconductor layer used as a common source. By using the raised portion on the second side of the semiconductor layer, at least a portion of the raised portion is removed, which can avoid damage to, for example, the channel structure located on the first side of the semiconductor layer, which is beneficial to improving the yield. At the same time, after at least a portion of the raised portion is removed, the surface of the semiconductor layer is relatively flat, which is more friendly to the subsequent thin film deposition process on the surface of the semiconductor layer. Compared with the above embodiment, a mask can also be saved, which is beneficial to reducing the difficulty and cost of manufacturing.

[0047] FIG. 3A to FIG. 3D is based on Figure 2 A schematic cross-sectional view of a semiconductor device during the manufacturing process is shown in the manufacturing method. Figure 4 is based on Figure 2 A schematic top view of a semiconductor device formed by the manufacturing method is shown. Figure 5 yes Figure 3A FIG. 1 is a partial enlarged schematic diagram of region C shown in FIG. 1 . It should be noted that in order to clearly show the spatial relationship between the components in the semiconductor device, Figure 4 The perspective relationship of the components shown has been appropriately adjusted. FIG. 3A to FIG. 3D Can be along Figure 4 The cross-sectional schematic diagram of the line A-A' and the line BB' is shown. FIG. 3A to FIG. 3D , Figure 4 as well as Figure 5 The above steps S210 and S220 are explained by way of example.

[0048] In step S210, Figure 3A As shown, the semiconductor structure 300a (excluding the mask layer 301) may be an intermediate structure of a semiconductor device that is finally formed. For example, the semiconductor device may be a 3D NAND memory or a part of a 3D NAND memory. It should be noted that the semiconductor structure 300a may be formed by any process known in the art. The components in the semiconductor structure 300a are exemplarily described below.

[0049] In the semiconductor structure 300a, the semiconductor layer 311 may extend laterally on a plane perpendicular to the z-direction. For example, the semiconductor layer 311 may be roughly plate-shaped. In some embodiments, the material of the semiconductor layer 311 may include single crystal silicon, polycrystalline silicon, amorphous silicon, or any other suitable semiconductor material. For example, the material of the semiconductor layer 311 is polycrystalline silicon. For another example, the semiconductor layer 311 may be doped with an N-type or P-type dopant. The semiconductor layer 311 has a protrusion 312, which will be described in detail below.

[0050] In some embodiments, the stacked structure 321 may be located on one side of the semiconductor layer 311 (hereinafter referred to as the first side of the semiconductor layer 311). The stacked structure 321 may include dielectric layers 322 and gate layers 323 alternately arranged in the z direction. The more stacked layers of the dielectric layer 322 and the gate layer 323, the higher the integration of the memory cell, that is, the greater the unit storage density. The material of the dielectric layer 322 may include silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. The material of the gate layer 323 may include tungsten, cobalt, copper, aluminum, polysilicon, silicide, or any other suitable conductive material. For example, the gate layer 323 may include a conductive layer and an adhesive layer and a gate barrier layer (not shown) that sequentially surround the conductive layer.

[0051] In some embodiments, the plurality of channel structures 342 penetrate the stacked structure 321 and extend to the semiconductor layer 311. Figure 5 As shown, the channel structure 342 may include a functional layer 343 and a channel layer 344 arranged in sequence from the outside to the inside. The functional layer 343 may be a tubular structure with two ends open, which penetrates the stack structure 321 and extends to the semiconductor layer 311. The functional layer 343 may include a blocking layer 3431, a charge capture layer 3432, and a tunneling layer 3433 arranged in sequence from the outside to the inside. For example, the materials of the blocking layer 3431, the charge capture layer 3432, and the tunneling layer 3433 may be silicon oxide, silicon nitride, and silicon oxide in sequence. The channel layer 344 may be a tubular structure with one end closed, which penetrates the stack structure 321 and extends to the semiconductor layer 311. The material of the channel layer 344 may include single crystal silicon, polycrystalline silicon, amorphous silicon, or any other appropriate semiconductor material. For example, the material of the channel layer 344 may be the same as that of the semiconductor layer 311. Optionally, the inner side of the channel layer 344 may be at least partially filled with an insulating material.

[0052] In some embodiments, Figure 5As shown, the portion of the channel structure 342 surrounded by a gate layer 323 and a portion of the gate layer 323 constitute a memory cell MC. A plurality of memory cells MC are arranged in series along the extension direction (e.g., z direction) of the channel structure 342 to constitute a memory string, and share the channel layer 344. The remaining portion of the gate layer 323 can be used as a word line connecting a plurality of memory cells MC at the same height in different memory strings. For example, by applying a voltage to the gate layer 323, the memory cell MC can cause the charge in the channel layer 344 to enter the charge capture layer 3432, or cause the charge in the charge capture layer 3432 to return to the channel layer 344, thereby placing the memory cell MC in a programmed state or an erased state (unprogrammed state).

[0053] In some embodiments, Figure 3A and Figure 5 As shown, the semiconductor layer 311 contacts the channel layer 344 of each of the plurality of channel structures 342 (eg, the plurality of channel structures 342 in the same memory block). For example, the semiconductor layer 311 may serve as a common source of the memory cell array in the same memory block.

[0054] like Figure 3A and Figure 4 As shown, the gate line gap structure 332 (hereinafter referred to as the first gate line gap structure 332) is located at the first side of the semiconductor layer 311 and extends to the semiconductor layer 311 along the z direction. In some embodiments, the first gate line gap structure 332 penetrates the stacked structure 321 to the semiconductor layer 311. The first gate line gap structure 332 may also extend (e.g., continuously extend) along the x direction, and the first gate line gap structures 332 adjacent to each other in the y direction may define the storage block BLK. For example, the first gate line gap structure 332 may be a wall-like structure extending continuously along the x direction, which may include a polysilicon layer 3321 and an insulating layer 3322 located on opposite sides of the polysilicon layer 3321 in the y direction. Optionally, in the storage block BLK, a plurality of second gate line gap structures 333 may be further provided between adjacent first gate line gap structures 332. The second gate line gap structure 333 may penetrate the stacked structure 321 to the semiconductor layer 311 and extend along the x direction. For example, the second gate line gap structure 333 may extend discontinuously in the x-direction (not shown). The second gate line gap structure 333 may be used to provide mechanical support.

[0055] Reference below Figure 3A The raised portion 312 is described in detail. Figure 3AAs shown, the protrusion 312 may be located on a side of the semiconductor layer 311 away from the stacked structure 321 (hereinafter referred to as the second side), and the protrusion 312 is at least partially aligned with the first gate line gap structure 332. For example, the protrusion 312 and the semiconductor layer 311 may be an integral structure, in other words, there is no clear interface between the two. For another example, the protrusion 312 may extend along the x-direction, and the protrusion 312 has a strip-shaped structure. It should be noted that in the case where the semiconductor structure 300a includes a second gate line gap structure 333, the protrusion 312 may also be at least partially aligned with the second gate line gap structure 333.

[0056] In some embodiments, Figure 3A As shown, the insulating structure 324 may be located on the first side of the semiconductor layer 311 and arranged in parallel with the stacked structure 321. For example, the insulating structure 324 and the stacked structure 321 are located in different regions relative to the extension plane of the semiconductor layer 311. The material of the insulating structure 324 may include silicon oxide, silicon nitride, silicon oxynitride or any other appropriate insulating material.

[0057] The through contact 331 is located at the first side of the semiconductor layer 311 and extends to the semiconductor layer 311 along the z direction. In some embodiments, the through contact 331 penetrates the insulating structure 324 to the semiconductor layer 311. For example, the through contact 331 can be a substantially columnar structure. The material of the through contact 331 can include tungsten, cobalt, copper, aluminum, titanium, titanium nitride, or any other suitable conductive material.

[0058] In some embodiments, the interconnection layer 353 may be located on a side of the stacked structure 321 and the insulating structure 324 away from the semiconductor layer 311. For example, the interconnection layer 353 may include a plurality of contact via structures 3531 and a plurality of interconnection line structures 3532 alternately arranged in the z direction. The contact via structures 3531 may extend longitudinally in the z direction, and the interconnection line structures 3532 may extend laterally in a plane perpendicular to the z direction. The materials of the contact via structures 3531 and the interconnection line structures 3532 may include, but are not limited to, tungsten, cobalt, copper, aluminum, titanium, titanium nitride, or any other suitable conductive material.

[0059] In some embodiments, the semiconductor structure 300a may further include a peripheral circuit structure 351. The peripheral circuit structure 351 may be located on a side of the interconnect layer 353 away from the semiconductor layer 311. For example, the peripheral circuit structure 351 may be connected (e.g., electrically connected) to the interconnect layer 353 via a bonding layer 352. The peripheral circuit structure 351 may be used to provide a peripheral circuit that controls the memory cell array to implement various operations such as writing, reading, and erasing. Exemplarily, the peripheral circuit may include, but is not limited to, a page buffer / sense amplifier, a decoder (e.g., a row decoder or a column decoder), a word line driver, an input / output (I / O) circuit, a charge pump, a voltage source or a voltage generator, a current or voltage reference, and the like. It should be noted that the bonding referred to in the present application may be any appropriate bonding technology, such as hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, eutectic bonding, and the like.

[0060] In some embodiments, the through-contact 331 may be electrically connected to the peripheral circuit structure 351 , for example, through an interconnect layer 353 and a bonding layer 352 .

[0061] In some embodiments, the stop layer 341 may conformally cover the surface of the semiconductor layer 311 at the second side of the semiconductor layer 311. The material of the stop layer 341 may include silicon oxide, silicon nitride, silicon oxynitride or any other appropriate insulating material.

[0062] In step S220, Figure 3A and 3B As shown, the semiconductor layer 311 may be etched by an etching process (e.g., dry etching) to remove at least a portion of the protrusion 312 and form an opening 361 and an isolation groove 371 that expose the through contact 331. In the plane perpendicular to the z direction, at least a portion of the isolation groove 371 is located between the protrusion 312 and the opening 361. The opening 361 may be used to lead out the through contact 331, and the isolation groove 371 may be used to achieve electrical isolation between the lead-out structure of the through contact (corresponding to the opening 361) and the semiconductor layer used as a common source (i.e., the portion of the semiconductor layer 311 corresponding to the first gate line gap structure 332).

[0063] In some embodiments, an initial mask layer (not shown) may be formed on one side of the semiconductor layer 311 away from the stacked structure 321. The initial mask layer has no pattern. For example, when the material of the initial mask layer is a photoresist, a spin coating process may be first used to cover the surface of the semiconductor layer 311 (or the stop layer 341). The initial mask layer may then be exposed using a mask having a first pattern, and the initial mask layer may be developed to transfer the first pattern from the mask to the mask layer 301. It should be noted that the first pattern may correspond to the portion of the semiconductor layer 311 to be etched. Specifically, the first pattern may expose the opening 361 and the isolation trench 371 to be formed and expose the protrusion 312. The mask layer 301 having the first pattern is then used as a masking layer to etch the semiconductor layer 311 (or the stop layer 341 is first etched, and then the semiconductor layer 311 is etched), thereby forming the opening 361 and the isolation trench 371 and removing at least a portion of the protrusion 312. In some examples, a portion of the protrusion 312 may be removed to reduce the height of the protrusion 312 in the z direction. For example, for the semiconductor layer 311 with a portion of the protrusion 312 removed, in the z direction, the distance between the portion of the semiconductor layer 311 away from the first surface 313 of the stacked structure 321 corresponding to the first gate line gap structure 332 and the other portions of the first surface 313 is less than In some other examples, the protrusion 312 may be completely removed, so that the semiconductor layer 311 is substantially flush away from the first surface 313 of the stacked structure 321 (not shown).

[0064] In some embodiments, Figure 3B and Figure 4 As shown, the isolation trench 371 (corresponding to Figure 4 The isolation structure 372 shown in FIG. 1 may surround the memory block BLK. The opening 361 (corresponding to Figure 4 The conductive contact 362 shown is located outside the annular region defined by the isolation trench 371. In this way, the isolation trench 371 can achieve electrical isolation between the inside and outside of the annular region defined by it. In other embodiments, the isolation trench (not shown) can surround a set of openings 361, which is not limited in the present application.

[0065] In some embodiments, Figure 3B and Figure 4 As shown, on a plane parallel to the semiconductor layer 311, the size of the opening 361 is larger than the size of the through contact 331. For example, the minimum diameter of the opening 361 is larger than the maximum diameter of the through contact 331. In this way, it is possible to avoid the opening 361 being unable to fully expose the through contact 331 due to process deviation, thereby affecting the electrical performance after the through contact 331 is led out through the opening 361.

[0066] In some embodiments, Figure 2 As shown, the manufacturing method 200 may further include the following steps.

[0067] Step S230 , forming an insulating layer on the sidewalls of the opening and the isolation trench.

[0068] Step S240 , forming a metal layer filling the opening and the isolation trench and covering the surface of the stop layer.

[0069] In step S250 , a portion of the metal layer covering the surface of the stop layer is removed to the stop layer, so that the remaining metal layer is connected to the metal layer filled in the opening.

[0070] In step S230, if Figure 3C As shown, a first insulating layer 363 and a second insulating layer 373 may be formed on the sidewalls of the opening 361 and the sidewalls of the isolation trench 371, respectively. For example, a thin film deposition process of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or any combination thereof may be used to form an insulating layer on the inner wall of the opening 361, the inner wall of the isolation trench 371 and the surface of the stop layer 341, and the first insulating layer 363 and the second insulating layer 373 are formed by removing a portion of the insulating layer located at the bottom of the opening 361, the bottom of the isolation trench 371 and the surface of the stop layer 341. For example, the stop layer 341 may have an opening that exposes the semiconductor layer 311 corresponding to the first gate line gap structure 332. The materials of the first insulating layer 363 and the second insulating layer 373 may include silicon oxide, silicon nitride, silicon oxynitride or any other appropriate insulating material. The thickness of the first insulating layer 363 and the second insulating layer 373 may be adjusted. For example, the parasitic capacitance may be reduced by adjusting the thickness of the first insulating layer 363 and the second insulating layer 373.

[0071] In step S240, if Figure 3C As shown, a metal layer (not shown) can be formed on the surface of the stop layer 341 away from the semiconductor layer 311 by using a thin film deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or any combination thereof. The metal layer fills the opening 361 and the isolation trench 371, and covers the surface of the stop layer 341. The material of the metal layer may include tungsten, cobalt, copper, aluminum, titanium or any other appropriate metal material. Due to the protrusion 312 (refer to Figure 3A ) is removed, so that the first surface 313 of the semiconductor layer 311 away from the stacked structure 321 is relatively flat, which is beneficial to improving the coverage performance of the metal layer. For example, when the distance between the portion of the first surface 313 of the semiconductor layer 311 corresponding to the first gate line gap structure 332 and the other portions of the first surface 313 is less than When , the coverage performance of the metal layer is effectively improved. In some embodiments, such as Figure 3DAs shown, the first insulating layer 363 and the opening 361 (refer to Figure 3C ) The metal layer inside (ie, the first metal portion 364) can form a conductive contact 362. The second insulating layer 373 and the isolation trench 371 (refer to Figure 3C ) The metal layer inside (ie, the second metal portion 374) can form an isolation structure 372.

[0072] In step S250, if Figure 3D and Figure 4 As shown, a portion of the metal layer formed in step S240 and covering the surface of the stop layer 341 can be removed by photolithography and etching (e.g., dry etching) processes, and the retained metal layer can form a metal wiring layer 381. For example, the metal wiring layer 381 can include a plurality of metal wires, which can connect the portion of the semiconductor layer 311 corresponding to the first gate line gap structure 332 to the conductive contact 362. Signal transmission between the semiconductor layer 311 as a common source and the peripheral circuit structure 351 is achieved through the metal wiring layer 381, the conductive contact 362, and the through contact 331. In addition, the stop layer 341 can stop the etching of a portion of the metal layer on its surface or inside to avoid damage to the semiconductor layer 311 below.

[0073] The present application also provides a semiconductor device. Figure 3D and Figure 4 As shown, the semiconductor device 300 includes a semiconductor layer 311, a through contact 331, a gate line gap structure 332 (hereinafter referred to as the first gate line gap structure 332), a conductive contact 362 and an isolation structure 372. The through contact 362 is located on a first side of the semiconductor layer 311 and extends along the z direction. The first gate line gap structure 332 is located on a first side of the semiconductor layer and extends to the semiconductor layer 311 along the z direction. The conductive contact 362 penetrates the semiconductor layer 311 and is connected (e.g., electrically connected) to the through contact 331. The isolation structure 372 penetrates the semiconductor layer 311. On a plane perpendicular to the z direction, at least a portion of the isolation structure 372 is located between the conductive contact 362 and the first gate line gap structure 332.

[0074] In some embodiments, the semiconductor layer 311 has a first surface 313 away from the first gate line gap structure 332. In the z direction, the distance between the portion of the first surface 313 corresponding to the first gate line gap structure 332 and the other portions of the first surface 313 is less than

[0075] In some embodiments, the conductive contact 362 includes a first metal portion 364 and a first insulating layer 363 located on an outer sidewall of the first metal portion. The first metal portion 364 is connected (e.g., electrically connected) to the through contact 331. The isolation structure 372 includes a second metal portion 374 and a second insulating layer 373 located on an outer sidewall of the second metal portion 374.

[0076] In some embodiments, in a plane perpendicular to the z-direction, a dimension (eg, a minimum diameter) of the conductive contact 362 is larger than a dimension (eg, a maximum diameter) of the through contact 331 .

[0077] In some embodiments, the semiconductor device 300 may further include a stop layer 341 and a metal wiring layer 381. The stop layer 341 may be located on the first surface 313 of the semiconductor layer 311 and have an opening exposing a portion of the semiconductor layer 311 corresponding to the first gate line gap structure 332. The metal wiring layer 381 may be located on a side of the stop layer 341 away from the semiconductor layer 311, and include a metal wire connected to the conductive contact 362 and a portion of the semiconductor layer 311 corresponding to the first gate line gap structure 332. Exemplarily, the material of the stop layer 341 includes silicon oxide, and the material of the metal wiring layer 381 includes aluminum.

[0078] In some embodiments, the first gate line gap structure 332 also extends along the x direction, and the first gate line gap structures 332 adjacent to each other in the y direction define the storage block BLK. The isolation structure 372 is annular. In a plane perpendicular to the z direction, the isolation structure 372 surrounds the storage block BLK, and the conductive contact 362 is located outside the annular area defined by the isolation structure 372.

[0079] In some embodiments, the semiconductor device 300 may further include a stacked structure 321 and an insulating structure 324. The stacked structure may be located at a first side of the semiconductor layer 311. The first gate line gap structure 332 may penetrate the stacked structure 321. The insulating structure 324 may be located at a first side of the semiconductor layer 311 and arranged in parallel with the stacked structure 321. The through contact 331 may penetrate the insulating structure 324.

[0080] In some embodiments, the semiconductor device 300 may further include a channel structure 342 . The channel structure 342 may penetrate the stack structure 321 and extend to the semiconductor layer 311 .

[0081] In some embodiments, the semiconductor device 300 may further include a peripheral circuit structure 351. The peripheral circuit structure 351 is connected (eg, electrically connected) to the channel structure 342 at a side of the stack structure 321 away from the semiconductor layer 311. The through contact 331 may also be connected (eg, electrically connected) to the peripheral circuit structure 351.

[0082] Since the contents and structures involved in the above description of the preparation method 200 can be fully or partially applied to the semiconductor device described here, the related or similar contents will not be repeated.

[0083] An embodiment of the present application also provides a memory system. Figure 6 is a block diagram of a system having a memory system according to an exemplary embodiment of the present application.

[0084] The system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Figure 6 As shown, the system 11 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0085] The three-dimensional memory 14 may include a semiconductor device described in any embodiment of the present application, for example, Figure 3D and Figure 4The semiconductor device 300 is shown. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media-card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate functions may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0086] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig. 7AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Figure 6 The host 18 in the memory card connector 24 is coupled. Figure 7B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 6 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0087] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor layer and a through contact and a gate line gap structure located on a first side of the semiconductor layer, the through contact and the gate line gap structure extending to the semiconductor layer along a first direction perpendicular to the semiconductor layer, the semiconductor layer having a protrusion, the protrusion being located on a second side of the semiconductor layer opposite to the first side and at least partially aligned with the gate line gap structure; and The semiconductor layer is etched from the second side to remove at least a portion of the protrusion and form an opening exposing the through contact and an isolation trench, wherein at least a portion of the isolation trench is located between the protrusion and the opening on a plane perpendicular to the first direction.

2. The manufacturing method according to claim 1, wherein: Etching the semiconductor layer from the second side to remove at least a portion of the protrusion and form an opening and an isolation trench exposing the through contact comprises: forming a mask layer having a first pattern on a second side of the semiconductor layer, wherein the first pattern exposes the opening, the isolation trench, and the protrusion; and The semiconductor layer is etched using the mask layer to remove at least a portion of the protrusion and form the opening and the isolation trench.

3. The manufacturing method according to claim 1, wherein: In a plane parallel to the semiconductor layer, a size of the opening is larger than a size of the through contact.

4. The manufacturing method according to claim 1, wherein: The method further comprises: An insulating layer is formed on sidewalls of the opening and the isolation trench.

5. The manufacturing method according to claim 1, wherein: The semiconductor structure further includes a stop layer, the stop layer covering a surface of the semiconductor layer at the second side, wherein etching the semiconductor layer from the second side to remove at least a portion of the protrusion and form an opening and an isolation trench exposing the through contact further includes: The stop layer is etched from the second side to remove a portion of the stop layer covering the protrusion.

6. The manufacturing method according to claim 5, wherein: The stop layer is an insulating material. After the insulating layer is formed on the sidewalls of the opening and the isolation trench, the method further includes: forming a metal layer filling the opening and the isolation trench and covering the surface of the stop layer; and A portion of the metal layer covering the surface of the stop layer is removed to the stop layer, so that the remaining metal layer is connected to the metal layer filled in the opening.

7. The manufacturing method according to any one of claims 1 to 6, wherein: The gate line gap structure also extends along a second direction parallel to the semiconductor layer, the gate line gap structures adjacent to each other in the third direction define a storage block, and the isolation trench is annular; On a plane perpendicular to the first direction, the isolation trench surrounds the storage block, the opening is located outside the annular region defined by the isolation trench, and the third direction is perpendicular to the first direction and the second direction.

8. A semiconductor device, characterized in that: include: Semiconductor layer; a through contact located at a first side of the semiconductor layer and extending in a first direction perpendicular to the semiconductor layer; a gate line gap structure, located on the first side of the semiconductor layer and extending to the semiconductor layer along the first direction; A conductive contact penetrating the semiconductor layer and connected to the through contact; as well as The isolation structure penetrates the semiconductor layer, and on a plane perpendicular to the first direction, at least a portion of the isolation structure is located between the conductive contact and the gate line gap structure.

9. The semiconductor device according to claim 8, wherein: The semiconductor layer has a first surface away from the gate line gap structure, and in the first direction, a distance between a portion of the first surface corresponding to the gate line gap structure and other portions of the first surface is less than 10. The semiconductor device according to claim 8, wherein The conductive contact comprises a first metal portion and a first insulating layer located on an outer side wall of the first metal portion, wherein the first metal portion is connected to the through contact; The isolation structure includes a second metal portion and a second insulating layer located on an outer sidewall of the second metal portion.

11. The semiconductor device according to claim 8, wherein On a plane parallel to the semiconductor layer, a size of the conductive contact is larger than a size of the through contact.

12. The semiconductor device according to claim 9, wherein: Also includes: a stop layer, located on the first surface of the semiconductor layer and having an opening exposing a portion of the semiconductor layer corresponding to the gate line gap structure; as well as The metal wiring layer is located on a side of the stop layer away from the semiconductor layer, and includes metal wires connected to the conductive contacts and a portion of the semiconductor layer corresponding to the gate line gap structure.

13. The semiconductor device according to claim 12, wherein: The material of the stop layer includes silicon oxide, and the material of the metal wiring layer includes aluminum.

14. The semiconductor device according to claim 8, wherein: The gate line gap structure also extends along a second direction parallel to the semiconductor layer, the gate line gap structures adjacent to each other in the third direction define a storage block, and the isolation structure is annular; On a plane perpendicular to the first direction, the isolation structure surrounds the storage block, the conductive contact is located outside the annular region defined by the isolation structure, and the third direction is perpendicular to the first direction and the second direction.

15. The semiconductor device according to any one of claims 8 to 14, wherein: Also includes: a stacked structure located on the first side of the semiconductor layer; as well as an insulating structure, located at the first side of the semiconductor layer and arranged in parallel with the stacking structure; Wherein, the gate line gap structure penetrates the stacking structure, and the through contact penetrates the insulating structure.

16. The semiconductor device according to claim 15, wherein: Also includes: The channel structure penetrates the stacked structure and extends to the semiconductor layer.

17. The semiconductor device according to claim 16, wherein: Also includes: A peripheral circuit structure connected to the channel structure on a side of the stacked structure away from the semiconductor layer; Wherein, the through contact is connected to the peripheral circuit structure.

18. A memory system, characterized in that: include: A three-dimensional memory comprising at least one semiconductor device according to any one of claims 8 to 17; as well as The controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data.

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