Chip identity generation circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of electronics, in particular to a chip identity generation circuit, a chip and electronic equipment. The identity identification generation circuit comprises an identification sequence generation circuit and a plurality of sub-identification generation circuits, wherein each sub-identification generation circuit is used for receiving an input signal and outputting a corresponding output signal under the triggering of the input signal; and the identification sequence generation circuit is used for receiving the input signal and the output signal corresponding to each sub-identification generation circuit and generating an identity identification sequence according to the input signal and the output signal, and the identity identification sequence is used for representing the unique identity identification of one chip. The identity label generation circuit is simple in circuit structure, the generated identity label sequence is convenient to read, related burning and reading circuits do not need to be arranged, the occupied area of a chip is small, and the production cost of the chip is reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a chip identity generation circuit, a chip, and an electronic device. Background Art

[0002] In order to effectively trace the chip manufacturer information, production date, production line, chip coordinates on the wafer and other information when the chip breaks down or fails, a unique identity is usually set for the chip during the chip generation process. The identity can provide effective clues for chip failure or malfunction cause analysis.

[0003] In the related art, eFuse (Electrically programmable Fuse, one-time programmable memory) is mainly set in each chip, and then the identity information corresponding to the chip is burned in the eFuse. When the chip fails, the identity in the eFuse of the chip can be read. The identity information of a general chip mainly includes the XY coordinates of the chip on the wafer. It is understandable that when there are a large number of chips on a wafer, multiple groups of eFuses need to be set on each chip to record the identity of the chip. Due to the complex circuit structure of the eFuse, the occupied area of ​​multiple eFuses on a single chip is large; and each chip also needs to be equipped with a burning circuit and a reading circuit supporting the eFuse, which will also occupy a large area, thereby making the production cost of the chip higher. Summary of the invention

[0004] The present application provides a chip identity generation circuit, a chip and an electronic device to solve the technical problem of high chip production cost in related technologies.

[0005] In a first aspect, the present application provides a chip identity generation circuit for generating an identity of a chip, wherein the identity generation circuit comprises an identity sequence generation circuit and a plurality of sub-identity generation circuits;

[0006] Each sub-identification generation circuit is used to receive an input signal and output a corresponding output signal under the triggering of the input signal; the identification sequence generation circuit is used to receive the input signal and output signal corresponding to each of the sub-identification generation circuits;

[0007] The identification sequence generating circuit is further used to generate an identity identification sequence according to the multiple output signals corresponding to the multiple sub-identification generating circuits;

[0008] Alternatively, the identification sequence generating circuit is further used to generate a deviation value according to the input signal and the output signal corresponding to each of the sub-identification generating circuits, and to generate an identity identification sequence according to the plurality of deviation values;

[0009] Alternatively, the identification sequence generating circuit is further used to obtain a trigger value of the input signal when a state of an output signal corresponding to each of the sub-identification generating circuits changes; and to generate an identity identification sequence according to the trigger values ​​corresponding to the multiple sub-identification generating circuits;

[0010] The identity sequence is used to represent the unique identity of a chip.

[0011] In one possible design, the identity generation circuit further includes a plurality of switch circuits;

[0012] Each of the sub-identification generation circuits is connected to at least one switch circuit; the switch circuit is used to receive a control signal, and the control signal is used to control the conduction or shutdown of the switch circuit, thereby controlling the conduction or shutdown of the corresponding sub-identification generation circuit.

[0013] In a possible design, the sub-identification generating circuit is an operational amplifier; the input signal is a reference voltage signal, and the output signal is a clamping voltage signal;

[0014] The operational amplifier is used to receive an input reference voltage signal and clamp the reference voltage signal to output a corresponding clamp voltage signal;

[0015] The identification sequence generating circuit is used to generate a voltage deviation value according to the clamping voltage signal and the reference voltage signal corresponding to each of the operational amplifier circuits, and to generate the identity identification sequence according to the voltage deviation values ​​corresponding to the plurality of operational amplifiers.

[0016] In a possible design, the operational amplifier is a two-stage operational amplifier composed of multiple transistors.

[0017] In one possible design, the operational amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a first capacitor;

[0018] The first electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the first transistor is connected to the second electrode of the fourth transistor, the control electrode of the first transistor is short-circuited with the second electrode of the first transistor, and the first electrode of the fourth transistor is connected to the first electrode of the fifth transistor; the control electrode of the first transistor is connected to the control electrode of the second transistor, the second electrode of the second transistor is connected to the second electrode of the fifth transistor, and the control electrode of the fifth transistor is the input terminal of the operational amplifier;

[0019] The first electrode of the third transistor is connected to the first electrode of the second transistor, the control electrode of the third transistor is connected to the second electrode of the third transistor through the first capacitor, the second electrode of the third transistor is connected to the second electrode of the ninth transistor, and the first electrode of the ninth transistor is grounded; the second electrode of the sixth transistor is connected to the first electrode of the third transistor, the control electrode of the sixth transistor is connected to the second electrode of the third transistor, the first electrode of the sixth transistor is connected to the second electrode of the tenth transistor, the first electrode of the tenth transistor is grounded, and the control electrode of the fourth transistor is also connected to the second electrode of the tenth transistor;

[0020] The second electrode of the seventh transistor is used to receive the current signal, the first electrode of the seventh transistor is grounded, and the second electrode of the seventh transistor and the control electrode are short-circuited; the second electrode of the eighth transistor is connected to the first electrode of the fourth transistor; and the first electrode of the eighth transistor is grounded;

[0021] The control electrodes of the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are short-circuited with each other.

[0022] In a possible design, each of the sub-identification generation circuits is connected to the first switch circuit and the second switch circuit respectively;

[0023] Wherein, the first switch circuit includes an eleventh transistor and a first current source; the second switch circuit includes a twelfth transistor;

[0024] The positive electrode of the first current source is used to connect to the power supply, the negative electrode of the first current source is connected to the first electrode of the eleventh transistor, and the second electrode of the eleventh transistor is connected to the second electrode of the seventh transistor; the first electrode of the twelfth transistor is used to connect to the power supply, and the second electrode of the twelfth transistor is connected to the first electrode of the third transistor;

[0025] The control electrode of the eleventh transistor and the control electrode of the twelfth transistor are both used to receive a first control signal; the first control signal is used to control the conduction or off-state of the eleventh transistor and / or the twelfth transistor, thereby controlling the conduction or off-state of the corresponding operational amplifier.

[0026] In one possible design, the sub-identification generation circuit includes a thirteenth transistor, a first resistor, a second resistor, and an inverter;

[0027] The first electrode of the thirteenth transistor is connected to the first end of the first resistor, the second end of the first resistor is used to connect to the power supply, the second electrode of the thirteenth transistor is grounded, and the first electrode of the thirteenth transistor is connected to the input end of the inverter; the control electrode of the thirteenth transistor is used to receive the input signal, and the output end of the inverter is used to output the output signal;

[0028] The identification sequence generating circuit is further used to obtain the trigger value of the input signal when the output signal of the inverter in each of the sub-identification generating circuits is flipped from a low level to a high level; and generate the identity identification sequence according to the trigger values ​​corresponding to the multiple sub-identification generating circuits.

[0029] In one possible design, the sub-identification generation circuit is connected to a third switch circuit, and the third switch circuit includes a fourteenth transistor;

[0030] The first electrode of the fourteenth transistor is used to connect to a power supply, the second electrode of the fourteenth transistor is connected to the second end of the second resistor, and the control electrode of the fourteenth transistor is used to receive a second control signal; the second control signal is used to control the conduction or off-state of the fourteenth transistor, thereby controlling the conduction or off-state of the corresponding sub-identification generation circuit.

[0031] In a second aspect, the present application also provides a chip, which includes the chip identity generation circuit as described above.

[0032] In a third aspect, the present application also provides an electronic device, which includes the chip as described above.

[0033] The chip identity generation circuit provided by the first aspect above has a simple circuit structure compared to the eFuse structure in the related art, and the generated identity sequence is easy to read without the need for related burning and reading circuits, which reduces the chip's occupied area and reduces the chip's production cost.

[0034] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of a chip identity generation circuit structure provided in an embodiment of the present application;

[0036] Figure 2 A schematic diagram of the structure of an operational amplifier provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of the structure of a sub-identification generation circuit provided in this application. DETAILED DESCRIPTION

[0038] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0039] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0040] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] The transistor in the present application is a three-terminal transistor, and its three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor.

[0042] In order to overcome the technical problem in the related art that the eFuse and supporting circuits used to store the chip identity need to occupy a large area, resulting in a high production cost of the chip. This application is based on the random deviation value generated in the chip manufacturing process as the chip identity. Since the chip circuit has the same circuit structure, there will be slight differences in the performance of the circuit due to the differences in the production process of the components that make up the circuit. For example, for multiple circuits with the same structure, when the same signal is input, there are differences in their output signals, or there are differences in the deviation values ​​of the input signal and the output signal, or there are differences in the trigger value of a circuit. In this way, different output values, deviation values ​​or trigger values ​​can be used to characterize the identity information of the chip.

[0043] Based on the above concept, the present application provides a chip identity generation circuit, which includes an identification sequence generation circuit and multiple sub-identification generation circuits, wherein each sub-identification generation circuit is used to receive an input signal and output a corresponding output signal under the trigger of the input signal; the identification sequence generation circuit is used to receive the input signal and output signal corresponding to each sub-identification generation circuit, and generate an identity sequence according to multiple output signals, multiple deviation values ​​or trigger values, and the identity sequence is used to characterize the unique identity of a chip. In order to avoid the situation where the chip identity is not unique, multiple output signals, multiple deviation values ​​or trigger values ​​are used to generate an identity sequence, which can ensure the uniqueness of the chip identity. And the chip identity generation circuit provided by the present application has a simple structure, and the generated identity sequence is easy to read, without the need to be equipped with related burning and reading circuits, so that the chip occupies a small area and reduces the production cost of the chip.

[0044] Figure 1 For a schematic diagram of the chip identity generation circuit structure provided in the embodiment of the present application, please refer to Figure 1 As shown, the chip identity generation circuit includes an identification sequence generation circuit and multiple sub-identification generation circuits. For example, the multiple sub-identification generation circuits are respectively as follows Figure 1The first sub-identification generation circuit, the second sub-identification generation circuit, ... the Nth sub-identification generation circuit.

[0045] Each sub-identification generation circuit is used to receive an input signal and output a corresponding output signal under the triggering of the input signal; the identification sequence generation circuit is used to receive the input signal and output signal corresponding to each sub-identification generation circuit; the identification sequence generation circuit is also used to generate an identity identification sequence according to the multiple output signals corresponding to the multiple sub-identification generation circuits. For example, if multiple sub-identification generation circuits input the same input signal, then due to the deviation of the components constituting each sub-identification generation circuit, the output signals output by each sub-identification generation circuit are different. For example, the identification sequence generation circuit generates an identity identification sequence of a1, a2, a3, a4, a5, and a6 according to the multiple output signals. For example, a1 is the first sub-identification included in the output signal of the first sub-identification generation circuit.

[0046] It can be understood that each identity sequence includes different sub-identifiers and the arrangement order of each sub-identifier is also different, so each identity sequence is unique and can be used to represent the unique identity of the current chip.

[0047] The signal type of each sub-identifier may be a voltage value, a current value, a resistance value, a level signal, etc.

[0048] In some embodiments, the identification sequence generation circuit is further used to generate a deviation value according to the input signal and output signal corresponding to each sub-identification generation circuit, and generate an identity identification sequence according to multiple deviation values. For example, the deviation values ​​generated by the input signals and output signals corresponding to the multiple sub-identification generation circuits are d1, d2, ... dN, respectively, and d1 is the deviation value between the input signal and the output signal of the first sub-identification generation circuit. Then the multiple deviation values ​​can form an identity identification sequence d1, d2, ... dN.

[0049] In some embodiments, the identification sequence generation circuit is also used to obtain the trigger value of the input signal when the output signal corresponding to each sub-identification generation circuit changes state; and generate an identity identification sequence according to the trigger values ​​corresponding to multiple sub-identification generation circuits. For example, for the first sub-identification generation circuit, when its input signal is 1.211V, the trigger output signal is high, then the trigger value of the first sub-identification generation circuit can be determined as 1.211V, and so on, the trigger values ​​corresponding to multiple sub-identification generation circuits can form a group of identity identification sequences. Among them, due to the random deviations generated by the devices in each sub-identification generation circuit during the production process, the trigger values ​​of each sub-identification generation circuit have certain differences, and the identity identification sequence composed of multiple trigger values ​​in a certain order is unique, and can identify the unique identity of the chip.

[0050] In some embodiments, the identity generation circuit further includes a plurality of switch circuits; each sub-identification generation circuit is connected to at least one switch circuit, and the switch circuit is connected in series to the conduction loop of the sub-identification generation circuit. The switch circuit is used to receive a control signal, and the control signal is used to control the conduction or shutdown of the switch circuit, thereby controlling the conduction or shutdown of the corresponding sub-identification generation circuit. In this way, when the chip is working normally, the sub-identification generation circuit can be turned off by the switch circuit, that is, at this time, there is no need to read the identity of the chip generated by the identity generation circuit, which can reduce the power consumption of the chip on the one hand, and extend the service life of the identity generation circuit on the other hand.

[0051] In some embodiments, the sub-identification generation circuit may be an operational amplifier. Specifically, the sub-identification generation circuit may be an operational amplifier for voltage clamping. In this embodiment, the input signal of the input operational amplifier is a reference voltage signal, and the corresponding output signal is a clamping voltage signal. Among them, the operational amplifier is used to receive the input reference voltage signal and clamp the reference voltage signal to output a corresponding clamping voltage signal. The identification sequence generation circuit is used to generate a voltage deviation value according to the clamping voltage signal and the reference voltage signal corresponding to each operational amplifier circuit, and generate an identity identification sequence according to the voltage deviation values ​​corresponding to multiple operational amplifiers.

[0052] It is understandable that an operational amplifier of the same structure composed of multiple devices of the same specifications will have slight differences in the performance of each operational amplifier due to the deviations generated by each device during the production process. Therefore, for multiple operational amplifiers, the same reference voltage signal can be input. For example, multiple operational amplifiers all input a reference voltage signal of 4.500V. When each operational amplifier clamps the input reference voltage signal, due to different performance, it outputs a different clamping voltage signal, that is, outputs a different clamping voltage value. In this way, there are certain differences in the voltage deviation values ​​generated by the clamping voltage signal and the reference voltage signal corresponding to each operational amplifier circuit. Multiple voltage deviation values ​​can form an identity sequence to represent the unique identity of the chip.

[0053] In some embodiments, the operational amplifier may be a two-stage operational amplifier composed of multiple transistors. Generally, a two-stage operational amplifier is composed of multiple transistors, and each transistor has a certain deviation during the production process. Therefore, the combination of multiple transistors leads to a certain difference in the deviation.

[0054] Figure 2 For a schematic diagram of the operational amplifier structure provided in the embodiment of the present application, see Figure 2As shown, the operational amplifier 10 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10 and a first capacitor C1.

[0055] Among them, the first electrode of the first transistor Q1 is connected to the first electrode of the second transistor Q2, the second electrode of the first transistor Q1 is connected to the second electrode of the fourth transistor Q4, the control electrode of the first transistor Q1 is short-circuited with the second electrode of the first transistor Q1, and the first electrode of the fourth transistor Q4 is connected to the first electrode of the fifth transistor Q5; the control electrode of the first transistor Q1 is connected to the control electrode of the second transistor Q2, the second electrode of the second transistor Q2 is connected to the second electrode of the fifth transistor Q5, and the control electrode of the fifth transistor Q5 is the input end of the operational amplifier 10. The first electrode of the third transistor Q3 is connected to the first electrode of the second transistor Q2, the control electrode of the third transistor Q3 is connected to the second electrode of the third transistor Q3 through the first capacitor C1, the second electrode of the third transistor Q3 is connected to the second electrode of the ninth transistor Q9, and the first electrode of the ninth transistor Q9 is grounded; the second electrode of the sixth transistor Q6 is connected to the first electrode of the third transistor Q3, the control electrode of the sixth transistor Q6 is connected to the second electrode of the third transistor Q3, the first electrode of the sixth transistor Q6 is connected to the second electrode of the tenth transistor Q10, the first electrode of the sixth transistor Q6 is the output end of the operational amplifier 10, the first electrode of the tenth transistor Q10 is grounded, and the control electrode of the fourth transistor Q4 is also connected to the second electrode of the tenth transistor Q10.

[0056] The second electrode of the seventh transistor Q7 is used to receive a current signal, and the current signal is used to drive the operational amplifier to turn on. The first electrode of the seventh transistor Q7 is grounded, and the second electrode and the control electrode of the seventh transistor Q7 are short-circuited. The second electrode of the eighth transistor Q8 is connected to the first electrode of the fourth transistor Q4. The first electrode of the eighth transistor Q8 is grounded. The control electrodes of the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, and the tenth transistor Q10 are short-circuited.

[0057] When the operational amplifier 10 is turned on, a reference voltage signal VBG is input from the control electrode of the fifth transistor Q5 , and the first electrode of the sixth transistor Q6 outputs a corresponding clamping voltage signal Vout1 .

[0058] In this embodiment, each operational amplifier 10 is connected to the first switch circuit 20 and the second switch circuit 21, respectively. The first switch circuit 20 includes an eleventh transistor Q11 and a first current source IA; the second switch circuit 21 includes a twelfth transistor Q12. The positive electrode of the first current source IA is used to connect to the power supply AVDD, the negative electrode of the first current source IA is connected to the first electrode of the eleventh transistor Q11, and the second electrode of the eleventh transistor Q11 is connected to the second electrode of the seventh transistor Q7; the first electrode of the twelfth transistor Q12 is used to connect to the power supply AVDD, and the second electrode of the twelfth transistor Q12 is connected to the first electrode of the third transistor Q3.

[0059] Among them, the control electrode of the eleventh transistor Q11 and the control electrode of the twelfth transistor Q12 are both used to receive the first control signal EN1; the first control signal EN1 is used to control the eleventh transistor Q11 and the twelfth transistor Q12 to be turned on or off at the same time, thereby controlling the corresponding operational amplifier 10 to be turned on or off.

[0060] Generally, after the chip is produced, the XY coordinates of the chip on the wafer are obtained, and the identity of the chip is read at the same time, and the identity of the chip and the XY coordinates of the chip on the wafer are stored in correspondence.

[0061] When the chip is working normally, it is generally not necessary to read the chip's identity. The operational amplifier 10 can be turned off by the first switch circuit 20 and the second switch circuit 21, that is, at this time, there is no need to read the chip's identity generated by the identity generation circuit. This can reduce the power consumption of the chip on the one hand, and extend the service life of the identity generation circuit on the other hand. When the chip fails, the corresponding control signal is input to control the first switch circuit 20 and the second switch circuit 21 to be turned on, thereby controlling the operational amplifier 10 to start working, and the identification sequence generation circuit outputs the identity corresponding to the chip. Then, according to the identity corresponding to the chip, the XY coordinates of the chip on the wafer are found to complete the tracing of the relevant information of the chip.

[0062] For the operational amplifier 10 in the above embodiment, it is assumed that the random deviation coefficient of each transistor during the production process is A vt , the input pair of the operational amplifier 10 has a tube width of W and a length of L, and the influence of the transistor active load can be ignored. Then the average voltage deviation value of the operational amplifier 10 can be expressed as:

[0063]

[0064] Assuming that a chip includes n operational amplifiers as described above, the identity sequence can be obtained by reading the identity of the chip. The identity sequence can be expressed as [V OS0 ,VOS1 ,V OS2 ,…,V OSn ].

[0065] According to the measurement accuracy, each ±α is divided into a gear, and the probability that the voltage deviation value output by each operational amplifier falls within the range of ±α can be expressed as

[0066] For a chip including n operational amplifiers, its identity sequence [V Os0 ,V OS1 ,V OS2 ,…,V OSn The probability that each sub-marker in ] (i.e., the voltage deviation value output by each operational amplifier) ​​falls within the range of ±α can be expressed as

[0067]

[0068] Furthermore, assuming that βmV is used as the division accuracy of a gear, the probability p0 that the voltage deviation value output by each operational amplifier falls within [α, α+β] can be expressed as:

[0069]

[0070] For a chip including n operational amplifiers, its identity sequence [V OS0 ,V OS1 ,V OS2 ,…,V OSn The probability P1 that each subsequence in ] falls within the range [α,α+β] can be expressed as:

[0071]

[0072] Assume that the identity sequence [V OS0 ,V OS1 ,V OS2 ,…,V OSn ] is the same as each sub-identifier is M, then for N chips, the probability P2 that at least two chips have the same identity sequence can be expressed as:

[0073]

[0074] For example, a chip includes 8 operational amplifiers, and the average deviation value of each operational amplifier is 30mV. The operational amplifiers are divided into ±2mV levels, and the probability P3 of a single operational amplifier being within the ±2mV range is:

[0075]

[0076] Since the eight operational amplifiers are independent of each other, the probability that the deviation values ​​of the outputs of the eight operational amplifiers are all within the range of ±2mV is 0.0531529. 8 =6.37×10 -11 .

[0077] If 4mV is divided into one level, the probability that all the deviation values ​​of the eight operational amplifiers are in the same level and the same is 2.4374820164×10 -10 Assuming that there are 12,000 chips on each wafer, the probability that at least two chips on a wafer have the same identity is 1.74%; even if the customer complains about 50 chips, the probability that two of them have the same identity is 2.986E-07.

[0078] It can be seen that, by using the chip identity generation circuit provided in this embodiment, the probability that the identity sequences generated by any two chips on a wafer are the same is very low, so the identity sequence generated by the chip identity generation circuit can represent the unique identity of the chip.

[0079] It can be seen that compared with the circuit structure of setting multiple eFuses in the related technology, the chip identity identification generation circuit structure provided in this embodiment is simple, and the generated identity identification sequence is easy to read, and there is no need to be equipped with related burning and reading circuits, which makes the chip occupy a small area and reduces the production cost of the chip.

[0080] Figure 3 For a schematic diagram of a sub-identification generation circuit provided in this application, see Figure 3 As shown, the sub-identification generation circuit 31 includes a thirteenth transistor Q13, a first resistor R1, a second resistor R2 and an inverter D1; the first electrode of the thirteenth transistor Q13 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is used to connect to the power supply AVDD, the second electrode of the thirteenth transistor Q13 is grounded, and the first electrode of the thirteenth transistor Q13 is connected to the input end of the inverter D1; the control electrode of the thirteenth transistor Q13 is used to receive the input signal Vtest, and the output end of the inverter D1 is used to output the output signal Vout2. The identification sequence generation circuit is also used to obtain the trigger value of the input signal Vtest when the output signal of the inverter D1 in each sub-identification generation circuit 31 is flipped from a low level to a high level; and generate the identity identification sequence according to the trigger values ​​corresponding to the multiple sub-identification generation circuits 31.

[0081] It is understandable that due to the deviations in the production of the components constituting the sub-identification generation circuit 31, the trigger value of each sub-identification generation circuit 31 when it is turned on is different. For example, the value of the input signal Vtest when the inverter D1 of each sub-identification generation circuit 31 is flipped from a low level to a high level is recorded as the trigger value, and the trigger value is the threshold voltage for the sub-identification generation circuit 31 to be turned on. The multiple trigger values ​​output by the multiple sub-identification generation circuits 31 constitute an identity sequence, which is used to represent the identity of the chip.

[0082] Similarly, after the chip is generated, the identity sequence corresponding to each chip is read first, and the identity sequence of the chip and its corresponding identity are stored correspondingly. When the chip fails, the identity sequence of the chip can be read, and the identity of the chip can be found according to the identity sequence.

[0083] It is understandable that the identity of a general chip may include the chip's DIE ID, Lot ID, manufacturer information, production date, production line and other related information.

[0084] In some embodiments, please refer to Figure 3 As shown, the sub-identification generation circuit 31 is connected to the third switch circuit 30, and the third switch circuit 30 includes a fourteenth transistor Q14; the first electrode of the fourteenth transistor Q14 is used to connect to the power supply AVDD, the second electrode of the fourteenth transistor Q14 is connected to the second end of the second resistor R2, and the control electrode of the fourteenth transistor Q14 is used to receive the second control signal EN2; the second control signal EN2 is used to control the conduction or cutoff of the fourteenth transistor Q14, thereby controlling the conduction or cutoff of the corresponding sub-identification generation circuit 31. When the chip is working normally, the fourteenth transistor Q14 is controlled to be turned off to disconnect the sub-identification generation circuit 31, and the control electrode of the thirteenth transistor Q13 is pulled down to the ground through the first resistor R1 to reduce device aging.

[0085] It is understandable that when the chip is working normally, the sub-ID generation circuit 31 can be turned off by the third switch circuit 30 to avoid device aging, extend the working life of the sub-ID generation circuit 31, and save power consumption.

[0086] It is understandable that the number of sub-identification generation circuits 31 required to be set for each chip is determined according to the number of chips on the wafer to ensure that the identity identification sequence generated by each chip is unique.

[0087] It can be seen that compared with the circuit structure of setting multiple eFuses in the related technology, the sub-identification generation circuit structure provided in this embodiment is simple, and the generated identity identification sequence is easy to read, and there is no need to be equipped with related burning and reading circuits, which makes the chip occupy a small area and reduces the production cost of the chip.

[0088] In one embodiment, the embodiment further provides a chip, which includes the chip identity recording circuit and related functional circuits as described above. The working process and functional effects of the chip of this embodiment can refer to the above chip identity recording circuit, which will not be repeated here.

[0089] In one embodiment, the embodiment also provides an electronic device, which includes the chip as described above.

[0090] It is understandable that in other embodiments, the electronic device includes not only the above-mentioned chip, but also some related hardware, such as an outer shell, a circuit board, a power supply, and a communication interface, etc., which will not be described in detail here.

[0091] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip identity generation circuit, used to generate a chip identity, characterized in that: The identity identification generation circuit includes an identification sequence generation circuit and a plurality of sub-identification generation circuits; Each sub-identification generation circuit is used to receive an input signal and output a corresponding output signal under the triggering of the input signal; the identification sequence generation circuit is used to receive the input signal and output signal corresponding to each of the sub-identification generation circuits; The identification sequence generating circuit is further used to generate an identity identification sequence according to the multiple output signals corresponding to the multiple sub-identification generating circuits; Alternatively, the identification sequence generating circuit is further used to generate a deviation value according to the input signal and the output signal corresponding to each of the sub-identification generating circuits, and to generate an identity identification sequence according to the plurality of deviation values; Alternatively, the identification sequence generating circuit is further used to obtain a trigger value of the input signal when a state of an output signal corresponding to each of the sub-identification generating circuits changes; and to generate an identity identification sequence according to the trigger values ​​corresponding to the multiple sub-identification generating circuits; The identity sequence is used to represent the unique identity of a chip.

2. The chip identity generation circuit according to claim 1, characterized in that: The identity identification generation circuit also includes a plurality of switch circuits; Each of the sub-identification generation circuits is connected to at least one switch circuit; the switch circuit is used to receive a control signal, and the control signal is used to control the conduction or shutdown of the switch circuit, thereby controlling the conduction or shutdown of the corresponding sub-identification generation circuit.

3. The chip identity generation circuit according to claim 2, characterized in that: The sub-identification generating circuit is an operational amplifier; the input signal is a reference voltage signal, and the output signal is a clamping voltage signal; The operational amplifier is used to receive an input reference voltage signal and clamp the reference voltage signal to output a corresponding clamp voltage signal; The identification sequence generating circuit is used to generate a voltage deviation value according to the clamping voltage signal and the reference voltage signal corresponding to each of the operational amplifier circuits, and to generate the identity identification sequence according to the voltage deviation values ​​corresponding to the plurality of operational amplifiers.

4. The chip identity recording circuit according to claim 3, characterized in that: The operational amplifier is a two-stage operational amplifier composed of multiple transistors.

5. The chip identity recording circuit according to claim 3 or 4, characterized in that: The operational amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a first capacitor; The first electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the first transistor is connected to the second electrode of the fourth transistor, the control electrode of the first transistor is short-circuited with the second electrode of the first transistor, and the first electrode of the fourth transistor is connected to the first electrode of the fifth transistor; the control electrode of the first transistor is connected to the control electrode of the second transistor, the second electrode of the second transistor is connected to the second electrode of the fifth transistor, and the control electrode of the fifth transistor is the input terminal of the operational amplifier; The first electrode of the third transistor is connected to the first electrode of the second transistor, the control electrode of the third transistor is connected to the second electrode of the third transistor through the first capacitor, the second electrode of the third transistor is connected to the second electrode of the ninth transistor, and the first electrode of the ninth transistor is grounded; the second electrode of the sixth transistor is connected to the first electrode of the third transistor, the control electrode of the sixth transistor is connected to the second electrode of the third transistor, the first electrode of the sixth transistor is connected to the second electrode of the tenth transistor, the first electrode of the tenth transistor is grounded, and the control electrode of the fourth transistor is also connected to the second electrode of the tenth transistor; The second electrode of the seventh transistor is used to receive the current signal, the first electrode of the seventh transistor is grounded, and the second electrode of the seventh transistor and the control electrode are short-circuited; the second electrode of the eighth transistor is connected to the first electrode of the fourth transistor; and the first electrode of the eighth transistor is grounded; The control electrodes of the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are short-circuited with each other.

6. The chip identity recording circuit according to claim 5, characterized in that: Each of the sub-identification generation circuits is connected to the first switch circuit and the second switch circuit respectively; Wherein, the first switch circuit includes an eleventh transistor and a first current source; the second switch circuit includes a twelfth transistor; The positive electrode of the first current source is used to connect to the power supply, the negative electrode of the first current source is connected to the first electrode of the eleventh transistor, and the second electrode of the eleventh transistor is connected to the second electrode of the seventh transistor; the first electrode of the twelfth transistor is used to connect to the power supply, and the second electrode of the twelfth transistor is connected to the first electrode of the third transistor; The control electrode of the eleventh transistor and the control electrode of the twelfth transistor are both used to receive a first control signal; the first control signal is used to control the conduction or off-state of the eleventh transistor and / or the twelfth transistor, thereby controlling the conduction or off-state of the corresponding operational amplifier.

7. The chip identity recording circuit according to claim 2, characterized in that: The sub-identification generating circuit includes a thirteenth transistor, a first resistor, a second resistor and an inverter; The first electrode of the thirteenth transistor is connected to the first end of the first resistor, the second end of the first resistor is used to connect to the power supply, the second electrode of the thirteenth transistor is grounded, and the first electrode of the thirteenth transistor is connected to the input end of the inverter; the control electrode of the thirteenth transistor is used to receive the input signal, and the output end of the inverter is used to output the output signal; The identification sequence generating circuit is further used to obtain the trigger value of the input signal when the output signal of the inverter in each of the sub-identification generating circuits is flipped from a low level to a high level; and generate the identity identification sequence according to the trigger values ​​corresponding to the multiple sub-identification generating circuits.

8. The chip identity recording circuit according to claim 7, characterized in that: The sub-identification generation circuit is connected to the third switch circuit, and the third switch circuit includes a fourteenth transistor; The first electrode of the fourteenth transistor is used to connect to a power supply, the second electrode of the fourteenth transistor is connected to the second end of the second resistor, and the control electrode of the fourteenth transistor is used to receive a second control signal; the second control signal is used to control the conduction or off-state of the fourteenth transistor, thereby controlling the conduction or off-state of the corresponding sub-identification generation circuit.

9. A chip, characterized in that: It comprises a chip identity generating circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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