Capacitor array layout structure and electronic equipment

Abstract

The invention provides a capacitor array layout structure and electronic equipment, the capacitor array layout structure comprises at least two first capacitors and a plurality of second capacitors, the first capacitors and the second capacitors form a capacitor array, the first capacitors are located at the center of the capacitor array, and the plurality of second capacitors are symmetrically arranged at two opposite sides of the first capacitors. The upper pole plates of the second capacitors are connected with each other and connected with the upper pole plates of the first capacitors, the lower pole plates of the second capacitors are connected with the input signals in a one-to-one correspondence mode, and the lower pole plates of the first capacitors are connected with each other and output the output signals. The capacitor array layout structure provided by the invention not only is bilaterally symmetrical, but also realizes central symmetry and axial symmetry, so that the matching performance of capacitors in the assembly line analog-to-digital converter is improved.

Description

Technical Field

[0001] The invention relates to the field of analog-to-digital converter design, and in particular to a capacitor array layout structure and electronic equipment. Background Art

[0002] In circuit design, the function of the capacitor array layout of a pipeline analog-to-digital converter is to achieve high matching of capacitors in the capacitor array. Currently, the most commonly used method to achieve high matching of capacitors is the symmetrical layout of capacitors, that is, the capacitors in the capacitor array are placed symmetrically. However, as the accuracy requirements of pipeline analog-to-digital converters increase, the conventional layout and wiring of capacitor arrays are symmetrical, which can no longer meet the matching requirements of capacitors in pipeline analog-to-digital converters.

[0003] Therefore, how to provide a capacitor array layout structure with high matching is a problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a capacitor array layout structure to solve at least one of the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned purpose and other related purposes, the technical solution provided by this application is as follows.

[0006] In the first aspect, the present application provides a capacitor array layout structure, including: at least two first capacitors and multiple second capacitors, the first capacitors and the second capacitors constitute a capacitor array, the first capacitor is located at the center of the capacitor array, and multiple second capacitors are symmetrically arranged on two opposite sides of the first capacitor; wherein the upper plates of each second capacitor are interconnected and connected to the upper plate of the first capacitor, the lower plates of the multiple second capacitors are respectively connected to multiple input signals one by one, and the lower plates of each first capacitor are interconnected and output output signals to the outside.

[0007] In one embodiment of the present invention, the number of the first capacitors is M, the number of the second capacitors is N, and the N second capacitors are divided into S columns according to a preset column division condition, the M first capacitors are arranged in the same column, the S columns of the second capacitors are symmetrically arranged on two opposite sides of the first capacitors, a signal transmission line is arranged between two adjacent columns of capacitors, and a wire is arranged between two adjacent rows of capacitors; wherein, M≥2, N≥8, S≥2, N is an integer multiple of 8, and S is an integer multiple of 2.

[0008] In one embodiment of the present invention, the capacitor array layout structure further includes a plurality of auxiliary capacitors, and the plurality of auxiliary capacitors fill the capacitor array to protect the capacitor array.

[0009] In one embodiment of the present invention, the signal transmission line between the column where the first capacitor is located and the adjacent column includes a signal input line and a signal output line; the signal transmission line between columns other than the column where the first capacitor is located is the signal input line.

[0010] In one embodiment of the present invention, the number of signal transmission lines between two adjacent columns of capacitors is equal to the sum of the signal input lines and the signal output lines, or; the number of signal transmission lines between two adjacent columns of capacitors is equal to the sum of multiple signal input lines.

[0011] In one embodiment of the present invention, the number of signal transmission lines between two adjacent columns of capacitors is the same as the number of second capacitors in a single column.

[0012] In one embodiment of the present invention, the lower plate of the first capacitor is connected to the signal output line through the wire, the lower plate of the second capacitor is connected to the signal output line through the wire, and the upper plate of the first capacitor and the upper plate of the second capacitor are connected through a wire.

[0013] In an embodiment of the present invention, the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor, and the size of the first capacitor is equal to the size of the second capacitor.

[0014] In a second aspect, the present application also provides an electronic device comprising one or more capacitor array layout structures as described above.

[0015] The present application provides a capacitor array layout structure and an electronic device, the capacitor array layout structure includes at least two first capacitors and multiple second capacitors, the first capacitor and the second capacitor form a capacitor array, the first capacitor is located at the center of the capacitor array, and the multiple second capacitors are symmetrically arranged on the two opposite sides of the first capacitor, the upper plates of each second capacitor are interconnected and connected to the upper plate of the first capacitor, the lower plates of the multiple second capacitors are respectively connected to multiple input signals one by one, and the lower plates of each first capacitor are interconnected and output output signals to the outside. The capacitor array layout structure provided by the present application is not only bilaterally symmetrical, but also realizes central symmetry and axisymmetry, which improves the matching of capacitors in pipeline analog-to-digital converters.

[0016] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 is a connection diagram of a capacitor array in a pipeline analog-to-digital converter;

[0019] Figure 2 A schematic diagram of the layout structure of a capacitor array according to an exemplary embodiment of the present invention;

[0020] Figure 3 A schematic diagram of the layout structure of a capacitor array is shown in another exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0022] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present invention in a schematic manner, and thus the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0023] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0024] like Figure 1As shown, the wiring principle of the capacitor array in the pipeline analog-to-digital converter is as follows: the lower plates of multiple capacitors (C1-CN) are respectively connected to multiple input signals (D1-DN), the upper plates of multiple capacitors (C2-CN) are connected to the upper plate of capacitor C1, the upper plate of capacitor C1 is connected to the upper plate of the first capacitor (C01), multiple capacitors (C02-C0N) are connected in parallel with the first capacitor (C01), and the lower plate of the first capacitor (C01) outputs a signal to the outside.

[0025] In circuit design, the function of the capacitor array layout of a pipeline analog-to-digital converter is to achieve high matching of capacitors in the capacitor array. Currently, the most commonly used method to achieve high matching of capacitors is the symmetrical layout of capacitors, that is, the capacitors in the capacitor array are placed symmetrically. However, as the accuracy requirements of pipeline analog-to-digital converters increase, the conventional layout and wiring of capacitor arrays are symmetrical, which can no longer meet the matching requirements of capacitors in pipeline analog-to-digital converters.

[0026] Example 1

[0027] like Figure 2 As shown, the present application provides a capacitor array layout structure, including: at least two first capacitors and multiple second capacitors, the first capacitors and the second capacitors form a capacitor array, the first capacitor is located at the center of the capacitor array, and the multiple second capacitors are symmetrically arranged on two opposite sides of the first capacitor; wherein the upper plates of each second capacitor are interconnected and connected to the upper plate of the first capacitor, the lower plates of the multiple second capacitors are respectively connected to multiple input signals one by one, and the lower plates of each first capacitor are interconnected and output output signals to the outside.

[0028] Specifically, there are M first capacitors and N second capacitors, and the N second capacitors are divided into S columns according to a preset column division condition, the M first capacitors are arranged in the same column, and the S columns of second capacitors are symmetrically arranged on opposite sides of the first capacitors, a signal transmission line is arranged between two adjacent columns of capacitors, and a wire is arranged between two adjacent rows of capacitors; wherein, M≥2, N≥8, S≥2, N is an integer multiple of 8, and S is an integer multiple of 2. Specifically, as Figure 2 As shown, there are 2 first capacitors (C01, C02), 8 second capacitors (C1-C8), the 2 first capacitors (C01, C02) are located in the same column, the preset column division condition is 4 second capacitors in each column, the 8 second capacitors (C1-C8) are divided into 2 columns, the 2 columns of second capacitors (C1-C8) are symmetrically arranged on both sides of the two first capacitors (C01, C02), and a signal transmission line (red line) is arranged between two adjacent columns of capacitors, and a conductor (green line) is arranged between two adjacent rows.

[0029] Specifically, the capacitor array layout structure further includes a plurality of auxiliary capacitors, and the plurality of auxiliary capacitors fill the capacitor array to protect the capacitor array. Figure 2 As shown, the capacitor array layout structure also includes multiple auxiliary capacitors (D). The number of auxiliary capacitors (D) is 2. The two auxiliary capacitors (D) are filled into the capacitor array, and the formed capacitor array is 4 rows and 3 columns; the number of auxiliary capacitors (D) is 10. The 10 auxiliary capacitors (D) are filled into the gaps in the capacitor array and both sides of the two columns of the second capacitors, and the formed capacitor array is 4 rows and 5 columns; the number of auxiliary capacitors (D) is 20. The 20 auxiliary capacitors (D) are filled around the capacitor array to wrap the entire capacitor array, and the formed capacitor array is 6 rows and 5 columns.

[0030] Specifically, the signal transmission line between the column where the first capacitor is located and the adjacent column includes a signal input line and a signal output line; the signal transmission line between the columns other than the column where the first capacitor is located is a signal input line. Figure 2 As shown, the signal transmission line arranged between the column of two first capacitors (C01, C02) and the column of four second capacitors (C1-C4) includes a signal input line and a signal output line, and the signal transmission line arranged between the column of two first capacitors (C01, C02) and the column of four second capacitors (C5-C8) includes a signal input line and a signal output line, that is: the third column of the capacitor array is respectively provided with a signal input line and a signal output line between the second column and the fourth column; the signal transmission line between the column of four second capacitors (C1-C4) and the column only provided with auxiliary capacitors is a signal input line, and the signal transmission line between the column of four second capacitors (C5-C8) and the column only provided with auxiliary capacitors is a signal input line, that is: the signal input line is arranged between the first column and the second column of the capacitor array, and the signal input line is arranged between the fourth column and the fifth column of the capacitor array.

[0031] In detail, the number of signal transmission lines between two adjacent columns of capacitors is equal to the sum of the signal input lines and the signal output lines, or the number of signal transmission lines between two adjacent columns of capacitors is equal to the sum of multiple signal input lines. Specifically, when the capacitor array has 6 rows and 5 columns, the number of signal transmission lines set between the third column of the capacitor array and the second column and the fourth column is 3 (i.e., 2 signal input lines and 1 signal output line), and the number of signal transmission lines set between the first column and the second column, and between the fourth column and the fifth column of the capacitor array is 2 (2 signal input lines).

[0032] Specifically, the number of signal transmission lines between two adjacent columns of capacitors is equal to the number of second capacitors in a single column. Figure 2 As shown, in order to reduce the parasitic effects of the capacitor array, the number of signal transmission lines between two adjacent columns of capacitors in the capacitor array is set to the number of second capacitors in a single column, that is, there are 4 signal transmission lines between two adjacent columns of capacitors, and the signal transmission lines are expanded in the capacitor array.

[0033] Specifically, the lower plate of the first capacitor is connected to the signal output line through a wire, the lower plate of the second capacitor is connected to the signal input line through a wire, and the upper plate of the first capacitor is connected to the upper plate of the second capacitor through a wire. Figure 2 As shown, the lower plate of the first capacitor (C01, C02 blue rectangles) is connected to the signal output line (red line) OUT through a wire (blue line), the lower plate of the second capacitor (C1~C8 blue rectangles) is connected to multiple signal input lines one by one through wires (blue lines), and the multiple signal input lines are respectively input D1~D8, and the upper plate of the first capacitor (C01, C02 green rectangles) is connected to the second capacitor (C1~C8 green rectangles) through a wire (green line).

[0034] In detail, the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor, and the size of the first capacitor is equal to the size of the second capacitor.

[0035] Example 2

[0036] like Figure 3 As shown, there are 2 first capacitors (C01, C02), and 16 second capacitors (C1-C16). The 2 first capacitors (C01, C02) are located in the same column, and the preset column division condition is 4 second capacitors in each column. The 16 second capacitors (C1-C16) are divided into 4 columns, and the 4 columns of second capacitors (C1-C16) are symmetrically arranged on both sides of the two first capacitors (C01, C02), and a signal transmission line (red line) is arranged between two adjacent columns of capacitors, and a conductor (green line) is arranged between two adjacent rows.

[0037] The number of auxiliary capacitors (D) is 2, and 2 auxiliary capacitors (D) are filled into the capacitor array, forming a capacitor array of 4 rows and 5 columns; the number of auxiliary capacitors (D) is 10, and 10 auxiliary capacitors (D) are filled into the gaps in the capacitor array and on both sides of the two columns of the second capacitors, forming a capacitor array of 4 rows and 7 columns; the number of auxiliary capacitors (D) is 24, and 24 auxiliary capacitors (D) are filled around the capacitor array to wrap the entire capacitor array, forming a capacitor array of 6 rows and 7 columns.

[0038] like Figure 2 As shown, the signal transmission line arranged between the column of two first capacitors (C01, C02) and the column of four second capacitors (C5-C8) includes a signal input line and a signal output line, and the signal transmission line arranged between the column of two first capacitors (C01, C02) and the column of four second capacitors (C9-C12) includes a signal input line and a signal output line, that is, the fourth column of the capacitor array is respectively provided with a signal input line and a signal output line between the third column and the fifth column.

[0039] The signal transmission line between the column of four second capacitors (C1-C4) and the column of only auxiliary capacitors is set as a signal input line, and the signal transmission line between the column of four second capacitors (C13-C16) and the column of only auxiliary capacitors is set as a signal input line, that is: a signal input line is set between the first column and the second column of the capacitor array, and a signal input line is set between the fourth column and the fifth column of the capacitor array; the signal transmission line between the column of four second capacitors (C1-C4) and the column of four second capacitors (C2-C8) is set as a signal input line, and the signal transmission line between the column of four second capacitors (C9-C12) and the column of four second capacitors (C13-C16) is set as a signal input line, that is: a signal input line is set between the second column and the third column of the capacitor array, and a signal input line is set between the fifth column and the sixth column of the capacitor array.

[0040] When the capacitor array has 6 rows and 7 columns, 3 signal transmission lines are set between the fourth column of the capacitor array and the third column and the fifth column (i.e., 2 signal input lines and 1 signal output line), 2 signal transmission lines are set between the first column and the second column, and between the sixth column and the seventh column of the capacitor array (2 signal input lines), and 4 signal transmission lines are set between the second column and the third column, and between the fifth column and the sixth column of the capacitor array (4 signal input lines).

[0041] It should be noted that the preset column arrangement condition for the layout of the capacitor array is 8 capacitors per column, so as to realize the column arrangement of M second capacitors. The capacitors are classified according to the actual situation, and the preset column arrangement condition satisfies a multiple of 4.

[0042] The present application provides a capacitor array layout structure and electronic equipment, the capacitor array layout structure includes at least two first capacitors and multiple second capacitors, the first capacitor and the second capacitor form a capacitor array, the first capacitor is located at the center of the capacitor array, and multiple second capacitors are symmetrically arranged on both sides of the first capacitor. The layout of the capacitor array realizes central symmetry, improves the matching of the capacitor array, and can meet the high-precision requirements of the pipeline analog-to-digital converter; the upper plates of each second capacitor are interconnected and connected to the upper plate of the first capacitor, the lower plates of multiple second capacitors are respectively connected to multiple input signals one by one, the lower plates of each first capacitor are interconnected and output output signals to the outside, the second capacitor and the second capacitor are cleverly connected, the connection mode of the capacitor array is not changed, the design is simple, and auxiliary capacitors are added to the capacitor array to enhance the protection of the capacitor array. The capacitor array layout structure provided by the present application is not only bilaterally symmetrical, but also realizes central symmetry and axisymmetry, which improves the matching of capacitors in the pipeline analog-to-digital converter.

[0043] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A capacitor array layout structure, characterized in that: include: At least two first capacitors and multiple second capacitors, the first capacitors and the second capacitors form a capacitor array, the first capacitor is located at the center of the capacitor array, and the multiple second capacitors are symmetrically arranged on two opposite sides of the first capacitor; wherein the upper plates of each of the second capacitors are connected to each other and to the upper plate of the first capacitor, the lower plates of the multiple second capacitors are respectively connected to multiple input signals one by one, and the lower plates of each of the first capacitors are connected to each other and output output signals to the outside.

2. The capacitor array layout structure according to claim 1, characterized in that: There are M first capacitors and N second capacitors. The N second capacitors are divided into S columns according to a preset column division condition. The M first capacitors are arranged in the same column, and the S columns of second capacitors are symmetrically arranged on two opposite sides of the first capacitors. A signal transmission line is arranged between two adjacent columns of capacitors, and a wire is arranged between two adjacent rows of capacitors; wherein, M≥2, N≥8, S≥2, N is an integer multiple of 8, and S is an integer multiple of 2.

3. The capacitor array layout structure according to claim 2, characterized in that: The capacitor array layout structure further includes a plurality of auxiliary capacitors, and the plurality of auxiliary capacitors fill the capacitor array to protect the capacitor array.

4. The capacitor array layout structure according to claim 3, characterized in that: The signal transmission line between the column where the first capacitor is located and the adjacent column includes a signal input line and a signal output line; the signal transmission line between the columns other than the column where the first capacitor is located is the signal input line.

5. The capacitor array layout structure according to claim 4, characterized in that: The number of signal transmission lines between two adjacent columns of capacitors is equal to the sum of the signal input lines and the signal output lines, or the number of signal transmission lines between two adjacent columns of capacitors is equal to the sum of a plurality of the signal input lines.

6. The capacitor array layout structure according to claim 4, characterized in that: The number of signal transmission lines between two adjacent columns of capacitors is the same as the number of second capacitors in a single column.

7. The capacitor array layout structure according to claim 4, characterized in that: The lower plate of the first capacitor is connected to the signal output line through the wire, the lower plate of the second capacitor is connected to the signal input line through the wire, and the upper plate of the first capacitor and the upper plate of the second capacitor are connected through the wire.

8. The capacitor array layout structure according to claim 1, characterized in that: The capacitance value of the first capacitor is equal to the capacitance value of the second capacitor, and the size of the first capacitor is equal to the size of the second capacitor.

9. An electronic device, characterized in that: The invention comprises one or more capacitor array layout structures as described in any one of claims 1 to 8.

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