Packaging structure, manufacturing method thereof and electronic equipment
By forming a microchannel structure on the chip and bonding it to the second wafer, combined with the use of potting glue, the problem of microchannel non-closing in chip-level liquid-cooled radiator manufacturing is solved, and efficient heat dissipation and mass production are achieved ability.
Patent Information
- Application Number
- CN202310802271.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-30
- Publication Date
- 2025-01-07
AI Technical Summary
The manufacturing method of chip-level liquid-cooled radiators is challenging, especially the lack of enclosure of the microchannel structure leads to difficulty in mass production, and the prior art is difficult to effectively reduce thermal resistance in the chip.
By forming a microchannel structure of the chip heat sink on the first wafer and bonding it to the empty second wafer to form a third wafer, the second wafer is used to cover the microchannel structure, and the existing mass production process The suction cup is adsorbed, and at the same time, a fence is formed on the substrate and a potting glue is injected to achieve sealing.
The problem of wafer inabsorbability caused by microchannels is solved, and a feasible manufacturing method for chip-level liquid-cooled radiators is realized, which reduces the thermal resistance in the chip, and improves the connection strength and sealing of the packaging structure.
Smart Images
Figure CN119275105A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a packaging structure and a manufacturing method thereof, and an electronic device. Background Art
[0002] The chip manufacturing process is shrinking towards a smaller size, which makes the chip power consumption and heat flux density continue to rise. In addition, with the rapid development of 2.5D and 3D heterogeneous chips, there are serious heat dissipation problems inside the chip. The chip-level liquid cooling design designs micro-scale channels (channel width is between a few microns and a few hundred microns) inside the chip package, so that the liquid working fluid can directly take away the heat from the inside of the chip, greatly reducing the thermal resistance inside the chip or the thermal resistance at the interface. At present, the manufacturing method of chip-level liquid cooling radiators is a concern of the industry. Summary of the invention
[0003] The present disclosure provides a packaging structure and a manufacturing method thereof, and an electronic device, which can provide a feasible method for manufacturing a packaging structure including a chip-level liquid-cooling radiator.
[0004] In a first aspect, the present disclosure provides a method for manufacturing a packaging structure, comprising:
[0005] forming a microchannel structure of a chip heat sink on a first side of a first wafer, wherein a device layer is formed on a second side of the first wafer opposite to the first side;
[0006] The first wafer is bonded to an empty second wafer to form a third wafer, so that the second wafer covers the microchannel structure.
[0007] In some embodiments, it also includes:
[0008] Slicing and packaging the third wafer into a plurality of first chip packaging structures; wherein each of the first chip packaging structures contains a portion of the second wafer as a temporary cover;
[0009] removing the temporary cover from each of the first chip packaging structures;
[0010] forming a plurality of second chips having a liquid separation structure with a chip heat sink;
[0011] Each of the second chips is bonded onto the first chip packaging structure with the temporary cover removed to form a second chip packaging structure.
[0012] In some embodiments, it also includes:
[0013] An inlet and outlet hole communicating with the liquid separation structure is formed on the top of the second chip packaging structure;
[0014] The inlet and outlet tubes are connected to the second chip packaging structure so that the inlet and outlet tubes are communicated with the inlet and outlet holes.
[0015] In some embodiments, it also includes:
[0016] forming a blocking portion on the substrate of the second chip packaging structure, wherein the blocking portion is open at the top and surrounds the chip of the second chip packaging structure;
[0017] Injecting potting glue into the area surrounded by the enclosure and curing it into a packaging layer;
[0018] The thickness of the injected potting glue is greater than the distance from the connection position between the inlet and outlet pipes and the second chip packaging structure to the substrate.
[0019] In some embodiments, the step of forming a plurality of second chips having a liquid separation structure with a chip heat sink comprises:
[0020] forming a liquid separation structure of a chip heat sink on one side of the fourth wafer;
[0021] The fourth wafer is sliced into a plurality of the second chips.
[0022] In some embodiments, in the step of bonding the first wafer to the empty second wafer to form a third wafer, the bonding temperature is less than 400° C.
[0023] In some embodiments, in the step of bonding each of the second chips to the first chip package structure with the temporary cover removed, the bonding temperature is less than 150° C.
[0024] In some embodiments, the thickness of the third wafer is less than 1 mm.
[0025] In a second aspect, an embodiment of the present disclosure further provides a packaging structure, including:
[0026] substrate;
[0027] A first chip is located on the substrate, a microchannel structure of a chip heat sink is formed on a first side of the first chip, a device layer is formed on a second side of the first chip opposite to the first side, and the device layer is electrically connected to the substrate;
[0028] a second chip, the second chip is bonded to the first chip and has inlet and outlet holes corresponding to the microchannel structure formed on the top;
[0029] An inlet and outlet pipe, the inlet and outlet pipe is connected to the second chip and communicates with the inlet and outlet holes;
[0030] A blocking portion, the blocking portion is disposed on the substrate, the blocking portion is open at the top and surrounds the first chip and the second chip;
[0031] The packaging layer is located in the area surrounded by the enclosure, and the thickness of the packaging layer is greater than the distance from the connection position between the inlet and outlet pipes and the second chip to the substrate.
[0032] In some embodiments, a liquid separation structure of the chip heat sink is formed on the second chip, and the liquid separation structure is connected to the inlet and outlet holes and the microchannel structure.
[0033] In a third aspect, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned packaging structure.
[0034] In the disclosed embodiment, after the microchannel structure of the chip heat sink is formed on the first wafer, the empty second wafer is bonded to the first wafer to form a third wafer, so that the second wafer covers the microchannel structure. At this time, the suction cup in the existing packaging mass production process can be used to adsorb the third wafer, thereby solving the problem of the wafer being unable to be adsorbed due to the unclosed microchannel structure, which is conducive to mass production. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:
[0036] Figure 1 The present invention is a flow chart of a method for manufacturing a packaging structure provided in an embodiment of the present disclosure.
[0037] Figure 2 A flow chart of another method for manufacturing the packaging structure provided in an embodiment of the present disclosure.
[0038] Figure 3 A flow chart of another method for manufacturing the packaging structure provided in the embodiment of the present disclosure.
[0039] Figure 4 1 and 2 are plan views and cross-sectional views of a first wafer provided in an embodiment of the present disclosure, on which a device layer and a microchannel structure are formed.
[0040] Figure 5 It is a schematic diagram of a third wafer provided in an embodiment of the present disclosure.
[0041] Figure 6 It is a schematic diagram of slicing a third wafer having bumps formed thereon provided in an embodiment of the present disclosure.
[0042] Figure 7 It is a schematic diagram of a first chip packaging structure provided in an embodiment of the present disclosure.
[0043] Figure 8 It is a schematic diagram of the first chip packaging structure with the temporary cover removed provided in an embodiment of the present disclosure.
[0044] Fig. 9 It is a schematic diagram of forming a second chip provided in an embodiment of the present disclosure.
[0045] Fig.10 It is a schematic diagram of a second chip packaging structure provided in an embodiment of the present disclosure.
[0046] Fig.11 This is a schematic diagram after inlet and outlet holes are formed on the top of the second chip packaging structure provided in an embodiment of the present disclosure.
[0047] Fig.12 This is a schematic diagram of an embodiment of the present disclosure after inlet and outlet pipes are provided on the second chip packaging structure.
[0048] Fig.13 This is a schematic diagram of a second chip packaging structure provided in an embodiment of the present disclosure after a blocking portion is formed on the substrate.
[0049] Fig.14 It is a schematic diagram after forming a packaging layer in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0050] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.
[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0052] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0053] As used herein, "parallel" and "perpendicular" include the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 10°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 10°.
[0054] The chip-level liquid cooling design uses micro-scale channels (channel widths range from a few microns to several hundred microns) inside the chip package to allow the liquid medium to directly remove heat from the chip, greatly reducing the thermal resistance inside the chip or the thermal resistance at the interface. Research shows that the chip-level liquid cooling solution can solve 300-1000W / cm 2 At present, the manufacturing method of chip-level liquid cooling heat sink is a concern of the industry.
[0055] In a first aspect, the present disclosure provides a method for manufacturing a packaging structure, such as Figure 1 As shown, the method for manufacturing the packaging structure includes the following steps S1 and S2.
[0056] S1, such as Figure 4 As shown, a microchannel structure 30 of a chip heat sink is formed on a first side of a first wafer 21 a , wherein a device layer 23 is formed on a second side of the first wafer 21 a opposite to the first side. Figure 2 FIG. 2A (a) is a plan view of a first wafer 21 a on which a microchannel structure 30 is formed, and FIG. 2B (b) is a cross-sectional view of a first wafer 21 a on which a microchannel structure 30 is formed.
[0057] The microchannel structure 30 can contain liquid working medium to dissipate heat for the chip. The microchannel structure 30 corresponds to the position of the device layer 23. The width of the microchannel structure 30 is, for example, between 20 μm and 200 μm.
[0058] In some embodiments, the first wafer 21a may be silicon-based. In addition, the microchannel structure 30 may be formed by an etching process, such as a BOSCH deep silicon etching process, or a wet etching process, a laser etching process, or the like.
[0059] S2, such as Figure 5 As shown, the first wafer 21 a is bonded to the empty second wafer 90 a to form a third wafer 90 b , such that the second wafer 90 a covers the microchannel structure 30 .
[0060] In some embodiments, the bonding method in step S2 may be: using a polymer and an adhesive (epoxy resin, dry film, benzocyclobutene (BCB), polyimide, UV curable compound, etc.) to connect the first wafer 21 a and the empty second wafer 90 a to each other.
[0061] The disclosed embodiment can provide a feasible method for manufacturing a packaging structure including a chip-level liquid-cooled heat sink. In the manufacturing method of the packaging structure provided by the disclosed embodiment, after forming the microchannel structure 30 of the chip heat sink on the first wafer 21a, the empty second wafer 90a is bonded to the first wafer 21a to form a third wafer 90b, so that the second wafer 90a covers the microchannel structure 30. At this time, the suction cup in the existing packaging mass production process can be used to adsorb the third wafer 90b, thereby solving the problem that the wafer cannot be sucked due to the unclosed microchannel structure, which is conducive to mass production.
[0062] In some embodiments, the bonding temperature in step S2 is less than 400° C. to prevent the device layer 23 from being damaged at high temperature.
[0063] In some embodiments, in step S2, the overall thickness of the third wafer 90b is controlled to be less than 1 mm to facilitate subsequent cutting.
[0064] In some embodiments, Figure 2 As shown, the method for manufacturing the packaging structure further includes the following steps S3 to S6:
[0065] S3, such as Figure 6 and Figure 7 As shown, the third wafer 90 b is sliced and packaged into a plurality of first chip package structures PKG1 ; wherein each first chip package structure PKG1 contains a portion of the second wafer 90 a serving as a temporary cover plate 90 .
[0066] Among them, Figure 6 As shown, according to the FCBGA packaging process, a bump 24 (bump) can be formed on the third wafer 90b, and the third wafer 90b with the bump 24 is sliced, reflowed, etc., and the third wafer 90b is packaged on the substrate 10 to form a first chip packaging structure PKG1, as shown in FIG. Figure 7 As shown in . The first chip package structure PKG1 includes a substrate 10, a portion of a second wafer 90a as a temporary cover plate 90, and a portion of a first wafer 21a as a first chip 21. Bumps 24 are formed on the first chip 21, and the bumps 24 are electrically connected to the substrate 10. The third wafer 90b and the substrate 10 can be bonded by a first bonding layer 81.
[0067] S4, such as Figure 8 As shown, the temporary cover plate 90 is removed from each first chip package structure PKG1 .
[0068] The method for removing the temporary cover 90 corresponds to the bonding method in step S2. When the first wafer 21a and the empty second wafer 90a are connected by using a polymer and an adhesive in step S2, the method for removing the temporary cover 90 may include heating, or using a sol to perform sol. When heating, the heating temperature should ensure the reliability of the package.
[0069] After the temporary cover plate 90 is removed, the first chip packaging structure PKG1 from which the temporary cover plate 90 has been removed may be cleaned to remove residual impurities.
[0070] S5, such as Fig. 9 As shown, a plurality of second chips 22 having a liquid separation structure 40 of a chip heat sink are formed.
[0071] The liquid separation structure 40 is located at one side of the second chip 22 and does not completely penetrate the second chip 22. The size of the liquid separation structure 40 corresponds to the size of the microchannel structure 30.
[0072] In some embodiments, Fig. 9 As shown, the liquid separation structure 40 includes: a first liquid separation structure 41 and a second liquid separation structure 42. The first liquid separation structure 41 includes: a first main channel structure 41a and a plurality of first branch channel structures 41b connected to the first main channel structure 41a. The second liquid separation structure 42 includes: a second main channel structure 42a and a plurality of second branch channel structures 42b connected to the second main channel structure 42a. The first branch channel structures 41b and the second branch channel structures 42b are alternately arranged in the first direction and extend along the second direction.
[0073] In some embodiments, Fig. 9 As shown, step S5 may specifically include the following steps S51 and S52:
[0074] S51 , forming a liquid separation structure 40 of a chip heat sink on one side of the fourth wafer 22 a .
[0075] The fourth wafer 22 a may be made of glass or a material having a thermal expansion coefficient similar to that of silicon.
[0076] The liquid separation structure 40 may be formed by an etching process, such as wet etching, laser etching, etc.
[0077] S52, slicing the fourth wafer 22a into a plurality of second chips 22. The size of the second chip 22 corresponds to the size of the first chip 21 in the first chip package structure PKG1.
[0078] After step S5, proceed to step S6: Fig.10 As shown, each second chip 22 is bonded to a first chip packaging structure PKG1 with the temporary cover 90 removed, to form a second chip packaging structure PKG2.
[0079] In step S6, a low temperature bonding method may be adopted, and the bonding temperature is less than 150°C to prevent the bumps 24 in the first chip packaging structure PKG1 from being damaged at high temperature.
[0080] After the second chip 22 is bonded to the first chip package structure PKG1 without the first chip package structure PKG1, the microchannel structure 30 is connected to the liquid separation structure 40. For example, the first branch channel structure 41b and the second branch channel structure 42b of the liquid separation structure 40 are alternately arranged in the first direction, and the microchannel structure 30 extends along the first direction.
[0081] In some embodiments, Figure 3 As shown, the method for manufacturing the packaging structure includes, in addition to the above steps S1 to S6, the following steps S7 and S8 are also included:
[0082] S7, such as Fig.11 As shown, an inlet and outlet hole 50 communicating with the liquid separation structure 40 is formed on the top of the second chip packaging structure PKG2.
[0083] The first liquid separation channel structure 41 and the second liquid separation channel structure 42 are both connected to an inlet and outlet hole 50 .
[0084] The inlet and outlet holes 50 may be formed by wet etching, dry etching, laser etching or other processes.
[0085] S8, such as Fig.12 As shown, the inlet and outlet tubes 60 are connected to the second chip packaging structure PKG2 , so that the inlet and outlet tubes 60 are communicated with the inlet and outlet holes 50 .
[0086] The material of the inlet and outlet pipe 60 can be silicon, glass, resin, etc. In step S8, the wall of the inlet and outlet pipe 60 can be bonded to the second chip packaging structure PKG2 using an adhesive, and the adhesive is cured. The curing temperature can be between 140°C and 180°C, for example, 160°C; the curing time can be between 1.5h and 3h, for example, 2h.
[0087] In some embodiments, Figure 3 As shown, the method for manufacturing the packaging structure may further include the following steps S9 and S10:
[0088] S9, such as Fig.13 As shown, a blocking portion 70 is formed on the substrate 10 of the second chip package structure PKG2 , and the blocking portion 70 is opened at the top and surrounds the chip of the second chip package structure PKG2 .
[0089] The enclosure portion 70 may be bonded to the substrate 10 via the second bonding layer 82 .
[0090] The shape of the enclosure portion 70 may correspond to the shape of the chip in the second chip packaging structure PKG2 , for example, both are square.
[0091] S10, such as Fig.14 As shown, a potting compound is injected into the area surrounded by the enclosure portion 70 and solidified to form a packaging layer 71 .
[0092] There is a certain gap between the enclosure 70 and the chip in the second chip packaging structure PKG2 so that the injected potting glue can surround the side of the chip.
[0093] Among them, the thickness of the potting glue injected in step S10 is greater than the distance from the connection position between the inlet and outlet tubes 60 and the second chip packaging structure PKG2 to the substrate 10, so that the potting glue can surround the first chip, the second chip 22, and surround the connection position between the inlet and outlet tubes 60 and the second chip packaging structure PKG2, thereby improving the connection strength and sealing between the first chip 21 and the second chip 22, as well as the connection strength and sealing between the inlet and outlet tubes 60 and the second chip packaging structure PKG2.
[0094] In a second aspect, the present disclosure also provides a packaging structure, which is manufactured using the manufacturing method in the above embodiment. Fig.14 As shown, the packaging structure includes: a substrate 10, a first chip 21, a second chip 22, an inlet and outlet pipes 60, a blocking portion 70 and a packaging layer 71.
[0095] The first chip 21 is disposed on the substrate 10 , a microchannel structure 30 of a chip heat sink is formed on a first side of the first chip 21 , a device layer 23 is formed on a second side of the first chip 21 opposite to the first side, and the device layer 23 is electrically connected to the substrate 10 .
[0096] The second chip 22 is bonded to the first chip 21 and has an inlet and outlet hole 50 formed on the top corresponding to the microchannel structure 30. The inlet and outlet pipes 60 are connected to the second chip 22 and communicated with the inlet and outlet hole 50.
[0097] The enclosure 70 is disposed on the substrate 10 , and the enclosure 70 is open at the top and surrounds the first chip and the second chip 22 . For example, the enclosure 70 may be bonded to the substrate 10 by a second bonding layer 82 .
[0098] The packaging layer 71 is located in the area surrounded by the enclosure 70 , and the thickness of the packaging layer 71 is greater than the distance from the connection position between the inlet and outlet pipes 60 and the second chip 22 to the substrate 10 .
[0099] The inlet and outlet pipes 60 can input liquid working fluid into the microchannel structure 30, and output the liquid working fluid in the microchannel structure 30, so as to dissipate heat for the chip. Since the thickness of the encapsulation layer 71 is greater than the distance from the connection position between the inlet and outlet pipes 60 and the second chip 22 to the substrate 10, the encapsulation layer 71 can surround the first chip 21 and the second chip 22, and cover the connection position between the inlet and outlet pipes 60 and the second chip 22, so as to improve the connection strength and sealing between the first chip 21 and the second chip 22, and the connection strength and sealing between the inlet and outlet pipes 60 and the second chip 22.
[0100] like Fig.14 As shown, a liquid separation structure 40 of a chip heat sink is formed on the second chip 22, and the liquid separation structure 40 is connected to the inlet and outlet holes 60 and the microchannel structure 30. The specific structure of the liquid separation structure 40 can be found in the description of the above embodiment, and will not be repeated here.
[0101] Fig.14 The structures and materials of the various parts in the packaging structure shown are similar to those described in the above embodiments and will not be described again here.
[0102] The embodiment of the present disclosure also provides an electronic device, including the above-mentioned packaging structure, wherein the electronic device can be a switch, a router, or other device.
[0103] The above is a description of the packaging structure and its manufacturing method of the embodiment of the present disclosure. In the embodiment of the present disclosure, after forming the microchannel structure 30 of the chip heat sink on the first wafer 21a, the empty second wafer 90a is bonded to the first wafer 21a to form a third wafer 90b, so that the second wafer 90a covers the microchannel structure 30. At this time, the suction cup in the existing packaging mass production process can be used to adsorb the third wafer 90b, which solves the problem that the wafer cannot be sucked due to the microchannel not being closed, which is conducive to mass production. In addition, a barrier portion 70 surrounding the chip is formed on the substrate 10, and a potting compound is injected into the barrier portion 70 and solidified into a packaging layer, so as to seal the chip as a whole and improve the bonding strength between the layers in the chip; and the thickness of the potting compound is greater than the distance from the connection position of the inlet and outlet pipes 60 and the chip to the substrate 10, so as to improve the connection strength between the inlet and outlet pipes 60 and the chip.
[0104] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.
Claims
1. A method for manufacturing a packaging structure, characterized in that: include: forming a microchannel structure of a chip heat sink on a first side of a first wafer, wherein a device layer is formed on a second side of the first wafer opposite to the first side; The first wafer is bonded to an empty second wafer to form a third wafer, so that the second wafer covers the microchannel structure.
2. The method according to claim 1, characterized in that: Also includes: Slicing and packaging the third wafer into a plurality of first chip packaging structures; wherein each of the first chip packaging structures contains a portion of the second wafer as a temporary cover; removing the temporary cover from each of the first chip packaging structures; forming a plurality of second chips having a liquid separation structure with a chip heat sink; Each of the second chips is bonded onto the first chip packaging structure with the temporary cover removed to form a second chip packaging structure.
3. The method according to claim 1, characterized in that: Also includes: An inlet and outlet hole communicating with the liquid separation structure is formed on the top of the second chip packaging structure; The inlet and outlet tubes are connected to the second chip packaging structure so that the inlet and outlet tubes are communicated with the inlet and outlet holes.
4. The method according to claim 3, characterized in that: Also includes: forming a blocking portion on the substrate of the second chip packaging structure, wherein the blocking portion is open at the top and surrounds the chip of the second chip packaging structure; Injecting potting glue into the area surrounded by the enclosure and curing it into a packaging layer; The thickness of the injected potting glue is greater than the distance from the connection position between the inlet and outlet pipes and the second chip packaging structure to the substrate.
5. The method according to any one of claims 1 to 4, characterized in that: The step of forming a plurality of second chips with a liquid separation structure having a chip heat sink comprises: forming a liquid separation structure of a chip heat sink on one side of the fourth wafer; The fourth wafer is sliced into a plurality of the second chips.
6. The method according to any one of claims 1 to 4, characterized in that: In the step of bonding the first wafer to the empty second wafer to form a third wafer, the bonding temperature is less than 400°C.
7. The production method according to any one of claims 1 to 4, characterized in that: In the step of bonding each of the second chips to the first chip packaging structure with the temporary cover removed, the bonding temperature is less than 150° C.
8. The method according to any one of claims 1 to 4, characterized in that: The thickness of the third wafer is less than 1 mm.
9. A packaging structure, characterized in that: include: substrate; A first chip is located on the substrate, a microchannel structure of a chip heat sink is formed on a first side of the first chip, a device layer is formed on a second side of the first chip opposite to the first side, and the device layer is electrically connected to the substrate; a second chip, the second chip is bonded to the first chip and has inlet and outlet holes corresponding to the microchannel structure formed on the top; An inlet and outlet pipe, the inlet and outlet pipe is connected to the second chip and communicates with the inlet and outlet holes; A blocking portion, the blocking portion is disposed on the substrate, the blocking portion is open at the top and surrounds the first chip and the second chip; The packaging layer is located in the area surrounded by the enclosure, and the thickness of the packaging layer is greater than the distance from the connection position between the inlet and outlet pipes and the second chip to the substrate.
10. The packaging structure according to claim 9, characterized in that: A liquid separation structure of the chip heat sink is formed on the second chip, and the liquid separation structure is communicated with the inlet and outlet holes and the microchannel structure.
11. An electronic device, characterized in that: Includes the packaging structure described in claim 9 or 10.