Package-on-package structure and forming method thereof

Abstract

The invention discloses a stacked packaging structure and a forming method thereof, and the method comprises the steps: enabling a first active surface of a first chip to face downwards, and enabling the first active surface to be mounted on the upper surface of a substrate; a chip stacking structure is formed on the first back face of the first chip and comprises a plurality of second chips which are sequentially stacked in the vertical direction, the second active faces of the second chips are provided with micro-protrusions, the second back faces are provided with second connecting terminals, and when the second chips are sequentially stacked, the micro-protrusions are matched with the second connecting terminals; the second chips on the upper layer and the lower layer are bonded and fixed through a bonding layer located between the second chips on the upper layer and the lower layer; carrying out a batch reflow process, and welding the micro bulges of the second chip on the upper layer with the second connecting terminals of the second chip on the adjacent lower layer; and performing a molding bottom filling process to form a plastic packaging layer which is filled between the second chips on the upper layer and the lower layer and between the second chip on the bottom layer and the first chip. The packaging efficiency is improved, the micro convex points are prevented from collapsing, and the smoothness of the stacking process is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a stacked packaging structure and a method for forming the same. Background Art

[0002] HBM (High Bandwidth Memory) is a new type of CPU / GPU memory chip (i.e. "RAM"), which is actually a number of DDR chips stacked together and packaged together with the GPU to achieve a large-capacity, high-bit-width DDR combination array.

[0003] The existing 3D HBM (3D High Bandwidth Memory) packaging structure vertically stacks multiple memory chips (such as DRAM) through advanced packaging technology (such as TSV silicon through-via technology and micro-bump technology) to increase storage capacity, and then interconnects them with the computing unit chip (GPU / CPU / SOCDie) based on the high-speed interface of the interposer.

[0004] The existing stacking processes for HBM production mainly include TC-NCF (Thermal Compression bonding, TC, Non-Conductive Film, NCF, thermal compression non-conductive adhesive film) process and MR-MUF (Mass Reflow bonding with Molded Underfill, batch reflow molding bottom filling) process.

[0005] The TC-NCF process requires placing a layer of non-conductive adhesive film (Non-Conductive Film) between each layer of memory chips during each stacking process to isolate the upper and lower layers of memory chips from each other and protect the soldering points from impact. This process has the problems of complex manufacturing process, low efficiency and high cost.

[0006] In order to fix the upper and lower layers of memory chips during the memory chip stacking process of the MR-MUF process, the solder balls at the bottom of each layer of memory chips need to be preheated and pressed together first, so that the solder balls at the bottom will undergo more reflows, and the solder balls at the bottom will collapse and become unstable. In addition, the upper and lower layers of memory chips are prone to uneven stacking during the stacking process. Summary of the invention

[0007] The problem to be solved by the present application is to provide a stacked packaging structure and a method for forming the same, so as to improve the efficiency of packaging, prevent the micro-bumps on the second chip at the bottom from collapsing and becoming unstable, and ensure the flatness and stability of the stacking process of the second chip.

[0008] To solve the above problems, an embodiment of the present application first provides a method for forming a stacked package structure, including:

[0009] providing a substrate, the substrate comprising opposing upper and lower surfaces;

[0010] Providing a first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, mounting the first active surface of the first chip on the upper surface of the substrate with the first active surface facing downward, and the welding protrusion being welded to the substrate;

[0011] A chip stacking structure is formed on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second active surface having a micro-bump, the second back side having a second connection terminal, and when the plurality of second chips are stacked in sequence, the second active surface of each second chip faces downward, and the second chip on the upper layer is bonded and fixed to the adjacent second chip on the lower layer through a bonding layer located between the second chip on the upper layer and the second chip on the lower layer;

[0012] Performing a batch reflow process to weld the micro-bumps on the second active surface of the second chip in the upper layer of the chip stacking structure to the second connection terminals on the second back surface of the second chip in the adjacent lower layer, and to weld the micro-bumps on the second active surface of the second chip in the lower layer to the first connection terminals on the first back surface of the first chip;

[0013] A molding bottom filling process is performed to form a plastic sealing layer that covers the chip stacking structure and the first chip, and fills between the second chips on the upper and lower layers, between the second chip on the bottom layer and the first chip, and between the first chip and the upper surface of the substrate.

[0014] In an optional embodiment, the bonding layer is a mechanical bonding layer, which still adheres and fixes the first chips of the upper and lower layers during the batch reflow process.

[0015] In an optional embodiment, the material of the bonding layer is non-conductive glue or non-conductive adhesive film; the bonding layer is also formed between the second chip and the first chip of the bottom layer.

[0016] In an optional embodiment, the bonding layer is in a softened state or a semi-softened state at the reflow temperature during the batch reflow process.

[0017] In an optional embodiment, the bonding layer is a temporary bonding layer, which is completely or partially decomposed during a batch reflow process.

[0018] In an optional embodiment, the material of the bonding layer is UV glue or thermal decomposition glue that can be decomposed at the reflow temperature during the batch reflow process; when the batch reflow process is performed, the bonding layer is completely decomposed.

[0019] In an optional embodiment, the reflow temperature of the batch reflow process is 230 degrees Celsius to 250 degrees Celsius.

[0020] In an optional embodiment, the bonding layer includes a micro-support bump and a covering layer covering the micro-support bump, the material of the covering layer is a non-conductive glue or a non-conductive adhesive film, and the material of the micro-support bump is a metal material, an organic material or an inorganic material that will not soften at the reflow temperature during a batch reflow process.

[0021] In an optional embodiment, the bonding layer includes micro-support bumps and a covering layer covering the micro-support bumps, the material of the covering layer is UV glue or thermal decomposition glue that can be decomposed at the reflow temperature of the batch reflow process, and the material of the micro-support bumps is metal material, organic material or inorganic material that will not decompose at the reflow temperature of the batch reflow process; when the batch reflow process is performed, the covering layer in the bonding layer is decomposed and the micro-support bumps are retained.

[0022] In an optional embodiment, when the plurality of second chips are stacked in sequence, the bonding layer is pre-formed on the second back surface of the stacked lower second chip, or the bonding layer is pre-formed on the second active surface of the upper second chip to be stacked.

[0023] In an optional embodiment, the number of the bonding layers includes a plurality of discrete ones, which are evenly distributed between the second chip in the upper layer and the adjacent second chip in the lower layer.

[0024] In an optional embodiment, positions of bonding layers of different layers are the same.

[0025] In an optional embodiment, a third chip is further mounted on the upper surface of the substrate on one side of the second chip, and the third chip is electrically connected to the substrate.

[0026] Another embodiment of the present application further provides a stacked package structure, including:

[0027] a substrate comprising opposing upper and lower surfaces;

[0028] A first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, the first active surface of the first chip being mounted downward on the upper surface of the substrate, the welding protrusion being welded to the substrate;

[0029] A chip stacking structure located on a first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second active surface having a micro-bump, the second back side having a second connection terminal, and the second active surface of each second chip facing downward, the second chip of the upper layer being bonded and fixed to the second chip of the adjacent lower layer via a bonding layer located between the second chip of the upper layer and the second chip of the lower layer, the micro-bump of the second active surface of the second chip of the upper layer in the chip stacking structure being welded to the second connection terminal of the second back side of the adjacent second chip of the lower layer, and the micro-bump of the second active surface of the second chip of the bottom layer being welded to the first connection terminal of the first back side of the first chip;

[0030] A plastic packaging layer covers the chip stacking structure and the first chip, and fills between the second chips on the upper and lower layers, between the second chip on the bottom layer and the first chip, and between the first chip and the upper surface of the substrate.

[0031] In an optional embodiment, the bonding layer is also formed between the second chip and the first chip of the bottom layer.

[0032] In an optional embodiment, the bonding layer is a mechanical bonding layer, and the bonding layer is entirely the non-conductive glue or non-conductive adhesive film.

[0033] In an optional embodiment, the bonding layer includes a micro-support bump and a covering layer covering the micro-support bump, the material of the covering layer is a non-conductive glue or a non-conductive adhesive film, and the material of the micro-support bump is a metal material, an organic material or an inorganic material that will not soften at the reflow temperature during a batch reflow process.

[0034] In an optional embodiment, the number of the bonding layers includes a plurality of discrete ones, which are evenly distributed between the second chip in the upper layer and the adjacent second chip in the lower layer.

[0035] In an optional embodiment, positions of bonding layers of different layers are the same.

[0036] In an optional embodiment, it further includes: a third chip mounted on the upper surface of the substrate on one side of the first chip, and the third chip is electrically connected to the substrate.

[0037] The advantages of the technical solution of this application are:

[0038] When forming a stack of multiple layers of second chips in the present application, the second chip of the upper layer is bonded and fixed to the second chip of the adjacent lower layer through the bonding layer between the second chip of the upper layer and the second chip of the lower layer, rather than being fixed by welding between the micro-protrusions of the second active surface of the second chip of the upper layer and the second connection terminals of the second back surface of the adjacent lower layer second chip. That is, the second chips of the upper and lower layers mentioned in the present application are bonded and fixed through the bonding layer, and there is no need to place a layer of non-conductive adhesive film (Non-Conductive Film) for bonding and isolation of each layer of storage chips when stacking chips, as in the existing TC-NCF process, so the process is simple and efficient. Moreover, the chip stacking method in which the second chips of the upper and lower layers mentioned above in the present application are bonded and fixed by a bonding layer, and there is no need to perform a hot compression bonding on the solder balls at the bottom of each layer of the storage chip when stacking chips as in the existing MR-MUF process, thereby avoiding multiple reflows of the micro-bumps on the second chip (especially reducing the number of reflows of the micro-bumps on the bottom second chip), thereby preventing the collapse or instability of the micro-bumps on the second chip in the stacked chip structure, and also preventing the problem of uneven stacking of the upper and lower layers of the second chips.

[0039] Furthermore, when the bonding layer is a temporary bonding layer, it will be completely or partially decomposed during the batch reflow process, thereby preventing or reducing the influence of the bonding layer on the flow of the plastic encapsulation layer material during the molding bottom filling process. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1-Figure 12 This is a structural schematic diagram of a stacked package structure forming process in one embodiment of the present application;

[0041] Figure 13-Figure 22 It is a structural schematic diagram of a stacked package structure forming process in another embodiment of the present application. DETAILED DESCRIPTION

[0042] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0043] In one embodiment of the present application, a method for forming a stacked package structure is first provided. The formation process of the stacked package structure of the present application is described in detail below with reference to the accompanying drawings.

[0044] refer to Figure 1, providing a substrate 101, wherein the substrate 101 includes a relative upper surface and a lower surface; providing a first chip 201, wherein the first chip 201 includes a relative first active surface and a first back surface, wherein the first active surface has a welding protrusion 202, and the first back surface has a first connecting terminal 203, and the first active surface of the first chip 201 is mounted downward on the upper surface of the substrate 101, and the welding protrusion 202 is welded to the substrate 101.

[0045] The substrate 101 serves as a support carrier and a connection carrier in the packaging process. In one embodiment, the upper surface of the substrate 101 has a plurality of discrete first pads (not shown in the figure), the lower surface of the substrate 101 has a plurality of discrete second pads (not shown in the figure), and the substrate 101 has a connection circuit (not shown in the figure), and the connection circuit may include one or more of a metal layer, a connection plug, a through silicon via connection structure (TSV), a via connection structure, and a metal conductive column. The connection circuit can be used for the electrical connection between the first pad on the upper surface of the substrate 101 and the corresponding second pad on the lower surface of the substrate 101. The connection circuit can also be used for the electrical connection between some of the first pads on the upper surface of the substrate 101, and the connection circuit is also used for the electrical connection between some of the second pads on the lower surface of the substrate 101. The first pad on the upper surface of the substrate 101 is electrically connected to the first chip 201 and other devices mounted on the upper surface of the substrate 101. External protrusions can be formed on the second pads on the lower surface of the substrate later, and the external protrusions are used to connect with other devices or packaging structures. In one embodiment, the material of the first pad, the second pad and the connecting line is metal, specifically one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the external protrusion is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony. In one embodiment, the substrate may be a silicon substrate, an RDL substrate (Re-distribution Layer), a resin substrate, a printed circuit board (PCB), a ceramic substrate, a glass substrate, or a flexible circuit board (FPC). In one embodiment, the substrate may be a single-layer board or a multi-layer board. In one embodiment, the substrate 101 may be used as an interposer.

[0046] The first chip 201 includes a first active surface and a first back surface opposite to each other, the first active surface has a welding protrusion 202, the first back surface has a first connection terminal 203, the first connection terminal 203 includes a through silicon via interconnection structure (TSV, Through Silicon Via), an integrated circuit (with specific functions) (such as a logic control circuit, not shown in the figure) is formed in the first chip 201, and the welding protrusion 202 and the first connection terminal 203 are electrically connected to the integrated circuit. In one embodiment, the welding protrusion 202 can be a solder protrusion or include a metal bump and a solder layer located on the top surface of the metal bump. In a specific embodiment, the material of the first connecting terminal 203 is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver; the material of the metal bump is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver; the material of the solder bump or solder layer is tin or a tin alloy; the tin alloy is one or more of tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.

[0047] The first chip 201 can function together with the second chip 301 (see Figure 3 ) have the same or different functions. In one embodiment, the function of the first chip 201 may be different from the function of the second chip 301 stacked later. The first chip 201 is a logic chip, and the second chip 301 is a memory chip. The logic chip is used to control and manage the storage, reading (and deletion) of data in the memory chip. In other embodiments, the function of the first chip 201 may be different from the function of the second chip 301 stacked later (refer to Figure 3 ) have the same functions, and the first chip 201 and the second chip 301 are both storage chips.

[0048] In one embodiment, a third chip (not shown in the figure) is also mounted on the upper surface of the substrate 101 on one side of the first chip 201, and the third chip is electrically connected to the substrate 101. Specifically, the third chip can be electrically connected to the second chip 301 through some connecting lines in the substrate 101. The first chip 201 is a logic chip, the second chip 301 is a storage chip, and the third chip is a processing chip, which can be a CPU chip or a GPU chip.

[0049] Combined with reference Figure 2-Figure 4 ,in Figure 2 for Figure 3 or Figure 4 A schematic diagram of a top view of a second chip 301 stacked in the middle, Figure 3The cross-sectional structure of the package structure obtained along the cutting line AA1 direction of the second chip 301 after the second chip 301 is stacked, Figure 4 In order to obtain a cross-sectional structure of the packaging structure along the cutting line AA2 direction of the second chip 301 after stacking the second chip 301, a chip stacking structure is formed on the first back side of the first chip 201, and the chip stacking structure includes a plurality of second chips 301 stacked in sequence along a vertical direction, each of the second chips 301 includes a second active surface and a second back side relative to each other, the second active surface has a micro-protrusion 302, and the second back side has a second connecting terminal 303, and when the plurality of second chips 301 are stacked in sequence, the second active surface of each second chip 301 faces downward, and the upper second chip 301 is bonded and fixed to the adjacent lower second chip 301 through a bonding layer 304 located between the upper second chip 301 and the lower second chip 301.

[0050] The second active surface of the second chip 301 has a micro-bump 302, and the second back surface of the second chip 301 has a second connection terminal 303, the micro-bump 302 is a micro solder ball, and the second connection terminal 303 includes a through silicon via interconnection structure (TSV, Through Silicon Via), and an integrated circuit with a specific function (such as data storage, reading circuit, not shown in the figure) is formed in the second chip 301, and the second connection terminal 303 and the micro-bump 302 are electrically connected to the integrated circuit. In a specific embodiment, the material of the second connection terminal 303 is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver, and the material of the micro-bump 302 is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony. It should be noted that, in some embodiments, the second chip 301 at the top layer in the chip stacking structure may have a second connection terminal 303 or a through silicon via interconnection structure (TSV, Through Silicon Via).

[0051] In one embodiment, the second chip 301 is a memory chip, which may include a volatile memory chip (such as dynamic random access memory (DRAM) or static RAM (SRAM) or a non-volatile memory chip (such as flash memory (Flash), phase change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM) or resistive RAM (ReRAM)).

[0052] When the plurality of second chips 301 are stacked in sequence, the second active surface of each second chip 301 faces downward, and the upper second chip 301 is bonded and fixed to the adjacent lower second chip 301 via a bonding layer 304 between the upper second chip 301 and the lower second chip 301, rather than being fixed via welding between the micro-protrusion 302 on the second active surface of the upper second chip 301 and the second connection terminal 303 on the second back surface of the adjacent lower second chip 301. Specifically, when the upper and lower second chips 301 are bonded and fixed by the bonding layer 304, the micro-bump 302 of the second active surface of the upper second chip 301 is not in contact with the second connection terminal 303 of the second back side of the adjacent lower second chip 301 (or the micro-bump 302 of the second active surface of the upper second chip 301 is suspended above the second back side of the lower second chip 301), or the micro-bump 302 of the second active surface of the upper second chip 301 is slightly in contact with the second connection terminal 303 of the second back side of the adjacent lower second chip 301, but there is no bonding connection or welding connection between the micro-bump 302 and the second connection terminal 303. That is, the upper and lower second chips 301 mentioned above in the present application are bonded and fixed by the bonding layer 304, and there is no need to place a layer of non-conductive adhesive film (Non-Conductive Film) for bonding and isolation of each layer of storage chips when stacking chips, as in the existing TC-NCF process, so the process is simple and efficient. Moreover, the upper and lower layers of the second chips 301 mentioned above in the present application are both bonded and fixed by a bonding layer 304. There is no need to perform a hot-pressing bonding on the solder balls at the bottom of each layer of the storage chip when stacking chips as in the existing MR-MUF process. This avoids the micro-bumps 302 on the second chip 301 from undergoing multiple reflows (especially reducing the number of reflows of the micro-bumps 302 on the bottom second chip 301), thereby preventing the collapse or instability of the micro-bumps 302 on the second chip 301 in the stacked chip structure, and also preventing the problem of uneven stacking of the upper and lower layers of the second chips 301.

[0053] In one embodiment, the bonding layer 304 is also formed between the second chip 301 and the first chip 201 of the bottom layer. In one embodiment, the thickness of the bonding layer 304 is equal to or greater than (slightly greater than) the thickness of the micro-bump 302 .

[0054] The bonding layer 304 may be a temporary bonding layer or a mechanical bonding layer. The temporary bonding layer will be completely or partially decomposed during the subsequent batch reflow process. The mechanical bonding layer will not decompose at high temperatures, and the mechanical bonding layer may be in a softened or semi-softened state at the reflow temperature during the subsequent batch reflow process, and still provide support for the second chip on the upper layer.

[0055] In one embodiment, the bonding layer 304 is a temporary bonding layer, and the material of the temporary bonding layer is UV glue or thermal decomposition glue that can be decomposed at the reflow temperature of the subsequent batch reflow process; the temporary bonding layer is entirely made of UV glue or thermal curing glue that can be decomposed at the reflow temperature of the batch reflow process, and the temporary bonding layer is completely decomposed when the batch reflow process is performed later. On the one hand, the temporary bonding layer is used for bonding and fixing between the upper and lower second chips 301 when the second chips 301 are stacked, preventing movement or offset between the second chips 301, and ensuring the flatness of the stacking of the upper and lower second chips 301. The temporary bonding layer will not decompose in the initial heating stage of the batch reflow process and can still support the upper and lower second chips 301, ensuring the mechanical stability and flatness of the chip stacking structure during the batch reflow process, thereby improving the second connection terminal of the micro-bump 302 of the upper second chip 301 and the lower second chip 301 during the batch reflow process. The welding accuracy of the micro-bumps 303 can be improved, and the deformation or short circuit caused by excessive pressure between the micro-bumps 302 on the second chip 301 in the lower layer can be effectively prevented. On the other hand, in the subsequent batch reflow process, the micro-bumps 302 on the second active surface of the second chip 301 in the upper layer of the chip stacking structure are welded with the second connecting terminals 303 on the second back side of the adjacent second chip 301 in the lower layer, and the micro-bumps 302 on the second active surface of the second chip 301 in the bottom layer are welded with the first connecting terminals 203 on the first back side of the first chip 201 (reference Figure 7 and Figure 8 ), the bonding layer 304 can be easily completely decomposed during the batch reflow process, thereby preventing or reducing the influence of the bonding layer 304 on the flow of the plastic encapsulation layer material during the subsequent molding bottom filling process.

[0056] In another embodiment, reference Fig.13 and Fig.14 The temporary bonding layer (bonding layer 304) includes a micro-support bump 305 and a coating layer 306 coating the micro-support bump 305, wherein the coating layer 306 is made of a UV glue or a heat-curing glue that can be decomposed at the reflow temperature during the batch reflow process, and the micro-support bump 305 is made of a metal material, an organic material or an inorganic material that will not decompose at the reflow temperature during the batch reflow process; when the batch reflow process is subsequently performed, the coating layer 306 in the temporary bonding layer is decomposed, and the micro-support bump 305 is retained (refer to Fig.17 and Fig.18). The coating layer 306 serves to bond and fix the upper and lower second chips 301 during the aforementioned chip stacking. During the subsequent batch reflow process, the coating layer 306 decomposes at the reflow temperature, while the micro-support bumps 305 do not decompose at the reflow temperature during the batch reflow process and are retained between the upper and lower second chips 301 to support the upper second chip 301, so as to better ensure the mechanical stability and flatness of the chip stacking structure, prevent the chip stacking structure from being tilted or uneven during the batch reflow process, thereby further improving the welding accuracy of the micro-bumps 302 of the upper second chip 301 and the second connection terminals 203 of the lower second chip 301 during the batch reflow process, and more effectively prevent deformation or short circuit between the micro-bumps 302 on the lower second chip 301 due to excessive pressure.

[0057] In one embodiment, the formation process of the temporary bonding layer includes a glue dispensing process (or glue printing process) and a curing process. The glue dispensing process (or glue printing process) is used to dispense (or print) UV glue or thermal curing glue on the second active surface or the second back surface of the second chip 301, and the curing process is used to cure the dispensed (or printed) UV glue or thermal curing glue.

[0058] In one embodiment, when the temporary bonding layer is UV glue, the temporary bonding layer is cured by UV light irradiation during the stacking process; when the temporary bonding layer is thermal decomposition glue, the temporary bonding layer is cured by thermal reflow during the stacking process. In one embodiment, the process of stacking a plurality of the second chips 301 is performed in a bonding device, and the bonding device includes a thermal compression bonding (TCB) device or a laser compression bonding (LCB) device.

[0059] In one embodiment, the thickness of the temporary bonding layer is equal to or greater than (slightly greater than) the thickness of the micro-bump 302 .

[0060] In one embodiment, the bonding layer 304 is a mechanical bonding layer, and the material of the mechanical bonding layer is a non-conductive glue or a non-conductive adhesive film. On the one hand, the mechanical bonding layer can be used for bonding and fixing the upper and lower second chips 301 when the second chips 301 are stacked. On the other hand, during the subsequent batch reflow process, the mechanical bonding layer will not decompose at high temperature. The mechanical bonding layer is in a softened or semi-softened state and can still provide support for the upper second chip 301, thereby improving the flatness and mechanical stability of the chip stacking structure during the batch reflow process, preventing the chip stacking structure from tilting or being uneven during the batch reflow process, thereby improving the welding accuracy of the micro-bumps 302 of the upper second chip 301 and the second connection terminals 203 of the lower second chip 301 during the batch reflow process, and preventing deformation or short circuit between the micro-bumps 302 on the lower second chip 301 due to excessive pressure.

[0061] In one embodiment, the mechanical bonding layer of the non-conductive glue or non-conductive adhesive film material may be in a softened state or a semi-softened state at a reflow temperature during a subsequent batch reflow process. The reflow temperature of the batch reflow process is generally 230 degrees Celsius to 250 degrees Celsius.

[0062] In one embodiment, the mechanical bonding layer is entirely made of non-conductive glue or non-conductive adhesive film.

[0063] In another embodiment, reference Fig.13 and Fig.14The mechanical bonding layer (bonding layer 304) includes a micro-support bump 305 and a coating layer 306 covering the micro-support bump 305. The material of the coating layer 306 is a non-conductive glue or a non-conductive adhesive film material. The material of the micro-support bump 305 is a metal material, an organic material or an inorganic material that will not soften at the reflow temperature during the batch reflow process. The metal material is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver. The organic material is a polymer or a resin. The inorganic material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The process of forming the mechanical bonding layer includes first forming the micro-support bump 305 on the second back side or second active surface of the second chip 301, and then forming a covering layer 306 covering the micro-support bump 305. The micro-support bump 305 can be formed when the second chip 301 is formed by a front-end integrated manufacturing process, that is, before a plurality of second chips 301 on a wafer are cut, the micro-support bump 305 is formed on the second back side or second active surface of the second chip on the wafer. The coating layer 306 plays a role in bonding and fixing the upper and lower second chips 301 during the aforementioned chip stacking. During the subsequent batch reflow process, the coating layer 306 is softened or semi-softened at the reflow temperature, while the micro-support bumps 305 will not soften at the reflow temperature during the batch reflow process, and can better and more stably support the upper second chip 301, so as to better ensure the mechanical stability and flatness of the chip stacking structure, and prevent the chip stacking structure from being tilted or uneven during the batch reflow process, thereby further improving the welding accuracy of the micro-bumps 302 of the upper second chip 301 and the second connection terminals 203 of the lower second chip 301 during the batch reflow process, and can more effectively prevent deformation or short circuit between the micro-bumps 302 on the lower second chip 301 due to excessive pressure.

[0064] Continue to refer Figure 3-Figure 4 In one embodiment, when the plurality of second chips 301 are stacked in sequence, the bonding layer 304 can be pre-formed on the second back surface of the stacked lower second chip 301, or the bonding layer 304 can also be pre-formed on the second active surface of the upper second chip 301 to be stacked.

[0065] The number of the bonding layers 304 between the upper and lower second chips 301 includes a discrete plurality. In one embodiment, the discrete plurality of bonding layers 304 are evenly distributed between the upper second chip 301 and the adjacent lower second chip 301 to stably support and fix the upper second chip 301. In one embodiment, the positions of the bonding layers 304 of different layers are the same to simplify the stacking process while ensuring stability and flatness during the stacking process. In a specific embodiment, the discrete plurality of bonding layers 304 are evenly distributed between the upper second chip 301 and the adjacent lower second chip 301 at a plurality of positions close to the edge, or may also be other optimized positions.

[0066] refer to Figure 5-Figure 6 , a mass reflow bonding (MR) process is performed to weld the micro-bump 302 of the second active surface of the second chip 301 in the upper layer of the chip stacking structure to the second connection terminal 303 of the second back side of the adjacent second chip 301 in the lower layer, and the micro-bump 302 of the second active surface of the second chip 301 in the bottom layer to the first connection terminal 203 on the first back side of the first chip 201.

[0067] The purpose of the batch reflow process is to realize batch welding of all the micro-bumps 302 between the upper and lower second chips 302 in the chip stacking structure with the corresponding first connection terminals 203 at one time, so as to improve the manufacturing efficiency.

[0068] In one embodiment, the batch reflow process basically includes an initial heating stage, a reflow stage and a cooling stage. The reflow temperature of the reflow stage is the highest temperature in the batch reflow process. In one embodiment, the reflow temperature of the batch reflow process is 230 degrees Celsius to 250 degrees Celsius.

[0069] In one embodiment, continue to refer to Figure 5 and Figure 6 When the bonding layer 304 is a mechanical bonding layer, and the mechanical bonding layer is entirely non-conductive glue or non-conductive adhesive film, the bonding layer 304 will not soften or will only be partially softened during the initial heating stage of the batch reflow process. During the reflow stage of the batch reflow process, the bonding layer 304 is in a softened state or a semi-softened state, that is, during the batch reflow process, the bonding layer 304 can still effectively bond and support the upper and lower second chips 301, thereby ensuring the mechanical stability and flatness of the chip stacking structure during the batch reflow process.

[0070] In another embodiment, reference Fig.15 and Fig.16, when the bonding layer 304 is a mechanical bonding layer, and the mechanical bonding layer includes a micro-support bump 305 and a covering layer 306 covering the micro-support bump 305, the material of the covering layer 306 is a non-conductive glue or a non-conductive adhesive film material, and the material of the micro-support bump 305 is a metal material, an organic material or an inorganic material that will not soften at the reflow temperature during the batch reflow process. During the batch reflow process, the covering layer 306 is softened or semi-softened at the reflow temperature, and the micro-support bump 305 will not soften at the reflow temperature during the batch reflow process.

[0071] In another embodiment, reference Figure 7 and Figure 8 When the bonding layer 304 is a temporary bonding layer, and the temporary bonding layer is entirely made of UV glue or heat-curing glue that can be decomposed at the reflow temperature during the batch reflow process, the bonding layer 304 will not decompose during the initial heating stage of the batch reflow process and can still support the upper and lower second chips 301, thereby ensuring the mechanical stability and flatness of the chip stacking structure during the batch reflow process, thereby improving the welding accuracy of the micro-bumps 302 of the upper second chip 301 and the second connection terminals 203 of the lower second chip 301 during the batch reflow process, and can effectively prevent deformation or short circuit between the micro-bumps 302 on the lower second chip 301 due to excessive pressure. The bonding layer 304 is completely decomposed during the reflow stage of the batch reflow process.

[0072] In yet another embodiment, reference Figure 17-Figure 18 , when the bonding layer 304 is a temporary bonding layer, and the temporary bonding layer includes a micro-support bump 305 and a covering layer 306 covering the micro-support bump 305, the material of the covering layer 306 is a UV glue or a thermal curing glue that can be decomposed at the reflow temperature during the batch reflow process, and the material of the micro-support bump 305 is a metal material, an organic material or an inorganic material that will not decompose at the reflow temperature during the batch reflow process; when the batch reflow process is performed, the covering layer 306 in the temporary bonding layer is decomposed, and the micro-support bump 305 is retained.

[0073] In one embodiment, during the batch reflow process, a certain pressure 11 is applied to the second back side of the topmost second chip 301. The applied pressure 11 may be gradually reduced or eliminated in the second half of the batch reflow process.

[0074] refer to Fig. 9 and Fig.10 , or refer to Fig.11 and Fig.12 , or refer to Fig.19 and Fig. 20 , or refer to Fig.21 and Fig. 22, a molded underfill (MUF) process is performed to form a plastic encapsulation layer 102 that covers the chip stacking structure and the first chip 201, and fills the second chips 301 in the upper and lower layers, between the second chip 301 in the bottom layer and the first chip 201, and between the first chip 201 and the upper surface of the substrate 101.

[0075] In one embodiment, the material of the molding layer 102 is liquid epoxy molding compound (LMC). In other embodiments, the material of the molding layer 102 may also be other liquid resin molding compounds, such as liquid polyimide resin molding compounds, liquid benzocyclobutene resin molding compounds, or liquid polybenzoxazole resin molding compounds.

[0076] In one embodiment, the reflow curing temperature when forming the plastic encapsulation layer 102 is 160 degrees Celsius to 180 degrees Celsius.

[0077] In one embodiment, the plastic encapsulation layer 102 may cover or expose the second back side of the second chip 301 on the top layer.

[0078] Another embodiment of the present application further provides a stacked package structure. Fig. 9 and Fig.10 ,include:

[0079] A substrate 101, wherein the substrate 101 includes an upper surface and a lower surface opposite to each other;

[0080] A first chip 201, wherein the first chip 201 comprises a first active surface and a first back surface opposite to each other, wherein the first active surface has a welding protrusion 202, and the first back surface has a first connection terminal 203, and the first active surface of the first chip 201 is mounted on the upper surface of the substrate 101 with the first active surface facing downward, and the welding protrusion 202 is welded to the substrate 101;

[0081] A chip stacking structure located on the first back side of the first chip 201, the chip stacking structure comprising a plurality of second chips 301 stacked in sequence in a vertical direction, each of the second chips 301 comprising a second active surface and a second back side opposite to each other, the second active surface having a micro-bump 302, the second back side having a second connection terminal 303, and the second active surface of each second chip 301 facing downward, the second chip 301 of the upper layer and the second chip 301 of the adjacent lower layer being bonded and fixed by a bonding layer 304 located between the second chip 301 of the upper layer and the second chip 301 of the lower layer, the micro-bump 302 of the second active surface of the second chip 301 of the upper layer in the chip stacking structure being welded to the second connection terminal 303 of the second back side of the adjacent second chip 301 of the lower layer, and the micro-bump 302 of the second active surface of the second chip 301 of the bottom layer being welded to the first connection terminal 203 of the first back side of the first chip 201;

[0082] A plastic encapsulation layer 102 covers the chip stacking structure and the first chip 201 , and fills between the second chips 301 on the upper and lower layers, between the second chip 301 on the bottom layer and the first chip 201 , and between the first chip 201 and the upper surface of the substrate 101 .

[0083] In one embodiment, the bonding layer 304 is also formed between the second chip 301 and the first chip 201 of the bottom layer.

[0084] In one embodiment, the bonding layer 304 is a mechanical bonding layer, and the entire bonding layer 304 is a non-conductive glue or a non-conductive adhesive film. The non-conductive glue or the non-conductive adhesive film will not decompose at the reflow temperature during the batch reflow process. In one embodiment, the reflow temperature of the batch reflow process is 230 degrees Celsius to 250 degrees Celsius.

[0085] In another embodiment, reference Fig.19 and Fig. 20 The bonding layer 304 includes a micro-support bump 305 and a covering layer 306 covering the micro-support bump 305. The material of the covering layer 306 is a non-conductive glue or a non-conductive adhesive film. The material of the micro-support bump 305 is a metal material, an organic material or an inorganic material that will not decompose at the reflow temperature during the batch reflow process.

[0086] In one embodiment, the bonding layers 304 are discretely multiple and evenly distributed between the second chip 301 of the upper layer and the adjacent second chip 301 of the lower layer. The bonding layers 304 of different layers are located at the same position.

[0087] In one embodiment, it further includes: a third chip (not shown in the figure) mounted on the upper surface of the substrate 101 on one side of the first chip 201, and the third chip is electrically connected to the substrate.

[0088] In one embodiment, the first chip 201 is a logic chip, the second chip 301 is a memory chip, and the third chip is a processing chip.

[0089] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A method for forming a stacked package structure, characterized in that: include: providing a substrate, the substrate comprising opposing upper and lower surfaces; Providing a first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, mounting the first active surface of the first chip on the upper surface of the substrate with the first active surface facing downward, and the welding protrusion being welded to the substrate; A chip stacking structure is formed on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second active surface having a micro-bump, the second back side having a second connection terminal, and when the plurality of second chips are stacked in sequence, the second active surface of each second chip faces downward, and the second chip on the upper layer is bonded and fixed to the adjacent second chip on the lower layer through a bonding layer located between the second chip on the upper layer and the second chip on the lower layer; Performing a batch reflow process to weld the micro-bumps on the second active surface of the second chip in the upper layer of the chip stacking structure to the second connection terminals on the second back surface of the second chip in the adjacent lower layer, and to weld the micro-bumps on the second active surface of the second chip in the lower layer to the first connection terminals on the first back surface of the first chip; A molding bottom filling process is performed to form a plastic sealing layer that covers the chip stacking structure and the first chip, and fills between the second chips on the upper and lower layers, between the second chip on the bottom layer and the first chip, and between the first chip and the upper surface of the substrate.

2. The method for forming a stacked package structure according to claim 1, wherein: The bonding layer is a mechanical bonding layer, which is used to bond and fix the first chips of the upper and lower layers during the batch reflow process.

3. The method for forming a stacked package structure according to claim 2, wherein: The material of the bonding layer is non-conductive glue or non-conductive adhesive film; the bonding layer is also formed between the second chip and the first chip of the bottom layer.

4. The method for forming a stacked package structure according to claim 2, wherein: The bonding layer is in a softened state or a semi-softened state at the reflow temperature during the batch reflow process.

5. The method for forming a package-on-package structure according to claim 1, wherein: The bonding layer is a temporary bonding layer and is completely or partially decomposed during the batch reflow process.

6. The method for forming a stacked package structure according to claim 5, wherein: The material of the bonding layer is UV glue or thermal decomposition glue that can be decomposed at the reflow temperature during the batch reflow process; when the batch reflow process is performed, the bonding layer is completely decomposed.

7. The method for forming a stacked package structure according to claim 4 or 6, wherein: The reflux temperature of the batch reflux process is 230 degrees Celsius to 250 degrees Celsius.

8. The method for forming a package-on-package structure according to claim 2, wherein: The bonding layer includes a micro-support bump and a coating layer covering the micro-support bump, the coating layer is made of a non-conductive glue or a non-conductive adhesive film, and the micro-support bump is made of a metal material, an organic material or an inorganic material that will not soften at the reflow temperature during a batch reflow process.

9. The method for forming a package-on-package structure according to claim 5, wherein: The bonding layer includes a micro-support bump and a coating layer coating the micro-support bump, wherein the coating layer is made of UV glue or thermally decomposable glue that can be decomposed at the reflow temperature during a batch reflow process, and the micro-support bump is made of a metal material, an organic material or an inorganic material that will not decompose at the reflow temperature during a batch reflow process; when the batch reflow process is performed, the coating layer in the bonding layer is decomposed and the micro-support bump is retained.

10. The method for forming a package-on-package structure according to claim 1, wherein: When the plurality of second chips are stacked in sequence, the bonding layer is pre-formed on the second back surface of the stacked lower second chip, or the bonding layer is pre-formed on the second active surface of the upper second chip to be stacked.

11. The method for forming a package-on-package structure according to claim 1 or 10, wherein: The number of the bonding layers includes a plurality of discrete ones, which are evenly distributed between the second chip of the upper layer and the adjacent second chip of the lower layer.

12. The method for forming a package-on-package structure according to claim 11, wherein: The positions of the bonding layers of different layers are the same.

13. The method for forming a package-on-package structure according to claim 1, wherein: A third chip is also mounted on the upper surface of the substrate on one side of the second chip, and the third chip is electrically connected to the substrate.

14. A stacked package structure, characterized in that: include: a substrate comprising opposing upper and lower surfaces; A first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, the first active surface of the first chip being mounted downward on the upper surface of the substrate, the welding protrusion being welded to the substrate; A chip stacking structure located on a first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second active surface having a micro-bump, the second back side having a second connection terminal, and the second active surface of each second chip facing downward, the second chip of the upper layer being bonded and fixed to the second chip of the adjacent lower layer via a bonding layer located between the second chip of the upper layer and the second chip of the lower layer, the micro-bump of the second active surface of the second chip of the upper layer in the chip stacking structure being welded to the second connection terminal of the second back side of the adjacent second chip of the lower layer, and the micro-bump of the second active surface of the second chip of the bottom layer being welded to the first connection terminal of the first back side of the first chip; A plastic packaging layer covers the chip stacking structure and the first chip, and fills between the second chips on the upper and lower layers, between the second chip on the bottom layer and the first chip, and between the first chip and the upper surface of the substrate.

15. The package-on-package structure according to claim 14, wherein: The bonding layer is also formed between the second chip and the first chip of the bottom layer.

16. The package-on-package structure according to claim 14, wherein: The bonding layer is a mechanical bonding layer, and the bonding layer is entirely made of the non-conductive glue or non-conductive adhesive film.

17. The package-on-package structure according to claim 14, wherein: The bonding layer includes a micro-support bump and a coating layer covering the micro-support bump, the coating layer is made of a non-conductive glue or a non-conductive adhesive film, and the micro-support bump is made of a metal material, an organic material or an inorganic material that will not soften at the reflow temperature during a batch reflow process.

18. The package-on-package structure according to claim 16 or 17, wherein: The number of the bonding layers includes a plurality of discrete ones, which are evenly distributed between the second chip of the upper layer and the adjacent second chip of the lower layer.

19. The package-on-package structure according to claim 18, wherein: The positions of the bonding layers of different layers are the same.

20. The package-on-package structure according to claim 14, wherein: Also includes: A third chip is mounted on the upper surface of the substrate at one side of the first chip, and the third chip is electrically connected to the substrate.

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