Manufacturing method and packaging method of semiconductor adapter plate

Abstract

The invention provides a manufacturing method of a semiconductor adapter plate, which comprises the following steps: S1, a first substrate and a second substrate with flat surfaces are prepared, the first substrate comprises a first semiconductor layer and a first dielectric layer formed on the surface of the first semiconductor layer, and the second substrate comprises a second substrate layer and a second dielectric layer formed on the surface of the second substrate layer; s2, bonding the first substrate and the second substrate to obtain a bonding structure, wherein the free surfaces of the first dielectric layer and the second dielectric layer are bonding surfaces; s3, performing first etching on the bonding structure by taking the first dielectric layer as an etching stop layer so as to form a plurality of through holes penetrating through the first semiconductor layer in the bonding structure, and exposing the first dielectric layer from the through holes; s4, etching the first dielectric layer in the through hole to enable the through hole to extend downwards; s5, filling a conductive interconnection layer in the through hole; and S6, removing the second substrate and exposing the through hole. According to the invention, the in-chip and inter-chip depths of the through holes are ensured to be consistent, and metal diffusion is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing and packaging a semiconductor adapter plate. Background Art

[0002] During the dry etching process of TSV (through silicon via) holes, it is difficult to completely ensure the uniformity of etching, so the depth of the etched holes will have different depth distributions on the entire wafer. The length of the TSV copper pillars formed is difficult to ensure uniformity. Generally, the TSV holes in the edge area of ​​the wafer will be deeper than those in the middle area. At the same time, the TSV depth distribution between wafers from different batches will also be inconsistent.

[0003] Therefore, it is difficult to ensure that the TSV wafers produced by the existing technology will eventually obtain a uniform and consistent length of copper pillars in the silicon adapter plate without copper diffusion during TSV reveal (BVR non-copper reveal process). Different batches of TSV wafers may have copper diffusion contamination during the Si CMP, Si etch and cleaning processes of TSV exposure, resulting in product scrapping.

[0004] Even if there is no copper diffusion contamination during the TSV reveal process, the difficulty of mass production and risk control of existing technologies is still extremely high, and the length of TSV copper pillars in the final silicon adapter board will still vary, which will still have a significant adverse effect on the consistency of electrical performance in various areas on the adapter board. There is a risk that short TSV copper pillars in the silicon adapter board will not be exposed, thereby failing to achieve the purpose of electrical transfer. In order to control the TSV copper pillars of varying lengths in the silicon adapter board to the same length and expose the surface of the silicon adapter board, copper diffusion contamination is likely to occur, causing the product to be scrapped.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for manufacturing and packaging a semiconductor adapter board, which is used to solve the problem that when using the prior art to manufacture TSV, it is difficult to ensure that a uniform and consistent length of copper columns in the silicon adapter board is finally obtained without causing copper diffusion, which may lead to electrical failure of the device.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor adapter plate, comprising the steps of:

[0008] S1: preparing a first substrate and a second substrate having flat surfaces, wherein the first substrate comprises a first semiconductor layer and a first dielectric layer formed on the surface of the first semiconductor layer, and the second substrate comprises a second substrate layer and a second dielectric layer formed on the surface of the second substrate layer;

[0009] S2: bonding the first substrate and the second substrate to each other to obtain a bonding structure, wherein free surfaces of the first dielectric layer and the second dielectric layer are bonding surfaces;

[0010] S3: performing a first etching on the bonding structure using the first dielectric layer as an etching stop layer to form a plurality of through holes penetrating the first semiconductor layer in the bonding structure, wherein the through holes expose the first dielectric layer;

[0011] S4: etching the first dielectric layer in the through hole so that the through hole extends downward;

[0012] S5: filling a conductive interconnection layer in the through hole;

[0013] S6: removing the second substrate and revealing the through hole.

[0014] Optionally, the first semiconductor layer and the second substrate layer are made of the same material, the first dielectric layer includes a first etch stop layer and a first buffer layer sequentially formed on the surface of the first semiconductor layer, and the first buffer layer and the second dielectric layer are bonded to each other.

[0015] Optionally, the first semiconductor layer and the second substrate layer include a silicon wafer, the first etch barrier layer includes a SiN layer and / or a SiCN layer, the first buffer layer includes a silicon oxide layer, and the second dielectric layer includes several of a SiN layer, a SiCN layer and a SiO2 layer.

[0016] Optionally, in step S4, a bottom surface of the through hole is located in the first etch stop layer, or the through hole penetrates the first etch stop layer.

[0017] Optionally, after bonding is completed in step S2, the step further includes thinning the first semiconductor layer to a thickness consistent with the length of the through hole of the adapter plate.

[0018] Optionally, step S5 includes first using several methods such as ALD, PVD and ECP to form a conductive interconnect layer filling the through hole and covering the surface of the first semiconductor layer, and then performing surface planarization to make the conductive interconnect layer in the through hole flush with the surface of the first semiconductor layer.

[0019] Optionally, the method of removing the second substrate comprises chemical mechanical polishing.

[0020] Optionally, after etching in step S4 , the total thickness of the first dielectric layer and the second dielectric layer at the bottom of the through hole is greater than or equal to 0.5 μm.

[0021] Optionally, in step S3, an etching stop signal is captured to ensure that all through holes stop at the surface of the first dielectric layer, and in step S4, etching time is controlled to ensure that all through holes stop at a preset depth of the first dielectric layer.

[0022] The present invention also provides a packaging method, which includes the steps of preparing a semiconductor adapter board by using the method for manufacturing a semiconductor adapter board as described in any of the above schemes, and then bonding a chip to the semiconductor adapter board.

[0023] As described above, the manufacturing method and packaging method of the semiconductor transfer board of the present invention have the following beneficial effects:

[0024] The present invention innovates the manufacturing process and structure of a semiconductor adapter plate. At least one dielectric layer is deposited on each of the two substrates and fused together in a face-to-face manner. After the through-hole is etched, the etch stop layer is micro-etched. The micro-etched etch stop layer ensures that the through-holes are highly consistent within the wafer, between wafers and between batches, and the final through-hole etching depth is stopped at a certain depth position inside the dielectric layer. Metal diffusion can be effectively avoided in all links of the entire process of adapter plate manufacturing, thereby completely avoiding uncontrollable effects such as device failure caused by metal diffusion / cross-contamination on the adapter plate structure and the 2.5D overall packaging structure, which helps to improve the device packaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The flowchart of the method for manufacturing the semiconductor transfer board provided by the present invention is shown.

[0026] Figure 2 Shown is a schematic diagram of an exemplary cross-sectional structure of the first substrate provided by the present invention.

[0027] Figure 3 Shown is a schematic diagram of an exemplary cross-sectional structure of the second substrate provided by the present invention.

[0028] Figure 4 Shown is a schematic diagram of the cross-sectional structure after the first substrate and the second substrate are bonded.

[0029] Figure 5 Shown is a schematic diagram of the cross-sectional structure after the first etching of the bonding structure.

[0030] Figure 6 The figure shows an exemplary cross-sectional structure schematic diagram after the bonding structure is etched for the second time.

[0031] Figure 7 Displayed as Figure 6Schematic diagram of the cross-sectional structure after the conductive interconnect layer is filled in the structure.

[0032] Figure 8 Display as Figure 7 Schematic diagram of the cross-sectional structure obtained after the second substrate is removed.

[0033] Fig. 9 Another exemplary cross-sectional structural schematic diagram is shown after the bonding structure is etched for the second time.

[0034] Fig.10 Displayed as Fig. 9 Schematic diagram of the cross-sectional structure after the conductive interconnect layer is filled in the structure.

[0035] Fig.11 Display as Fig.10 Schematic diagram of the cross-sectional structure obtained after the second substrate is removed. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0037] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0038] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0039] It should be noted that the diagrams provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the diagrams only show the components related to the present invention rather than the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed arbitrarily, and the layout of the components may also be more complicated. In order to make the diagrams as concise as possible, not all structures are marked in the drawings.

[0040] like Figure 1 As shown, the present invention provides a method for manufacturing a semiconductor adapter plate, which will be described in detail below with reference to the accompanying drawings.

[0041] First, step S1 is performed: preparing a first substrate 11 and a second substrate 12 with flat surfaces, wherein the first substrate 11 includes a first semiconductor layer 111 and a first dielectric layer formed on the surface of the first semiconductor layer 111 , and the second substrate 12 includes a second substrate layer 121 and a second dielectric layer 122 formed on the surface of the second substrate layer 121 .

[0042] The first semiconductor layer 111 may be, for example, a common semiconductor substrate on the market, such as a silicon wafer, a germanium wafer, or a germanium silicon wafer. The first dielectric layer may be a single-layer or multi-layer structure, but preferably includes at least a material layer having a significantly different etching rate from the first semiconductor layer 111. For example, when the first semiconductor layer 111 is a silicon wafer, the second dielectric layer 122 includes at least one material layer as an etching stop layer, for example, the first dielectric layer includes a SiN layer and / or a SiCN layer.

[0043] In a preferred example, Figure 2 As shown, the first dielectric layer includes a first etch stop layer 112a and a first buffer layer 112b sequentially formed on the surface of the first semiconductor layer 111. The first etch stop layer 112a includes, for example, a SiN layer, which can be formed by a chemical vapor deposition process, or obtained by surface nitriding of a silicon wafer. The first etch stop layer 112a can also be a SiCN layer, or a stack of a SiN layer and a SiCN layer. The first buffer layer 112b includes but is not limited to a silicon oxide layer. The silicon oxide layer can also be formed by a chemical vapor deposition process or an atomic layer deposition process. In a further example, when the first etch stop layer 112a is a SiN layer and the first buffer layer 112b is a silicon oxide layer, a SiON layer that can improve interlayer stress can be further provided between the first etch stop layer 112a and the first buffer layer 112b.

[0044] An exemplary structure of the second substrate 12 is as follows: Figure 3As shown, it includes a second substrate layer 121 and a second dielectric layer 122 located on the surface of the second substrate layer 121. The second substrate layer 121 can be a layer of the same material as the first semiconductor layer 111. The second dielectric layer 122 preferably includes at least a second buffer layer of the same material as the first buffer layer 112b, which will help improve the bonding quality and reduce the stress between the bonding structure layers. For example, the first buffer layer 112b and the second buffer layer are both silicon oxide layers. If the second substrate layer 121 is a silicon wafer and the second buffer layer is a silicon oxide layer, the second buffer layer can be formed on the surface of the second substrate layer 121 by a thermal oxidation process. Alternatively, it can also be formed by a chemical vapor deposition process or an atomic layer deposition process. However, the material of the second buffer layer is not limited thereto, for example, it can also be a SiN layer, a SiCN layer, a SiON layer or a combination of several of the aforementioned material layers. For example, in a preferred example, the first semiconductor material layer is a silicon wafer, the first etch barrier layer is a SiN layer formed on the surface of the silicon wafer by nitriding the silicon wafer, and the first buffer layer is a silicon oxynitride layer obtained by high-temperature oxidation of the SiN layer. The second substrate layer is located on the silicon wafer, and the second dielectric layer includes a silicon oxide layer formed on the surface of the silicon wafer by thermal oxidation and a SiON layer obtained by high-temperature nitridation of the silicon oxide layer. Such a structure helps to greatly improve interlayer stress and improve bonding quality.

[0045] The etching barrier layer not only facilitates the control of the etching endpoint in the subsequent etching process, but also serves as a barrier layer for the conductive metal layer (such as the copper metal layer) in the final structure. The buffer layer provides a better material for the bonding of the two substrates, which helps to reduce the bonding difficulty and improve the stability of the bonding structure.

[0046] After the preparation of each material layer is completed, each substrate can be subjected to surface planarization treatment to make the surface of each substrate a flat surface. Of course, if the original preparation process of each material layer can ensure that the surface of each substrate has a good flatness, then no planarization treatment is required. A flat surface will help improve the accuracy of subsequent photolithography and etching, which is very important for finally obtaining a through hole 13 with a consistent depth.

[0047] In other structures, the second substrate layer 121 may also be other material layers that can withstand high temperature bonding and subsequent etching atmosphere, such as glass substrates, metal substrates, and other material layers that can be recycled. In the case where the second substrate layer 121 is a non-semiconductor material layer, the second dielectric layer 122 may also be an organic dielectric layer, such as a polymer material layer with good viscosity, and the method for forming the second dielectric layer 122 may also be a coating method or the like.

[0048] By forming corresponding dielectric layers on the first substrate 11 and the second substrate 12 respectively, the number, thickness and type of each dielectric layer can be adjusted as needed, which can effectively improve the warping and stress of the wafer and is more conducive to the uniformity of the subsequent through hole 13 production.

[0049] Next, step S2 is performed: the first substrate 11 and the second substrate 12 are bonded to each other to obtain a bonding structure, wherein the free surfaces of the first dielectric layer and the second dielectric layer 122 are bonding surfaces, and the free surfaces are surfaces that are not bonded to other material layers. When the first dielectric layer includes the first etch stop layer 112a and the second buffer layer, and the second dielectric layer 122 includes the second buffer layer, the first buffer layer 112b and the second buffer layer are bonded to each other.

[0050] The bonding method can be determined according to the material of the first substrate 11 and the second substrate 12. When the first buffer layer 112b and the second buffer layer are made of the same material, fusion bonding is preferably used. After bonding, the two are melted into the same material layer without an obvious boundary line. The structure obtained after bonding is as follows: Figure 4 shown.

[0051] In some examples, if the initially provided first semiconductor layer 111 is relatively thick, then after bonding is completed, the first semiconductor layer 111 may be thinned to a thickness consistent with the depth of the adapter plate through hole 13. The thinning method is preferably a chemical mechanical polishing method, but is not limited thereto. In other examples, the thinning of the first semiconductor layer 111 may also be completed before bonding, for example, after forming the first dielectric layer on the first semiconductor layer 111, the first substrate 11 is double-sided polished to thin the first semiconductor layer 111 to a target thickness. However, thinning after bonding helps reduce the risk of fragmentation due to the role of the buffer layer.

[0052] Next, step S3 is performed: the bonding structure is etched for the first time using the first dielectric layer as an etching stop layer to form a plurality of through holes 13 penetrating the first semiconductor layer 111 in the bonding structure, wherein the through holes 13 expose the first dielectric layer.

[0053] Specifically, this step includes first forming a photoresist layer on the surface of the first semiconductor layer 111, then performing exposure and development to define the position of the through hole 13, and then performing reactive ion etching on the first semiconductor layer 111 according to the patterned photoresist layer to form the through hole 13. For example, if the first semiconductor layer 111 is a silicon wafer, this step can use a fluorine-containing gas, such as a gas including CF4, to perform silicon etching. During the etching process, an endpoint detection device (endpoint) is used to capture an etching stop signal to ensure that all the through holes 13 stop on the surface of the first dielectric layer, more specifically, stop on the surface of the first etching stop layer 112a, to obtain the following. Figure 5The structure shown.

[0054] Next, step S4 is performed: etching the first dielectric layer in the through hole 13, for example, by using reactive ion etching to extend the through hole 13 downward.

[0055] In this step, the etching time can be controlled so that all through holes 13 stop at a preset depth of the first dielectric layer. For example, in one example, the bottom surface of the through hole 13 is located in the first etching stop layer 112a, that is, the etched through hole 13 does not penetrate the first dielectric layer, or even the first etching stop layer 112a, and the obtained structure is as follows: Figure 6 In another example, the through hole 13 penetrates the first etch stop layer 112a and can continue to extend downward into the first buffer layer 112b and even the second buffer layer, and the resulting structure is as shown in FIG. Fig. 9 The etching depth of the dielectric layer can be determined as required, but in a preferred example, after the etching of this step is completed, the total thickness of the first dielectric layer and the second dielectric layer 122 at the bottom of the through hole 13 is greater than or equal to 0.5 μm, which can reserve a suitable space for subsequent grinding.

[0056] By etching the first dielectric layer, not only can it be further ensured that all through holes 13 penetrate the first semiconductor layer 111, but also in the subsequent revealing process of the through holes 13, for example, in the subsequent back grinding to the SiN / SiCN or SiO2 layer and other dielectric layers by Grinding / CMP method, it can eliminate the possibility of contact between the interconnecting metal and the semiconductor material, prevent the diffusion of the metal material, and help ensure the electrical performance of the device.

[0057] Then, the process proceeds to step S5 : filling the through hole 13 with a conductive interconnection layer 14 .

[0058] In a preferred example, this step includes first using several methods such as ALD, PVD and ECP (electroplating) to form a conductive interconnection layer 14 filling the through hole 13 and covering the surface of the first semiconductor layer 111, and then performing a surface planarization process to make the conductive interconnection layer 14 in the through hole 13 flush with the surface of the first semiconductor layer 111, so as to obtain the following: Figure 7 or Fig.10 The structure shown ( Figure 7 and Fig.10 The thickness of the conductive interconnect layer 14 may be determined by the etching depth of the through hole 13. For example, an ALD (atomic layer deposition) process is first used to form a metal seed layer on the inner wall surface of the through hole 13, and then an ECP process is used to fill the through hole 13. The conductive interconnect layer 14 includes but is not limited to a copper layer, a tungsten layer, and an aluminum layer. In other examples, the method of forming the conductive interconnect layer 14 may also be a method of filling the through hole 13 with liquid metal, which is not specifically limited.

[0059] Finally, step S6 is performed: removing the second substrate 12 and exposing the through hole 13 .

[0060] The method for removing the second substrate 12 can be flexibly selected according to the material of the second substrate 12. However, in a preferred example, the method for removing the second substrate 12 adopts chemical mechanical polishing. The thickness of the chemical mechanical polishing can be determined according to the etching depth of the dielectric layer before. For example, if the through hole 13 does not penetrate the first etch barrier layer 112a, the back grinding of this step needs to grind away part of the first etch barrier layer 112a, and the obtained structure is as follows: Figure 8 If the through hole 13 penetrates the first etching stopper layer 112a, the back surface of the first buffer layer 112b is ground in this step until the through hole 13 is exposed. The obtained structure is as shown in FIG. Fig.11 shown.

[0061] The existing chemical mechanical polishing method usually controls the polishing end point according to the polishing rate, but the polishing process is affected by various factors, and the polishing rate may vary. Therefore, the polishing time calculated according to the polishing rate may not reach the preset polishing thickness. Therefore, in a preferred example provided by the present invention, the polishing end point is determined by detecting the polishing product. For example, a sampling pipeline connected to the polishing equipment is set, and the sampling pipeline is connected to an analytical instrument, such as an inductively coupled plasma emission spectrometer. If the metal elements in the conductive interconnect layer begin to appear in the polishing product, it means that the back of the through hole has been exposed and the polishing can be terminated. In addition, in order to improve the accuracy of the polishing end point detection, before depositing the conductive interconnect layer metal, for example, before depositing the copper metal, a detection metal thin layer (for example, a thickness of less than 20nm) for polishing end point detection can be deposited in the through hole. The detection metal layer is, for example, a titanium layer. The titanium layer can not only play the role of an adhesion layer, but also facilitate the uniform deposition of the conductive interconnect layer in the through hole, and can also play a good diffusion barrier role. Most importantly, titanium has abundant high-intensity analytical spectral lines. Once titanium ions appear in the grinding product, they can be easily detected, which helps to improve the accuracy of grinding endpoint detection. In other examples, other metal layers that are easier to detect than the metal of the conductive interconnect layer can also be used, which will not be elaborated one by one.

[0062] The present invention innovates the manufacturing process and structure of the semiconductor adapter plate. At least one dielectric layer (such as SiN or SiCN or SiO2 layer) is deposited on each of two substrates (at least one of which is a semiconductor substrate, such as a silicon wafer), and the two substrates are fused together in a face-to-face manner. After the through-hole is etched, the etch stop layer (SiN or SiCN) is micro-etched. The micro-etched etch stop layer (SiN or SiCN) ensures the high consistency of the manufactured through-holes within the wafer, between wafers and between batches, and stops the final through-hole (such as TSV) etching depth at a certain depth position inside the SiN / SiCN or SiO2 layer. At the same time, the risk of interconnect metal diffusion can be avoided by the protection of the etch stop layer (SiN or SiCN) in the TSV reveal stage, and there is no need to use high-risk non-copper exposed TSV in the TSV reveal stage. The reveal (BVR) process can achieve the same or better performance of the transfer board structure and the ability to be more suitable for large-scale industrial mass production. The diffusion of metal can be effectively avoided in all links of the entire process of transfer board production, thereby completely avoiding the uncontrollable effects of copper diffusion / cross contamination on the transfer board structure and the 2.5D overall packaging structure, such as device failure. The semiconductor transfer board produced based on the present invention is particularly suitable for new 2.5D advanced packaging with high computing power and high performance.

[0063] The present invention also provides a packaging method, which includes the steps of preparing a semiconductor adapter board using the method for preparing a semiconductor adapter board as described in any of the above schemes, and then bonding the chip to the semiconductor adapter board. The above introduction to the adapter board manufacturing process can be quoted in its entirety here, and will not be repeated for the purpose of brevity.

[0064] After the transfer board is made, the chip can be directly bonded to the transfer board, or a wiring layer electrically connected to the conductive interconnect layer can be made on the transfer board first, and then the chip can be bonded to the wiring layer. After that, the chip can be plastic-sealed and conductive solder balls can be made, and then slicing and other steps can be performed.

[0065] Since the method provided by the present invention is used to manufacture the adapter plate, the quality of the packaged device is improved.

[0066] In summary, the present invention provides a method for manufacturing and packaging a semiconductor adapter. The manufacturing of the adapter includes the following steps: S1: preparing a first substrate and a second substrate with a flat surface, the first substrate including a first semiconductor layer and a first dielectric layer formed on the surface of the first semiconductor layer, and the second substrate including a second substrate layer and a second dielectric layer formed on the surface of the second substrate layer; S2: bonding the first substrate and the second substrate to each other to obtain a bonding structure, wherein the free surfaces of the first dielectric layer and the second dielectric layer are bonding surfaces; S3: etching the bonding structure for the first time using the first dielectric layer as an etching stop layer to form a plurality of through holes penetrating the first semiconductor layer in the bonding structure, wherein the through holes expose the first dielectric layer; S4: etching the first dielectric layer located in the through holes to extend the through holes downward; S5: filling the through holes with a conductive interconnect layer; S6: removing the second substrate and exposing the through holes. The improved process and flow design of the present invention can ensure the high consistency of the manufactured through holes within the chip, between chips and between batches, and stop the final through hole etching depth at a certain depth position inside the dielectric layer. The diffusion of metal can be effectively avoided in all links of the whole process of the adapter board production, thereby completely avoiding the uncontrollable effects of metal diffusion / cross contamination on the adapter board structure and the 2.5D overall packaging structure, such as device failure, which helps to improve the device packaging quality. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor adapter plate, characterized in that: Includes steps: S1: preparing a first substrate and a second substrate having flat surfaces, wherein the first substrate comprises a first semiconductor layer and a first dielectric layer formed on the surface of the first semiconductor layer, and the second substrate comprises a second substrate layer and a second dielectric layer formed on the surface of the second substrate layer; S2: bonding the first substrate and the second substrate to each other to obtain a bonding structure, wherein free surfaces of the first dielectric layer and the second dielectric layer are bonding surfaces; S3: performing a first etching on the bonding structure using the first dielectric layer as an etching stop layer to form a plurality of through holes penetrating the first semiconductor layer in the bonding structure, wherein the through holes expose the first dielectric layer; S4: etching the first dielectric layer in the through hole so that the through hole extends downward; S5: filling a conductive interconnection layer in the through hole; S6: removing the second substrate and revealing the through hole.

2. The method for manufacturing a semiconductor transfer board according to claim 1, characterized in that: The first semiconductor layer and the second substrate layer are made of the same material. The first dielectric layer includes a first etch stop layer and a first buffer layer sequentially formed on the surface of the first semiconductor layer. The first buffer layer and the second dielectric layer are bonded to each other.

3. The method for manufacturing a semiconductor transfer board according to claim 2, characterized in that: The first semiconductor layer and the second substrate layer include silicon wafers, the first etch barrier layer includes a SiN layer and / or a SiCN layer, the first buffer layer includes a silicon oxide layer, and the second dielectric layer includes several of a SiN layer, a SiCN layer and a SiO2 layer.

4. The method for manufacturing a semiconductor transfer board according to claim 2, characterized in that: In step S4, the bottom surface of the through hole is located in the first etch stop layer, or the through hole passes through the first etch stop layer.

5. The method for manufacturing a semiconductor transfer board according to claim 1, characterized in that: After the bonding is completed in step S2, the step of thinning the first semiconductor layer to a thickness consistent with the length of the through hole of the adapter plate is also included.

6. The method for manufacturing a semiconductor transfer board according to claim 1, characterized in that: Step S5 includes first using some of the ALD, PVD and ECP methods to form a conductive interconnect layer filling the through hole and covering the surface of the first semiconductor layer, and then performing a surface planarization process to make the conductive interconnect layer in the through hole flush with the surface of the first semiconductor layer.

7. The method for manufacturing a semiconductor transfer board according to claim 1, characterized in that: The method of removing the second substrate includes chemical mechanical polishing.

8. The method for manufacturing a semiconductor transfer board according to claim 1, characterized in that: After etching in step S4 , the total thickness of the first dielectric layer and the second dielectric layer at the bottom of the through hole is greater than or equal to 0.5 μm.

9. The method for manufacturing a semiconductor transfer board according to any one of claims 1 to 8, characterized in that: In step S3, the etching stop signal is captured to ensure that all through holes stop at the surface of the first dielectric layer. In step S4, the etching time is controlled to ensure that all through holes stop at a preset depth of the first dielectric layer.

10. A packaging method, characterized in that: The packaging method comprises the steps of preparing a semiconductor adapter board by using the method for manufacturing a semiconductor adapter board as described in any one of claims 1 to 9, and then bonding the chip to the semiconductor adapter board.

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