Semiconductor package

Abstract

A semiconductor package includes: a first redistribution substrate; the module structure is positioned on the first redistribution substrate; a first molding layer on the first redistribution substrate and surrounding the module structure; and a vertical connection structure on one side of the modular structure, the vertical connection structure extending vertically and connected to the first redistribution substrate, where the modular structure comprises: an interposer substrate comprising a glass substrate; a first semiconductor chip that is mounted on the interposer substrate; and a second semiconductor chip, which is mounted on the interposer substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package including a connection substrate and a method for manufacturing the same. Background Art

[0002] A semiconductor package is provided to realize an integrated circuit chip suitable for use in electronic products. With the recent development of the electronics industry, semiconductor packages have been variously developed to achieve goals such as compact size, light weight, and low manufacturing cost. The size of semiconductor chips has become smaller and smaller as semiconductor chips are highly integrated. However, due to the small size of semiconductor chips, it is difficult to adhere, handle, and test solder balls. In addition, due to the small size of semiconductor chips, there are problems in obtaining diversified mounting boards. A fan-out panel level package (FO-PLP) is proposed to solve the above problems. In a fan-out panel semiconductor package, the area of ​​the redistribution line is inevitably larger than the area of ​​the semiconductor chip. Therefore, there is a problem that the area allocated to the semiconductor chip is too large compared to the utilization rate of the semiconductor chip. Summary of the invention

[0003] Provided are a semiconductor package having improved electrical properties and a method for manufacturing the same.

[0004] In addition, a semiconductor package having improved structural stability and a method for manufacturing the same are provided.

[0005] In addition, a method for manufacturing a semiconductor package which simplifies the process and reduces the cost, and a semiconductor package manufactured by the method are also provided.

[0006] According to one aspect of an example embodiment, a semiconductor package includes: a first redistribution substrate; a module structure located on the first redistribution substrate; a first mold layer located on the first redistribution substrate and surrounding the module structure; and a vertical connection structure located on one side of the module structure, the vertical connection structure extending vertically and connected to the first redistribution substrate, wherein the module structure includes: an interposer substrate including a glass substrate; a first semiconductor chip mounted on the interposer substrate; and a second semiconductor chip mounted on the interposer substrate.

[0007] According to one aspect of an example embodiment, a semiconductor package includes: a first redistribution substrate; a connection substrate, the connection substrate is located on the first redistribution substrate, the connection substrate has an opening penetrating the connection substrate; a module structure, the module structure is located on the first redistribution substrate and is located in the opening of the connection substrate; and a first mold layer, the first mold layer is located on the first redistribution substrate, the first mold layer covers the module structure and the connection substrate, wherein the module structure includes: an interposer substrate; a first semiconductor chip, the first semiconductor chip is located on the interposer substrate; and a second semiconductor chip, the second semiconductor chip is located on the interposer substrate, wherein the interposer substrate includes: a core portion; an upper build-up portion, the upper build-up portion is located on a top surface of the core portion; and a lower build-up portion, the lower build-up portion is located on a bottom surface of the core portion, wherein the first semiconductor chip and the second semiconductor chip are electrically connected through the upper build-up portion, and the lower build-up portion directly contacts the first redistribution substrate.

[0008] According to one aspect of an example embodiment, a semiconductor package includes: a first redistribution substrate; a second redistribution substrate, the second redistribution substrate being located on the first redistribution substrate; a connecting substrate, the connecting substrate connecting the first redistribution substrate to the second redistribution substrate, the connecting substrate having an opening penetrating the connecting substrate; a module structure, the module structure being located between the first redistribution substrate and the second redistribution substrate, the module structure being located in the opening of the connecting substrate; a plurality of external terminals, the plurality of external terminals being located on a bottom surface of the first redistribution substrate; and an upper package, the upper package being mounted on the second redistribution substrate, wherein the module structure includes: an interposer substrate, the interposer substrate being connected to the first redistribution substrate; a first semiconductor chip, the first semiconductor chip being located on the interposer substrate; and a second semiconductor chip, the second semiconductor chip being located on the interposer substrate and spaced apart from the first semiconductor chip, and a core portion of the interposer substrate and a dielectric pattern of the first redistribution substrate comprising materials different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 illustrates a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0011] Figure 2 The diagram shows Figure 1An enlarged view of part A;

[0012] Figure 3 illustrates a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0013] Figure 4 The diagram shows Figure 3 An enlarged view of part B;

[0014] Figure 5 illustrates a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0015] Figure 6 The diagram shows Figure 5 An enlarged view of part C;

[0016] Figure 7 illustrates a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0017] Figure 8 The diagram shows Figure 7 An enlarged view of part D;

[0018] Fig. 9 illustrates a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0019] Fig.10 The diagram shows Fig. 9 An enlarged view of part E;

[0020] Fig.11 illustrates a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0021] Fig.12 The diagram shows Fig.11 An enlarged view of part F;

[0022] Fig.13 illustrates a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0023] Fig.14 The diagram shows Fig.13 An enlarged view of part G;

[0024] Fig.15 and Fig.16 illustrates a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0025] Figures 17 to 26Illustrated is a cross-sectional view showing a method of manufacturing a semiconductor package according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] A semiconductor package according to the present disclosure will now be described below with reference to the accompanying drawings.

[0027] Figure 1 Illustrated is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure. Figure 2 The diagram shows Figure 1 Magnified view of part A.

[0028] refer to Figure 1 and Figure 2 , a first redistribution substrate 100 may be provided. The first redistribution substrate 100 may include one first substrate wiring layer or a plurality of first substrate wiring layers stacked on each other. Each first substrate wiring layer may include a first substrate dielectric pattern 110 and a first substrate wiring pattern 120 located in the first substrate dielectric pattern 110. The first substrate wiring pattern 120 in one first substrate wiring layer may be electrically connected to the first substrate wiring pattern 120 located in an adjacent first substrate wiring layer. An example in which the configuration of the first substrate dielectric pattern 110 and the first substrate wiring pattern 120 is explained using one first substrate wiring layer will be described below.

[0029] The first substrate dielectric pattern 110 may include a polymer. The first substrate dielectric pattern 110 may include a dielectric polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric may include at least one selected from photosensitive polyimide, polybenzoxazole (PBO), phenolic polymer, and benzocyclobutene polymer. For example, the first substrate dielectric pattern 110 may include a dielectric material. For example, the first substrate dielectric pattern 110 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a dielectric polymer.

[0030] The first substrate wiring pattern 120 may be disposed below the first substrate dielectric pattern 110. The first substrate wiring pattern 120 may extend horizontally below the first substrate dielectric pattern 110. The first substrate wiring pattern 120 may be disposed on the bottom surface of the first substrate dielectric pattern 110. The first substrate wiring pattern 120 may protrude onto the bottom surface of the first substrate dielectric pattern 110. Below the first substrate dielectric pattern 110, the first substrate wiring pattern 120 may be covered by another first substrate dielectric pattern 110 located below the first substrate wiring pattern 120. The first substrate wiring pattern 120 disposed in the lowest first substrate wiring layer may be a substrate pad 122 coupled to an external terminal 150 to be discussed below. As described above, the first substrate wiring pattern 120 may be a pad or line portion of the first substrate wiring layer. In this sense, the first substrate wiring pattern 120 may be a component for horizontal redistribution in the first redistribution substrate 100. The first substrate wiring pattern 120 may include a conductive material. For example, the first substrate wiring pattern 120 may include a metal such as copper (Cu).

[0031] The first substrate wiring pattern 120 may have a mosaic structure. For example, the first substrate wiring pattern 120 may have a via protruding onto the top surface of the first substrate wiring pattern 120. The via may be a component that vertically connects the first substrate wiring patterns 120 of two adjacent first substrate wiring layers to each other. For example, the via may extend from the top surface of the first substrate wiring pattern 120, and may penetrate the first substrate dielectric pattern 110 to couple to the bottom surface of the first substrate wiring pattern 120 in another first substrate wiring layer located above the via. For example, the via may be a component for connecting the first substrate wiring pattern 120 of the topmost first substrate wiring layer to the connection substrate 200 or the module structure MS to be discussed below. For example, the via may extend from the top surface of the first substrate wiring pattern 120, and may penetrate the topmost first substrate dielectric pattern 110 to couple to the connection substrate 200 or the module structure MS to be discussed. In this configuration, the lower portion of the first substrate wiring pattern 120 located on the bottom surface of the first substrate dielectric pattern 110 may be a head used as a horizontal line or a pad, and the via of the first substrate wiring pattern 120 may be a tail. The first substrate wiring pattern 120 may have an inverted T shape.

[0032] A substrate protection layer 130 may be provided. On the bottom surface of the lowermost first substrate wiring layer, the substrate protection layer 130 may cover the substrate pad 122. According to one or more embodiments, the substrate protection layer 130 may expose the bottom surface of the substrate pad 122 while covering the bottom surface of the lowermost first substrate wiring layer. The substrate protection layer 130 may include a dielectric polymer or a photoimageable dielectric (PID).

[0033] The substrate pad 122 may be provided with an external terminal 150 on the bottom surface of the substrate pad 122. For example, the external terminal 150 may penetrate the substrate protection layer 130 to be coupled to the substrate pad 122. The external terminal 150 may include a solder ball or a solder bump. According to the type and arrangement of the external terminal 150, a ball grid array (BGA) type, a fine ball grid array (FBGA) type, or a land grid array (LGA) type semiconductor package may be provided.

[0034] exist Figure 1 In an embodiment, a semiconductor package may be provided in the form of a fan-out panel level package (FO-PLP). For example, a connection substrate 200 may be disposed on a first redistribution substrate 100. The connection substrate 200 may have an opening OP that penetrates the connection substrate 200. For example, the shape of the opening OP may be similar to an opening that connects the top surface and the bottom surface of the connection substrate 200. The opening OP may be defined as indicating a space (region) in which a module structure MS to be discussed below is disposed. The bottom surface of the connection substrate 200 may be in contact with the top surface of the first redistribution substrate 100. However, the embodiments of the present disclosure are not limited thereto, and when the semiconductor package is manufactured in a chip-later scheme, the bottom surface of the connection substrate 200 may be spaced apart from the top surface of the first redistribution substrate 100. For example, the connection substrate 200 may be connected to the first redistribution substrate 100 via separate terminals such as micro solder balls. The following description will focus on Figure 1 Embodiment of the invention.

[0035] The connection substrate 200 may include a base layer 210 and a conductive member 220, which is a line pattern disposed in the base layer 210. The conductive member 220 may have a line structure that vertically connects the first redistribution substrate 100 to the second redistribution substrate 500 to be discussed below. The conductive member 220 may be disposed between the opening OP and the outer side surface of the connection substrate 200. The conductive member 220 may include an upper pad 222, a lower pad 224, and a via 226. The upper pad 222 may be disposed on the top surface of the connection substrate 200. The upper pad 222 may protrude onto the top surface of the connection substrate 200. Unlike what is shown, the upper pad 222 may be buried in the base layer 210, and the top surface of the upper pad 222 may be coplanar with the top surface of the connection substrate 200. The lower pad 224 may be disposed on the bottom surface of the connection substrate 200. The lower pad 224 may be buried in the base layer 210, and the bottom surface of the lower pad 224 may be coplanar with the bottom surface of the connection substrate 200. The via 226 may penetrate the base layer 210, and the upper pad 222 may be electrically connected to the lower pad 224. The base layer 210 may include a polymer. For example, the base layer 210 may include a dielectric polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric may include at least one selected from photosensitive polyimide, polybenzoxazole (PBO), phenolic polymers, and benzocyclobutene polymers. For example, the base layer 210 may include a dielectric material. For example, the base layer 210 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a dielectric polymer. The upper pad 222, the lower pad 224, and the via 226 may include a conductor or metal such as copper (Cu).

[0036] The connection substrate 200 may be mounted on the first redistribution substrate 100. For example, the connection substrate 200 may be in contact with the first redistribution substrate 100. The first substrate wiring pattern 120 in the uppermost first substrate wiring layer may penetrate the uppermost first substrate dielectric pattern 110 to be coupled to the lower pad 224. Therefore, the connection substrate 200 may be electrically connected to the external terminal 150 and the module structure MS to be discussed below.

[0037] The module structure MS may be disposed on the first redistribution substrate 100. The module structure MS may be disposed in the opening OP of the connection substrate 200. In this case, the module structure MS may be located on the first redistribution substrate 100 exposed by the opening OP. The module structure MS may be in contact with the top surface of the first redistribution substrate 100. The module structure MS may be spaced apart from the connection substrate 200. For example, the module structure MS may be spaced apart from the inner side surface of the opening OP. The top surface of the module structure MS may be higher in level from the first redistribution substrate 100 than the top surface of the connection substrate 200. For example, the height of the module structure MS may be higher than the height of the connection substrate 200. In an embodiment, the top surface of the module structure MS may be the same as the top surface of the connection substrate 200 or lower than the top surface of the connection substrate 200. For example, the height of the module structure MS may be the same as the height of the connection substrate 200 or lower than the height of the connection substrate 200. The configuration of the module structure MS will be discussed in detail below.

[0038] The module structure MS may include an interposer substrate 310 , and may further include a first semiconductor chip 320 and a second semiconductor chip 330 mounted on the interposer substrate 310 .

[0039] The interposer substrate 310 may include a core portion CP, an upper build-up portion UP, and a lower build-up portion LP.

[0040] The core part CP may extend in one direction. When viewed in a top view, the core part CP may include a core pattern. The present embodiment may exemplarily describe a core part CP having a core pattern, but the embodiments of the present disclosure are not limited thereto. According to one or more embodiments, the core part CP may include two or more core patterns. For example, the interposer substrate 310 may include a plurality of core patterns spaced horizontally from each other or stacked vertically from each other. The core part CP may include a dielectric material. For example, the core part CP may include one of a glass plate, a glass fiber, a ceramic plate, an epoxy resin, and a resin. The core part CP may include a glass fiber. In this case, the interposer substrate 310 may be a glass substrate. For example, the core part CP may include silicon (Si). As another example, the core part CP may include one selected from stainless steel, aluminum (Al), nickel (Ni), magnesium (Mg), zinc (Zn), tantalum (Ta), and any combination of these materials.

[0041] The core part CP may have a vertical connection terminal 311 that vertically penetrates the core part CP. The vertical connection terminal 311 may extend from the top surface of the core part CP to the bottom surface. A portion of the vertical connection terminal 311 may extend to the bottom surface of the core part CP, and another portion of the vertical connection terminal 311 may extend to the top surface of the core part CP. The portions of the vertical connection terminal 311 that protrude onto the bottom and top surfaces of the core part CP may correspond to pads to which the upper build-up part UP and the lower build-up part LP are coupled. Figure 1 and Figure 2 The pad portion extending to the top and bottom surfaces of the core part CP of the vertical connection terminal 311 is illustrated as a component that is independent of the via portion of the vertical connection terminal 311 that penetrates the core part CP, but the embodiments of the present disclosure are not limited thereto. The pad portion and the via portion of the vertical connection terminal 311 can be provided in an integrated form. In an embodiment, the top surface of the vertical connection terminal 311 can be coplanar with the top surface of the core part CP, and the bottom surface of the vertical connection terminal 311 can be coplanar with the bottom surface of the core part CP. The vertical connection terminal 311 can be provided in plurality. The vertical connection terminal 311 may include a conductive material or a metal material, such as copper (Cu).

[0042] The upper build-up portion UP may cover the top surface of the core portion CP. The upper build-up portion UP may include an upper dielectric pattern 312 and an upper wiring pattern 313 sequentially stacked on the top surface of the core portion CP. The upper wiring pattern 313 may be connected to the vertical connection terminal 311 of the core portion CP. For example, the lowermost upper dielectric pattern 312 may contact the top surface of the core portion CP, and some of the upper wiring patterns 313 may penetrate the lowermost upper dielectric pattern 312 to contact the vertical connection terminal 311. The uppermost upper dielectric pattern 312 may expose some of the upper wiring patterns 313, and the exposed upper wiring patterns 313 may correspond to the first interposer pad 314 and the second interposer pad 315, the first interposer pad being used to mount the first semiconductor chip 320 on the interposer substrate 310, and the second interposer pad being used to mount the second semiconductor chip 330 on the interposer substrate 310.

[0043] The lower build-up portion LP may cover the bottom surface of the core portion CP. The lower build-up portion LP may include a lower dielectric pattern 316 and a lower wiring pattern 317 sequentially stacked on the bottom surface of the core portion CP. The lower wiring pattern 317 may be connected to the vertical connection terminal 311. For example, the uppermost lower dielectric pattern 316 may be in contact with the bottom surface of the core portion CP, and some of the lower wiring patterns 317 may penetrate the uppermost lower dielectric pattern 316 to contact the vertical connection terminal 311. Therefore, the upper wiring pattern 313 may be electrically connected to the lower wiring pattern 317 through the vertical connection terminal 311. The lowermost lower dielectric pattern 316 may expose some of the lower wiring patterns 317, and the exposed lower wiring patterns 317 may correspond to the third interposer pad 318 for coupling the interposer substrate 310 to the first redistribution substrate 100.

[0044] The first semiconductor chip 320 and the second semiconductor chip 330 may be mounted on the interposer substrate 310. The first semiconductor chip 320 and the second semiconductor chip 330 may be disposed to be spaced apart from each other. Figure 1 The first semiconductor chip 320 and the second semiconductor chip 330 are depicted as having the same size, but the embodiments of the present disclosure are not limited thereto. According to one or more embodiments, the first semiconductor chip 320 and the second semiconductor chip 330 may have different sizes, such as different heights or widths. The first semiconductor chip 320 and the second semiconductor chip 330 may be of the same type or of different types.

[0045] The first semiconductor chip 320 and the second semiconductor chip 330 may include semiconductor materials such as silicon (Si). The first semiconductor chip 320 and the second semiconductor chip 330 may each include a first circuit layer 322 and a second circuit layer 332. The first circuit layer 322 and the second circuit layer 332 may both include a logic circuit. For example, the first semiconductor chip 320 and the second semiconductor chip 330 may both be logic chips. For example, the first circuit layer 322 and the second circuit layer 332 may both include a memory circuit. For example, the first semiconductor chip 320 and the second semiconductor chip 330 may both be memory chips. For example, the first circuit layer 322 and the second circuit layer 332 may both include a logic circuit, a memory circuit, a passive element, or a combination of these circuits / elements. In one or more embodiments of the present disclosure, if necessary, the first circuit layer 322 and the second circuit layer 332 may include various integrated circuits. The second semiconductor chip 330 may be provided in plurality. In this case, the plurality of second semiconductor chips 330 may have a vertical chip stacking structure.

[0046] The first semiconductor chip 320 and the second semiconductor chip 330 may be in contact with the top surface of the interposer substrate 310. For example, the first chip pad 324 may be disposed on one surface of the first circuit layer 322 of the first semiconductor chip 320. The second chip pad 334 may be disposed on one surface of the second circuit layer 332 of the second semiconductor chip 330. The first semiconductor chip 320 and the second semiconductor chip 330 may be in contact with the interposer substrate 310. For example, the first circuit layer 322 of the first semiconductor chip 320 and the second circuit layer 332 of the second semiconductor chip 330 may be in contact with the upper build-up portion UP of the interposer substrate 310. The first chip pad 324 may be in contact with the first interposer pad 314. The second chip pad 334 may be in contact with the second interposer pad 315.

[0047] The first semiconductor chip 320 may be mounted on the first interposer pad 314. The first chip pad 324 may be directly connected to the first interposer pad 314. For example, a metal-to-metal bond may be implemented between the first chip pad 324 and the first interposer pad 314. In this specification, the term "hybrid bonding" may refer to a bonding in which two components of the same kind are merged at an interface between them. For example, a continuous configuration may be provided between the first chip pad 324 and the first interposer pad 314 coupled to each other, and an invisible interface may exist between the first chip pad 324 and the first interposer pad 314. The first chip pad 324 and the first interposer pad 314 may be formed of the same material and provided in the form of one component. For example, the first chip pad 324 and the first interposer pad 314 may constitute a single entity.

[0048] The second semiconductor chip 330 may be mounted on the second interposer pad 315. The second chip pad 334 may be directly connected to the second interposer pad 315. For example, a metal-to-metal bond may be implemented between the second chip pad 334 and the second interposer pad 315. A continuous configuration may be provided between the second chip pad 334 and the second interposer pad 315 coupled to each other, and an invisible interface may exist between the second chip pad 334 and the second interposer pad 315. The second chip pad 334 and the second interposer pad 315 may be formed of the same material and provided in the form of a component. For example, the second chip pad 334 and the second interposer pad 315 may constitute a single entity.

[0049] The upper wiring pattern 313 of the upper build-up portion UP may connect at least some of the first interposer pads 314 to at least some of the second interposer pads 315. The first semiconductor chip 320 and the second semiconductor chip 330 are electrically connected through the upper build-up portion UP. For example, the first interposer pad 314 on which the first semiconductor chip 320 is mounted may be connected to the second interposer pad 315 on which the second semiconductor chip 330 is mounted through the upper wiring pattern 313. Therefore, a chip-to-chip connection may be achieved between the first semiconductor chip 320 and the second semiconductor chip 330. Since the first semiconductor chip 320 and the second semiconductor chip 330 are connected through the upper build-up portion UP of the interposer substrate 310 located below the first semiconductor chip 320 and the second semiconductor chip 330, a short length electrical connection may be provided between the first semiconductor chip 320 and the second semiconductor chip 330, and the electrical properties of the semiconductor package may be improved.

[0050] The module structure MS may be connected to the first redistribution substrate 100. The module structure MS may be mounted on the first redistribution substrate 100 using a direct bonding method. For example, the third interposer pad 318 of the module structure MS may be disposed on the bottom surface of the interposer substrate 310. The interposer substrate 310 of the module structure MS may be in contact with the first redistribution substrate 100, and the module structure MS may be coupled to the first redistribution substrate 100 by penetrating the uppermost first substrate dielectric pattern 110 to couple to the first substrate wiring pattern 120 of the third interposer pad 318. Thus, the module structure MS may be electrically connected to the connection substrate 200 and the external terminal 150.

[0051] However, the embodiments of the present disclosure are not limited thereto. The bottom surface of the module structure MS may be spaced apart from the top surface of the first redistribution substrate 100. For example, the module structure MS may be connected to the first redistribution substrate 100 via terminals (e.g., micro solder balls) separately disposed on the third interposer pads 318. The following description will focus on Figure 1 Embodiment of the invention.

[0052] According to one or more embodiments of the present disclosure, a glass substrate with high strength may be used as the interposer substrate 310 for connecting the first semiconductor chip 320 and the second semiconductor chip 330 to each other. Therefore, the interposer substrate 310 may suppress warping of the semiconductor package. Therefore, the semiconductor package may have enhanced structural stability.

[0053] The mold layer 400 may be disposed on the connection substrate 200. The mold layer 400 may cover the connection substrate 200 and the module structure MS. The mold layer 400 may fill the opening OP of the connection substrate 200. For example, in the opening OP of the connection substrate 200, the mold layer 400 may fill the gap between the connection substrate 200 and the module structure MS. In one or more embodiments, when the module structure MS and the first redistribution substrate 100 are spaced apart from each other, the mold layer 400 may fill the space (region) between the module structure MS and the first redistribution substrate 100. The mold layer 400 may cover the top surface of the connection substrate 200 and the top surface of the module structure MS. For example, on the interposer substrate 310, the mold layer 400 may cover the first semiconductor chip 320 and the second semiconductor chip 330. In an embodiment, the mold layer 400 may not cover the top surface of the connection substrate 200, for example, any top surface of the first semiconductor chip 320 and the second semiconductor chip 330. The mold layer 400 may include a dielectric polymer material. For example, the molding layer 400 may include epoxy molding compound (EMC).

[0054] In one or more embodiments of the present disclosure, since the module structure MS does not have a separate molding member, the molding layer 400 can be in direct contact with the interposer substrate 310, the first semiconductor chip 320, and the second semiconductor chip 330. Since the module structure MS does not have a separate molding member, the size of the module structure MS can be reduced. In addition, since the first semiconductor chip 320 and the second semiconductor chip 330 of the module structure MS are buried and protected by the molding layer 400 of the semiconductor package, the first semiconductor chip 320 and the second semiconductor chip 330 may not be exposed to external impact, and the structural stability of any one of the module structure MS and the semiconductor package is not reduced.

[0055] The second redistribution substrate 500 may be disposed on the mold layer 400. The second redistribution substrate 500 may include one second substrate wiring layer or a plurality of second substrate wiring layers stacked on each other. Each second substrate wiring layer may include a second substrate dielectric pattern 510 and a second substrate wiring pattern 520 located in the second substrate dielectric pattern 510. The second substrate wiring pattern 520 in one second substrate wiring layer may be electrically connected to the second substrate wiring pattern 520 located in an adjacent second substrate wiring layer. An example in which the configuration of the second substrate dielectric pattern 510 and the second substrate wiring pattern 520 is explained using one second substrate wiring layer will be described below.

[0056] The second substrate dielectric pattern 510 may include a polymer. The second substrate dielectric pattern 510 may include a dielectric polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric may include at least one selected from photosensitive polyimide, polybenzoxazole (PBO), phenolic polymer, and benzocyclobutene polymer. For example, the second substrate dielectric pattern 510 may include a dielectric material. For example, the second substrate dielectric pattern 510 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a dielectric polymer.

[0057] The second substrate wiring pattern 520 may be disposed on the second substrate dielectric pattern 510. The second substrate wiring pattern 520 may extend horizontally on the second substrate dielectric pattern 510. The second substrate wiring pattern 520 may be disposed on the top surface of the second substrate dielectric pattern 510. The second substrate wiring pattern 520 may protrude onto the top surface of the second substrate dielectric pattern 510. On the second substrate dielectric pattern 510, the first substrate wiring pattern 520 may be covered by another second substrate dielectric pattern 510 located on the second substrate wiring pattern 520. The lowermost second substrate wiring pattern 520 may be disposed on the top surface of the mold layer 400, and on the mold layer 400, may be covered by the second substrate dielectric pattern 510 located on the lowermost second substrate wiring pattern 520. The second substrate wiring pattern 520 may be a pad or line portion of the second substrate wiring layer. In this sense, the second substrate wiring pattern 520 may be a component for horizontal redistribution in the second redistribution substrate 500. The second substrate wiring pattern 520 may include a conductive material. For example, the second substrate wiring pattern 520 may include copper (Cu). The second substrate wiring patterns 520 of the uppermost second substrate wiring layer may be exposed on the top surface of the second redistribution substrate 500 and may be used as pads on which an external package or electronic device is mounted.

[0058] The second substrate wiring pattern 520 may have a mosaic structure. For example, the second substrate wiring pattern 520 may have a via protruding from the bottom surface of the second substrate wiring pattern 520. The via may be a component that vertically connects the second substrate wiring patterns 520 of two adjacent second substrate wiring layers to each other. For example, the via may extend from the bottom surface of the second substrate wiring pattern 520, and may penetrate the second substrate dielectric pattern 510 to couple to the second substrate wiring pattern 520 of another second substrate wiring layer located below the via. For example, the via may connect the lowermost second substrate wiring pattern 520 to the connection substrate 200. For example, the via may extend from the bottom surface of the second substrate wiring pattern 520, and may penetrate the mold layer 400 to couple to the upper pad 222 of the connection substrate 200. In this configuration, the upper portion of the second substrate wiring pattern 520 located on the top surface of the second substrate dielectric pattern 510 may be a head used as a horizontal line or pad, and the via of the second substrate wiring pattern 520 may be a tail. The second substrate wiring pattern 520 may have a T shape.

[0059] In the following examples, Figure 1 and Figure 2 The components described in the embodiments are given the same reference numerals, and for the convenience of description, repeated descriptions of the components with the same reference numerals will be omitted or deleted. Figure 1 and Figure 2 The differences between the embodiment and other embodiments described below.

[0060] Figure 3 Illustrated is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure. Figure 4 The diagram shows Figure 3 Magnified view of part B.

[0061] refer to Figure 3 and Figure 4 , the module structure MS may further include an inner mold layer 340 .

[0062] The inner mold layer 340 may be disposed on the interposer substrate 310. On the interposer substrate 310, the inner mold layer 340 may cover the first semiconductor chip 320 and the second semiconductor chip 330. The inner mold layer 340 may surround the first semiconductor chip 320 and the second semiconductor chip 330. The inner mold layer 340 may have the same width as the width of the interposer substrate 310. For example, the side surface of the inner mold layer 340 may be vertically aligned with the side surface of the interposer substrate 310. In this case, the inner mold layer 340 may cover the top surface of the first semiconductor chip 320 and the second semiconductor chip 330. In an embodiment, the inner mold layer 340 may expose the top surface of the first semiconductor chip 320 or the top surface of the second semiconductor chip 330. The inner mold layer 340 may include a dielectric polymer material. For example, the inner mold layer 340 may include an epoxy mold compound (EMC).

[0063] The molding layer 400 may be disposed on the connection substrate 200. The molding layer 400 may cover the connection substrate 200 and the module structure MS. The molding layer 400 may cover the top surface of the connection substrate 200 and the top surface of the module structure MS. For example, the molding layer 400 may surround the interposer substrate 310 and the inner molding layer 340, and may cover the top surface of the inner molding layer 340. In an embodiment, the molding layer 400 may not cover the top surface of the inner molding layer 340.

[0064] Figure 5 Illustrated is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure. Figure 6 The diagram shows Figure 5 Magnified view of part C.

[0065] refer to Figure 5 and Figure 6 , the module structure MS may include an interposer substrate 310 , and may further include a first semiconductor chip 320 and a second semiconductor chip 330 mounted on the interposer substrate 310 .

[0066] The interposer substrate 310 may include a core portion CP and an upper build-up portion UP. Figure 1 and Figure 2 Different from the embodiments, the interposer substrate 310 may not include the lower build-up portion LP.

[0067] The module structure MS may be connected to the first redistribution substrate 100. The module structure MS may be mounted on the first redistribution substrate 100 using a direct bonding method. The interposer substrate 310 of the module structure MS may be in contact with the first redistribution substrate 100. For example, the core portion CP of the interposer substrate 310 may be in contact with the top surface of the first redistribution substrate 100. Some of the first substrate wiring patterns 120 of the first redistribution substrate 100 may penetrate the uppermost first substrate dielectric pattern 110 to be coupled to the vertical connection terminals 311 of the core portion CP. Thus, the module structure MS may be electrically connected to the connection substrate 200 and the external terminal 150.

[0068] Figure 7 Illustrated is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure. Figure 8 The diagram shows Figure 7 Magnified view of part D.

[0069] refer to Figure 7 and Figure 8 , the first semiconductor chip 320 and the second semiconductor chip 330 may further include a chip path. The first semiconductor chip 320 may further include a first chip path 326, which vertically penetrates the first semiconductor chip 320 to couple to the first circuit layer 322. The end of the first chip path 326 may be exposed on the top surface of the first semiconductor chip 320. The second semiconductor chip 330 may further include a second chip path 336, which vertically penetrates the second semiconductor chip 330 to couple to the second circuit layer 332. The end of the second chip path 336 may be exposed on the top surface of the second semiconductor chip 330. The first chip path 326 and the second chip path 336 may include a conductive material. For example, the first chip path 326 and the second chip path 336 may include a metal material, such as copper (Cu) or tungsten (W).

[0070] The first semiconductor chip 320 and the second semiconductor chip 330 may further include backside pads. The first semiconductor chip 320 may further include a first backside pad 328 disposed on the top surface of the first semiconductor chip 320 and connected to the first chip via 326. The second semiconductor chip 330 may further include a second backside pad 338 disposed on the top surface of the second semiconductor chip 330 and connected to the second chip via 336.

[0071] The mold layer 400 may be disposed on the connection substrate 200. The mold layer 400 may cover the connection substrate 200 and the module structure MS.

[0072] The second redistribution substrate 500 may be disposed on the mold layer 400. The second redistribution substrate 500 may include one second substrate wiring layer or a plurality of second substrate wiring layers stacked on each other. Each second substrate wiring layer may include a second substrate dielectric pattern 510 and a second substrate wiring pattern 520 located in the second substrate dielectric pattern 510. The lowermost second substrate wiring pattern 520 of the second redistribution substrate 500 may extend from the bottom surface of the second substrate wiring pattern 520 and may penetrate the mold layer 400 to be coupled to the upper pad 222 of the connection substrate 200, the first backside pad 328 of the first semiconductor chip 320, and the second backside pad 338 of the second semiconductor chip 330.

[0073] According to one or more embodiments of the present disclosure, the second redistribution substrate 500 may be electrically connected to the first semiconductor chip 320 and the second semiconductor chip 330 through the first chip via 326 of the first semiconductor chip 320 and the second chip via 336 of the second semiconductor chip 330. Therefore, a short length electrical connection may be provided between the second redistribution substrate 500 and the first semiconductor chip 320 and the second semiconductor chip 330, and electrical characteristics of the semiconductor package may be enhanced.

[0074] exist Figures 1 to 8 In the embodiment, the first semiconductor chip 320 and the second semiconductor chip 330 are mounted on the interposer substrate 310 using a hybrid bonding method, but the embodiments of the present disclosure are not limited thereto.

[0075] Fig. 9 Illustrated is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure. Fig.10 The diagram shows Fig. 9 Magnified view of part E.

[0076] refer to Fig. 9 and Fig.10 , the first semiconductor chip 320 may be mounted on the interposer substrate 310. For example, the first semiconductor chip 320 may be mounted on the interposer substrate 310 in a flip chip manner. In this case, the first semiconductor chip 320 may be electrically connected to the first interposer pad 314 of the interposer substrate 310 through the first connection terminal 352. The first connection terminal 352 may be disposed between the first interposer pad 314 and the first chip pad 324. The first semiconductor chip 320 may be electrically connected to the interposer substrate 310 through the first chip pad 324, the first connection terminal 352, and the first interposer pad 314. When the first semiconductor chip 320 is mounted through the first connection terminal 352, the first semiconductor chip 320 may be spaced apart from the top surface of the interposer substrate 310.

[0077] The second semiconductor chip 330 may be mounted on the interposer substrate 310. For example, the second semiconductor chip 330 may be mounted on the interposer substrate 310 in a flip chip manner. In this case, the second semiconductor chip 330 may be electrically connected to the second interposer pad 315 of the interposer substrate 310 through the second connection terminal 354. The second connection terminal 354 may be disposed between the second interposer pad 315 and the second chip pad 334. The second semiconductor chip 330 may be electrically connected to the interposer substrate 310 through the second chip pad 334, the second connection terminal 354, and the second interposer pad 315. When the second semiconductor chip 330 is mounted through the second connection terminal 354, the second semiconductor chip 330 may be spaced apart from the top surface of the interposer substrate 310.

[0078] Fig.11 Illustrated is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure. Fig.12 The diagram shows Fig.11 Magnified view of part F.

[0079] refer to Fig.11 and Fig.12 ,and Fig. 9 and Fig.10 In different embodiments, the first semiconductor chip 320 may be mounted on the interposer substrate 310 in a wire bonding manner. For example, the first semiconductor chip 320 and the second semiconductor chip 330 may be disposed on the interposer substrate 310 in a face-up manner. In an embodiment, the first semiconductor chip 320 and the second semiconductor chip 330 may both be attached to the top surface of the interposer substrate 310 by an adhesive layer. The first chip pad 324 may be exposed on the top surface of the first semiconductor chip 320, and the second chip pad 334 may be exposed on the top surface of the second semiconductor chip 330.

[0080] The first chip pad 324 may be connected to the first interposer pad 314 through a first bonding wire 356. For example, each first bonding wire 356 may extend from a top surface of one first chip pad 324 toward a top surface of one first interposer pad 314. The second chip pad 334 may be connected to the second interposer pad 315 through a second bonding wire 358. For example, each second bonding wire 358 may extend from a top surface of one second chip pad 334 toward a top surface of one second interposer pad 315. At least one first bonding wire 356 of the first semiconductor chip 320 and at least one second bonding wire 358 of the second semiconductor chip 330 may be simultaneously coupled to the interposer pads 319 in the first interposer pad 314 and the second interposer pad 315. Therefore, the first semiconductor chip 320 and the second semiconductor chip 330 may be electrically connected to each other through the first bonding wire 356, the second bonding wire 358, and the interposer pad 319.

[0081] Fig.13 Illustrated is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure. Fig.14 The diagram shows Fig.13 Magnified view of part G.

[0082] and Figures 1 to 12 Compared with the semiconductor package of FIG. 2 , the semiconductor package may not include the connection substrate 200 .

[0083] refer to Fig.13 and Fig.14 , the mold layer 400 may fill the space (area) between the first redistribution substrate 100 and the second redistribution substrate 500. On the first redistribution substrate 100, the mold layer 400 may bury the module structure MS. For example, the mold layer 400 may surround the module structure MS and may cover the top surface of the module structure MS. In this case, the module structure MS may contact the first redistribution substrate 100 and may be directly bonded to the first redistribution substrate 100.

[0084] The semiconductor package may include a through electrode 450. The through electrode 450 may be disposed to be laterally spaced apart from the module structure MS. The through electrode 450 may be disposed between the module structure MS and the outer side surface of the mold layer 400. The through electrode 450 may vertically penetrate the mold layer 400. The through electrode 450 may be coupled to the uppermost first substrate wiring pattern 120 of the first redistribution substrate 100. For example, a portion of the uppermost first substrate wiring pattern 120 may penetrate the uppermost first substrate dielectric pattern 110 to be coupled to the bottom surface of the through electrode 450. The through electrode 450 may be electrically connected to the external terminal 150 or the module structure MS through the first redistribution substrate 100. The through electrode 450 may be coupled to the uppermost second substrate wiring pattern 520 of the second redistribution substrate 500. The through electrode 450 may include a metal pillar. The through electrode 450 may have a width that increases in a direction from the first redistribution substrate 100 toward the second redistribution substrate 500. The through electrode 450 may be provided in plurality.

[0085] exist Fig.13 and Fig.14 In an embodiment, the through-electrode 450 of the second redistribution substrate 500 and the lowermost second substrate wiring pattern 520 may be connected to form a single entity. For example, when the lowermost second substrate wiring pattern 520 is formed, the through-electrode 450 may be formed at the same time. In an embodiment, the through-electrode 450 may be provided as a component provided separately from the lowermost second substrate wiring pattern 520.

[0086] Fig.15 Illustrated is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure.

[0087] refer to Fig.15 , the semiconductor package may include a lower package BP and an upper semiconductor chip 600 .

[0088] The lower package BP can be referenced with Figures 1 to 14The lower package BP may be the same as or similar to one of the semiconductor packages discussed. For example, the lower package BP may include a first redistribution substrate 100, a connection substrate 200 mounted on the first redistribution substrate, a module structure MS on the first redistribution substrate 100 and in an opening OP of the connection substrate 200, a mold layer 400 disposed on the first redistribution substrate 100 and covering the module structure MS, and a second redistribution substrate 500 located on the mold layer 400. In an embodiment, the lower package BP may include a first redistribution substrate 100, a module structure MS mounted on the first redistribution substrate 100, a mold layer 400 disposed on the first redistribution substrate 100 and covering the module structure MS, a second redistribution substrate 500 located on the module structure MS, and a through electrode (see FIG. 2 ) disposed on one side of the module structure MS and connecting the first redistribution substrate 100 to the second redistribution substrate 500. Fig.14 and Fig.15 of 450).

[0089] The upper semiconductor chip 600 may include an integrated circuit, and the integrated circuit may include a memory circuit, a logic circuit, or a combination of these circuits. The upper semiconductor chip 600 may be a semiconductor chip whose type is different from that of the first semiconductor chip 320 and the second semiconductor chip 330. For example, the upper semiconductor chip 600 may be a memory chip. Fig.15 It is depicted that one upper semiconductor chip 600 is disposed on one lower package BP, but the embodiments of the present disclosure are not limited thereto. According to one or more embodiments, a plurality of stacked upper semiconductor chips 600, such as a high bandwidth memory (HBM) device, may be disposed on the lower package BP. In an embodiment, a plurality of upper semiconductor chips 600 horizontally spaced apart from each other may be disposed on the lower package BP.

[0090] The upper chip terminal 610 may be disposed between the lower package BP and the upper semiconductor chip 600. The upper chip terminal 610 may be interposed between the upper chip pad 602 of the upper semiconductor chip 600 and the uppermost second substrate wiring pattern 520 of the second redistribution substrate 500, and may be electrically connected to the second substrate wiring pattern 520 and the upper chip pad 602. Therefore, the upper semiconductor chip 600 may be electrically connected to the external terminal 150 and the first semiconductor chip 320 and the second semiconductor chip 330 of the module structure MS through the upper chip terminal 610, the second redistribution substrate 500, and the first redistribution substrate 100.

[0091] Fig.16 Illustrated is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure.

[0092] refer to Fig.16, the semiconductor package may include a lower package BP and an upper package TP. For example, the semiconductor package may be a package-on-package (POP) in which an upper package TP is mounted on a lower package BP.

[0093] The lower package BP can be referenced with Figures 1 to 14 The lower package BP may be the same as or similar to one of the semiconductor packages discussed. For example, the lower package BP may include a first redistribution substrate 100, a connection substrate 200 mounted on the first redistribution substrate, a module structure MS on the first redistribution substrate 100 and in an opening OP of the connection substrate 200, a mold layer 400 disposed on the first redistribution substrate 100 and covering the module structure MS, and a second redistribution substrate 500 located on the mold layer 400. In an embodiment, the lower package BP may include a first redistribution substrate 100, a module structure MS mounted on the first redistribution substrate 100, a mold layer 400 disposed on the first redistribution substrate 100 and covering the module structure MS, a second redistribution substrate 500 located on the module structure MS, and a through electrode (see FIG. 2 ) disposed on one side of the module structure MS and connecting the first redistribution substrate 100 to the second redistribution substrate 500. Fig.14 and Fig.15 of 450).

[0094] The upper package TP may be mounted on the lower package BP. The upper package TP may include an upper package substrate 710 , an upper package chip 720 , and an upper molding layer 730 .

[0095] The upper package substrate 710 may be a printed circuit board (PCB). For example, the upper package substrate 710 may be a redistribution substrate. The upper package substrate 710 may have a first upper substrate pad 712 disposed on the bottom surface of the upper package substrate 710. The upper package substrate 710 may have a second upper substrate pad 714 disposed on the top surface of the upper package substrate 710.

[0096] The upper package chip 720 may be disposed on the upper package substrate 710. The upper package chip 720 may include an integrated circuit, and the integrated circuit may include a memory circuit, a logic circuit, or a combination of these circuits. The upper package chip 720 may be a semiconductor chip whose type is different from that of the first semiconductor chip 320 and the second semiconductor chip 330. For example, the upper package chip 720 may be a memory chip. The upper chip pad 722 of the upper package chip 720 may be electrically connected to the second upper substrate pad 714 of the upper package substrate 710 through a bonding wire 724. Fig.16 It is depicted that the upper package chip 720 is mounted in a wire bonding method, but the upper package chip 720 may be mounted in various ways.

[0097] An upper molding layer 730 covering the upper package chip 720 may be disposed on the upper package substrate 710. The upper molding layer 730 may include a dielectric polymer, such as an epoxy-based polymer.

[0098] The conductive terminal 716 may be disposed between the lower package BP and the upper package TP. The conductive terminal 716 may be interposed between the uppermost second substrate wiring pattern 520 of the second redistribution substrate 500 and the first upper substrate pad 712 of the upper package substrate 710, and may be electrically connected to the second substrate wiring pattern 520 and the first upper substrate pad 712. Therefore, the upper package TP may be electrically connected to the external terminal 150 and the first semiconductor chip 320 and the second semiconductor chip 330 of the module structure MS through the conductive terminal 716, the second redistribution substrate 500, and the first redistribution substrate 100.

[0099] Figures 17 to 26 Illustrated is a cross-sectional view showing a method of manufacturing a semiconductor package according to one or more embodiments of the present disclosure. Figures 17 to 21 Describes a method for forming a modular structure, and Figure 22 to Figure 26 Depicted is the use of a module structure and a connection substrate to form a semiconductor package.

[0100] refer to Fig.17 , a core part CP may be provided. A vertical connection terminal 311 connected to the core part CP may be formed. For example, the vertical connection terminal 311 may be formed by forming a hole penetrating the core part CP and then filling the hole with a conductive material.

[0101] The lower build-up portion LP may be formed on the core portion CP. For example, a dielectric layer may be formed on the top surface of the core portion CP, and then the dielectric layer may be patterned to form a lower dielectric pattern 316. A conductive layer may be formed on the lower dielectric pattern 316, and then the conductive layer may be patterned to form a lower wiring pattern 317. The processes of forming the lower dielectric pattern 316 and the lower wiring pattern 317 may be repeatedly performed. A plurality of lower dielectric patterns 316 and a plurality of lower wiring patterns 317 may constitute a reference numeral. Figure 1 Discuss the lower stacking part LP.

[0102] The resulting structure may be inverted. Thus, the lower buildup portion LP may be disposed below the core portion CP.

[0103] The upper build-up portion UP may be formed on the core portion CP. For example, a dielectric layer may be formed on the top surface of the core portion CP, and then the dielectric layer may be patterned to form an upper dielectric pattern 312. A conductive layer may be formed on the upper dielectric pattern 312, and then the conductive layer may be patterned to form an upper wiring pattern 313. The processes for forming the upper dielectric pattern 312 and the upper wiring pattern 313 may be repeatedly performed. A plurality of upper dielectric patterns 312 and a plurality of lower wiring patterns 313 may constitute a reference numeral. Figure 1 The upper piled portion of the discussion is UP.

[0104] refer to Fig.18 , the first semiconductor chip 320 and the second semiconductor chip 330 may be coupled to the upper build-up portion UP. The first semiconductor chip 320 and the second semiconductor chip 330 may be respectively connected to the reference Figures 1 to 16 The first semiconductor chips 320 and the second semiconductor chips 330 discussed are substantially the same or similar. For example, each first semiconductor chip 320 may include a first circuit layer 322 and a first chip pad 324. Each second semiconductor chip 330 may include a second circuit layer 332 and a second chip pad 334.

[0105] The first semiconductor chip 320 and the second semiconductor chip 330 may be mounted on the first interposer pad 314 and the second interposer pad 315. The first semiconductor chip 320 and the second semiconductor chip 330 may be aligned on the interposer substrate 310 so that the first chip pad 324 is located on the first interposer pad 314 of the interposer substrate 310, and the second chip pad 334 is also located on the second interposer pad 315 of the interposer substrate 310. The first semiconductor chip 320 may be disposed on the interposer substrate 310 so that the first chip pad 324 contacts the first interposer pad 314. The second semiconductor chip 330 may be disposed on the interposer substrate 310 so that the second chip pad 334 contacts the second interposer pad 315. An annealing process may be performed on the first semiconductor chip 320 and the second semiconductor chip 330. In the annealing process, the first chip pad 324 may be coupled to the first interposer pad 314, and the second chip pad 334 may be coupled to the second interposer pad 315. For example, the first chip pad 324 and the first interposer pad 314 may be bonded to form a single entity, and the second chip pad 334 and the second interposer pad 315 may be bonded to form a single entity. The bonding between the first chip pad 324 and the first interposer pad 314 may be automatically performed, and the bonding between the second chip pad 334 and the second interposer pad 315 may be automatically performed. For example, the first chip pad 324 and the first interposer pad 314 may be formed of the same material (e.g., copper (Cu)), and may be bonded to each other by a metal-to-metal hybrid bonding process generated by surface activation at an interface between the first chip pad 324 and the first interposer pad 314 that are in contact with each other, and this may be applied to the second chip pad 334 and the second interposer pad 315.

[0106] Reference again Fig.19 , a singulation process such as a sawing process may be performed to form a module structure MS. For example, the sawing process may be performed along a first sawing line SL1. The upper build-up part UP, the core part CP, and the lower build-up part LP may be cut to form an interposer substrate 310, and the module structures MS may be separated from each other, wherein the first semiconductor chip 320 and the second semiconductor chip 330 are mounted on the interposer substrate 310.

[0107] According to one or more embodiments of the present disclosure, a separate process may be performed to form a module structure MS having a structure in which the first semiconductor chip 320 and the second semiconductor chip 330 are connected to each other. For example, the process for forming the module structure MS may be performed separately from the subsequent process for forming the connection substrate 200 and the subsequent process for embedding the module structure MS into the connection substrate 200, and if necessary, the process for forming the module structure may be changed differently. Therefore, the module structure MS may become modular, and a method for manufacturing a semiconductor package that simplifies the process and reduces the manufacturing cost may be provided.

[0108] According to one or more embodiments, a module structure MS including the inner mold layer 340 may be formed.

[0109] refer to Fig. 20 ,exist Fig.18 On the resulting structure, an inner mold layer 340 may be formed on the upper build-up part UP. For example, a dielectric material may be coated on the top surface of the upper build-up part UP to surround the first semiconductor chip 320 and the second semiconductor chip 330, and then the dielectric material may be cured to form the inner mold layer 340. The dielectric material may include a dielectric polymer or a thermosetting resin.

[0110] refer to Fig.21 , a singulation process such as a sawing process may be performed to form the module structure MS. For example, the sawing process may be performed along the first sawing line SL1. The inner mold layer 340, the upper build-up part UP, the core part CP, and the lower build-up part LP may be cut. Thus, the module structure MS may be separated from each other, wherein the first semiconductor chip 320 and the second semiconductor chip 330 are mounted on the interposer substrate 310. In this case, the reference structure MS may be manufactured. Figure 3 and Figure 4 The following description will focus on the semiconductor package discussed. Fig.19 Embodiment of the invention.

[0111] refer to Fig. 22 , a connection substrate 200 may be provided. The connection substrate 200 may be connected to the reference Figures 1 to 12 The connection substrate 200 discussed is the same or similar. For example, the connection substrate 200 may include a base layer 210 and a conductive member 220. The conductive member 220 may include an upper pad 222, a lower pad 224, and a via 226.

[0112] The carrier substrate 900 may be attached to the bottom surface of the connection substrate 200. The carrier substrate 900 may be a dielectric substrate including glass or polymer, or may be a conductive substrate including metal. The carrier substrate 900 may be attached to the lower pad 224 and the base layer 210 of the connection substrate 200 by an adhesive member provided on the top surface of the carrier substrate 900. For example, the adhesive member may include an adhesive tape.

[0113] refer to Fig.23 , an opening OP may be formed in the connection substrate 200. A portion of the connection substrate 200 may be removed to form the opening OP penetrating the connection substrate 200. The opening OP may be formed by, for example, an etching process such as drilling, laser ablation, or laser cutting. The removed portion of the connection substrate 200 may be a region where the module structure MS is provided in a subsequent process.

[0114] refer to Fig.24 , a module structure MS may be provided on the carrier substrate 900. The module structure MS may be provided in the opening OP of the connection substrate 200. The module structure MS may be attached to the carrier substrate 900. In this stage, the module structure MS may be attached to the carrier substrate 900 so that the interposer substrate 310 faces the carrier substrate 900.

[0115] A molding layer 400 may be formed on the carrier substrate 900. The molding layer 400 may fill the space (region) between the connection substrate 200 and the module structure MS. For example, a dielectric member may be injected into the space (region) between the connection substrate 200 and the module structure MS, and then the dielectric member may be cured to form the molding layer 400. According to one or more embodiments, the dielectric member may be formed to cover the module structure MS. Therefore, the first semiconductor chip 320 and the second semiconductor chip 330 of the module structure MS may not be exposed. In an embodiment, a portion of the dielectric member may be provided to cover the top surface of the connection substrate 200. Therefore, the upper pad 222 of the connection substrate 200 may not be exposed. In an embodiment, the molding layer 400 may be formed so as not to cover the top surface of the connection substrate 200.

[0116] refer to Fig.25, a second redistribution substrate 500 may be formed on the connection substrate 200 and the module structure MS. For example, the mold layer 400 may be patterned to expose the upper pad 222 of the connection substrate 200. A conductive layer may be formed on the top surface of the mold layer 400, and the conductive layer may be patterned to form a second substrate wiring pattern 520. A dielectric layer may be formed on the upper surface of the mold layer 400 to cover the second substrate wiring pattern 520, the dielectric layer may be patterned to form a second substrate dielectric pattern 510, a conductive layer may be formed on the second substrate dielectric pattern 510, and the conductive layer may be patterned to form a second substrate wiring pattern 520, resulting in a second substrate wiring layer being formed. The formation of the second substrate wiring layer may be repeatedly performed to form the second redistribution substrate 500.

[0117] refer to Fig.26 , can be reversed Fig.25 Thus, the carrier substrate 900 may be disposed over the connection substrate 200 and the module structure MS.

[0118] The carrier substrate 900 may be removed. Thus, the bottom surface of the connection substrate 200 may be exposed, and likewise, the bottom surface of the module structure MS may be exposed. For example, the lower pad 224 of the connection substrate 200 may be exposed, and the third interposer pad 318 of the lower build-up portion LP of the interposer substrate 310 may be exposed.

[0119] The first redistribution substrate 100 may be formed on the connection substrate 200 and the module structure MS. For example, a dielectric layer may be formed on the top surface of the connection substrate 200 and the top surface of the module structure MS, the dielectric layer may be patterned to form a first substrate dielectric pattern 110, a conductive layer may be formed on the first substrate dielectric pattern 110, and the conductive layer may be patterned to form a first substrate wiring pattern 120, with the result that one first substrate wiring layer may be formed. The formation of the first substrate wiring layer may be repeatedly performed to form the first redistribution substrate 100. The first substrate wiring pattern 120 disposed in the uppermost first substrate wiring layer may be a substrate pad 122. Thereafter, a substrate protection layer 130 covering the substrate pad 122 may be formed on the first substrate wiring layer.

[0120] Return to reference Figure 1 , the substrate protection layer 130 may be patterned to expose the substrate pad 122. The external terminal 150 may be attached to the substrate pad 122.

[0121] In the semiconductor package according to one or more embodiments of the present disclosure, since the semiconductor chip is connected through the upper stacking portion of the interposer substrate located below the semiconductor chip, a short-length electrical connection can be provided between the semiconductor chips, and the electrical properties of the semiconductor package can be improved. In addition, a glass substrate with high strength can be used as an interposer substrate for connecting the semiconductor chip. Therefore, the interposer substrate can suppress the warping of the semiconductor package. Therefore, the semiconductor package can have improved structural stability. In addition, the module structure may not have a separate molding member used only for the module structure, and the size of the module structure can be reduced. In addition, because the molding structure of the semiconductor package buries and covers the semiconductor chip of the module structure, the semiconductor chip may not be exposed to external impact, and the structural stability of either the module structure and the semiconductor package will not be reduced.

[0122] According to one or more embodiments of the present disclosure, the process for forming the module structure can be performed separately from the subsequent process for forming the connection substrate and the subsequent process for embedding the module structure into the connection substrate, and if necessary, the process for forming the module structure can be changed differently. Therefore, the module structure can become modular, and a method for manufacturing a semiconductor package that simplifies the process and reduces the manufacturing cost can be provided.

[0123] Although certain embodiments of the present disclosure have been described and shown, it will be appreciated by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and essential features of the present disclosure. Therefore, the embodiments disclosed above should be considered as illustrative rather than restrictive.

Claims

1. A semiconductor package, comprising: a first redistribution substrate; a module structure, the module structure being located on the first redistribution substrate; a first molding layer, the first molding layer being located on the first redistribution substrate and surrounding the module structure; as well as a vertical connection structure, the vertical connection structure being located at one side of the module structure, the vertical connection structure extending vertically and connected to the first redistribution substrate, Wherein, the module structure includes: an interposer substrate, the interposer substrate comprising a glass substrate; a first semiconductor chip mounted on the interposer substrate; and A second semiconductor chip is mounted on the interposer substrate.

2. The semiconductor package according to claim 1, wherein: The vertical connection structure includes a connection substrate located on the first redistribution substrate, the connection substrate having an opening penetrating the connection substrate, wherein the module structure is located in the opening, and The first molding layer fills the area between the connection substrate and the module structure in the opening.

3. The semiconductor package according to claim 2, wherein: The connection substrate includes a base layer and a conductive member located in the base layer, and Wherein, the base layer of the connection substrate includes a polymer.

4. The semiconductor package according to claim 1, wherein: The first mold layer covers the first semiconductor chip and the second semiconductor chip.

5. The semiconductor package according to claim 1, wherein: The interposer substrate directly contacts a top surface of the first redistribution substrate, and Wherein, the wiring pattern of the interposer substrate is connected to the wiring pattern of the first redistribution substrate.

6. The semiconductor package according to claim 1, wherein: The first redistribution substrate includes a dielectric pattern, and Wherein, the dielectric pattern comprises a polymer. 7 . The semiconductor package according to claim 1 , further comprising a second redistribution substrate located on the first molding layer, in, The vertical connection structure connects the first redistribution substrate to the second redistribution substrate at the one side of the module structure, wherein the first semiconductor chip includes a plurality of chip vias vertically penetrating the first semiconductor chip, and The plurality of chip vias of the first semiconductor chip are connected to wiring patterns of the second redistribution substrate.

8. The semiconductor package according to claim 1, further comprising: a second redistribution substrate located on the first molding layer, wherein the vertical connection structure connects the first redistribution substrate to the second redistribution substrate at the one side of the module structure; and An upper package is located on the second redistribution substrate.

9. The semiconductor package according to claim 1, wherein: The first semiconductor chip and the second semiconductor chip are both coupled to the interposer substrate through solder balls or bonding wires, or A first die pad of the first semiconductor chip and a second die pad of the second semiconductor chip are directly connected to a wiring pattern of the interposer substrate.

10. The semiconductor package according to claim 1, wherein The module structure further includes a second molding layer located on the interposer substrate, the second molding layer covers the first semiconductor chip and the second semiconductor chip, and Wherein, the width of the second molding layer is the same as the width of the interposer substrate.

11. The semiconductor package according to claim 1, wherein: The interposer substrate comprises: a core portion, the core portion comprising glass fibers; an upper buildup portion located on a top surface of the core portion; and a lower accumulation portion located on a bottom surface of the core portion, and Wherein, the first semiconductor chip and the second semiconductor chip are mounted on the upper build-up portion.

12. The semiconductor package according to claim 11, wherein The first semiconductor chip and the second semiconductor chip are electrically connected through the upper build-up portion.

13. A semiconductor package, comprising: a first redistribution substrate; a connection substrate, the connection substrate being located on the first redistribution substrate, the connection substrate having an opening penetrating the connection substrate; a module structure, the module structure being located on the first redistribution substrate and in the opening of the connection substrate; as well as a first molding layer, the first molding layer being located on the first redistribution substrate, the first molding layer covering the module structure and the connection substrate, Wherein, the module structure includes: Interposer substrate; a first semiconductor chip, the first semiconductor chip being located on the interposer substrate; and a second semiconductor chip, the second semiconductor chip being located on the interposer substrate, Wherein, the interposer substrate comprises: Core part; an upper buildup portion located on a top surface of the core portion; and a lower accumulation portion, the lower accumulation portion being located on a bottom surface of the core portion, wherein the first semiconductor chip and the second semiconductor chip are electrically connected via the upper build-up portion, and Wherein, the lower accumulation portion directly contacts the first redistribution substrate.

14. The semiconductor package according to claim 13, wherein: The core portion includes glass or silicon. 15 . The semiconductor package according to claim 13 , further comprising a second redistribution substrate located on the first molding layer, in, The connection substrate connects the first redistribution substrate to the second redistribution substrate.

16. The semiconductor package according to claim 15, wherein: The first semiconductor chip includes a plurality of chip vias vertically penetrating the first semiconductor chip, and The plurality of chip vias of the first semiconductor chip are connected to wiring patterns of the second redistribution substrate. 17 . The semiconductor package of claim 15 , further comprising an upper package on the second redistribution substrate.

18. The semiconductor package according to claim 13, wherein: The first mold layer covers the first semiconductor chip and the second semiconductor chip.

19. The semiconductor package according to claim 13, wherein: The module structure further includes a second molding layer located on the interposer substrate, the second molding layer covers the first semiconductor chip and the second semiconductor chip, and Wherein, the width of the second molding layer is the same as the width of the interposer substrate.

20. A semiconductor package, comprising: a first redistribution substrate; a second redistribution substrate, the second redistribution substrate being located on the first redistribution substrate; a connection substrate connecting the first redistribution substrate to the second redistribution substrate, the connection substrate having an opening penetrating the connection substrate; a module structure, the module structure being located between the first redistribution substrate and the second redistribution substrate, the module structure being located in the opening of the connection substrate; a plurality of external terminals, the plurality of external terminals being located on a bottom surface of the first redistribution substrate; as well as an upper package, wherein the upper package is mounted on the second redistribution substrate, Wherein, the module structure includes: an interposer substrate connected to the first redistribution substrate; a first semiconductor chip, the first semiconductor chip being located on the interposer substrate; and a second semiconductor chip located on the interposer substrate and spaced apart from the first semiconductor chip, and The core portion of the interposer substrate and the dielectric pattern of the first redistribution substrate include different materials from each other.

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