Chip structure and wafer level packaging method

Abstract

The invention discloses a chip structure and a wafer level packaging method.The chip structure comprises a first base layer, a second base layer and a box dam structure connecting the first base layer and the second base layer, the first base layer is provided with a through hole penetrating in the thickness direction of the first base layer, and the second base layer comprises a first welding pad area; the chip structure comprises a heat dissipation column arranged in the through hole, and the box dam structure comprises a second metal supporting dam used for connecting the heat dissipation column and the first welding pad area; the first welding pad area, the second metal supporting dam and the heat dissipation column form an upward heat dissipation channel, so that the heat dissipation capability is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging and testing, and in particular to a chip structure and a wafer-level packaging method. Background Art

[0002] In the prior art, the packaging structure of an image sensor chip usually includes a cover wafer, a device wafer and a dam structure. A pad area is set on the surface of the device wafer facing the cover wafer, and a through hole and a welding column are set on the surface of the device wafer facing away from the cover wafer. On the one hand, the welding column is used for electrical connection to the outside, and on the other hand, the through hole and the welding column can form a downward heat dissipation channel for heat dissipation of the chip structure.

[0003] However, with the advancement of semiconductor chip packaging structure manufacturing processes, the number of transistors per unit area is increasing, and the unit heat generation of the chip packaging structure will also increase accordingly, requiring the heat dissipation capacity of the chip packaging structure to be enhanced. Summary of the invention

[0004] One of the purposes of the present invention is to provide a chip structure to solve the technical problem of insufficient heat dissipation capacity in the prior art.

[0005] One of the objectives of the present invention is to provide a wafer-level packaging method.

[0006] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a chip structure, comprising: a first base layer, a second base layer and a dam structure connecting the first base layer and the second base layer, the first base layer is provided with a through hole penetrating along its thickness direction, the second base layer includes a first solder pad area, the chip structure includes a heat dissipation column arranged in the through hole, and the dam structure includes a second metal support dam for connecting the heat dissipation column and the first solder pad area.

[0007] As a further improvement of an embodiment of the present invention, the second base layer has a functional surface and a functional area arranged on the functional surface, the first pad area is located outside the functional area, and the second metal support dam is surrounded outside the functional area.

[0008] As a further improvement of one embodiment of the present invention, the first base layer has a first surface facing the second base layer and a second surface away from the second base layer, the through hole passes through the first surface and the second surface, the chip structure includes a heat dissipation layer arranged on the second surface, and the heat dissipation column is connected to the heat dissipation layer at one end away from the second metal support dam.

[0009] As a further improvement of an embodiment of the present invention, the area covered by the heat dissipation layer is opposite to the area outside the functional area.

[0010] As a further improvement of an embodiment of the present invention, the area covered by the heat dissipation layer is opposite to the functional area and the first pad area.

[0011] As a further improvement of an embodiment of the present invention, the chip structure includes a heat dissipation module arranged on the heat dissipation layer.

[0012] As a further improvement of an embodiment of the present invention, the chip structure includes a circuit board arranged on the side of the second base layer away from the first base layer, the first pad area is connected to the circuit board, and the heat dissipation module is connected to the heat dissipation area of ​​the circuit board.

[0013] As a further improvement of an embodiment of the present invention, the dam structure includes a first metal support dam located outside a second metal support dam, the first metal support dam is located outside the first pad area, and there is a gap between the first metal support dam and the second metal support dam.

[0014] As a further improvement of an embodiment of the present invention, the dam structure includes an organic support dam located between the first base layer and the second base layer, and the organic support dam is located outside the functional area.

[0015] As a further improvement of one embodiment of the present invention, the first base layer has a first surface facing the second base layer and a second surface away from the second base layer, and the chip structure includes a metal shading layer attached to the first surface, and the metal shading layer is located on the outside of the functional area, and the metal shading layer is thinner than the dam structure.

[0016] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a wafer-level packaging method, comprising the following steps:

[0017] Providing a first wafer and a second wafer, wherein the second wafer has a first pad area;

[0018] Making a through hole in the first wafer, wherein the through hole passes through the first surface and the second surface of the first wafer;

[0019] Making a heat dissipation column in the through hole;

[0020] Making a second metal support dam, wherein the second metal support dam is connected to the heat dissipation column;

[0021] The second metal support dam is connected to the first pad area.

[0022] As a further improvement of an embodiment of the present invention, “making a heat dissipation column in the through hole” includes:

[0023] Metal is plated on the surface of the first wafer and in the through hole to form a metal seed layer located on the surface of the first wafer and a heat dissipation column located in the through hole.

[0024] As a further improvement of an embodiment of the present invention, after “making a heat dissipation column in the through hole”, the method further includes: patterning the metal seed layer to form a heat dissipation layer located on the second surface.

[0025] As a further improvement of an embodiment of the present invention, “making a second metal support dam” includes:

[0026] Applying a glue layer on one side of the first wafer and patterning it to form transition layers and through grooves arranged at intervals;

[0027] Electroplating metal in the through groove to form a metal support dam, wherein the metal support dam includes the second metal support dam;

[0028] The transition layer is removed.

[0029] As a further improvement of an embodiment of the present invention, “making a second metal support dam” includes:

[0030] Applying a glue layer on one side of the first wafer for the first time and performing a first patterning to form a first transition layer and a first through groove arranged at intervals;

[0031] Electroplating metal in the first through groove to form a metal light shielding layer;

[0032] Applying a glue layer on one side of the metal light shielding layer for a second time and performing a second patterning to form a second transition layer and a second through groove arranged at intervals;

[0033] Electroplating metal in the second through groove to form a metal support dam, wherein the metal support dam includes the second metal support dam;

[0034] The first transition layer and the second transition layer are removed.

[0035] As a further improvement of one embodiment of the present invention, "connecting the second metal support dam and the first pad area" includes: connecting the second metal support dam and the first pad area by metal bonding, conductive adhesive bonding, insulating adhesive bonding, or dielectric-free bonding.

[0036] As a further improvement of an embodiment of the present invention, "connecting the second metal support dam and the first pad area" includes: making an organic support dam between the first wafer and the second wafer.

[0037] As a further improvement of one embodiment of the present invention, the steps are as follows:

[0038] Making a metal bump on a side of the second wafer facing away from the first wafer, wherein the metal bump is connected to the first pad area to form a wafer-level packaging structure;

[0039] The wafer-level packaging structure is cut to form a single chip structure.

[0040] As a further improvement of one embodiment of the present invention, the steps are as follows:

[0041] A heat dissipation module is provided, connected to the heat dissipation layer of the chip structure.

[0042] As a further improvement of one embodiment of the present invention, the steps are as follows:

[0043] Providing a circuit board, the metal bumps of the chip structure being welded to the circuit board;

[0044] The heat dissipation module is connected to the heat dissipation area of ​​the circuit board.

[0045] Compared with the prior art, the present invention provides a chip structure and a wafer-level packaging method. The heat dissipation column, the first pad area, and the second metal support dam connecting the heat dissipation column and the first pad area of ​​the chip structure form an upward heat dissipation channel to enhance the heat dissipation capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Schematic diagram of the chip structure in the first embodiment of the present invention.

[0047] Figure 2 Schematic diagram of the chip structure in the second embodiment of the present invention.

[0048] Figure 3 Schematic diagram of the chip structure in the third embodiment of the present invention.

[0049] Figure 4 Schematic diagram of the chip structure in the fourth embodiment of the present invention.

[0050] Figure 5 It is a schematic diagram of manufacturing a heat dissipation column in one embodiment of the present invention.

[0051] Figure 6 It is a schematic diagram of the steps of making the second metal support dam in the first embodiment of the present invention.

[0052] Figure 7 It is a schematic diagram of the steps of making the second metal support dam in the second embodiment of the present invention.

[0053] Figure 8 It is a schematic diagram of the steps of making the second metal support dam in the third embodiment of the present invention.

[0054] Fig. 9 It is a schematic diagram of the steps of making the second metal support dam in the fourth embodiment of the present invention.

[0055] Fig.10It is a schematic diagram of the steps of bonding a first wafer and a second wafer in one embodiment of the present invention.

[0056] Fig.11 Schematic diagram of the steps of cutting a wafer-level packaging structure in one embodiment of the present invention.

[0057] Fig.12 Schematic diagram of a first wafer surface heat dissipation layer in one embodiment of the present invention.

[0058] Fig.13 It is a schematic diagram of a heat dissipation module disposed on the surface of the heat dissipation layer in one embodiment of the present invention.

[0059] Fig.14 Schematic diagram of a heat dissipation module connected to a circuit board in one embodiment of the present invention. DETAILED DESCRIPTION

[0060] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0061] It should be noted that the term "comprises" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, the terms "first", "second", "third", "fourth", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0062] The terms "connected", "connected to" or any other variants are intended to cover various relative positions in a connection relationship, so as to include direct connection or indirect connection. Among them, the direct connection can be formed by a gas pipeline, the indirect connection can be a connection relationship established by a device such as a valve body, a sensor, etc., can be a connection relationship established by a gas circuit component such as a brake control unit, or can be a connection relationship established by any other medium such as air.

[0063] See also Figure 1 , is a schematic structural diagram of a chip structure 1000 provided in one embodiment of the present invention.

[0064] The chip structure 1000 includes a first base layer 10, a second base layer 20, and a dam structure 30 connecting the first base layer 10 and the second base layer 20. The first base layer 10 is provided with a through hole 101 penetrating along its thickness direction. The second base layer 20 includes a first pad area 22. The chip structure 1000 includes a heat dissipation column 40 arranged in the through hole 101. The dam structure 30 includes a second metal support dam 32 for connecting the heat dissipation column 40 and the first pad area 21.

[0065] The heat dissipation column 40 , the first pad area 22 and the second metal support dam 32 form an upward heat dissipation channel to enhance the heat dissipation capability of the chip structure 1000 .

[0066] The connection between the first pad area 21 and the second metal support dam 32 can be an electrical connection or an insulating connection. It can be understood that when the two are electrically connected, other wiring electrical connection designs can be reduced and thermal conductivity can be enhanced, but the second metal support dam 32 needs to be set as an intermittent ring structure in conjunction with the first pad area 21 to prevent a loop from forming between several first pad areas 21; when the two are insulated connections, the first pad area 21 can be optionally set as a continuous ring structure or an intermittent ring structure; the connected ring structure has better air tightness.

[0067] The first base layer 10 may be optionally a cover base layer, the first base layer 10 having a first surface facing the second base layer 20 and a second surface away from the second base layer 20, the through hole 101 passes through the first surface and the second surface, the heat dissipation column 40 is arranged in the through hole 101, the heat dissipation column 40 is made of metal material, can conduct heat, transfer the heat of the first surface of the first base layer 10 to the second surface and dissipate it.

[0068] The chip structure 1000 includes a heat dissipation layer 41 arranged on the second surface, and the end of the heat dissipation column 40 away from the second metal support dam 32 is connected to the heat dissipation layer 41. The heat dissipation layer 41 is also made of metal material. The heat dissipation layer 41 is attached to the second surface and has a relatively thin thickness, so as to increase the heat dissipation area and improve the heat dissipation efficiency.

[0069] refer to Figure 1 In the first embodiment, the area covered by the heat dissipation layer 41 is opposite to the functional area 21 and the first pad area 22. The heat dissipation layer 41 basically covers the entire area of ​​the second surface to increase the heat dissipation area and improve the heat dissipation efficiency. This heat dissipation layer 41 is designed for a chip structure 1000 with high requirements for heat dissipation.

[0070] refer to Figure 2In the second embodiment, the area covered by the heat dissipation layer 41 is opposite to the area outside the functional area 21. It can be seen that the heat dissipation layer 41 does not block the functional area 21, but is only arranged in the peripheral area of ​​the second surface. On the one hand, it can be used to dissipate heat, and on the other hand, it can be used to block light in special applications to improve optical performance.

[0071] In other implementations, the heat dissipation layer 41 may be selectively set to other shapes or structures. The key point is that the heat dissipation layer 41 should be connected to the heat dissipation column 40 to conduct away the heat generated by the first pad area 22 .

[0072] The chip structure 1000 includes a heat dissipation module 42 disposed on the heat dissipation layer 41, Fig.13 As shown, an independent heat dissipation block or heat dissipation sheet is added on the surface of the heat dissipation layer 41 .

[0073] Combination Fig.14 As shown, the chip structure includes a circuit board 50 arranged on the side of the second base layer 20 away from the first base layer 10, the first pad area 22 is connected to the circuit board 50, and the heat dissipation module 42 is connected to the heat dissipation area of ​​the circuit board 50. In other embodiments, the heat dissipation module 42 can also be selected to be connected to the circuit board 50 at the same time to enhance the heat dissipation performance.

[0074] The second base layer 20 may be a device base layer. The second base layer 20 includes an electrically coupled functional area 21 and a first pad area 22. The dam structure 30 is disposed outside the functional area 21 and is in a ring shape.

[0075] The second base layer 20 has a functional surface, which faces the first base layer 10. The functional area 21 is arranged on the functional surface. The first welding pad area 22 is located outside the functional area 21. The second metal support dam 32 is ring-shaped and is surrounded outside the functional area 21. When the second metal support dam 32 and the first welding pad area 22 are connected with insulating glue, the second metal support dam 32 can be optionally set as a continuous ring structure to enhance the sealing.

[0076] The dam structure 30 includes a first metal support dam 31 located outside a second metal support dam 32 . The first metal support dam 31 is located outside the first pad area 22 . There is a gap between the first metal support dam 31 and the second metal support dam 32 .

[0077] The first metal support dam 31 is configured as a continuous annular structure and is close to the outer periphery of the chip structure 1000, and is sealed near the outer side to prevent moisture and water vapor from entering; the second metal support dam 32 is configured in the second pad area, which is not only used to enhance heat dissipation, but is also used for sealing connection in one application scenario. In other application scenarios, it can also be used to achieve electrical connection between the first base layer 10 and the second base layer 20, reduce other routing designs, and facilitate miniaturization of the chip structure 1000.

[0078] The first and second metal support dams are both ring-shaped. In other words, the dam structure 30 includes at least two circles of metal support dams, and at least one circle of metal support dams is a continuous ring structure to enhance air tightness. In other embodiments, a continuous ring-shaped metal support dam can be further added to provide better air tightness and support.

[0079] The dam structure 30 includes an organic support dam 33 located between the first base layer 10 and the second base layer 20, and the organic support dam 33 is located outside the functional area 21. The dam structure 30 is formed as a mixed support dam to prevent the metal support dam from being too soft and not providing good support, while saving costs. The organic support dam 33 is arranged outside the first and second metal support dams.

[0080] The chip structure 1000 includes a metal light shielding layer 60 attached to the first surface. The metal light shielding layer 60 is located outside the functional area 21 and is thinner than the dam structure 30. Figure 3-4 As shown, a metal light shielding layer 60 is provided between the inner side of the second metal support dam 32 and the outer side of the functional area 21 , and the metal light shielding layer 60 is used to shield the stray light and other light having a negative effect on imaging from entering, so as to improve the optical performance.

[0081] This case also protects a wafer-level packaging method, combined with Figure 5-6 As shown, the chip structure 1000 is manufactured by the wafer-level packaging method. The wafer-level packaging method includes the following steps:

[0082] A first wafer 100 and a second wafer 200 are provided. The first wafer 100 is a cover wafer, and the second wafer 200 is a device wafer. The second wafer 200 includes an electrically coupled functional area 21 and a pad area 22 .

[0083] A through hole 101 is made in the first wafer 100 , and the through hole 101 passes through the first surface and the second surface of the first wafer 100 ; the through hole 101 is arranged to pass through the first wafer 100 in a thickness direction.

[0084] A heat dissipation column 40 is manufactured in the through hole 101 .

[0085] A second metal support dam 32 is manufactured, wherein the second metal support dam 32 is connected to the heat dissipation column 40 .

[0086] Connecting the second metal support dam 32 and the first pad area 22 is equivalent to connecting the first wafer 100 and the second wafer 200 .

[0087] In this way, the first pad area 22 , the second metal support dam 32 and the heat dissipation column 40 form a heat dissipation channel.

[0088] The “fabrication of the heat dissipation column 40 in the through hole 101” includes:

[0089] Combination Figure 5 As shown in FIG. 2 b , metal is plated on the surface of the first wafer 100 and in the through hole 101 to form a metal seed layer on the surface of the first wafer 100 and a heat dissipation column 40 in the through hole 101 .

[0090] After “making the heat dissipation column 40 in the through hole 101”, the method further includes: patterning the metal seed layer to form a heat dissipation layer 41 located on the second surface. Figure 6-7 As shown, the shape of the heat dissipation layer 41 actually required can be obtained by graphic processing as needed.

[0091] Combination Figure 6 As shown in a, 7a and 8a, 9a, the "patterned metal seed layer" includes: coating a colloid on a portion of the surface of the metal seed layer, and the place where the colloid is coated is the location of the heat dissipation layer 41 that needs to be retained. Therefore, the colloid can be coated at a suitable place as needed to obtain the required heat dissipation layer 41, and the exposed metal seed layer is removed by etching with a chemical solution.

[0092] In the first and second embodiments, Figure 6-7 As shown, “making the second metal support dam 32” includes:

[0093] Combination Figure 6 As shown in FIG. 7b , a glue layer is coated on one side of the first wafer 100 and patterned to form a transition layer 110 and through grooves arranged at intervals. It can be understood that the transition layer 110 and the heat dissipation layer 41 are located on opposite sides of the first wafer 100 .

[0094] Metal is electroplated in the through groove to form a metal support dam, and the metal support dam includes the first metal support dam 31 and the second metal support dam 32. The first metal support dam 31 is located outside the first pad area 22, and the second metal support dam 32 is located in the first pad area 22. In other embodiments, more metal support dams can be made as needed.

[0095] Remove the transition layer 110. It is understood that after removing the transition layer 110, it is also necessary to remove the metal seed layer located in other places outside the metal support dam. Figure 6 c, as shown in 7c.

[0096] In the third and fourth embodiments, Figure 8-9 As shown, if the metal light shielding layer 60 needs to be manufactured at the same time, two metal electroplating steps need to be performed after the heat dissipation layer 41 is manufactured. The “manufacturing of the second metal support dam 32” specifically includes:

[0097] A first adhesive layer is coated on one side of the first wafer 100 and patterned for the first time to form a first transition layer 111 and a first through groove arranged at intervals; similar to the first and second embodiments, the first transition layer 111 is arranged on opposite sides of the heat dissipation layer 41 .

[0098] The first through groove is electroplated with metal to form a metal light shielding layer 60. The metal light shielding layer 60 is relatively thin and can be formed by sputtering, evaporation or stripping. Figure 8 b, as shown in 9b.

[0099] A second adhesive layer is coated on one side of the metal light shielding layer 60 and patterned for the second time to form a second transition layer 112 and a second through groove arranged at intervals.

[0100] Electroplating metal in the second through groove forms a metal support dam, wherein the metal support dam includes the second metal support dam 32, and the metal support dam may also include the first metal support dam 31. Figure 8 c, as shown in 9c.

[0101] Remove the first transition layer 111 and the second transition layer 112. Similarly, remove the metal seed layer located in other places other than the metal support dam and the metal light shielding layer 60. Figure 8 d, as shown in 9d.

[0102] Combination Fig.10 As shown, the wafer-level packaging method includes the steps:.

[0103] “Connecting the second metal support dam 32 and the first pad area 22” includes: connecting the second metal support dam and the first pad area by metal bonding or conductive adhesive bonding, the second metal support dam and the first pad area are electrically connected, and the second metal support dam 32 should be formed into a discontinuous ring structure; or connecting the second metal support dam 32 and the first pad area 22 by insulating adhesive bonding, the second metal support dam 32 and the first pad area 22 are insulated, and the second metal support dam can be a continuous ring structure; or connecting the second metal support dam 32 and the first pad area 22 by dielectric-free bonding. The present case does not limit the specific bonding method between the second metal support dam 32 and the first pad area 22, which can be selected according to actual needs.

[0104] In one embodiment, the dam structure 30 may include only the second metal support dam 32 , or may include the first metal support dam 31 at the same time, and the sealing connection is achieved only by the metal support dam.

[0105] In one embodiment, “connecting the second metal support dam 32 and the first pad area 22” includes: making an organic support dam 33 between the first wafer 100 and the second wafer 200. In one embodiment, combining Fig.10 As shown in a, in order to strengthen the support of the dam structure 30, an organic support dam 33 can also be made at the same time. The organic support dam 33 can be arranged around the metal support dam, or can be spaced apart from the metal support dam. The positions of the organic support dam 22 and the metal support dam can be adjusted as needed.

[0106] In a specific embodiment, the dam structure 30 may be fabricated on the surface of the first wafer 100 .

[0107] Combination Fig.10 As shown in FIG. 2 b , the first wafer 100 and the second wafer 200 are bonded to each other via the dam structure 30 . In other words, the first wafer 100 and the second wafer 200 are bonded to each other via the metal support dam and / or the organic support dam.

[0108] The wafer-level packaging method comprises the steps of:

[0109] A metal bump 70 is formed on a side of the second wafer 200 facing away from the first wafer 100 . The metal bump 70 is connected to the first pad area 22 to form a wafer-level packaging structure.

[0110] The wafer-level packaging structure is cut into individual chip structures 1000 .

[0111] Combination Fig.11As shown, the first pad area 22 is arranged on the side of the second wafer 200 facing the first wafer 100, and a metal connecting column is made on the side of the second wafer 200 facing away from the first wafer 100. The metal bump 70 is connected to the first pad area 22 through the metal connecting column. The metal bump 70 is used to be welded to the circuit board 50 to achieve electrical connection between the chip structure 1000 and the circuit board 50.

[0112] In one embodiment, combining Fig.12 As shown, the entire second wafer 200 should include several second pad areas 22. The surface of the first wafer 100 can form a whole metal heat dissipation layer, and then be divided into several different second pad areas 22. The second pad areas with high heat generation are divided into larger areas, and the second pad areas with low heat generation are divided into relatively smaller areas.

[0113] In one embodiment, the wafer-level packaging method comprises the steps of:

[0114] A heat dissipation module 42 is provided, connected to the heat dissipation layer 41 of the chip structure 1000. Fig.13 As shown, a heat dissipation module 42 is disposed on a side of the first wafer 100 facing away from the second wafer 200 and is connected to the heat dissipation layer 41 to assist in heat dissipation.

[0115] A circuit board 50 is provided, and the metal bumps 70 of the chip structure 1000 are welded to the circuit board 50 to achieve the connection of the chip structure 1000 to the outside.

[0116] Connect the heat dissipation module 42 and the heat dissipation area of ​​the circuit board 50. Fig.14 As shown, the heat dissipation module 42 is also used for dissipating heat of the circuit board 50 .

[0117] The beneficial effects of the present invention are: the heat dissipation column 40, the first pad area 22 and the second metal support dam 32 form an upward heat dissipation channel to enhance the heat dissipation capacity of the chip structure 1000; the heat dissipation layer 41 further increases the heat dissipation area and improves the heat dissipation performance; and a heat dissipation module 42 is added to assist in heat dissipation.

[0118] It can be formed by referring to any of the technical solutions provided above, and will not be described in detail here.

[0119] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0120] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip structure, characterized in that: include: A first base layer, a second base layer and a dam structure connecting the first base layer and the second base layer, the first base layer is provided with a through hole penetrating along the thickness direction thereof, the second base layer includes a first solder pad area, the chip structure includes a heat dissipation column arranged in the through hole, and the dam structure includes a second metal support dam for connecting the heat dissipation column and the first solder pad area.

2. The chip structure according to claim 1, characterized in that: The second base layer has a functional surface and a functional area arranged on the functional surface, the first pad area is located outside the functional area, and the second metal support dam is surrounded outside the functional area.

3. The chip structure according to claim 1, characterized in that: The first base layer has a first surface facing the second base layer and a second surface away from the second base layer, the through hole passes through the first surface and the second surface, the chip structure includes a heat dissipation layer arranged on the second surface, and the heat dissipation column is connected to the heat dissipation layer at one end away from the second metal support dam.

4. The chip structure according to claim 3, characterized in that: The area covered by the heat dissipation layer is opposite to the area outside the functional area.

5. The chip structure according to claim 3, characterized in that: The area covered by the heat dissipation layer is opposite to the functional area and the first pad area.

6. The chip structure according to claim 3, characterized in that: The chip structure includes a heat dissipation module arranged on the heat dissipation layer.

7. The chip structure according to claim 6, characterized in that: The chip structure includes a circuit board arranged on a side of the second base layer away from the first base layer, the first pad area is connected to the circuit board, and the heat dissipation module is connected to a heat dissipation area of ​​the circuit board.

8. The chip structure according to claim 1, characterized in that: The dam structure includes a first metal support dam located outside a second metal support dam, the first metal support dam is located outside the first pad area, and a gap is provided between the first metal support dam and the second metal support dam.

9. The chip structure according to claim 1, characterized in that: The dam structure includes an organic support dam located between the first base layer and the second base layer, and the organic support dam is located outside the functional area.

10. The chip structure according to claim 1, characterized in that: The first base layer has a first surface facing the second base layer and a second surface away from the second base layer. The chip structure includes a metal light shielding layer attached to the first surface. The metal light shielding layer is located outside the functional area and is thinner than the dam structure.

11. A wafer-level packaging method, characterized in that: The following steps are involved: Providing a first wafer and a second wafer, wherein the second wafer has a first pad area; Making a through hole in the first wafer, wherein the through hole passes through the first surface and the second surface of the first wafer; Making a heat dissipation column in the through hole; Making a second metal support dam, wherein the second metal support dam is connected to the heat dissipation column; The second metal support dam is connected to the first pad area.

12. The wafer-level packaging method according to claim 11, characterized in that: “Making a heat dissipation column in the through hole” includes: Metal is plated on the surface of the first wafer and in the through hole to form a metal seed layer located on the surface of the first wafer and a heat dissipation column located in the through hole.

13. The wafer level packaging method according to claim 12, characterized in that: After "making a heat dissipation column in the through hole", it also includes: patterning the metal seed layer to form a heat dissipation layer located on the second surface.

14. The wafer-level packaging method according to claim 11, characterized in that: "Construction of the Second Metal Support Dam" includes: Applying a glue layer on one side of the first wafer and patterning it to form transition layers and through grooves arranged at intervals; Electroplating metal in the through groove to form a metal support dam, wherein the metal support dam includes the second metal support dam; The transition layer is removed.

15. The wafer-level packaging method according to claim 11, characterized in that: "Construction of the Second Metal Support Dam" includes: Applying a glue layer on one side of the first wafer for the first time and performing a first patterning to form a first transition layer and a first through groove arranged at intervals; Electroplating metal in the first through groove to form a metal light shielding layer; Applying a glue layer on one side of the metal light shielding layer for a second time and performing a second patterning to form a second transition layer and a second through groove arranged at intervals; Electroplating metal in the second through groove to form a metal support dam, wherein the metal support dam includes the second metal support dam; The first transition layer and the second transition layer are removed.

16. The wafer level packaging method according to claim 11, characterized in that: “Connecting the second metal support dam and the first pad area” includes: connecting the second metal support dam and the first pad area by metal bonding, conductive adhesive bonding, insulating adhesive bonding, or dielectric-free bonding.

17. The wafer-level packaging method according to claim 11, characterized in that: "Connecting the second metal support dam and the first pad area" includes: making an organic support dam between the first wafer and the second wafer.

18. The wafer level packaging method according to claim 11, characterized in that: Includes steps: Making a metal bump on a side of the second wafer facing away from the first wafer, wherein the metal bump is connected to the first pad area to form a wafer-level packaging structure; The wafer-level packaging structure is cut to form a single chip structure.

19. The wafer level packaging method according to claim 18, characterized in that: Includes steps: A heat dissipation module is provided, connected to the heat dissipation layer of the chip structure.

20. The wafer level packaging method according to claim 19, characterized in that: Includes steps: Providing a circuit board, the metal bumps of the chip structure being welded to the circuit board; The heat dissipation module is connected to the heat dissipation area of ​​the circuit board.

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