Semiconductor structure, manufacturing method thereof and semiconductor device

Abstract

The embodiment of the invention discloses a semiconductor structure, a manufacturing method thereof and a semiconductor device. The semiconductor structure includes a semiconductor substrate, a conductive pillar, and a stress relief structure. The conductive pillar is disposed in the semiconductor substrate. The stress relief structure is arranged on at least one side, perpendicular to the thickness direction of the semiconductor substrate, of the conductive column; the stress relief structure includes a cavity.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, and a semiconductor device. Background Art

[0002] As the size of semiconductor devices becomes smaller and smaller, and the integration becomes higher and higher, high-density three-dimensional integrated chip structures have become an important research direction, and the electrical connection of multiple integrated chips is achieved through silicon through glass via (TSV) technology. However, in the process of filling copper in TSV, since the thermal expansion coefficient of copper is much greater than that of silicon, large thermal stress will be generated, affecting the chip structure and the electrical connection performance between multiple chips. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, as well as a semiconductor device, to solve at least one problem existing in the background technology, which can reduce the stress around the first silicon groove in the semiconductor structure, improve the yield and electrical connection performance of the semiconductor structure, and have simple process steps.

[0004] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0005] On the one hand, an embodiment of the present application provides a semiconductor structure. The semiconductor structure includes: a semiconductor substrate, a conductive column and a stress relief structure. The conductive column is arranged in the semiconductor substrate. The stress relief structure is arranged on at least one side of the conductive column along a direction perpendicular to the thickness of the semiconductor substrate; the stress relief structure includes a cavity.

[0006] In some examples, the number of the stress relief structures includes a plurality; the plurality of stress relief structures are spaced apart in a direction surrounding the conductive pillar.

[0007] In some examples, the number of the stress relief structures includes a plurality of stress relief structures, the spacing between each two adjacent stress relief structures in the plurality of stress relief structures is equal; and / or the spacing between at least two stress relief structures and the same conductive pillar is equal.

[0008] In some examples, the spacing between different stress relief structures and the same conductive pillar includes a first spacing and a second spacing; the first spacing is smaller than the second spacing. The volume of the cavity of the stress relief structure spaced from the conductive pillar by the first spacing is greater than or equal to the volume of the cavity of the stress relief structure spaced from the conductive pillar by the second spacing.

[0009] In some examples, along the thickness direction of the semiconductor substrate, the size of the stress relief structure spaced apart from the conductive pillar by the first spacing is greater than or equal to the size of the stress relief structure spaced apart from the conductive pillar by the second spacing. The maximum size of the stress relief structure along the thickness direction of the semiconductor substrate is less than the thickness of the semiconductor substrate.

[0010] In some examples, along the thickness direction perpendicular to the semiconductor substrate, the size of the cross-sectional figure of the stress relief structure spaced from the conductive pillar by the first spacing is greater than or equal to the size of the cross-sectional figure of the stress relief structure spaced from the conductive pillar by the second spacing. And the maximum size of the cross-sectional figure of the stress relief structure along the thickness direction perpendicular to the semiconductor substrate is 1 / 12 to 1 / 8 of the size of the cross-sectional figure of the conductive pillar along the thickness direction perpendicular to the semiconductor substrate.

[0011] In some examples, along the arrangement direction of the plurality of conductive pillars, at least one column of stress relief structures is disposed between two adjacent conductive pillars, and the arrangement direction of the column of stress relief structures intersects with the arrangement direction of the two adjacent conductive pillars.

[0012] In some examples, the cross-sectional shape of the stress relief structure along the direction perpendicular to the thickness of the semiconductor substrate includes at least one of a circle, a rectangle and an arc. The cross-sectional shapes of the multiple stress relief structures surrounding the same conductive pillar along the direction perpendicular to the thickness of the semiconductor substrate may be different.

[0013] In some examples, the stress relief structure includes a dielectric layer and the cavity surrounded by the dielectric layer. The thickness of the dielectric layer is greater than the dimension of the cross-sectional shape of the stress relief structure along a direction perpendicular to the thickness of the semiconductor substrate, and the difference between the two is greater than or equal to 1 / 5 of the minimum dimension of the cross-sectional shape of the stress relief structure along a direction perpendicular to the thickness of the semiconductor substrate.

[0014] The stress relief structure with a cavity arranged around the conductive column has a structural property of the cavity that can provide a certain degree of elastic deformation and is conducive to absorbing part of the heat, thereby reducing the thermal stress caused by the difference in expansion coefficient between the conductive column material and the semiconductor substrate material, reducing the adverse effects of deformation of the conductive column due to factors such as thermal stress, and improving the structural stability of the conductive column. In addition, the stress relief structure is a closed solid structure (not an open groove), and the cavity is located inside the stress relief structure. When the stress relief structure absorbs stress, compared with the open groove type structure, the closed stress relief structure absorbs stress through the cavity, and the overall deformation of the stress relief structure is smaller and the structure is more stable, which is conducive to improving the structural stability and precision of the formed conductive column, and is conducive to improving the stability of the semiconductor substrate, thereby improving the stability of the electrical connection of different semiconductor structures through the conductive column.

[0015] On the other hand, an embodiment of the present application provides a method for manufacturing a semiconductor structure. The manufacturing method includes: providing a semiconductor substrate. Forming a first groove and a second groove located at least on one side of the first groove on the semiconductor substrate; the size of the opening of the second groove is smaller than the size of the opening of the first groove. Forming a dielectric layer on the semiconductor substrate; the material of the dielectric layer partially fills the second groove and covers the opening of the second groove, forming a stress relief structure with a cavity in the second groove.

[0016] In some examples, the forming of the dielectric layer on the semiconductor substrate includes: forming the dielectric layer by a deposition process, wherein a portion of the dielectric layer is located on the sidewall of the first groove to form a barrier layer. The thickness of the dielectric layer is greater than the size of the opening of the second groove, and the difference between the two is greater than or equal to 1 / 5 of the minimum size of the opening of the second groove.

[0017] In some examples, forming a first groove and a second groove located at least on one side of the first groove on the semiconductor substrate includes: forming a plurality of second grooves at intervals along a direction surrounding the first groove. The spacing between each two adjacent second grooves in the plurality of second grooves is equal; and / or the spacing between at least two second grooves and the same first groove is equal.

[0018] In some examples, forming a first groove and a second groove located at least on one side of the first groove on the semiconductor substrate includes: forming a portion of the second groove in a region spaced a first distance from the first groove; forming a portion of the second groove in a region spaced a second distance from the first groove; and the first distance is smaller than the second distance.

[0019] Among them, the depth of the second groove spaced from the first groove by the first spacing is greater than or equal to the depth of the second groove spaced from the first groove by the second spacing; and / or the size of the opening of the second groove spaced from the first groove by the first spacing is greater than or equal to the size of the opening of the second groove spaced from the first groove by the second spacing; the maximum size of the opening of the second groove is 1 / 12 to 1 / 8 of the size of the opening of the first groove.

[0020] In some examples, forming a first groove and a second groove located on at least one side of the first groove on the semiconductor substrate includes: forming at least one column of the second grooves between two adjacent first grooves along the arrangement direction of the plurality of the first grooves, and the arrangement direction of the column of the second grooves intersects with the arrangement direction of the two adjacent first grooves.

[0021] In some examples, after forming the dielectric layer on the semiconductor substrate, the manufacturing method further includes: forming a conductive material in the first groove to form a conductive column.

[0022] The beneficial effects of the method for manufacturing the semiconductor structure provided in the embodiment of the present application are the same as the beneficial effects of the semiconductor structure provided in any of the above examples, and will not be described in detail here. In addition, in the method for manufacturing the semiconductor structure, the material forming the stress relief structure is the same as the material of a dielectric layer in the process of forming the conductive column, and can be manufactured and formed by a synchronous process, with simple process steps and no additional process cost.

[0023] In yet another aspect, some embodiments of the present application provide a semiconductor device, wherein the semiconductor device comprises at least two semiconductor structures provided in any of the above examples, and the at least two semiconductor structures are coupled via the conductive pillar.

[0024] The beneficial effects of the semiconductor device provided by the embodiment of the present application are the same as the beneficial effects of the semiconductor structure provided by any of the above examples, and will not be repeated here.

[0025] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 1 ;

[0027] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 2 ;

[0028] Figure 3 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 3 ;

[0029] Figure 4 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 4 ;

[0030] Figure 5 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 5 ;

[0031] Figure 6 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 6 ;

[0032] Figure 7 A schematic diagram of an integrated structure provided in an embodiment of the present application Figure 7 ;

[0033] Figure 8 for Figure 6 A schematic cross-sectional view of the semiconductor structure along AA is shown;

[0034] Fig. 9 A schematic diagram of a process for manufacturing a semiconductor structure provided in an embodiment of the present application Figure 1 ;

[0035] Fig.10 A schematic diagram of a process for manufacturing a semiconductor structure provided in an embodiment of the present application Figure 2 ;

[0036] Fig.11 A schematic diagram of a process for manufacturing a semiconductor structure provided in an embodiment of the present application Figure 3 ;

[0037] Fig.12 (a)~ Fig.12 (e) is a schematic diagram of a process flow of a semiconductor structure provided in one embodiment of the present application;

[0038] Fig.13 A schematic diagram of the structure of a semiconductor device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0039] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0040] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0041] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0042] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers.

[0043] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part. When the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has a first element, component, region, layer or part.

[0044] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0047] In the semiconductor industry, integrated packaging technology is being continuously researched to meet the demands for miniaturization and mounting reliability. For example, the demand for miniaturization has led to the accelerated development of packages with a size close to that of a chip, while the demand for mounting reliability has emphasized the importance of packaging technology that can improve the efficiency of mounting operations and the structural and electrical reliability after mounting.

[0048] In the related art, multiple chip-sized semiconductor structures are integrated together through stacking technology and electrically connected, which can reduce the volume and area of ​​semiconductor devices. Among them, the stacked multiple semiconductor structures are electrically connected through through-silicon vias (TSV) and conductive structures formed in TSV. Therefore, the structural stability of TSV is one of the important factors affecting the electrical connection performance of the conductive structure in TSV.

[0049] At present, the conductive structure is formed by depositing copper material in the TSV hole. This process may involve the influence of factors such as electrochemical reaction, physical conditions of the electroplating process or thermodynamic characteristics of the TSV structure (differences in thermal expansion coefficients of different materials will lead to thermal stress, which will cause local temperature rise, especially in high-temperature processes). This may cause the structure of the TSV hole or the conductive structure to deform to varying degrees, reduce the stability of the electrical connection performance of the conductive structure, and cause problems such as poor contact of the conductive structure.

[0050] To this end, the related art adopts the method of forming multiple unclosed grooves around the TSV hole, and absorbing the stress generated by the conductive structure formed in the TSV hole through the deformation of the groove. However, since the groove is an unclosed structure, the deformation of the groove is unstable (for example, the deformation degree of the opening of the groove is large), which can easily lead to a large deformation degree of the TSV, especially the deformation degree of the conductive structure corresponding to the opening of the TSV hole is large, affecting the accuracy and structural stability of the conductive structure in the TSV hole, and reducing the performance of the subsequent product that realizes electrical connection through the conductive structure. Furthermore, under the research direction of improving the stress absorption effect by setting an unclosed groove in an area closer to the TSV, or increasing the number of unclosed grooves, it is more likely to cause a large deformation degree of the TSV, affecting the accuracy and structural stability of the conductive structure in the TSV hole.

[0051] In order to solve the above problems, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, and a semiconductor device, which can reduce the stress around the silicon via in the semiconductor structure, improve the structural stability of the conductive column in the silicon via, improve the yield and electrical connection performance of the semiconductor structure, and have simple process steps.

[0052] like Figures 1 to 8 As shown, an embodiment of the present application provides a semiconductor structure 100. For example, the semiconductor structure 100 can be a chip (Chip), a die (Die), or a wafer (Wafer). It should be noted that the chip (Chip) and the die (Die) can refer to the same structure (the names can be interchangeable), or the die can be a chip that is not packaged. Different levels of chip structures are set according to requirements. For example, the chip Chip, the die Die and the wafer Wafer are three different levels of chip structures. The embodiments provided in the present application are not limited to this, and semiconductor structures formed with TSV holes can be implemented using the technology provided in the present application. Subsequent examples all use "semiconductor structure" for illustrative purposes.

[0053] In some embodiments, Figure 1 As shown, the semiconductor structure 100 includes: a semiconductor substrate 110 , a conductive pillar 120 and a stress relief structure 130 .

[0054] The semiconductor substrate 110 may be a semiconductor structure 100 without TSV technology and without forming the stress relief structure 130 provided in the present application. Based on the above example of the semiconductor structure 100 , the present application does not specifically limit the material and layer structure of the semiconductor substrate 110 .

[0055] The conductive pillar 120 is disposed in the semiconductor substrate 110. For example, the conductive pillar 120 may be made of at least one of copper (Cu), aluminum (Al), tin (Sn) and nickel (Ni). For example, copper (Cu) is used.

[0056] For example, the conductive pillar 120 may penetrate the semiconductor substrate 110, that is, two opposite surfaces of the conductive pillar 120 along the thickness direction of the semiconductor substrate 110 are exposed, so as to realize the electrical connection of different semiconductor substrates 110. Alternatively, one side surface of the conductive pillar 120 along the thickness direction of the semiconductor substrate 110 may be exposed and substantially flush with the surface of the semiconductor substrate 110, so as to realize the electrical connection of different semiconductor substrates 110.

[0057] The stress relief structure 130 is disposed on at least one side of the conductive pillar 120 along a direction perpendicular to the thickness of the semiconductor substrate 110 ; the stress relief structure 130 includes a cavity 131 .

[0058] For example, the stress relief structure 130 is disposed in the semiconductor substrate 110 and extends along the thickness direction of the semiconductor substrate 110. For example, along the thickness direction of the semiconductor substrate 110, the size of the stress relief structure 130 is smaller than the size of the conductive pillar 120, that is, the size of the stress relief structure 130 does not penetrate the semiconductor substrate 110.

[0059] Furthermore, the stress relief structure 130 is disposed on at least one side of the conductive pillar 120 along a direction perpendicular to the thickness of the semiconductor substrate 110. For example, the stress relief structure 130 can be disposed on one side of the conductive pillar 120 (see Figure 2 ), can be disposed on opposite sides of the conductive pillar 120 (see Figure 3 Alternatively, a plurality of stress relief structures 130 may be disposed around one or half of the conductive pillar 120 (see Figure 4 and Figure 5 The specific number and position of the stress relief structures 130 may be adjusted according to the actual formation process of the conductive pillars 120 , which will be exemplified in the subsequent examples of this application.

[0060] The stress relief structure 130 includes a cavity 131 . The stress relief structure 130 is characterized as a closed solid structure (not an open groove). The cavity 131 is located inside the stress relief structure 130 .

[0061] The stress relief structure 130 having the cavity 131 disposed around the conductive pillar 120 has a structural property of the cavity 131 that can provide a certain degree of elastic deformation and is conducive to absorbing part of the heat, thereby reducing the thermal stress caused by the difference in expansion coefficient between the conductive pillar 120 material and the semiconductor substrate 110 material, reducing the adverse effects of deformation of the conductive pillar 120 due to factors such as thermal stress, and improving the structural stability of the conductive pillar 120. In addition, the stress relief structure 130 is a closed solid structure (not an open groove), and the cavity 131 is located inside the stress relief structure 130. When the stress relief structure 130 absorbs stress, compared with the open groove type structure, the closed stress relief structure 130 absorbs stress through the cavity 131, and the overall deformation of the stress relief structure 130 is smaller and the structure is more stable, which is conducive to improving the structural stability and precision of the formed conductive pillar 120, and is conducive to improving the stability of the semiconductor substrate 110, thereby improving the stability of the electrical connection of different semiconductor structures 100 through the conductive pillar 120.

[0062] In some examples, such as Figure 1 As shown, the stress relief structure 130 includes a dielectric layer 132 and a cavity 131 surrounded by the dielectric layer 132 .

[0063] The thickness H of the dielectric layer 132 is greater than the dimension of the cross-sectional shape of the stress relief structure 130 along a direction perpendicular to the thickness of the semiconductor substrate 110 (e.g., direction X or direction Y), and the difference between the two is greater than or equal to 1 / 5 of the minimum dimension of the cross-sectional shape of the stress relief structure 130 along a direction perpendicular to the thickness of the semiconductor substrate 110 (e.g., direction X or direction Y).

[0064] It should be noted that “the dimension of the cross-sectional shape of the stress relief structure 130 along the direction perpendicular to the thickness of the semiconductor substrate 110” refers to the dimension of the stress relief structure 130 along any direction in a plane parallel to the plane where the semiconductor substrate 110 is located, for example, Figure 1 The dimensions of the cross-sectional shape in the direction X shown may also be Figure 1 The cross-sectional dimensions in the direction Y shown in the example provided in this application do not limit the dimensions in which direction the “cross-sectional dimensions” are, as long as the material of the dielectric layer 132 mentioned in the example can form a stress relief structure 130 with a cavity 131 .

[0065] It is understandable that in the process of using the material of the dielectric layer 132 to form the stress relief structure 130, it is necessary to ensure that the material of the dielectric layer 132 can fill the groove forming the stress relief structure 130 and cover the opening of the groove to form a closed structure with a cavity 131.

[0066] For example, the thickness H of the dielectric layer 132 is greater than the thickness H of the stress relief structure 130 along the Figure 1 The dimensions of the cross-sectional shape in the direction X shown, and greater than the Figure 1 The dimensions of the cross-sectional shape in the direction Y shown, and greater than Figure 1 The dimensions of the cross-sectional shape in any direction within the plane where the directions X and Y are shown.

[0067] Furthermore, the difference between the thickness H of the dielectric layer 132 and the dimension of the stress relief structure 130 in any direction in a plane parallel to the plane where the semiconductor substrate 110 is located is greater than or equal to 1 / 5 of the minimum dimension of the stress relief structure 130 in any direction in a plane parallel to the plane where the semiconductor substrate 110 is located. Figure 1 As shown, the minimum value of the dimension of the cross-sectional shape of the stress relief structure 130 in any direction in a plane parallel to the plane where the semiconductor substrate 110 is located is the cross-sectional shape of the stress relief structure 130 along the Figure 1 If the dimension M in the direction X is shown, the difference between the thickness H of the dielectric layer 132 and the dimension M is greater than 1 / 5M. In this way, it is beneficial to form a side surface of the stress relief structure 130 that is substantially flush with the side surface of the semiconductor substrate 110 when the material of the dielectric layer 132 forms a structure with a cavity 131. Based on this, the surface of the stress relief structure 130 refers to a continuous surface located on one side of the cavity 131, and when the cavity 131 absorbs stress and deforms, it can reduce the deformation degree of the groove forming the conductive structure 120 nearby (that is, there is a certain traction effect), reduce the probability of forming a structurally unstable conductive column 120 in an over-deformed groove, and help improve the structural stability and precision of the formed conductive column 120, improve the structural stability of the semiconductor substrate 110, and improve the structural stability of the conductive column 120 in the semiconductor substrate 110.

[0068] For example, Figure 1 As shown, the cross-sectional shape of the stress relief structure 130 in a plane parallel to the plane where the semiconductor substrate 110 is located has the smallest dimension along the direction X, and the dimension M may be 500 nm; the thickness H of the dielectric layer 132 may be 600 nm.

[0069] In some examples, such as Figure 2 to Figure 7 As shown, the number of the stress relief structures 130 includes a plurality; the plurality of stress relief structures 130 are arranged at intervals along a direction surrounding the conductive pillar 120 .

[0070] For example, Figure 2 to Figure 4As shown, when multiple conductive pillars 120 are provided, multiple stress relief structures 130 can be provided in the region between adjacent conductive pillars 120. Considering that the stress generated around the conductive pillars 120 is relatively large, especially the stress between adjacent conductive pillars 120 is larger and will affect each other, the stress relief structure 130 with the cavity 131 can reduce the stress effect of the conductive pillars 120, and the stress relief structure 130 provided between adjacent conductive pillars 120 can reduce the mutual influence of the stress around the adjacent conductive pillars 120, and more significantly improve the stability of the semiconductor structure 100.

[0071] Another example, such as Figure 5 As shown, when multiple conductive pillars 120 are provided, multiple stress relief structures 130 are provided around each conductive pillar to reduce the stress around each conductive pillar 120 from multiple directions, which can significantly improve the structural stability of the conductive pillars 120 and improve the stability of the semiconductor structure 100.

[0072] Another example, such as Figure 6 As shown, a plurality of stress relief structures 130 are arranged around each conductive column 120 , and the number of stress relief structures 130 arranged in the area between adjacent conductive columns 120 is increased, which can further reduce the mutual influence of stress around adjacent conductive columns 120 and more significantly improve the stability of the semiconductor structure 100 .

[0073] In some examples, such as Figure 6 As shown, along the arrangement direction of the plurality of conductive pillars 120 , at least one column of stress relief structures 130 is disposed between two adjacent conductive pillars 120 , and the arrangement direction of one column of stress relief structures 130 intersects with the arrangement direction of two adjacent conductive pillars 120 .

[0074] For example, Figure 6 As shown, a plurality of conductive pillars 120 are arranged along directions X and Y, and two rows of stress relief structures 130 are arranged between two adjacent conductive pillars 120. Between the plurality of conductive pillars 120 arranged along direction X, two rows of stress relief structures 130 arranged along direction Y are arranged. Between the plurality of conductive pillars 120 arranged along direction Y, two rows of stress relief structures 130 arranged along direction X are arranged.

[0075] In this way, a plurality of stress relief structures 130 are arranged around each conductive column 120 to reduce the stress around each conductive column 120 from multiple directions. Furthermore, considering that the stress generated around the conductive column 120 is relatively large, especially the stress between adjacent conductive columns 120 is greater and will affect each other, two rows of stress relief structures 130 are arranged between two adjacent conductive columns 120. This can further reduce the mutual influence of stress around adjacent conductive columns 120 and more significantly improve the stability of the semiconductor structure 100.

[0076] In some examples, such as Figure 7 As shown, the cross-sectional shape of the stress relief structure 130 along the thickness direction perpendicular to the semiconductor substrate 110 includes at least one of a circle, a rectangle and an arc.

[0077] The multiple stress relief structures 130 surrounding the same conductive pillar 120 may have different cross-sectional shapes along a direction perpendicular to the thickness of the semiconductor substrate 110 .

[0078] For example, in a direction parallel and / or perpendicular to the arrangement of the multiple conductive pillars 120, multiple stress relief structures 130 with rectangular (or arc-shaped) cross-sectional shapes (perpendicular to the plane of direction Z) are arranged on one side of the conductive pillars 120, and multiple independent stress relief structures 130 with circular cross-sectional shapes (perpendicular to the plane of direction Z) are arranged in other directions.

[0079] For example, continue to see Figure 7 A stress relief structure 130 with a rectangular cross-section is disposed on one side of the conductive pillar 120 along the direction X and the direction Y, respectively, and a stress relief structure 130 with a rectangular cross-section is disposed on two opposite sides of each conductive pillar 120 along the direction X and the direction Y. That is, there are four stress relief structures 130 with a rectangular cross-section around each conductive pillar 120, and two adjacent conductive pillars 120 share one stress relief structure 130 with a rectangular cross-section.

[0080] Furthermore, along the direction surrounding the conductive pillar 120 , at least one stress relief structure 130 with a circular cross-sectional shape is disposed between two adjacent stress relief structures 130 with a rectangular cross-sectional shape, and the cross-sectional shape size of the rectangle is larger than the cross-sectional shape size of the circle.

[0081] In this way, due to the larger size of the stress relief structure 130 with a rectangular cross-sectional shape (larger volume of the cavity 131 ), the effect of reducing the stress influence is greater than that of the stress relief structure 130 with a circular cross-sectional shape. Figure 6 The location and arrangement of the stress relief structure 130 shown can significantly reduce the stress around the plurality of conductive pillars 120 , thereby improving the structural stability of the conductive pillars 120 and the structural stability of the semiconductor structure 100 .

[0082] It is understandable that the specific shape and size of the stress relief structure 130 may be adjusted according to process conditions and the size of the setting area (eg, the spacing range between the stress relief structure 130 and the conductive pillar 120 ).

[0083] In some examples, the number of the stress relief structures 130 includes a plurality of stress relief structures 130. The spacing between each two adjacent stress relief structures 130 in the plurality of stress relief structures 130 is equal; and / or the spacing between at least two stress relief structures 130 and the same conductive pillar 120 is equal.

[0084] like Figure 5 As shown, the spacing between each two adjacent stress relief structures 130 is equal along the direction X or direction Y. For example, the cross-sectional shape of the conductive pillar 120 along the direction perpendicular to the thickness of the semiconductor substrate 110 is a circle (center point Q2), and the multiple stress relief structures 130 arranged around the same conductive pillar 120 surround a rectangle (center point Q1), and the center point Q2 of the circle overlaps the center point Q1 of the rectangle. In this case, the spacing between the multiple stress relief structures 130 surrounding the same conductive pillar 120 and the conductive pillar 120 can be equal or unequal.

[0085] Alternatively, the spacings between the plurality of stress relief structures 130 around the same conductive pillar 120 and the conductive pillar 120 are equal.

[0086] It should be noted that the spacing between the conductive pillar 120 and the stress relief structure 130 can be the spacing between the central axis of the conductive pillar 120 (extending along the thickness direction of the semiconductor substrate 110) and the central axis of the stress relief structure 130, or the spacing between one side of the conductive pillar 120 and one side of the stress relief structure 130 along a certain direction. The present application does not impose any specific restrictions on this. In the same scenario, the condition parameters for comparing the spacing between multiple stress relief structures 130 and the conductive pillars 120 are consistent. For example, in the subsequent examples, the spacing between the central axis of the conductive pillar 120 and the central axis of the stress relief structure 130 is used as an example to illustrate the spacing relationship between the two.

[0087] For example, the cross-sectional shape of the conductive pillar 120 along the direction perpendicular to the thickness of the semiconductor substrate 110 is circular, and the multiple stress relief structures 130 arranged around the same conductive pillar 120 enclose a circle, and the center points of the two circles overlap. In this case, the spacing between two adjacent stress relief structures 130 can be equal or unequal.

[0088] Alternatively, the spacings between the multiple stress relief structures 130 around the same conductive pillar 120 and the conductive pillar 120 are equal, and the spacings between every two adjacent stress relief structures 130 are equal.

[0089] For example, the cross-sectional shape of the conductive pillar 120 along the direction perpendicular to the thickness of the semiconductor substrate 110 is circular, and the multiple stress relief structures 130 arranged around the same conductive pillar 120 enclose a circle, and the center points of the two circles overlap. In addition, the spacing between two adjacent stress relief structures 130 is equal.

[0090] The arrangement of the conductive pillars 120 and the stress relief structures 130 provided in the above three examples can be selected according to the size of the entire semiconductor structure 100 and the density distribution of the conductive pillars 120 , which is beneficial to improving the structural stability of the conductive pillars 120 .

[0091] In some examples, such as Figure 6 and Figure 8 As shown, the distances between different stress relief structures 130 and the same conductive pillar 120 include a first distance D1 and a second distance D2; the first distance D1 is smaller than the second distance D2.

[0092] The volume of the cavity 131 of the stress relief structure 130 spaced apart from the conductive pillar 120 by a first distance D1 is greater than or equal to the volume of the cavity 131 of the stress relief structure 130 spaced apart from the conductive pillar 120 by a second distance D2.

[0093] It is understandable that the strength of stress elimination around the conductive pillar 120 can be controlled by setting the volume of the cavity 131. The larger the volume of the cavity 131, the better the stress elimination effect.

[0094] In some examples, such as Figure 8 As shown, along the thickness direction (eg, direction Z) of the semiconductor substrate 110 , a size L1 of the stress relief structure 130 spaced apart from the conductive pillar 120 by a first distance D1 is greater than or equal to a size L2 of the stress relief structure 130 spaced apart from the conductive pillar 120 by a second distance D2.

[0095] The maximum dimension of the stress relief structure 130 along the thickness direction of the semiconductor substrate 110 is smaller than the thickness of the semiconductor substrate 110 .

[0096] It can be understood that the stress relief structure 130 is arranged in the semiconductor substrate 110 to eliminate the stress around the conductive column 120, and a cavity 131 needs to be formed inside the stress relief structure 130. The maximum dimension of the stress relief structure 130 along the thickness direction of the semiconductor substrate 110 is set to be smaller than the thickness of the semiconductor substrate 110, which is conducive to the manufacture of the stress relief structure 130.

[0097] Furthermore, based on the size range of the stress relief structure 130 along the thickness direction of the semiconductor substrate 110 , the volume of the cavity 131 can be adjusted from different angles to improve the effect of eliminating stress around the conductive pillar 120 .

[0098] For examples, see Figure 8 By setting the size of the stress relief structure 130 along the thickness direction (e.g., direction Z) of the semiconductor substrate 110, under the conditions of the process steps for forming the stress relief structure 130 (i.e., filling the groove with dielectric material to form the stress relief structure 130 having the cavity 131), the greater the groove depth, the more favorable it is to form a larger cavity 131, thereby improving the effect of eliminating the stress around the conductive pillar 120. Furthermore, the larger the volume of the cavity 131 in the stress relief structure 130 closer to the conductive pillar 120, the further improved the effect of eliminating the stress around the conductive pillar 120.

[0099] Among them, for the stress relief structure 130 between two adjacent conductive pillars 120, the volume of the cavity 131 can be the same (such as the volume of the cavity 131 of the stress relief structure 130 spaced apart from the conductive pillar 120 by the second spacing D2, or the volume of the cavity 131 of the stress relief structure 130 spaced apart from the conductive pillar 120 by the first spacing D1), or the volume of the cavity 131 of the stress relief structure 130 spaced apart from the conductive pillar 120 by the first spacing D1.

[0100] In addition to adjusting the size of the stress relief structure 130 along the thickness direction (e.g., direction Z) of the semiconductor substrate 110, based on the conditions of the process step of forming the stress relief structure 130 (i.e., filling the groove with dielectric material to form the stress relief structure 130 with the cavity 131), the opening size of the groove can also be set to adjust the amount of dielectric material filled in the groove and adjust the volume of the cavity 131 other than the dielectric material. The opening size of the groove in the process can be characterized as the size of the cross-sectional figure of the stress relief structure 130 in the semiconductor structure 100 along the thickness direction (e.g., direction X or direction Y) perpendicular to the semiconductor substrate.

[0101] In some examples, such as Figure 6 and Figure 8 As shown, along the thickness direction perpendicular to the semiconductor substrate 110 (e.g., direction Z), the size of the cross-sectional figure of the stress relief structure 130 spaced apart from the conductive pillar 120 by a first spacing D1 is greater than or equal to the size of the cross-sectional figure of the stress relief structure 130 spaced apart from the conductive pillar 120 by a second spacing D2.

[0102] Furthermore, the maximum size of the cross-sectional figure of the stress relief structure 130 along the thickness direction perpendicular to the semiconductor substrate 110 (eg, direction X or direction Y) is 1 / 12 to 1 / 8 of the size of the cross-sectional figure of the conductive pillar 120 along the thickness direction perpendicular to the semiconductor substrate 110 (eg, direction X or direction Y).

[0103] It should be noted that the size of the cross-sectional figure of the stress relief structure 130 along the thickness direction perpendicular to the semiconductor substrate 110 can be the size of the cross-sectional figure along the direction X, the size of the cross-sectional figure along the direction Y, or the size of the cross-sectional figure along any direction in the plane perpendicular to the direction Z; it can also be the area of ​​the cross-sectional figure, and the examples provided in this application are not limited to this. The subsequent examples take the area of ​​the cross-sectional figure of the stress relief structure 130 along the thickness direction perpendicular to the semiconductor substrate 110 as an example, and illustrate the effect of the volume size of the cavity 131 on the stress relief effect on the surrounding stress of the conductive pillar 120 from the perspective of the area size of the cross-sectional figure.

[0104] For example, Figure 6 and Figure 8 As shown, along the direction X, the stress relief structure 130 spaced apart from the conductive pillar 120 by a first distance D1 includes a first stress relief structure 1301. The cross-sectional shape of the first stress relief structure 1301 along the direction perpendicular to the direction Z is circular.

[0105] The stress relief structure 130 spaced apart from the conductive pillar 120 by a first distance D1 includes a second stress relief structure 1302. The cross-sectional shape of the second stress relief structure 1302 along a direction perpendicular to the direction Z is circular.

[0106] Furthermore, a size of a cross-sectional shape of the first stress relief structure 1301 along a direction perpendicular to the direction Z is greater than a size of a cross-sectional shape of the second stress relief structure 1302 along a direction perpendicular to the direction Z.

[0107] For example, continue to see Figure 6 and Figure 8 The cross-sectional shape of the first stress relief structure 1301 along the direction perpendicular to the direction Z and the cross-sectional shape of the second stress relief structure 1302 along the direction perpendicular to the direction Z are both circular, and the area of ​​the cross-sectional shape of the first stress relief structure 1301 along the direction perpendicular to the direction Z is greater than the area of ​​the cross-sectional shape of the second stress relief structure 1302 along the direction perpendicular to the direction Z.

[0108] Based on the conditions of the process steps for forming the stress relief structure 130 (i.e., filling the groove with dielectric material to form the stress relief structure 130 having the cavity 131), setting the opening size of the groove (i.e., the area of ​​the cross-sectional shape of the stress relief structure 1301 along the direction perpendicular to the direction Z) can adjust the amount of dielectric material filled in the groove and the volume of the cavity 131 other than the dielectric material. The larger the area of ​​the cross-sectional shape of the first stress relief structure 1301 closer to the conductive pillar 120 along the direction perpendicular to the direction Z, the larger the volume of the cavity 131 is, which is conducive to forming a larger volume of the cavity 131 and improving the effect of eliminating the stress around the conductive pillar 120.

[0109] In addition, the cross-sectional shape of the first stress relief structure 1301 along the direction perpendicular to the direction Z and the cross-sectional shape of the second stress relief structure 1302 along the direction perpendicular to the direction Z can be the same, and the sizes of the cross-sectional shapes of the two can also be equal. In this way, when a plurality of first stress relief structures 1301 and second stress relief structures 1302 are arranged around the same conductive column 120, the cavities 131 in the plurality of stress relief structures 130 can also significantly eliminate the stress around the conductive column 120.

[0110] On the other hand, Figures 9 to 12 As shown, the embodiment of the present application provides a method for manufacturing a semiconductor structure 100. The manufacturing method includes: S100-S400.

[0111] S100: Fig. 9 and Fig.12 As shown in (a) in FIG. 8 , a semiconductor substrate 110 is provided.

[0112] For example, the semiconductor substrate 110 may be a chip (Chip), a die (Die) or a wafer (Wafer) that has not been subjected to TSV technology and has not formed a stress relief structure 130 as provided in the present application. It should be noted that the chip (Chip) and the die (Die) may refer to the same structure (the names are interchangeable), or the die may be a chip that has not been packaged. The embodiments provided in the present application do not limit the type of the semiconductor substrate 110, and the present application does not specifically limit the layer structure and materials within the semiconductor substrate 110.

[0113] In order to illustrate the effects of the conductive pillars 120 and the stress relief structure 130 fabricated subsequently, an example is given in which the semiconductor substrate 110 includes a die that has not been subjected to TSV technology and has not formed the stress relief structure 130 provided in the present application.

[0114] S200: Fig. 9 and Fig.12 As shown in (b) of FIG. 1 , a first groove 101 and a second groove 102 located at at least one side of the first groove 101 are formed on the semiconductor substrate 110 . The opening size of the second groove 102 is smaller than the opening size of the first groove 101 .

[0115] It should be noted that the first groove 101 may be a TSV hole in the semiconductor structure, and the first groove 101 after the conductive pillar 120 is formed may be processed to form a through hole exposing both ends of the conductive pillar 120 along the thickness direction of the semiconductor substrate 110, and the present application does not limit this.

[0116] For example, the first groove 101 and the second groove 102 can be formed by setting a mask structure in a single process, or by using two photolithography processes to form the first groove 101 and the second groove 102 in steps, which is not limited in the present application.

[0117] For example, the first groove 101 and the second groove 102 are formed simultaneously during one process step. Different opening sizes of the mask and the transmittance of the opening areas for forming the first groove 101 and the second groove 102 can be set to form first grooves 101 and second grooves 102 of different depths.

[0118] In this way, the formed first groove 101 is used for forming the conductive pillar 120 in the subsequent process step, and the formed second groove 102 is used for forming the stress relief structure 130 in the subsequent process.

[0119] For example, the opening shape of the first groove 101 may be circular, and the diameter of the opening of the first groove 101 may be 5 micrometers. The opening shape of the second groove 102 may be circular, and the diameter of the opening of the second groove 102 may be 0.5 micrometers. The size of the opening of the second groove 102 is smaller than the size of the opening of the first groove 101.

[0120] Furthermore, the second groove 102 may be formed on at least one side of the first groove 101. For example, the second groove 102 may be disposed on one side of the first groove 101 (see Figure 2 The stress relief structure 130 may be disposed on one side of the conductive pillar 120 or on two opposite sides of the first groove 101 (see Figure 3 The stress relief structure 130 may be disposed on opposite sides of the conductive pillar 120), or a plurality of second grooves 102 may be disposed around a circle or a half circle of the first groove 101 (see Figure 4 and Figure 5 The stress relief structure 130 may be provided with a plurality of stress relief structures 130 around one or half of the conductive pillar 120. The number and position of the second grooves 102 may be adjusted according to the formation process of the first groove 101. The number and position of the second grooves 102 are not described in detail in this application. For details, please refer to the semiconductor structure 100 in the above-mentioned Figure 2 to Figure 8 and the method for making the second groove 102 can refer to the subsequent examples.

[0121] S300: Fig. 9 and Fig.12 As shown in (c) of FIG. 1 , a dielectric layer 132 is formed on the semiconductor substrate 110 . The material of the dielectric layer 132 partially fills the second groove 102 and covers the opening of the second groove 102 , forming a stress relief structure 130 having a cavity 131 in the second groove 102 .

[0122] For example, a dielectric layer 132 is formed by a deposition process on a semiconductor substrate 110 having a first groove 101 and a second groove 102. Since the opening size of the second groove 102 is relatively small, the material of the dielectric layer 132 is partially filled in the second groove 102, and the opening of the second groove 102 is first covered without completely filling the second groove 102, thereby forming a stress relief structure 130 having a cavity 131.

[0123] During this process step, the opening size of the second groove 102 and / or the depth of the second groove 102 can be set to adjust the volume of the cavity 131. In particular, based on covering the opening of the second groove 102, a stress relief structure 130 having a cavity 131 is formed. When the cavity 131 absorbs stress and deforms, the dielectric layer 132 is located on a continuous surface on one side of the cavity 131, which can reduce the deformation degree of the groove for forming the conductive pillar 120 nearby (i.e., there is a certain pulling effect), reduce the probability of forming a structurally unstable conductive pillar 120 in an over-deformed groove, and is conducive to improving the structural stability and precision of the formed conductive pillar 120, improving the structural stability of the semiconductor substrate 110, and improving the structural stability of the conductive pillar 120 in the semiconductor substrate 110.

[0124] It is understandable that the semiconductor substrate 110 is provided with a first groove 101 and a second groove 102 . During the formation of the dielectric layer 132 , in addition to partially filling the material in the second groove 102 , the material of the dielectric layer 132 is also deposited on the inner wall of the first groove 101 .

[0125] In some examples, such as Fig. 9 and Fig.12 As shown in (d), S300: after forming a dielectric layer 132 on the semiconductor substrate 110, the manufacturing method further includes S400: forming a conductive material in the first groove 101 to form a conductive column 120.

[0126] For example, a deposition process is used to fill the first groove 101 with a conductive material, which may include at least one of copper (Cu), tin (Sn), aluminum (Al), and the like.

[0127] After the above steps S100 to S400, the semiconductor substrate 110 with the conductive pillars 120 and the stress relief structure 130 can be subjected to chemical mechanical polishing to form the conductive pillars 120 exposed from the two opposite sides of the semiconductor substrate 110 and to make the end surfaces of the conductive pillars 120 flat (see Fig.12(e)); or, only the end surface of the conductive pillar 120 exposed from one side of the semiconductor substrate 110 is polished to obtain a flat surface. The example provided in this application does not specifically limit this, and an example is given by taking the structure of exposing the end surface of the conductive pillar 120 from the opposite two sides of the semiconductor substrate 110 as an example for illustrative description.

[0128] Furthermore, the stress relief structure 130 having the cavity 131 disposed around the conductive pillar 120 has a structural property of the cavity 131 that can provide a certain degree of elastic deformation and is conducive to absorbing part of the heat, thereby reducing the thermal stress caused by the difference in expansion coefficient between the conductive pillar 120 material and the semiconductor substrate 110 material, reducing the adverse effects of deformation of the conductive pillar 120 due to factors such as thermal stress, and improving the structural stability of the conductive pillar 120. Furthermore, the stress relief structure 130 is a closed solid structure (not an open groove), and the cavity 131 is located inside the stress relief structure 130. When the stress relief structure 130 absorbs stress, compared with the open groove type structure, the closed stress relief structure 130 absorbs stress through the cavity 131, and the overall deformation of the stress relief structure 130 is smaller and the structure is more stable, which is conducive to improving the structural stability and precision of the formed conductive pillar 120, and is conducive to improving the stability of the semiconductor substrate 110, thereby improving the stability of the electrical connection of different semiconductor structures 100 through the conductive pillar 120.

[0129] In some examples, such as Fig.10 and Fig.12 As shown in (c), step S300: forming a dielectric layer 132 on the semiconductor substrate 110, including S310: forming the dielectric layer 132 by a deposition process, wherein part of the material of the dielectric layer 132 is located on the sidewall of the first groove 101 to form a barrier layer 1321.

[0130] It is understandable that the blocking layer 1321 is part of the dielectric layer 132 , and different names are used here to distinguish the dielectric layer 132 of the stress relief structure 130 formed in one process step and the functional layer used to block impurities from diffusing into the semiconductor substrate 110 during the process of making the conductive pillar 120 .

[0131] The thickness of the dielectric layer 132 is greater than the size of the opening of the second groove 102 , and the difference between the thickness of the dielectric layer 132 is greater than or equal to 1 / 5 of the minimum size of the opening of the second groove 102 .

[0132] For example, based on the need to form a conductive column 120 in the first groove 101, a barrier layer and a seed layer need to be formed in the first groove 101 to improve the structural uniformity of the subsequent deposition of conductive materials to form the conductive column 120. Among them, the dielectric material forming the barrier layer can be used to form the dielectric layer 132 of the stress relief structure 130. In this way, the process steps for forming the stress relief structure 130 in the present application are simple and will not increase additional process costs.

[0133] The above-mentioned method is performed by setting the thickness of the dielectric layer 132 to be greater than the size of the opening of the second groove 102, and the difference between the thickness of the dielectric layer 132 and the opening of the second groove 102 is greater than or equal to 1 / 5 of the minimum size of the opening of the second groove 102. Figure 1 and Fig.12 As shown in (e), the cross-sectional shape of the stress relief structure 130 in a plane parallel to the plane where the semiconductor substrate 110 is located has the smallest dimension along the direction X, and the dimension M may be 500 nm; the thickness H of the dielectric layer 132 may be 600 nm.

[0134] In this way, the material of the dielectric layer 132 can at least cover the opening of the second groove 102, forming a stress relief structure 130 having a cavity 131. Such a stress relief structure 130 is characterized as a closed entity structure (not an open groove), and the cavity 131 is located inside the stress relief structure 130. When the stress relief structure 130 absorbs the stress effect, the stability of the semiconductor substrate 110 structure will not be affected, which is conducive to improving the stability of the semiconductor structure 100, and further improving the stability of the electrical connection of different semiconductor structures 100 through the conductive pillar 120.

[0135] In some examples, such as Fig.10 As shown, step S200: forming a first groove 101 and a second groove 102 located at at least one side of the first groove 101 on the semiconductor substrate 110, including S210.

[0136] S210 : forming a plurality of second grooves 102 at intervals along a direction surrounding the first groove 101 .

[0137] The distance between every two adjacent second grooves 102 in the plurality of second grooves 102 is equal; and / or the distance between at least two second grooves 102 and the same first groove 101 is equal.

[0138] For example, along direction X or direction Y, every two adjacent second grooves 102 ( Figure 5 For example, the first groove 101 ( Figure 5The cross-sectional shape of the conductive pillar 120 in the semiconductor substrate 110 along the direction perpendicular to the thickness of the semiconductor substrate 110 is a circle (center point Q2), and the multiple second grooves 102 arranged around the same first groove 101 surround a rectangle (center point Q1), and the center point Q2 of the circle overlaps the center point Q1 of the rectangle. In this case, the spacings between the multiple second grooves 102 around the same first groove 101 and the first groove 101 can be equal or unequal.

[0139] Alternatively, the intervals between the plurality of second grooves 102 around the same first groove 101 and the first groove 101 are equal.

[0140] It should be noted that the spacing between the first groove 101 and the second groove 102 can be the spacing between the central axis of the first groove 101 (extending along the thickness direction of the semiconductor substrate 110) and the central axis of the second groove 102, or the spacing between one side of the first groove 101 and one side of the second groove 102 along a certain direction. This application does not impose specific restrictions on this. In the same scenario, the condition parameters for comparing the spacing between multiple second grooves 102 and the first groove 101 are consistent. For example, in the subsequent examples, the spacing between the central axis of the first groove 101 and the central axis of the second groove 102 is used as an example to illustrate the spacing relationship between the two.

[0141] For example, the cross-sectional shape of the first groove 101 along the direction perpendicular to the thickness of the semiconductor substrate 110 is circular, and the plurality of second grooves 102 arranged around the same first groove 101 enclose a circle, and the center points of the two circles overlap. In this case, the spacing between two adjacent second grooves 102 can be equal or unequal.

[0142] Alternatively, the intervals between the plurality of second grooves 102 around the same first groove 101 are equal to the first groove 101 , and the intervals between every two adjacent second grooves 102 are equal.

[0143] For example, the cross-sectional shape of the first groove 101 along the direction perpendicular to the thickness of the semiconductor substrate 110 is circular, and the plurality of second grooves 102 arranged around the same first groove 101 enclose a circle, and the center points of the two circles overlap. Furthermore, the intervals between two adjacent second grooves 102 are equal.

[0144] The arrangement of the first grooves 101 and the second grooves 102 provided in the above three examples can be selected according to the size of the entire semiconductor structure 100 and the density distribution of the plurality of first grooves 101 , which is beneficial to improving the structural stability of the conductive pillar 120 .

[0145] In some examples, step S200: forming a first groove 101 and a second groove 102 located on at least one side of the first groove 101 on a semiconductor substrate 110, including: forming at least one column of second grooves 102 between two adjacent first grooves 101 along the arrangement direction of the plurality of first grooves 101, and the arrangement direction of a column of second grooves 102 intersects with the arrangement direction of the two adjacent first grooves 101.

[0146] For example, the plurality of first grooves 101 ( Figure 6 The conductive pillars 120 in the embodiment are arranged along the direction X and the direction Y, and two rows of second grooves 102 ( Figure 6 The stress relief structure 130 in the embodiment of the present invention is provided. Between the plurality of first grooves 101 arranged along the direction X, two rows of second grooves 102 arranged along the direction Y are provided. Between the plurality of first grooves 101 arranged along the direction Y, two rows of second grooves 102 arranged along the direction X are provided.

[0147] In this way, a plurality of second grooves 102 are arranged around each first groove 101 to reduce the stress effect on the periphery of each first groove 101 after the conductive column 120 is formed in each first groove 101 from multiple directions. Furthermore, considering that the stress generated on the periphery after the conductive column 120 is formed in the first groove 101 is relatively large, especially the stress between adjacent first grooves 101 (after the conductive column 120 is formed) is larger and will affect each other, two rows of second grooves 102 are arranged between two adjacent first grooves 101, which can further reduce the mutual influence of the stress on the periphery after the conductive column 120 is formed in the adjacent first grooves 101, and more significantly improve the stability of the semiconductor structure 100.

[0148] In some examples, such as Fig.11 As shown, step S200: forming a first groove 101 and a second groove 102 located at at least one side of the first groove 101 on a semiconductor substrate 110, including S211 and S212.

[0149] S211 : forming a portion of the second groove 102 in a region spaced apart from the first groove 101 by a first distance D1 .

[0150] S212 : forming a portion of the second groove 102 in a region spaced apart from the first groove 101 by a second distance D2 ; the first distance D1 is smaller than the second distance D2 .

[0151] The depth of the second groove 102 spaced apart from the first groove 101 by the first distance D1 is greater than or equal to the depth of the second groove 102 spaced apart from the first groove 101 by the second distance D2.

[0152] And / or, the size of the opening of the second groove 102 spaced apart from the first groove 101 by a first spacing D1 is greater than or equal to the size of the opening of the second groove 102 spaced apart from the first groove 101 by a second spacing D2; the maximum size of the opening of the second groove 102 is 1 / 12 to 1 / 8 of the size of the opening of the first groove 101.

[0153] For example, the second grooves 102 with different opening sizes can be formed based on the patterns of the masks for making the first grooves 101 and the second grooves 102. For example, based on the determined distribution positions of the first grooves 101, the mask pattern of the second groove 102 spaced apart from the first grooves 101 by a first spacing D1 is set as the first mask pattern, and the mask pattern of the second groove 102 spaced apart from the first grooves 101 by a second spacing D2 is set as the second mask pattern, and the transmittance or opening size of the first mask pattern is greater than the transmittance or opening size of the second mask pattern.

[0154] The depth of the second groove 102 formed in this way, which is spaced apart from the first groove 101 by the first spacing D1, is greater than or equal to the depth of the second groove 102 which is spaced apart from the first groove 101 by the second spacing D2; and / or the size of the opening of the second groove 102 which is spaced apart from the first groove 101 by the first spacing D1 is greater than or equal to the size of the opening of the second groove 102 which is spaced apart from the first groove 101 by the second spacing D2.

[0155] Among them, considering that in the subsequent process step of forming the dielectric layer 132, the material of the dielectric layer 132 will be deposited in the second groove 102 and on the inner wall of the first groove 101 in another process, the size relationship between the opening size of the second groove 102 and the opening size of the first groove 101 can be set, so that the material of the dielectric layer 132 can be deposited on the inner wall of the first groove 101 to form a barrier layer, and meet the conditions of not completely filling the second groove 102 and covering the opening of the second groove 102 (that is, forming a stress relief structure 130 with a cavity 131). For example, the maximum size of the opening of the second groove 102 is set to 1 / 12 to 1 / 8 of the size of the opening of the first groove 101. In this way, under the parameter condition based on the maximum size of the opening of the second groove 102, a stress relief structure 130 with a cavity 131 is formed in the second groove 102. For the second groove 102 with an opening of other sizes (smaller than the maximum size), the material of the dielectric layer 132 will at least cover the opening of the second groove 102, and can also satisfy the formation of the stress relief structure 130 with a cavity 131, thereby achieving the effect of eliminating stress.

[0156] For example, the maximum size of the opening of the second groove 102 may be 1 / 12, 1 / 10, or 1 / 8 of the size of the opening of the first groove 101. The opening of the first groove 101 may be circular with a diameter of 5 microns, and the opening of the second groove 102 may be circular with a maximum diameter of 0.5 microns.

[0157] In some examples, the opening shape of the second groove 102 may include at least one of a circle, a rectangle, and an arc. The opening shapes of the plurality of second grooves 102 surrounding the same first groove 101 may be different.

[0158] For example, in a direction parallel and / or perpendicular to the arrangement of the plurality of first grooves 101, a plurality of second grooves 102 with rectangular (or arc-shaped) opening shapes are arranged on one side of the first groove 101, and a plurality of independent second grooves 102 with circular opening shapes (perpendicular to the plane of direction Z) are arranged in other directions.

[0159] For example, continue to see Figure 7 , a second groove 102 with a rectangular opening shape is respectively provided on one side of the first groove 101 along the direction X and the direction Y, and a second groove 102 with a rectangular opening shape is provided on the opposite sides of each first groove 101 along the direction X and the direction Y. That is, there are four second grooves 102 with rectangular opening shapes around each first groove 101, and two adjacent first grooves 101 share a second groove 102 with a rectangular opening shape.

[0160] In this way, based on the larger size of the second groove 102 with a rectangular opening shape (the volume of the cavity 131 in the stress relief structure 130 formed subsequently is larger), the effect of reducing stress influence is greater than the stress relief structure 130 in the second groove 102 with a circular opening shape. Figure 6 The location and arrangement of the stress relief structure 130 shown can significantly reduce the stress around the plurality of conductive pillars 120 , thereby improving the structural stability of the conductive pillars 120 and the structural stability of the semiconductor structure 100 .

[0161] The beneficial effects of the method for manufacturing the semiconductor structure 100 provided in the embodiment of the present application are the same as the beneficial effects of the semiconductor structure provided in any of the above examples, and will not be described in detail here. In addition, in the method for manufacturing the semiconductor structure 100, the material forming the stress relief structure is the same as the material of a dielectric layer in the process of forming the conductive pillar, and can be manufactured and formed by a synchronous process, with simple process steps and no additional process cost.

[0162] On the other hand, Fig.13As shown, some embodiments of the present application provide a semiconductor device 200 . The semiconductor device 200 includes at least two semiconductor structures 100 provided in any of the above examples, and the at least two semiconductor structures 100 are coupled via a conductive pillar 120 .

[0163] For example, at least two semiconductor structures 100 may be the same or different. For example, the coupled at least two semiconductor structures 100 may include at least one of wafer to wafer (W2W) bonding, chip to wafer (C2W) bonding, die to wafer (C2C) bonding, and chip to chip (C2C) bonding. Different bonding objects can select conductive pillars 120 (and corresponding stress relief structures 130 with appropriate sizes and distribution positions) according to actual needs to form a semiconductor device 200 with a stable integrated structure and stable electrical connection performance.

[0164] Before coupling at least two semiconductor structures 100, a chemical mechanical polishing process can be used to polish the surface of the semiconductor structure 100 to improve the surface flatness of the semiconductor structure 100 (and the conductive pillar 120) so as to achieve stability and tightness of the electrical connection through the surfaces where the conductive pillars 120 on the two semiconductor structures 100 contact each other.

[0165] It should be noted that the embodiment of the method for manufacturing a semiconductor structure provided in the present application and the embodiment of the semiconductor structure 100 belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the semiconductor structure 100 provided in the embodiment of the present application can already solve the technical problem to be solved by the present application; therefore, the semiconductor structure 100 provided in the embodiment of the present application may not be limited by the method for manufacturing a semiconductor structure provided in the embodiment of the present application.

[0166] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor structure, characterized in that: include: Semiconductor substrates; A conductive column is disposed in the semiconductor substrate; A stress relief structure is arranged on at least one side of the conductive column along a direction perpendicular to the thickness of the semiconductor substrate; the stress relief structure includes a cavity.

2. The semiconductor structure according to claim 1, characterized in that: The number of the stress relief structures includes a plurality; the plurality of stress relief structures are arranged at intervals along a direction surrounding the conductive pillar.

3. The semiconductor structure according to claim 1, characterized in that: The number of the stress relief structures includes a plurality; The spacing between each two adjacent stress relief structures in the plurality of stress relief structures is equal; and / or, The distances between at least two of the stress relief structures and the same conductive pillar are equal.

4. The semiconductor structure according to claim 1, characterized in that: The spacing between different stress relief structures and the same conductive column includes a first spacing and a second spacing; the first spacing is smaller than the second spacing; The volume of the cavity of the stress relief structure spaced apart from the conductive pillar by the first interval is greater than or equal to the volume of the cavity of the stress relief structure spaced apart from the conductive pillar by the second interval.

5. The semiconductor structure according to claim 4, characterized in that: Along the thickness direction of the semiconductor substrate, the size of the stress relief structure spaced apart from the conductive pillar by the first spacing is greater than or equal to the size of the stress relief structure spaced apart from the conductive pillar by the second spacing; A maximum dimension of the stress relief structure along a thickness direction of the semiconductor substrate is smaller than a thickness of the semiconductor substrate.

6. The semiconductor structure according to claim 4, characterized in that: Along a thickness direction perpendicular to the semiconductor substrate, a size of a cross-sectional figure of the stress relief structure spaced apart from the conductive pillar by the first spacing is greater than or equal to a size of a cross-sectional figure of the stress relief structure spaced apart from the conductive pillar by the second spacing; Furthermore, the maximum size of the cross-sectional figure of the stress relief structure along the direction perpendicular to the thickness of the semiconductor substrate is 1 / 12 to 1 / 8 of the size of the cross-sectional figure of the conductive column along the direction perpendicular to the thickness of the semiconductor substrate.

7. The semiconductor structure according to claim 1, characterized in that: Along the arrangement direction of the plurality of conductive pillars, at least one column of stress relief structures is disposed between two adjacent conductive pillars, and the arrangement direction of the column of stress relief structures intersects with the arrangement direction of the two adjacent conductive pillars.

8. The semiconductor structure according to claim 1, characterized in that: The cross-sectional shape of the stress relief structure along the direction perpendicular to the thickness of the semiconductor substrate includes at least one of a circle, a rectangle and an arc; The multiple stress relief structures surrounding the same conductive pillar may have different cross-sectional shapes along a direction perpendicular to the thickness of the semiconductor substrate.

9. The semiconductor structure according to claim 1, characterized in that: The stress relief structure includes a dielectric layer and the cavity surrounded by the dielectric layer; The thickness of the dielectric layer is greater than the dimension of the cross-sectional shape of the stress relief structure along the direction perpendicular to the thickness of the semiconductor substrate, and the difference between the two is greater than or equal to 1 / 5 of the minimum dimension of the cross-sectional shape of the stress relief structure along the direction perpendicular to the thickness of the semiconductor substrate.

10. A method for manufacturing a semiconductor structure, characterized in that: include: providing a semiconductor substrate; forming a first groove and a second groove located at at least one side of the first groove on the semiconductor substrate; The size of the opening of the second groove is smaller than the size of the opening of the first groove; A dielectric layer is formed on the semiconductor substrate; a material portion of the dielectric layer is filled in the second groove and covers the opening of the second groove, so that a stress relief structure with a cavity is formed in the second groove.

11. The manufacturing method according to claim 10, characterized in that: The step of forming a dielectric layer on the semiconductor substrate comprises: A dielectric layer is formed by a deposition process, wherein part of the material of the dielectric layer is located on the sidewall of the first groove to form a barrier layer; The thickness of the dielectric layer is greater than the size of the opening of the second groove, and the difference between the thickness of the dielectric layer and the opening of the second groove is greater than or equal to 1 / 5 of the minimum size of the opening of the second groove.

12. The manufacturing method according to claim 10, characterized in that: The step of forming a first groove and a second groove located at at least one side of the first groove on the semiconductor substrate comprises: A plurality of the second grooves are formed at intervals along a direction surrounding the first groove; The distance between each two adjacent second grooves in the plurality of second grooves is equal; and / or the distance between at least two of the second grooves and the same first groove is equal.

13. The manufacturing method according to claim 10, characterized in that: The step of forming a first groove and a second groove located at at least one side of the first groove on the semiconductor substrate comprises: forming a portion of the second groove in a region spaced apart from the first groove by a first distance; Part of the second groove is formed in a region spaced apart from the first groove by a second spacing; the first spacing is smaller than the second spacing; wherein the depth of the second groove spaced apart from the first groove by the first interval is greater than or equal to the depth of the second groove spaced apart from the first groove by the second interval; and / or, The size of the opening of the second groove spaced from the first groove by the first spacing is greater than or equal to the size of the opening of the second groove spaced from the first groove by the second spacing; the maximum size of the opening of the second groove is 1 / 12 to 1 / 8 of the size of the opening of the first groove.

14. The manufacturing method according to claim 10, characterized in that: The step of forming a first groove and a second groove located at at least one side of the first groove on the semiconductor substrate comprises: Along the arrangement direction of the plurality of first grooves, at least one column of the second grooves is formed between two adjacent first grooves, and the arrangement direction of the column of the second grooves intersects with the arrangement direction of the two adjacent first grooves.

15. The manufacturing method according to claim 10, characterized in that: After forming the dielectric layer on the semiconductor substrate, the manufacturing method further includes: A conductive material is formed in the first groove to form a conductive column.

16. A semiconductor device, characterized in that: The semiconductor structure comprises at least two semiconductor structures according to any one of claims 1 to 9, and at least two of the semiconductor structures are coupled through the conductive pillar.

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