Safe and efficient Ascon lightweight cryptographic algorithm hardware implementation system

Abstract

The invention discloses a safe and efficient Ascon lightweight cryptographic algorithm hardware implementation system, which is characterized in that in a core module of the system, a finite state machine module is used for redefining an FSM of seven states required for implementing an authentication encryption mode and a hash function mode as an FSM comprising four states in a mode of combining certain states by using input multiplexing; the number of each state related input is changed from 7 to 3, an ROM-based finite-state machine module is designed according to the redefined FSM, transfer of four states is achieved according to the ROM-based finite-state machine module, and corresponding operation is output; and the round operation XOR module is used for designing a corresponding round operation module introduced with the DOM technology according to the side channel protection level set by the user, and completing corresponding XOR operation and round operation on the state data according to the received operation and the current state of the system. The method supports an authentication encryption mode, a hash function mode and any level of side channel security defense.

Description

Technical Field

[0001] The invention belongs to the technical field of cryptography, and in particular relates to a safe and efficient hardware implementation system of the Ascon lightweight cryptographic algorithm. Background Art

[0002] Embedded devices, with their efficient customization and real-time performance, have become the core control and monitoring components of the Internet of Things and critical infrastructure. To ensure the security and stability of these facilities, password protection is indispensable to prevent unauthorized access and tampering. However, most embedded devices use extremely low-power microcontrollers, which can only use a small part of their computing power to ensure system security. Traditional encryption algorithms are not suitable for resource-constrained embedded devices due to their high resource consumption. For this reason, lightweight cryptographic algorithms designed for low power and low resource consumption have emerged, which perfectly meet the needs of embedded devices.

[0003] Among the leading lightweight algorithms, the Ascon cryptographic suite is considered to have extremely high security and robustness in practice, while having a very small area footprint in hardware. The suite integrates authenticated encryption and hash functions with associated data, including authenticated encryption modes (Ascon-128, Ascon-128a) and hash function modes (Ascon-hash, Ascon-hasha). Ascon uses Sponge mode and uses SPN (Substitution-Permutation Network) round transformations to dynamically update 320-bit state data, ensuring that the algorithm operates efficiently in various environments, especially for resource-constrained devices. At the same time, more and more devices are running in environments that may be subject to physical attacks, and the hardware implementation of the Ascon cryptographic algorithm poses security risks. In the underlying implementation of the Ascon cryptographic algorithm, the data flip rounds of the CMOS logic circuit directly affect the power consumption. By connecting a resistor in parallel to the power line, the power consumption changes under different plaintext inputs can be measured, thereby inferring sensitive information such as encryption keys. In recent years, some solutions for implementing the Ascon algorithm based on FPGA have been proposed, striving to make breakthroughs in resource consumption, frequency, throughput, support mode and security of Ascon hardware implementation. According to the different focuses of each solution, the Ascon cryptographic scheme based on FPGA can be roughly divided into two categories: 1. Performance improvement, using pipeline, full expansion, parallel processing, serialization and other strategies to improve efficiency or reduce resource consumption. 2. Security improvement, using threshold implementation technology to defend against side channel attacks.Among the solutions focusing on performance improvement: the article "Xu D, Wang X, Hao Q, et al. A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024." proposed a transparent memory data encryption and authentication hardware protection solution based on Ascon-128. Through multi-stage pipeline design and multi-stage address tag optimization processing, low-latency and high-performance hardware implementation was completed; the article "Pallavi L, Singh P, Patnaik B, et al. High frequency architecture of lightweight authenticated cipher ASCON-128 for resource-constrained IoT devices [C] / / 2023 OITS International Conference on Information Technology (OCIT). IEEE, 2023: 405-410." focuses more on frequency improvement. By dividing the 320-bit internal sponge state S of Ascon-128 into two parts for parallel processing, a high-frequency hardware architecture is realized.Among the solutions focusing on security improvement: the article "Diehl W, Farhamand F, Abdulgadir A, et al. Face-off between the CAESAR Lightweight Finalists: ACORN vs. Ascon [C] / / 2018 International Conference on Field-Programmable Technology (FPT). IEEE, 2018: 330-333." compared the FPGA implementation of side channel protection of ACORN and Ascon, and applied a hybrid 2 / 3 share threshold to achieve protection in the two design strategies of Ascon-large and Ascon-small to effectively defend against differential power analysis; the article "Kandi A, Baksi A, Gerlich T, et al. Hardware Implementation of ASCON [C] / / NIST LWC Workshop. 2023." used a 3-share threshold to implement side channel protection for the three stages of round operations: the round constant XOR layer, the replacement layer, and the linear layer, and designed two sharing options for the only nonlinear component S-box.

[0004] However, the hardware implementation of the Ascon cryptographic algorithm has not been fully explored. There is a lack of a solution that can implement both the authenticated encryption mode and the hash function mode and achieve a good balance between resource consumption and performance. The security of the hardware implementation is crucial, but the existing solutions cannot effectively resist high-order side channel attacks. Therefore, it is very necessary to explore and design a hardware solution that can resist high-order side channel attacks, support multiple instance modes, and run efficiently. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a safe and efficient hardware implementation system of the Ascon lightweight cryptographic algorithm. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The embodiment of the present invention provides a safe and efficient hardware implementation system of the Ascon lightweight cryptographic algorithm, the system comprising:

[0007] A preprocessing module is used to transmit the data required for system operation to the system through a defined input interface according to the instance mode type, side channel protection level and current input data type set by the user; wherein the instance mode type includes an authenticated encryption mode and a hash function mode;

[0008] The core module includes a finite state machine module and a round operation_XOR module; the finite state machine module is used to redefine the FSM of 7 states required for implementing the authentication encryption mode and the hash function mode into an FSM containing 4 states by using input multiplexing to combine certain states, and change the input related to each state from 7 to 3, and design a ROM-based finite state machine module according to the redefined FSM, and implement the transfer of 4 states and output corresponding operations according to the ROM-based finite state machine module; the round operation_XOR module is used to design a corresponding round operation module according to the side channel protection level set by the user, when the side channel protection level is greater than 0, the DOM technology is introduced in the round operation module, and the corresponding XOR operation and round operation are completed on the state data according to the operation output by the finite state machine module and the current system state;

[0009] The post-processing module is used to store the data processed by the system and send a signal to the outside world indicating that the system operation is completed.

[0010] Beneficial effects of the present invention:

[0011] The hardware implementation system of the safe and efficient Ascon lightweight cryptographic algorithm proposed in the present invention uses an optimized ROM-based finite state machine and a round operation based on DOM technology to complete the hardware implementation of the safe and efficient Ascon algorithm that integrates the authentication encryption mode and the hash function mode. Compared with the existing implementation scheme, the use scenario of the system proposed in the present invention is more flexible. By using the optimized ROM-based FSM to replace the traditional register-based FSM, fewer resources can be used to achieve higher frequency and throughput, and side channel protection can be achieved by introducing DOM technology in round operations. The present invention can be easily extended to high-order side channel protection to overcome the problem that the existing implementation scheme is not secure enough and cannot achieve a good balance between resource consumption and efficiency, so that it can be applied in more resource-constrained embedded devices, such as encryption requirements in network systems, wireless sensor networks, radio frequency identification chips, smart home products and contactless smart cards. In general, the system proposed in the present invention can not only meet the requirements of resource-constrained embedded devices in terms of function, area, throughput, etc., but also play a key role in ensuring data security, providing a more solid backing for the Ascon cryptographic algorithm in a wide range of practical application scenarios.

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural diagram of a hardware implementation system of a secure and efficient Ascon lightweight cryptographic algorithm provided by an embodiment of the present invention;

[0014] Figure 2 It is a symbolic diagram of the 7 states and related input signals involved in the traditional FSM;

[0015] Figure 3 This is a state transition diagram of the 7 states corresponding to the traditional FSM;

[0016] Figure 4 is a schematic diagram of state transition of an optimized ROM-based FSM provided in an embodiment of the present invention;

[0017] Figure 5 It is a structural diagram of a ROM-based finite state machine module provided in an embodiment of the present invention;

[0018] Figure 6 1 is a schematic diagram of the structure of a round operation-XOR module provided in an embodiment of the present invention;

[0019] Figure 7 is a structural schematic diagram of a wheel operation module designed corresponding to the embodiment of the present invention when side channel protection is not performed;

[0020] Figure 8 It is a structural diagram of an AND gate based on DOM provided by an embodiment of the present invention;

[0021] Fig. 9 It is a structural schematic diagram of a wheel operation module designed corresponding to level 1 side channel protection provided by an embodiment of the present invention;

[0022] Fig.10 It is a schematic diagram of the overall operation flow of the Ascon cryptographic algorithm provided by an embodiment of the present invention;

[0023] Fig.11 It is a schematic diagram of the implementation of the authentication encryption mode of the Ascon cipher provided in an embodiment of the present invention;

[0024] Fig.12 It is a schematic diagram of the implementation of the hash function mode of the Ascon cryptographic algorithm provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0026] See also Figure 1 The embodiment of the present invention provides a safe and efficient hardware implementation system of the Ascon lightweight cryptographic algorithm, the system comprising:

[0027] A preprocessing module is used to transmit the data required for system operation to the system through a defined input interface according to the instance mode type, side channel protection level and current input data type set by the user; wherein the instance mode type includes an authenticated encryption mode and a hash function mode;

[0028] The core module includes a finite state machine module and a round operation_XOR module; the finite state machine module is used to redefine the FSM (Finite State Machine) of 7 states required for implementing the authentication encryption mode and the hash function mode into an FSM containing 4 states by combining certain states using input multiplexing, and change the input related to each state from 7 to 3, and design a ROM-based finite state machine module according to the redefined FSM, and implement the transfer of 4 states and output corresponding operations according to the ROM-based finite state machine module; the round operation_XOR module is used to design a corresponding round operation module according to the side channel protection level set by the user, when the side channel protection level is greater than 0, the DOM (Domain-Oriented Masking) technology is introduced in the round operation module, and the corresponding XOR operation and round operation are performed on the state data according to the operation output by the finite state machine module and the current system state;

[0029] The post-processing module is used to store the data processed by the system and send a signal to the outside world indicating that the system operation is completed.

[0030] It can be seen that the overall framework module of the hardware implementation system proposed in the present invention consists of three modules: a preprocessing module, a core module, and a post-processing module. Among them, the preprocessing module and the post-processing module are equipped with a first-in-first-out FIFO and a cascade register to ensure seamless storage and efficient processing of input and output data. In addition, the design of the external data interface with adjustable size enables it to flexibly adapt to various communication interface standards, such as UART, SPI, I2C interface, etc. The core module, as the main body of the design, is responsible for executing the core round operation p and system behavior control. The core module includes a finite state machine module and a round operation_XOR module. The finite state machine module is responsible for calculating and outputting the next state and necessary information according to the current input and state, while the round operation_XOR module performs the corresponding XOR operation and round operation p according to the output of the finite state machine. In the finite state machine module, an optimized ROM-based FSM is used instead of the traditional register-based FSM, thereby reducing resource consumption while increasing frequency and throughput; the introduction of DOM technology in the round operation XOR module can achieve any level of side channel protection.

[0031] Next, Figure 1 The framework shown is introduced in detail.

[0032] like Figure 1As shown: For the pre-processing module, 5 input interfaces are defined, which are respectively recorded as Mode, SHARES, I_Valid, I_Data, and Start, and 9 output interfaces are respectively recorded as StartEnc, Mode, Key, Nonce, BlockDin, PHCounter, AMCounter, Random, and RoundDone. For the core module, 9 input interfaces are defined, which correspond one-to-one to the output interfaces of the pre-processing module, and 5 output interfaces are respectively recorded as CHReady, TagReady, Done, BlockDout, and Tag. For the post-processing module, 5 input interfaces are defined, which correspond one-to-one to the output interfaces of the core module, and 4 output interfaces are respectively defined as O_CHReady, O_TagReady, O_Done, and O_Data. More specifically:

[0033] Mode defines the instance mode types that the system can support, including authentication encryption mode and hash function mode. The authentication encryption mode includes Ascon-128 and Ascon-128a, and the hash function mode includes Ascon-hash and Ascon-hasha. For different instance modes, the data processing path and core processing logic are basically the same; SHARES defines the side channel protection level. When the side channel protection level is 0, the corresponding input value of SHARES is 1, indicating that there is no protection measure. At this time, the round operation_XOR module is the initial implementation method of the design. When the side channel protection level is 1, the corresponding input value of SHARES is 2. When the side channel defense level is d1 (d1>1), the corresponding input value of SHARES is d1+1; Start defines the system start signal, which triggers the preprocessing module to start working; I_Valid defines the input data type, namely the one-time random number Nonce, key, and association Data / message, plaintext, ciphertext and random number Random; I_Data defines the interface size of the system receiving input data, O_Data defines the interface size of the system output data, these sizes can be adjusted according to the specific requirements of the external interface; Key defines the system's 128-bit key; Nonce defines the system's 128-bit random number; BlockDin defines the f-bit associated data / plaintext data (authentication encryption mode) or information (hash function mode) transmitted to the core module; PHCounter defines the number of plaintext data blocks / hash data blocks to be processed; AMCounter defines the number of associated data blocks / information data blocks to be processed; Random defines the random number used for side channel protection. The introduction of Random is to increase the uncertainty of calculation in side channel protection, and its size varies according to the protection level and strategy; RoundDone defines completion That is, a1 round operation p or b1 round operation p is completed, and a round operation completion signal is sent to the preprocessing module. This signal prompts the preprocessing module to transfer the next data block BlockDin to the core module until all data blocks are processed; CHReady defines that a ciphertext data / hash data block has been successfully obtained, and the data block can be transmitted to the post-processing module for storage; TagReady defines that the tag Tag is ready; Done defines that the system operation is completed; BlockDout defines the r-bit ciphertext / hash value transmitted to the post-processing module; Tag defines a 128-bit tag; O_CHReady informs the outside world that the ciphertext / hash value is ready; O_TagReady informs the outside world that the tag is ready; O_Done informs that the entire system is processed.

[0034] Furthermore, if Figure 2 and Figure 3 As shown in the figure, when the traditional FSM is used to implement the authentication encryption mode and the hash function mode at the same time, 7 states are involved, including the idle state s0, the initialization state s1, the associated data state s2, the plaintext state s3, the finalization state s4, the information absorption state s5 and the squeeze tag state s6, and the 7 related input signals involved in the traditional FSM are the start encryption signal a, the round operation completion signal b, the encryption mode signal c, the judgment signal d of whether the associated data exists, the judgment signal e of whether the processed associated data / information is the last data block, the judgment signal f of whether the processed plaintext data block / hash data block is the last data block, and the system completion signal g. Among them, s0 corresponds to the system idle state, that is, waiting for external signal triggering; s1 to s4 correspond to the four stages of initialization, associated data, plaintext and finalization of the authentication encryption mode respectively; s1, s5 and s6 correspond to the three stages contained in the hash function mode: initialization, information absorption and squeeze tag. In implementation, the initial a1 round operation of squeezing the tag is regarded as the last step of absorbing information and belongs to state s5.

[0035] In order to reduce resource consumption and improve efficiency, the inventors Figure 3An analysis of the traditional FSM shown in the figure reveals that: in the traditional FSM, the relevant inputs for a state to jump to the next state do not involve all inputs, and there are always some inputs that do not need to be concerned about. For example, in the idle state s0, the only thing related to its next state is the start encryption signal a, that is, no matter what the signals b~g are, as long as the start encryption signal a is 1, the system state jumps from the idle state s0 to the initialization state s1. For another example, in the initialization state s1, the signals related to its next state are b, c, and d. When a1 completes the round operation p (b=1): if the current selection mode is the authentication encryption mode (c=1) and there is no associated data (d=0), the next state is the plaintext state s3; if the current selection mode is the authentication encryption mode (c=1) but there is associated data (d=1), then enter the associated data state s2; if the current selection mode is the hash function mode (c=0), then directly enter the information absorption state s5. If the current If not completed (b=0), the initialization state s1 is maintained.

[0036] Therefore, the embodiment of the present invention proposes to use input multiplexing technology, which uses irrelevant inputs to combine certain states, and uses a multiplexer to select the corresponding input for each new state. Since the maximum number of relevant inputs for the next jump state of a specific state (s0~s6) is 3, that is, the relevant inputs of the initialization state s1 are b, c, and d, and the number of relevant inputs of other states is less than 3. The FSM redefined according to the input multiplexing technology is as follows Figure 4 As shown, the four states in the redefined FSM include the first state s 04 , second state s1, third state s 25 and the fourth state s 36 ; First state s 04 It is a combination of the idle state and the finalization state. The second state s1 is the initialization state, and the third state s 25 The fourth state s is the combination of the associated data state and the absorbed information state. 36 It is composed of the plain text state and the squeezed tag state. In the redefined FSM, the relevant input of each state jumping to the next state is updated to 3 bits in1, in2, in3. Among them, Figure 4 ps represents the current state, pis represents the relevant input of the current state, in represents the specific value of the relevant input of the current state, ns represents the next state, nis represents the relevant input of the next state, and out represents the operation corresponding to the output of the current state.

[0037] To implement the redefined FSM, the ROM-based finite state machine module designed in the embodiment of the present invention is as follows: Figure 5 As shown, it includes a 2-way selector MUX1, a 4-way selector MUX2, a 3-way selector MUX3, and a ROM memory; wherein,

[0038] A ROM memory, used for pre-storing in each storage unit a first selection signal, a second selection signal, a third selection signal, an operation corresponding to an output of a current state, and a next jump state of the current state;

[0039] The 2-way selector MUX1 is used to select and output the first signal in1 from the encryption start signal and the round operation completion signal according to the first selection signal; it can be seen that the related input signal of the first signal in1 is a / b.

[0040] The 4-way selector MUX2 is used to select and output the second signal in2 from the encryption mode signal, the judgment signal of whether the processed associated data / information is the last data block, the judgment signal of whether the processed plaintext data block / hash data block is the last data block, and the system completion signal according to the second selection signal; it can be seen that the related input signals of the second signal in2 are c / e / f / g.

[0041] The 3-way selector MUX3 is used to select and output the third signal in3 from 0, 1 and the judgment signal of whether the associated data exists according to the third selection signal; it can be seen that the related input signals of the third signal in3 are 0 / 1 / d.

[0042] The ROM memory is also used to retrieve and output the corresponding operation from the corresponding storage unit of the ROM memory according to the first signal in1, the second signal in2, the third signal in3 and the current state, and update the current state, the first selection signal, the second selection signal and the third selection signal at the same time. It can be seen that the content of each storage unit in the ROM memory is: the first selection signal sel1, the second selection signal sel2 and the third selection signal sel3 (5 bits) of the multiplexer, the output operation signal out (3 bits) and the next jump state ns (2 bits), and its size is 2 (3+2) ×(5+3+2)=320.

[0043] The operation process of the overall finite state machine module is as follows:

[0044] 1) At the start, the default initial value of each signal is: ps = s 04 , in3=0. The system is in the first state s 04 In idle state.

[0045] 2) The encryption start signal in1(a) changes to a high level, the system enters the initialization state s1, and selects the next state according to the round operation completion signal in1(b), the encryption mode signal in2(c) and the judgment signal in3(d) of whether the associated data exists. When b=0, the system maintains the initialization state s1; when b=1, if c=1, d=1, the system enters the third state s 25In the state of the associated data (in3=0); c=1, d=0, the system enters the fourth state s 36 Plain text state (in3 = 0); c = 0 enters the third state s 25 Absorbing information state (in3=1).

[0046] 3) If it is the third state s 25 , that is, the associated data state / absorbed information state. When the signal in1(b)=1, if the signal in2(e)=1, the system enters the fourth state s 36 ; If the signal e=0, it means that there are still related data blocks / information blocks that have not been processed, and the system remains in the original state to process the next data block until all data blocks are processed; when the signal b=0, it means that the b1 round operation has not been processed and remains in the original state.

[0047] 4) If it is the fourth state s 36 , that is, plaintext state / squeezed tag state. When the last plaintext data block (in2(f)=1) is processed or the 256-bit hash data (b=1, f=1) is successfully obtained, the plaintext phase of the system authentication encryption mode is completed and enters the first state s 04 The finalization state (in3 = 1), or the hash function mode is completed and returns to the first state s 04 Idle state (in3=0).

[0048] 5) The system is in the first state s 04 After completing 12 rounds of operations in the finalization state, the system completes the signal g = 1, and the authentication encryption mode is completed and returns to the first state s 04 In idle state.

[0049] During operation of the embodiment of the present invention, the ROM_finite state machine module reads the next jump state and the selection signal of the state-related input from the ROM according to the value of the input signal and the current state, and outputs the operation out to be performed at this time to the round operation_XOR module.

[0050] Furthermore, in order to resist any level of side channel attacks, the embodiments of the present invention are designed as follows: Figure 6 The round operation XOR module shown in the figure includes an 8-way selector MUX4, a 4-way selector MUX5 and a round operation module; wherein,

[0051] The 8-way selector MUX4 and the 4-way selector MUX5 are responsible for executing the XOR operation and state data update required by the Ascon lightweight cryptographic algorithm at each stage, and outputting the updated data as the current round input data; the round operation module is used to perform specific round operations on the current round input data. The operation process of the round operation_XOR module is as follows:

[0052] When the system is in idle state, out = 0, state = s 04 , in3=0, at this time, the 320-bit state data S processed by Ascon, the processed associated data / information block length AM, and the plaintext / hash block length PH are all 0. When the start encryption signal is triggered, the value of the fourth selection signal sel4 is 0, that is, the round operation input data I_P=(IV, Key, Nonce} (if it is the hash function mode at this time, the Key and Nonce values ​​are set to 0). Subsequently, after completing the a1 / b1 round operation, the selection signals of MUX4 and MUX5 are updated according to the latest out, state and in3, and the state data S, AM and PH are processed, and the processed state data is sent to the Permutation module for round operation. For example, it is currently in the authentication encryption mode, its initialization phase is over and there is no associated data, then the out value output by the ROM finite state machine module should be 7, that is, the XOR operation of the state data S at the end of the initialization phase with the key and the last bit flip operation at the end of the associated data phase need to be completed at this time, At the same time, if there is only one plaintext data block at present, the fourth selection signal sel4 should be 2, and the input data of the round operation needs to XOR the updated state data S with the plaintext and the key at the same time, that is, If the length of the plaintext data block is greater than 1, the value of the fourth selection signal sel4 is 1. Where S = S r ||S c =x0||x1||x2||x3||x4.

[0053] In the round operation module Permutation, the round constant XOR layer p C , replace layer p S and the linear layer p L The specific implementation formula is as follows:

[0054]

[0055] In the wheel operation module, slightly different wheel operation modules are designed for different levels of side channel protection.

[0056] Specifically:

[0057] In the embodiment of the present invention, when the side channel protection level is level 0, it indicates that the side channel protection is not performed; the round operation module includes a round constant XOR layer p C , replace layer p S and the linear layer p L ;in,

[0058] Round constant XOR layer p C, using XOR gates, bit splicing operators and inverters, which generate the corresponding round constant RC according to the current round operation counter; replacing layer p S , using combinational logic circuits, including XOR gates, AND gates, and inverters; linear layer p L , implemented using XOR gates and bit-splicing operators;

[0059] The current round input data passes through the round constant XOR layer p in turn C , replace layer p S and the linear layer p L Finally, the data after rounds of operations are output.

[0060] In the embodiment of the present invention, when the side channel protection level is level 1, the round operation module introduces the DOM technology, and the round input data is divided into two shares before entering the round operation, and the two shares belong to independent domains respectively; the round operation module includes a round constant XOR layer p C , replace layer p S and the linear layer p L , for a round constant XOR layer p containing only nonlinear operations C and the linear layer p L , respectively, in two independent domains, for the replacement layer p including linear and nonlinear operations S , linear operations need to be performed in two independent domains respectively, and non-linear operations use DOM-based AND gates to achieve cross-domain re-sharing; among them,

[0061] Round constant XOR layer p C , using XOR gates, bit splicing operators and inverters, which generate the corresponding round constant RC according to the current round operation counter; the linear layer p L , implemented using XOR gates and bit-splicing operators; replacing layer p S , where the linear operation is implemented using XOR gates and inverters, and the nonlinear operation is implemented using DOM-based AND gates ( Figure 8 The AND gate based on DOM is implemented using a multiplier, an XOR gate, and a register.

[0062] The two shares of corresponding input data are sequentially passed through the round constant XOR layer p C , replace layer p S and the linear layer p L After that, the output data corresponding to the two shares are XORed to obtain the output data of the current round.

[0063] In the embodiment of the present invention, when the side channel protection level is d1 (d1>1), the round operation module introduces the DOM technology, and the round operation input data is divided into d1+1 shares before entering the round operation, and these d1+1 shares belong to independent domains respectively; the round operation module includes a round constant XOR layer p C , replace layer p S and the linear layer p L , for a round constant XOR layer p containing only nonlinear operations C and the linear layer p L , and executes it in d1+1 independent domains respectively. For the replacement layer p including linear and nonlinear operations S , linear operations need to be performed in d1+1 independent domains respectively, and nonlinear operations use DOM-based AND gates and introduced random numbers to achieve cross-domain re-sharing; among them,

[0064] Round constant XOR layer p C , using XOR gates, bit splicing operators and inverters, which generate the corresponding round constant RC according to the current round operation counter; the linear layer p L , implemented using XOR gates and bit-splicing operators; replacing layer p S , where linear operations are implemented using XOR gates and inverters, and nonlinear operations are implemented using DOM-based AND gates, which are implemented using multipliers, XOR gates, and registers;

[0065] The data corresponding to d1+1 shares are sequentially passed through the round constant XOR layer p C , replace layer p S and the linear layer p L After that, the output data corresponding to d1+1 shares are XORed to obtain the output data of the current round.

[0066] It can be seen that for different levels of side channel protection, the round operation_XOR module framework design is the same, which is composed of 8-way selector MUX4, 4-way selector MUX5 and round operation module Permutation. MUX4 and MUX5 are mainly responsible for executing the XOR operation and status data update after the round operation of a1 / b1 in the Ascon cryptographic algorithm is completed, while the round operation module Permutation performs the specific round operation p. More specifically:

[0067] When side channel protection is not performed, the most basic framework can be used, such as Figure 7 As shown. That is, the round operation module Permutation in the round operation XOR module is composed of the round constant XOR layer p C , replace layer p S and the linear layer p LFor each layer, the embodiment of the present invention proposes to use basic components such as XOR gates, AND gates, inverters, etc. to implement it.

[0068] When side channel protection is selected, the embodiment of the present invention introduces DOM technology into the wheel operation module Permutation. Take level 1 side channel protection as an example for explanation. Figure 8 and Fig. 9 As shown. At this time, there are two shares and each variable share is associated with domain A and domain B respectively. The specific implementation steps are: 1) Select a 320-bit random number A x As a share, the other share value is 2) For p containing only linear operations c Layer and p L layer, the relevant operations in the basic implementation are performed once in both domain A and domain B; 3) For the nonlinear AND gate p S For the linear operation of the layer, the basic operation can be performed directly in each domain, but note that the reverse gate at the end of x2 only needs to be performed on one share. Cross-domain operation is required, use DOM_AND gate to complete the multiplier operation x i+1 x i+2 . And x i Statistically independent of x i+1 and x i+2 , which can be replaced by Figure 8 R0 in , so that level 1 side channel protection can be achieved when only two shares are used and no random numbers are used.

[0069] For nonlinear multiplier operation The specific process of using DOM to achieve this is as follows Figure 8 As described above, it includes three steps: calculation, re-sharing and integration.

[0070] Calculation: Perform the actual multiplication operation, that is, calculate the four multiplication terms A separately x A y , A x B y , B x A y and B x B y Among them, A x A y and B x B y To multiply terms in the same domain, the operation can be performed directly within domain A and domain B; A x B y and B x A y This is the multiplication of cross-domain items. In this case, it is only calculated without being added to any domain.

[0071] Re-sharing: Prepare to add cross-domain items to domains A and B. The calculated multiplication items are XORed with random numbers. At this time, the result is statistically independent of any multiplication item and can be added to any domain. At the same time, an additional register is used to store the re-shared multiplication items to solve the fault problem shown in the Boolean mask and the fault propagation problem. Among them, the registers in the dotted part are only required in the pipeline architecture.

[0072] Integration: Add the cross-domain term to the specific domain to obtain the multiplication term A under GF(2) q and B q , its specific form is as follows:

[0073]

[0074] Among them, FF out express Figure 8 The output of register FF in the middle. Since each domain only contains the combined items within the domain and the cross-domain re-shared items by adding random numbers, the attacker needs to combine two or more intermediate signals to obtain information related to variables x or y, so the first-level side channel protection can be achieved.

[0075] For high-order side channel protection, it is similar to the first-level side channel protection, but consumes more resources. For example, to achieve d1-level side channel protection, the linear part of the round operation needs to be executed once in d1+1 domains; and for the nonlinear part of DOM_AND, d1(d1+1) / 2 random numbers, d1+1 triggers and more XOR gates are required to implement it. The specific process is shown in the following formula.

[0076]

[0077] Further, Fig.10 The overall operation flow of the Ascon cryptographic algorithm is given, and the parameters involved in each instance mode of the ASCON cryptographic algorithm are given as shown in Table 1.

[0078] Table 1 Parameters involved in the ASCON cryptographic algorithm

[0079]

[0080] If the instance mode type is Ascon-128 / Ascon-128a, the corresponding operation process includes four stages: initialization, associated data, plaintext, and finalization. The specific parameters are shown in Table 1. The operation flow chart is as follows: Fig.10 The black and blue lines are shown in the figure. For example, Ascon processes 320 bits of state data S in each round, and S is composed of external state data S r and internal state data It consists of two parts, corresponding to the rate and capacity in the sponge structure. The more specific implementation of the Ascon lightweight cryptographic algorithm Ascon-128 / Ascon-128a is as follows Fig.11 As shown. Includes:

[0081] Preliminary preparation: pad the associated data A and plaintext data P into s and t groups. For the associated data A, if the initial length is 0, do not pad directly; otherwise, the padding bit string is {100....0}, so that the sum of the lengths of the associated data A and the padding data is an integer multiple of the group r. For the plaintext data P, directly pad the bit string so that the overall length after padding is an integer multiple of the group.

[0082] The plaintext data and associated data transmitted into the system are directly stored in the I_FIFO, which is configured using the IP core provided by vivado; the remaining random numbers, keys, random numbers, etc. are placed in the cascade registers.

[0083] Initialization phase: First, input the initialization state, which consists of IV, encryption key Key and random number Nonce, and the round operation counter counter value is 0. Then, when a1 round operation p (each time p operation is completed, the counter value increases by 1), the XOR circuit is used to perform an XOR operation on the last k bits of the state data S with the key. At this point, the initialization phase ends. Since this is the authentication encryption mode, the password enters the associated data phase. Here || is the concatenation operation of two strings.

[0084]

[0085] Related data stage: group the populated related data into groups A i Same as external status data S r The XOR operation is performed, and the data after each operation needs to be XORed with the next group after b1 round operation p to complete the corresponding processing process. After all groups are processed, the last bit of the state data S needs to be flipped using an inverter. Then, the cipher enters the plaintext stage.

[0086]

[0087] Plaintext stage: Sequentially group the filled plaintext with the external state data S r Perform an XOR operation and use the data after the operation as the input data of the round operation. After performing b1 round operations p continuously, the cipher can process the next plaintext group. r After XORing with the last plaintext block, the cipher enters the finalization phase. iSame as external status data S r The value after the XOR operation is the ciphertext C i On the contrary, if the group input here is ciphertext data, the result after XOR is plaintext data, which is the decryption operation. Ciphertext C i It will be transferred to the O_FIFO memory for storage and subsequent reading.

[0088]

[0089] Finalization phase: First, the internal state data The first k bits of data are XORed with the key Key, and the result of the operation is used as the input value of the continuous a1 round operation p for corresponding calculation. After the a1 round operation p is completed, the state data S out The last k bits of data are XORed with the key Key to get the value of the tag Tag. Refers to extracting the last k bits of bit string x.

[0090]

[0091] The specific implementation process of round operation p is as shown above. Figure 7 or Fig. 9 As shown, no further description is given here.

[0092] Furthermore, if the instance mode type is Ascon-hash / Ascon-hasha, the corresponding operation process includes three stages: initialization, absorbing information, and squeezing tags. The specific parameters are shown in Table 1. The operation flow chart is as follows: Fig.10 The black and green lines in the figure are shown in Figure 1. The more specific implementation process of the Ascon lightweight cryptographic algorithm Ascon-hash / Ascon-hasha is as follows: Fig.12 As shown. Includes:

[0093] Preliminary preparation: Same as Ascon-128 / Ascon-128a, where the information padding operation is the same as the plain text.

[0094] Initialization phase: First, 320 bits of data As the input data of the hash algorithm, after a1 rounds of operation p, since it belongs to the hash function mode at this time, the system enters the information absorption stage.

[0095]

[0096] Information absorption phase: for each information block M i , firstly compare it with the external state data S rPerform an XOR operation, then perform b1 round operation p, and then process the next information block until the last information block is processed. At this time, when the external state data S r After XORing with the last information block, the cipher enters the squeeze tag phase.

[0097]

[0098] Squeeze tag: First, perform a1 round operations on the state data, that is, the reset round operation counter counter counts to a1; then, after each r bit of data is obtained, perform continuous b1 round operations p to update the state data S until the set l=256 bit hash value is obtained.

[0099]

[0100] Similarly, the specific implementation process of round operation p is as shown above. Figure 7 or Fig. 9 As shown, no further description is given here.

[0101] In summary, the hardware implementation system of the safe and efficient Ascon lightweight cryptographic algorithm proposed in the embodiment of the present invention uses an optimized ROM-based state machine and a DOM-based round operation to complete the hardware implementation of the safe and efficient Ascon algorithm that integrates the authentication encryption mode and the hash function mode. Compared with the existing implementation scheme, the use scenario of the system proposed in the present invention is more flexible. By using the optimized ROM-based FSM to replace the traditional register-based FSM, fewer resources can be used to achieve higher frequency and throughput, and side channel protection can be achieved by introducing DOM technology in the round operation. The present invention can be easily extended to high-order side channel protection to overcome the problem that the existing implementation scheme is not secure enough and cannot achieve a good balance between resource consumption and efficiency, so that it can be applied in more resource-constrained embedded devices, such as encryption requirements in network systems, wireless sensor networks, radio frequency identification chips, smart home products and contactless smart cards. In general, the system proposed in the present invention can not only meet the requirements of resource-constrained embedded devices in terms of function, area, throughput, etc., but also play a key role in ensuring data security, providing a more solid backing for the Ascon cryptographic algorithm in a wide range of practical application scenarios.

[0102] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0103] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude multiple situations. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0104] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A secure and efficient hardware implementation system of the Ascon lightweight cryptographic algorithm, characterized in that: The system comprises: A preprocessing module is used to transmit the data required for system operation to the system through a defined input interface according to the instance mode type, side channel protection level and current input data type set by the user; wherein the instance mode type includes an authenticated encryption mode and a hash function mode; The core module includes a finite state machine module and a round operation-XOR module; the finite state machine module is used to redefine the FSM of 7 states required for implementing the authentication encryption mode and the hash function mode into an FSM containing 4 states by using input multiplexing to combine certain states, and change the input related to each state from 7 to 3, and realize the transfer of 4 states and output corresponding operations according to the redefined FSM; the round operation-XOR module is used to design the corresponding round operation module according to the side channel protection level set by the user, when the side channel protection level is greater than 0, the DOM technology is introduced in the round operation module, and the corresponding XOR operation and round operation are performed on the state data according to the operation output by the finite state machine module and the current system state; The post-processing module is used to store the data processed by the system and send a signal to the outside world indicating that the system operation is completed.

2. The hardware implementation system of the secure and efficient Ascon lightweight cryptographic algorithm according to claim 1 is characterized in that: The authentication encryption modes include Ascon-128 and Ascon-128a, and the hash function modes include Ascon-hash and Ascon-hasha.

3. The hardware implementation system of the secure and efficient Ascon lightweight cryptographic algorithm according to claim 1 is characterized in that: When using the traditional FSM to simultaneously implement the authentication encryption mode and the hash function mode, 7 states are involved, including an idle state, an initialization state, an associated data state, a plaintext state, a finalization state, an information absorption state, and a squeezed label state, and the 7 related input signals involved in the traditional FSM are respectively an encryption start signal, a round operation completion signal, an encryption mode signal, a judgment signal of whether the associated data exists, a judgment signal of whether the processed associated data / information is the last data block, a judgment signal of whether the processed plaintext data block / hash data block is the last data block, and a system completion signal; The four states in the FSM redefined according to the input multiplexing technology include the first state, the second state, the third state and the fourth state; the first state is a combination of the idle state and the termination state, the second state is the initialization state, the third state is a combination of the associated data state and the absorbed information state, and the fourth state is a combination of the plaintext state and the squeezed label state.

4. The hardware implementation system of the secure and efficient Ascon lightweight cryptographic algorithm according to claim 3 is characterized in that: The designed ROM-based finite state machine module includes a 2-way selector MUX1, a 4-way selector MUX2, a 3-way selector MUX3, and a ROM memory; among them, The ROM memory is used to pre-store in each storage unit a first selection signal, a second selection signal, a third selection signal, an operation corresponding to the output of the current state, and a next jump state of the current state; The 2-way selector MUX1 is used to select and output a first signal in1 from the encryption start signal and the round operation completion signal according to the first selection signal; The 4-way selector MUX2 is used to select and output the second signal in2 from the encryption mode signal, the judgment signal of whether the processed associated data / information is the last data block, the judgment signal of whether the processed plaintext data block / hash data block is the last data block, and the system completion signal according to the second selection signal; The 3-way selector MUX3 is used to select and output a third signal in3 from 0, 1 and the judgment signal of whether the associated data exists according to the third selection signal; The ROM memory is also used to retrieve and output corresponding operations from the corresponding storage unit of the ROM memory according to the first signal in1, the second signal in2, the third signal in3 and the current state, and simultaneously update the current state, the first selection signal, the second selection signal and the third selection signal.

5. The hardware implementation system of the secure and efficient Ascon lightweight cryptographic algorithm according to claim 1 is characterized in that: The round operation XOR module includes an 8-way selector MUX4, a 4-way selector MUX5 and a round operation module; wherein, The 8-way selector MUX4 and the 4-way selector MUX5 are responsible for executing the XOR operation and updating the state data required by the Ascon lightweight cryptographic algorithm at each stage, and outputting the updated data as the input data of the current round; The round operation module is used to perform specific round operations on the current round input data.

6. The hardware implementation system of the secure and efficient Ascon lightweight cryptographic algorithm according to claim 5 is characterized in that: When the side channel protection level is level 0, it indicates that no protection measures are added; the round operation module includes a round constant XOR layer p C , replace layer p S and the linear layer p L ;in, The round constant XOR layer p C , using an XOR gate, a bit splicing operator and an inverter, the bit splicing operator and the inverter generate the corresponding round constant according to the current round operation counter; the replacement layer p S , implemented using a combinational logic circuit, the combinational logic circuit includes an XOR gate, an AND gate and an inverter; the linear layer p L , implemented using XOR gates and bit-splicing operators; The current round input data passes through the round constant XOR layer p in turn C , replace layer p S and the linear layer p L Finally, the data after rounds of operations are output.

7. The hardware implementation system of the secure and efficient Ascon lightweight cryptographic algorithm according to claim 5 is characterized in that: When the side channel protection level is level 1, the current round input data has been divided into two shares before entering the round operation, and the two shares belong to independent domains respectively; the round operation module introduces DOM technology, and the round operation module includes a round constant XOR layer p C , replace layer p S and the linear layer p L , for a round constant XOR layer p containing only nonlinear operations C and the linear layer p L , respectively, in two independent domains, for the replacement layer p including linear and nonlinear operations S , linear operations need to be performed in two independent domains respectively, and non-linear operations use DOM-based AND gates to achieve cross-domain re-sharing; among them, The round constant XOR layer p C , using an XOR gate, a bit splicing operator and an inverter, the bit splicing operator and the inverter generate the corresponding round constant according to the current round operation counter; the linear layer p L , implemented using XOR gates and bit-splicing operators; the replacement layer p S , wherein the linear operation is implemented using an XOR gate and an inverter, and the nonlinear operation is implemented using an AND gate based on DOM, and the AND gate based on DOM is implemented using a multiplier, an XOR gate and a register; The two shares of corresponding input data are sequentially passed through the round constant XOR layer p C , replace layer p S and the linear layer p L After that, the output data corresponding to the two shares are XORed to obtain the output data of the current round.

8. The hardware implementation system of the secure and efficient Ascon lightweight cryptographic algorithm according to claim 5 is characterized in that: When the side channel protection level is d1 (d1>1), the input data of the current round operation has been divided into d1+1 shares before entering the round operation, and these d1+1 shares belong to independent domains respectively; the round operation module introduces DOM technology, and the round operation module includes a round constant XOR layer p C , replace layer p S and the linear layer p L , for a round constant XOR layer p containing only nonlinear operations C and the linear layer p L , and executes it in d1+1 independent domains respectively. For the replacement layer p including linear and nonlinear operations S , linear operations need to be performed in d1+1 independent domains respectively, and nonlinear operations use DOM-based AND gates and introduced random numbers to achieve cross-domain re-sharing; among them, The round constant XOR layer p C , using an XOR gate, a bit splicing operator and an inverter, the bit splicing operator and the inverter generate the corresponding round constant according to the current round operation counter; the linear layer p L , implemented using XOR gates and bit-splicing operators; the replacement layer p S , wherein the linear operation is implemented using an XOR gate and an inverter, and the nonlinear operation is implemented using an AND gate based on DOM, and the AND gate based on DOM is implemented using a multiplier, an XOR gate and a register; The data corresponding to d1+1 shares are sequentially passed through the round constant XOR layer p C , replace layer p S and the linear layer p L After that, the output data corresponding to d1+1 shares are XORed to obtain the output data of the current round.

9. The hardware implementation system of the secure and efficient Ascon lightweight cryptographic algorithm according to claim 1 is characterized in that: The pre-processing module and the post-processing module are both configured with a first-in-first-out queue FIFO for buffering and storing corresponding data.

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