Integrated circuit memory device and semiconductor device

Abstract

An integrated circuit memory device and a semiconductor device are provided. An integrated circuit memory device includes a substrate having a bit line thereon extending in a first horizontal direction and a channel structure extending on the bit line. The channel structure includes a horizontal portion on the bit line and a vertical channel portion extending upward from one end of the horizontal portion. A word line is provided that extends opposite the vertical channel portion and intersects the bit line to extend in a second horizontal direction that intersects the first horizontal direction. A landing pad structure is provided, and the landing pad structure is electrically connected to the vertical channel portion. The landing pad structure includes a first contact portion in contact with an upper surface of the vertical channel portion and a second contact portion protruding downward from a lower surface of the first contact portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the rights to Korean Patent Application No.

[0003] The disclosure of which is incorporated herein by reference. Technical Field

[0004] The inventive concept relates to a semiconductor device having a landing pad structure therein. Background Art

[0005] As the demand for high performance, high speed and / or multifunctionalization of semiconductor devices increases, the integration of semiconductor devices has increased. When manufacturing semiconductor devices with fine patterns corresponding to the high integration trend of semiconductor devices, it is generally necessary to realize patterns with fine width or fine spacing. Summary of the invention

[0006] An aspect of the inventive concept is to provide a semiconductor device having a landing pad structure including a first contact portion and a second contact portion contacting a channel structure.

[0007] According to one aspect of the present disclosure, a semiconductor device may include: a bit line extending in a first horizontal direction; a channel structure disposed on the bit line, wherein the channel structure includes a horizontal portion on the bit line and a vertical channel portion extending upward from one end of the horizontal portion; a word line disposed on the horizontal portion and crossing the bit line to extend in a second horizontal direction crossing the first horizontal direction; and a landing pad structure disposed on the vertical channel portion and electrically connected to the channel structure. The landing pad structure may include a first contact portion contacting an upper surface of the vertical channel portion and a second contact portion protruding downward from a lower surface of the first contact portion.

[0008] According to another aspect of the present disclosure, a semiconductor device may include: a bit line extending in a first horizontal direction; a molding structure disposed on the bit line and extending in a second horizontal direction intersecting the first horizontal direction, wherein the molding structure includes a molding layer and a liner on a side surface of the molding layer; a channel structure disposed on the bit line, wherein the channel structure includes a horizontal portion on the bit line and a vertical channel portion extending upward from one end of the horizontal portion and disposed on a side surface of the liner; a word line disposed on the horizontal portion and crossing the bit line to extend in a second horizontal direction; and a landing pad structure disposed on the vertical channel portion and electrically connected to the channel structure. The upper surface of the vertical channel portion may be disposed at a level higher than the upper surface of the liner. The landing pad structure may include a first contact portion in contact with the upper surface of the vertical channel portion, and a second contact portion in contact with the side surface of an upper region of the vertical channel portion and the upper surface of the liner.

[0009] According to another aspect of the present disclosure, a semiconductor device may include: a lower structure including a circuit element; a bit line, which is arranged on the lower structure and extends along a first horizontal direction; a molding structure, which is arranged on the bit line and extends in a second horizontal direction intersecting the first horizontal direction, wherein the molding structure includes a molding layer and a liner on a side surface of the molding layer; a channel structure, which is arranged on the bit line, wherein the channel structure includes a horizontal portion on the bit line and a vertical channel portion extending upward from one end of the horizontal portion and arranged on a side surface of the liner; a word line, which is arranged on the horizontal portion and crosses the bit line to extend in a second horizontal direction; an upper insulating structure, which is spaced apart from the molding structure in the second horizontal direction and is configured to cover the word line and the bit line; an upper capping layer, which is configured to cover the molding structure and the upper insulating structure; and a landing pad structure, which is arranged on the vertical channel portion, penetrates the upper capping layer, and is electrically connected to the channel structure; and an information storage structure, which is arranged on the landing pad structure. The landing pad structure may include a pad portion on the upper capping layer, a first contact portion contacting an upper surface of the vertical channel portion, a second contact portion contacting a side surface of the vertical channel portion and an upper surface of the liner, and a connecting portion between the pad portion and the first contact portion.

[0010] According to some example embodiments of the technical concept of the present disclosure, the landing pad structure may include a first contact portion and a second contact portion protruding downward from a lower surface of the first contact portion. Since the first contact portion and the second contact portion are in contact with the channel structure, the contact area between the landing pad structure and the channel structure may be advantageously increased, and the contact resistance may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1A is a plan view of a semiconductor device according to an example embodiment;

[0013] Figure 1B is along Figure 1A A vertical cross-sectional view of the semiconductor device shown in FIG. 1 taken along line II′;

[0014] Figure 1C is along Figure 1A A vertical cross-sectional view of the semiconductor device taken along line II-II' in FIG.

[0015] Figure 2 yes Figure 1B A partial enlarged view of the semiconductor device shown in FIG.

[0016] Figures 3 to 7 is a vertical cross-sectional view of a semiconductor device according to example embodiments;

[0017] Figure 8 is a vertical cross-sectional view of a semiconductor device according to example embodiments;

[0018] Fig. 9 is a vertical cross-sectional view of a semiconductor device according to example embodiments;

[0019] Fig.10 yes Fig. 9 A partial enlarged view of the semiconductor device shown in FIG. FIG. 11A to FIG. 21 are plan views and vertical cross-sectional views shown according to process sequence to explain a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0020] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0021] Figure 1A is a plan view of a semiconductor device according to an example embodiment; Figure 1B is along Figure 1A A vertical cross-sectional view of the semiconductor device shown in FIG. 1 taken along line II′; and Figure 1C is along Figure 1A A vertical cross-sectional view of the semiconductor device taken along line II-II' in FIG. Figures 1A to 1C , the semiconductor device 100 according to the example embodiment of the present disclosure may include a lower structure LS, a bit line 50, an upper structure US, and an information storage structure 87. The lower structure LS may include a substrate 3, a circuit element TR, a peripheral plug 20, a peripheral wiring 23, a first peripheral insulating layer 30, and a second peripheral insulating layer 32.

[0022] The substrate 3 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 3 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0023] The circuit element TR may include a word line driver, a sense amplifier, a row decoder, a column decoder, and a control circuit. The circuit element TR may include a peripheral transistor. For example, the peripheral transistor may include a gate structure 12 disposed on a peripheral active region 9a defined by a device isolation region 9b in the substrate 3 and a peripheral source / drain region 15 disposed in the peripheral active region 9a on both sides of the gate structure 12.

[0024] The gate structure 12 may include a peripheral gate electrode 12b and a peripheral gate dielectric layer 12a between the peripheral gate electrode 12b and the peripheral active region 9a. The peripheral gate electrode 12b may include at least two conductive layers, for example, a first conductive layer 12b1 and a second conductive layer 12b2 on the first conductive layer 12b1.

[0025] The peripheral plug 20 may be connected to the peripheral source / drain region 15 and may extend vertically, and the peripheral wiring 23 may be disposed on the peripheral plug 20. The peripheral wiring 23 may be electrically connected to the circuit element TR through the peripheral plug 20. The first peripheral insulating layer 30 may surround the side surfaces of the peripheral gate electrode 12b and the peripheral plug 20. The second peripheral insulating layer 32 may be disposed on the first peripheral insulating layer 30, and may surround the peripheral plug 20 and the peripheral wiring 23. The upper surface of the second peripheral insulating layer 32 may be coplanar with the upper surface of the peripheral wiring 23.

[0026] In example embodiments, the peripheral plug 20 and the peripheral wiring 23 may include a metal layer and a barrier layer configured to cover the side surface and the bottom surface of the metal layer. The barrier layer may include at least one of TiN, TaN, WN, TiSiN, TaSiN, and RuTiN, and the metal layer may include a metal material such as W or Mo. The first peripheral insulating layer 30 and the second peripheral insulating layer 32 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or a combination thereof.

[0027] The semiconductor device 100 may further include an etch stop layer 40 disposed on the lower structure LS. The etch stop layer 40 may cover the peripheral wiring 23 and the second peripheral insulating layer 32. The etch stop layer 40 may include SiBN, SiCN, SiN, or a combination thereof.

[0028] The bit line 50 may be disposed on the lower structure LS. The bit line 50 may extend in the Y direction and may be spaced apart from each other in the X direction. The semiconductor device 100 further includes a bit line plug 53 disposed under the bit line 50 and a bit line insulating layer 56 surrounding the bit line 50 and the bit line plug 53. The bit line 50 may be electrically connected to the lower structure LS through the bit line plug 53.

[0029] The bit line 50 may include a metal layer and a barrier layer configured to cover the side surface and the bottom surface of the metal layer. The barrier layer may include at least one of TiN, TaN, WN, TiSiN, TaSiN and RuTiN, and the metal layer may include a metal material such as W or Mo. The bit line plug 53 may include the same material as the peripheral plug 20 and the peripheral wiring 23. The bit line insulating layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material or a combination thereof.

[0030] The semiconductor device 100 may further include shielding patterns 60 extending in the Y direction and spaced apart from each other in the X direction. The shielding patterns 60 may be alternately disposed with the bit lines 50 in the X direction. A lower surface of the shielding pattern 60 may be disposed at a lower level than a lower surface of the bit line 50, and an upper surface of the shielding pattern 60 may be disposed at a lower level than an upper surface of the bit line 50. The shielding pattern 60 may reduce capacitance between the bit lines 50.

[0031] The shielding pattern 60 may include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof.

[0032] The upper structure US may be disposed on the bit line 50. The upper structure US may include a mold structure MS, a channel structure 73, a word line 79, an upper insulating structure 81, an upper capping layer 82, and a landing pad structure 83.

[0033] The molding structure MS may be disposed on the bit line 50. In a plan view, the molding structure MS may extend in the X direction and may be spaced apart from each other in the Y direction. The molding structure MS may include a lower molding layer M1, an upper molding layer M2, and a liner ML. The upper molding layer M2 may be disposed on the lower molding layer M1, and the lower molding layer M1 and the upper molding layer M2 may extend in the X direction. The liner ML may cover a portion of a side surface of the upper molding layer M2 and a side surface of the lower molding layer M1. In a cross-sectional view, an upper surface of the liner ML may be disposed at a level higher than an upper surface of the lower molding layer M1, and may be disposed at a level lower than an upper surface of the upper molding layer M2. In a plan view, the liner ML may be spaced apart from each other in the X direction and the Y direction.

[0034] The lower mold layer M1 and the upper mold layer M2 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In example embodiments, the lower mold layer M1 and the upper mold layer M2 may include different materials. For example, the lower mold layer M1 may include silicon oxide, and the upper mold layer M2 may include silicon nitride. The liner ML may include silicon oxide, silicon oxynitride, hafnium oxide, or a combination thereof.

[0035] The channel structure 73 may be disposed on the bit line 50. The channel structure 73 may include a horizontal portion 73L that contacts and is electrically connected to the bit line 50, and a vertical channel portion 73S that extends upward in the Z direction from one end of the horizontal portion 73L. The lower surface of the horizontal portion 73L may contact the bit line 50, and the horizontal portion 73L may be electrically connected to the bit line 50. In example embodiments, the vertical channel portion 73S may extend in a direction inclined to the vertical direction (Z direction), but the present disclosure is not limited thereto. When viewed in a plan view, the channel structure 73 may be disposed on a side surface of the liner ML. The liner ML may be disposed between the channel structure 73 and the lower mold layer M1, and the channel structure 73 may be spaced apart from the lower mold layer M1. The channel structures 73 may be spaced apart from each other in the X direction and the Y direction. In example embodiments, the horizontal width of each channel structure 73 in the X direction may be the same as the horizontal width of each liner ML in the X direction.

[0036] Although Figure 1B The channel structures 73 are shown to be spaced apart from each other, but the present disclosure is not limited thereto. In some example embodiments, the horizontal portions 73L of the channel structures 73 disposed adjacent to each other and facing each other in the Y direction may extend in the horizontal direction and may be integrally formed.

[0037] The channel structure 73 may be formed of a semiconductor material such as silicon. The channel structure 73 may be formed of single crystal silicon or polycrystalline silicon. However, the channel structure 73 is not limited to semiconductor materials such as silicon, but may be formed of other semiconductor materials that can be used as a channel region of a transistor. For example, the channel structure 73 may include an oxide semiconductor layer or a two-dimensional material layer that can be used as a channel region of a transistor.

[0038] The oxide semiconductor layer may be indium gallium zinc oxide (IGZO).However, example embodiments are not limited thereto. For example, the oxide semiconductor layer may include at least one of indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), indium tin zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO).

[0039] The two-dimensional material layer may include at least one of a transition metal dichalcogenide material layer, a black phosphorus material layer, and a hexagonal boron nitride (hBN) material layer that may have semiconductor properties. For example, the two-dimensional material layer may include BiOSe, Cr1, WSe 2 、MoS 2 , TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene and Janus 2D materials, which can form a two-dimensional material.

[0040] When viewed in a plan view, the word line 79 may cross the bit line 50. For example, the word line 79 may extend along the side surface of the mold structure MS in the X direction and may be spaced apart from each other in the Y direction. The word line 79 may be disposed on the channel structure 73. For example, the word line 79 may overlap the horizontal portion 73L of the channel structure 73 in the vertical direction. The upper end of the word line 79 may be located at a level lower than that of the upper surface of the mold structure MS.

[0041] The upper structure US may further include a dielectric structure 76 between the word line 79 and the channel structure 73. The dielectric structure 76 may be disposed between the word line 79 and the vertical channel portion 73S, and between the word line 79 and the horizontal portion 73L. In example embodiments, a portion of the dielectric structure 76 may cover an upper surface of the upper mold layer M2, but the present disclosure is not limited thereto.

[0042] In one example, each of the dielectric structures 76 may be a tunnel dielectric layer that does not include an information storage layer. For example, each of the dielectric structures 76 may include at least one of silicon oxide and a high-κ dielectric. The high-κ dielectric may include a metal oxide. For example, the high-κ dielectric may be composed of HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 Each of the dielectric structures 76 may be formed of a single layer or multiple layers of the above materials.

[0043] In another example, each of the dielectric structures 76 may include an information storage layer and a dielectric layer. For example, each of the dielectric structures 76 may have a polarization characteristic that depends on an electric field, and may include a ferroelectric layer that may have a residual polarization caused by a dipole in the absence of an external electric field. This polarization state in the ferroelectric layer may be used to record data. Therefore, each of the dielectric structures 76 may include a ferroelectric layer that may be referred to as an information storage layer. The ferroelectric layer that may serve as an information storage layer may include an Hf-based compound, a Zr-based compound, and / or an Hf-Zr-based compound. For example, the Hf-based compound may be an HfO-based ferroelectric material, the Zr-based compound may include a ZrO-based ferroelectric material, and the Hf-Zr-based compound may include a hafnium zirconium oxide (HZO)-based ferroelectric material. The ferroelectric layer that may serve as an information storage layer may include impurities, for example, a ferroelectric material doped with at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr. For example, the ferroelectric layer that may serve as an information storage layer may be a ferroelectric layer in which HfO 2 、ZrO 2 The information storage layer may be a material doped with at least one of impurities (i.e., at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr) of at least one of HfZrO and HfZrO. In the dielectric structure 76, the information storage layer is not limited to the above-mentioned material types and may include a material capable of storing information.

[0044] The upper insulating structure 81 may be disposed between the mold structures MS and may cover the word lines 79. The upper insulating structures 81 may extend in the X direction and may be spaced apart from each other in the Y direction. The upper insulating structures 81 may be alternately disposed with the mold structures MS in the Y direction. The upper insulating structure 81 may include a first upper insulating layer 81a and a second upper insulating layer 81b. The first upper insulating layer 81a may be conformally disposed along the surfaces of the bit lines 50, the channel structures 73, the dielectric structures 76, and the word lines 79. The second upper insulating layer 81b may be disposed on the first upper insulating layer 81a and may fill the space between the mold structures MS. In example embodiments, a portion of the first upper insulating layer 81a may cover a portion of the dielectric structure covering the upper surface of the upper mold layer M2. The first upper insulating layer 81a and the second upper insulating layer 81b may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric material, or a combination thereof. For example, the first upper insulating layer 81a may include silicon nitride, and the second upper insulating layer 81b may include silicon oxide.

[0045] The upper capping layer 82 may cover the mold structure MS and the upper insulating structure 81 and may extend in a horizontal direction. The upper capping layer 82 may contact the upper surface of the first upper insulating layer 81a and the upper surface of the second upper insulating layer 81b. The upper capping layer 82 may include silicon nitride.

[0046] The landing pad structure 83 may be disposed on the channel structure 73 and may penetrate the upper capping layer 82 to contact the vertical channel portion 73S of the channel structure 73. The landing pad structure 83 may be electrically connected to the bit line 50 through the channel structure 73.

[0047] Figure 2 yes Figure 1B A partial enlarged view of the semiconductor device shown in FIG. Figure 2 , the landing pad structure 83 may be composed of a metal layer 85 and a barrier layer 84 covering the side and bottom surfaces of the metal layer 85. The barrier layer 84 may include at least one of TiN, TaN, WN, TiSiN, TaSiN, and RuTiN, and the metal layer 85 may include a metal material such as W or Mo.

[0048] In an example embodiment, the landing pad structure 83 may include a first contact portion C1, a second contact portion C2, a protrusion P, a connection portion CP, and a pad portion PA. The pad portion PA may refer to a portion of the landing pad structure 83 disposed on the upper capping layer 82 and may contact the first electrode 88a of the information storage structure 87 described below. The connection portion CP may be disposed below the pad portion PA and may vertically penetrate the upper capping layer 82. For example, the connection portion CP may refer to a portion of the landing pad structure 83 disposed between the lower surface of the pad portion PA and the upper surface of the mold structure MS. The first contact portion C1 may be disposed below the connection portion CP and may contact the upper surface of the channel structure 73. For example, the first contact portion C1 may refer to a portion of the landing pad structure 83 disposed between the upper surface of the mold structure MS and the upper surface of the vertical channel portion 73S. The horizontal width of the first contact portion C1 in the Y direction may be greater than the horizontal width of the channel structure 73 in the Y direction.

[0049] The second contact portion C2 may contact the channel structure 73 and the liner ML. For example, the second contact portion C2 may refer to a portion of the landing pad structure 83 between the upper surface of the vertical channel portion 73S and the upper surface of the liner ML. The second contact portion C2 may have a shape protruding downward from the lower surface of the first contact portion C1. In example embodiments, the second contact portion C2 may contact the side surface of the vertical channel portion 73S, the upper surface of the liner ML, and the side surface of the upper mold layer M2. In example embodiments, the lower surface of the second contact portion C2 may be disposed at a level higher than the upper surface of the lower mold layer M1, but the present disclosure is not limited thereto. The second contact portion C2 may overlap with the first contact portion C1 in the vertical direction. The upper region of the vertical channel portion 73S may be disposed between the second contact portion C2 and the word line 79, for example, the horizontal distance between the second contact portion C2 and the adjacent word line 79 may be greater than the horizontal distance between the first contact portion C1 and the adjacent word line 79. The horizontal width of the second contact portion C2 in the Y direction may be the same as the horizontal width of the liner ML in the Y direction.

[0050] like Figure 2 As shown, the landing pad structure 83 according to the example embodiment of the present disclosure may contact the upper surface and the side surface of the vertical channel portion 73S of the channel structure 73, thereby increasing the contact area between the landing pad structure 83 and the channel structure 73. Therefore, the contact resistance between the landing pad structure 83 and the channel structure 73 may be reduced, and the electrical characteristics of the semiconductor device 100 may be improved.

[0051] The protrusion P may be in contact with the upper insulating structure 81. For example, the protrusion P may refer to a portion of the landing pad structure 83 protruding from the lower portion of the connection portion CP toward the upper insulating structure 81. The upper surface of the protrusion P may be disposed at a level lower than the upper surface of the connection portion CP, and the lower surface of the protrusion P may be disposed at a level lower than the lower surface of the connection portion CP. The protrusion P may be in contact with the lower surface of the upper capping layer 82 and the side surface of the second upper insulating layer 81b.

[0052] The upper structure US may further include an insulating pattern 86 disposed on the upper capping layer 82 and between the landing pad structures 83. The insulating pattern 86 may cover the side surfaces of the pad portions PA of the landing pad structures 83 and may electrically insulate the landing pad structures 83 from each other. The insulating pattern 86 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric material, or a combination thereof. For example, the insulating pattern 86 may include silicon oxide.

[0053] Return to reference Figure 1B The information storage structure 87 may be disposed on the upper structure US. The information storage structure 87 may include a first electrode 88a electrically connected to and in contact with the landing pad structure 83, a second electrode 88c on the first electrode 88a, and a dielectric layer 88b between the first electrode 88a and the second electrode 88c.

[0054] In an example, the information storage structure 87 may be a capacitor configured to store information in a DRAM. For example, the dielectric layer 88b of the information storage structure 87 may be a capacitor dielectric layer of a DRAM, and the dielectric layer 87b may include a high-κ dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0055] In another example, the information storage structure 87 may be a structure configured to store information of a memory different from a DRAM. For example, the information storage structure 87 may be a capacitor of a ferroelectric memory (FeRAM). For example, the dielectric layer 88b may be a ferroelectric layer configured to record data using a polarization state. In another example, the dielectric layer 88b may include a lower dielectric layer and a ferroelectric layer on the lower dielectric layer. Here, the lower dielectric layer may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-κ dielectric. In an example embodiment, when the dielectric structure 76 includes an information storage layer, the information storage structure 87 may be omitted.

[0056] Figures 3 to 7 is a vertical cross-sectional view of a semiconductor device according to an example embodiment. Figure 3 , the landing pad structure 83 of the semiconductor device 200 may include a first contact portion C1 and a second contact portion C2 disposed on a side surface of the mold structure MS and in contact with the vertical channel portion 73S of the channel structure 73. In example embodiments, Figure 2 The liner ML shown in FIG. 1 may include the same material as the lower mold layer M1 and may be integrally formed. The lower mold layer M1 may include a protrusion MP protruding upward. The upper surface of the protrusion MP may be set at a level higher than the level of the lower surface of the upper mold layer M2. The protrusion MP may contact the side surface of the upper mold layer M2, the side surface of the vertical channel portion 73S, and the lower surface of the second contact portion C2.

[0057] Reference Figure 4 , the landing pad structure 83 of the semiconductor device 300 may include a first contact portion C1 and a second contact portion C2 that contact the vertical channel portion 73S of the channel structure 73. In example embodiments, the lower surface of the second contact portion C2 may be rounded and protrude downward. The lower end of the second contact portion C2 may be disposed at a level higher than that of the upper surface of the lower molding layer M1. In example embodiments, the side surface of the protrusion P of the landing pad structure 83 may be rounded.

[0058] Reference Figure 5 , the landing pad structure 83 of the semiconductor device 400 may include a first contact portion C1 and a second contact portion C2 that contact the vertical channel portion 73S of the channel structure 73. In example embodiments, the second contact portion C2 may include a protrusion P2 that protrudes from a side surface of the second contact portion C2 toward the lower mold layer M1 (e.g., in a direction away from the adjacent word line 79). For example, the protrusion P2 may contact the lower mold layer M1, the lower surface of the upper mold layer M2, the upper surface of the liner ML, and the side surface of the vertical channel portion 73S.

[0059] The protrusion P1 may have a Figure 2 The protrusion P may have the same or similar structure as described above. For example, the protrusion P1 may protrude from a lower portion of the connection portion CP toward the upper insulating structure 81 .

[0060] Reference Figure 6 , the landing pad structure 83 of the semiconductor device 500 may include a first contact portion C1 and a second contact portion C2 contacting the vertical channel portion 73S of the channel structure 73. In example embodiments, Figure 1B and Figure 2 The upper and lower mold layers M2 and M1 shown in FIG. 4 may include the same material and may be integrally formed. For example, the mold structure MS may include a mold layer M and a liner ML disposed on a side surface of the mold layer M. In example embodiments, the mold layer M may include silicon nitride or silicon oxide.

[0061] Reference Figure 7 , the landing pad structure 83 of the semiconductor device 600 may include a first contact portion C1 and a second contact portion C2 contacting the vertical channel portion 73S of the channel structure 73. In example embodiments, Figure 1B and Figure 2 The upper mold layer M2 and the lower mold layer M1 shown in FIG. 4 may include the same material and may be integrally formed. Figure 6 In the example embodiment shown in , a step portion may exist between the lower mold layer M1 and the upper mold layer M2. For example, the lower mold layer M1 may have a horizontal width greater than that of the upper mold layer M2, and the lower mold layer M1 may have a shape that protrudes horizontally from the side surface of the upper mold layer M2. In example embodiments, the lower mold layer M1 and the upper mold layer M2 may include the same material as the liner ML. For example, the lower mold layer M1, the upper mold layer M2, and the liner ML may include silicon oxide.

[0062] In example embodiments, the horizontal width of the first contact portion C1 in the Y direction may be greater than the sum of the horizontal widths of the vertical channel portion 73S and the liner ML in the Y direction. The horizontal width of the second contact portion C2 in the Y direction may be greater than the horizontal width of the liner ML in the Y direction.

[0063] Reference Figure 8 , the semiconductor device 700 may include a mold structure MS including a void V therein. In example embodiments, Figure 1B and Figure 2 The upper and lower mold layers M2 and M1 shown in FIG. 1 may include the same material and may be integrally formed, thereby forming the mold layer M. The mold layer M may include a void V therein, and a liner ML may be disposed on a side surface of the mold layer M. The void may reduce coupling noise between word lines 79 adjacent to each other.

[0064] Fig. 9 is a vertical cross-sectional view of a semiconductor device according to example embodiments; and Fig.10 yes Fig. 9 A partially enlarged view of a semiconductor device shown in FIG. Fig. 9 and Fig.10 , the landing pad structure 83 of the semiconductor device 800 may include a first contact portion C1 and a second contact portion C2 in contact with the vertical channel portion 73S of the channel structure 73. In example embodiments, the channel structure 73 may be formed of a plurality of layers. For example, the channel structure 73 may include an inner channel structure 874 and an outer channel structure 873 disposed on the inner channel structure 874. The inner channel structure 874 may include an inner horizontal portion 874L in contact with and electrically connected to the bit line 50 and an inner vertical channel portion 874S extending upward in the Z direction from one end of the inner horizontal portion 874L. The outer channel structure 873 may include an outer horizontal portion 873L in contact with the inner horizontal portion 874L and an outer vertical channel portion 873S in contact with the inner vertical channel portion 874S.

[0065] In example embodiments, the inner channel structure 874 may include the same material as the outer channel structure 873. In example embodiments, the upper surface of the inner channel structure 874 may be disposed at a level lower than that of the upper surface of the outer channel structure 873. For example, the upper surface of the inner vertical channel portion 874S may be disposed at a level lower than that of the upper surface of the outer vertical channel portion 873S. The first contact portion C1 may contact the upper surface of the outer vertical channel portion 873S, and the second contact portion C2 may contact the side surface of the outer vertical channel portion 873S and the upper surface of the inner vertical channel portion 874S. Fig. 9 and Fig.10 It is illustrated that the thicknesses of the inner channel structure 874 and the outer channel structure 873 are different from each other, but the present disclosure is not limited thereto. In some example embodiments, the thicknesses of the inner channel structure 874 and the outer channel structure 873 may be the same.

[0066] FIG. 11A to FIG. 21 1 is a plan view and a vertical cross-sectional view shown in accordance with a process sequence to explain a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17A is with Figure 1A The corresponding floor plan. Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18 , Fig.19 , Fig. 20 and Fig.21 is with Figure 1B The corresponding vertical cross-section. Fig. 11C , Fig. 13C , Fig. 14C , Fig. 15C and Fig. 17C is with Figure 1C The corresponding vertical cross-section.

[0067] Reference FIG. 11A to FIG. 11C , a lower structure LS may be formed. The lower structure LS may include a substrate 3, a circuit element TR on the substrate 3, a peripheral wiring 23 and a peripheral plug 20 electrically connected to the circuit element TR, a first peripheral insulating layer 30 surrounding the side surface of the peripheral plug 20 and the side surface of the circuit element TR, and a second peripheral insulating layer 32 surrounding the peripheral wiring 23 and the peripheral plug 20.

[0068] An etch stop layer 40 may be formed on the lower structure LS. The etch stop layer 40 may cover the peripheral wiring 23 and the second peripheral insulating layer 32. Bit lines 50, bit line plugs 53, bit line insulating layers 56, and shielding patterns 60 may be formed on the etch stop layer 40. For example, the bit line plugs 53 may be formed to penetrate the etch stop layer 40 and contact the peripheral wiring 23, and the bit lines 50 may be formed on the bit line plugs 53. An insulating material may be deposited to cover the bit line plugs 53 and the bit lines 50, and a shielding pattern 60 may be formed on the insulating material. Then, an insulating material may also be deposited to cover the shielding pattern 60, thereby forming the bit line insulating layer 56. The bit lines 50 may extend in the Y direction and may be spaced apart from each other in the X direction. The shielding patterns 60 may extend in the Y direction and may be spaced apart from each other in the X direction. The shielding patterns 60 may be arranged alternately with the bit lines 50 in the X direction.

[0069] Reference Fig. 12A and Fig. 12B , a mold structure MS may be formed on the bit line 50 and the bit line insulating layer 56. A lower insulating material and an upper insulating material may be sequentially stacked to cover the bit line 50 and the bit line insulating layer 56, and then the lower insulating material and the upper insulating material may be patterned to form a lower mold layer M1 and an upper mold layer M2. Then, an insulating material may be formed to cover the bit line 50, the bit line insulating layer 56, the lower mold layer M1, and the upper mold layer M2, and then the insulating material may be anisotropically etched to form a liner ML. The lower mold layer M1, the upper mold layer M2, and the liner ML may form the mold structure MS. The lower mold layer M1 and the upper mold layer M2 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The liner ML may include silicon oxide, silicon oxynitride, hafnium oxide, or a combination thereof.

[0070] The mold structures MS may extend in the X direction and may be spaced apart from each other in the Y direction. The liner ML may cover side surfaces of the lower and upper mold layers M1 and M2. In example embodiments, the mold structure MS may have a tapered shape in which its horizontal width in the Y direction decreases as it moves upward, but the present disclosure is not limited thereto.

[0071] In example embodiments, the lower mold layer M1 and the upper mold layer M2 may include different materials. For example, the lower mold layer M1 may include silicon oxide, and the upper mold layer M2 may include silicon nitride. In some example embodiments, the lower mold layer M1 and the upper mold layer M2 may include the same material and may be integrally formed.

[0072] Reference FIG. 13A to FIG. 13C , a channel material layer 73p and a sacrificial layer SL may be formed. The channel material layer 73p may be formed to cover the bit line 50, the bit line insulating layer 56, and the mold structure MS. For example, the channel material layer 73p may conformally cover the mold structure MS. The sacrificial layer SL may be formed to cover the channel material layer 73p.

[0073] Reference FIG. 14A to FIG. 14C The liner ML, the channel material layer 73p, and the sacrificial layer SL may be planarized and patterned. The channel material layer 73p and the sacrificial layer SL may be planarized so that the upper surface of the mold structure MS is exposed, and the upper surface of the channel material layer 73p and the upper surface of the sacrificial layer SL may be coplanar with the upper surface of the mold structure MS.

[0074] In addition, the channel material layer 73p and the sacrificial layer SL may be patterned by an anisotropic etching process, and the upper surface of the bit line insulating layer 56 may be partially exposed. In a plan view, the liner ML may be disposed on the side surface of the lower mold layer M1 and may be spaced apart from each other in the X direction and the Y direction. The channel material layer 73p may be spaced apart from each other in the X direction and the Y direction while being in contact with the side surface of the liner ML.

[0075] Reference FIG. 15A to FIG. 15C , the sacrificial layer SL may be removed, and a dielectric material layer 76p and a conductive layer 79p may be formed. The dielectric material layer 76p may be conformally formed along the bit line insulating layer 56, the channel material layer 73p, and the mold structure MS. The conductive layer 79p may cover the dielectric material layer 76p.

[0076] Reference Fig.16A and Fig. 16B , the dielectric material layer 76p and the conductive layer 79p may be etched by an anisotropic etching process, thereby forming a dielectric structure 76 and a word line 79. In example embodiments, a portion of the dielectric structure 76 covering the upper surface of the mold structure MS may remain, but the present disclosure is not limited thereto. In some example embodiments, a portion of the dielectric structure 76 covering the upper surface of the mold structure MS may be removed, and the upper surface of the mold structure MS may be exposed.

[0077] In a plan view, the word lines 79 may intersect the bit lines 50. For example, the word lines 79 may be disposed on one side of the mold structure MS to extend in the X direction, and may be spaced apart from each other in the Y direction.

[0078] In example embodiments, portions of the channel material layer 73p between the mold structures MS may be etched to form the channel structure 73. The channel structure 73 may include a horizontal portion 73L that contacts the bit line 50 and extends horizontally, and a vertical channel portion 73S that extends upward along the side surface of the liner ML. In example embodiments, the vertical channel portion 73S may extend in a direction other than the vertical direction (Z direction), but the present disclosure is not limited thereto. In some example embodiments, the vertical channel portion 73S may extend in the vertical direction. A portion of the channel material layer 73p may be etched to partially expose the upper surface of the bit line 50 between the mold structures MS. In some example embodiments, the channel material layer 73p may extend between adjacent mold structures MS in the Y direction without being damaged. For example, the channel material layer 73p may cover the side surfaces of a plurality of mold structures MS, and Fig. 16B The upper surface of the bit line 50 may not be exposed.

[0079] Reference FIG. 17A to FIG. 17C , an upper insulating structure 81 and an upper capping layer 82 may be formed. The upper insulating structure 81 may include a first upper insulating layer 81a and a second upper insulating layer 81b. The first upper insulating layer 81a may be conformally formed along the bit line 50, the bit line insulating layer 56, the channel structure 73, the dielectric structure 76 and the word line 79. The second upper insulating layer 81b may be formed by depositing an insulating material to cover the first upper insulating layer 81a, and then planarizing the insulating material to expose the upper surface of the first upper insulating layer 81a. The upper insulating structure 81 may extend in the X direction and may be spaced apart from each other in the Y direction. The upper insulating structure 81 may be alternately arranged with the mold structure MS in the Y direction. The upper capping layer 82 may cover the upper surface of the upper insulating structure 81.

[0080] Reference Fig.18 , the upper capping layer 82 may be etched by an anisotropic etching process, and an opening OP exposing the channel structure 73 may be formed. The opening OP may expose the upper surface of the vertical channel portion 73S. The opening OP may also expose the upper molding layer M2, the liner ML, the dielectric structure 76, and the upper insulating structure 81.

[0081] Reference Fig.19 , the channel structure 73 may be selectively etched. Etching the channel structure 73 may include performing a first wet etching process. The etchant may flow into the opening OP, and the upper portion of the vertical channel portion 73S of the channel structure 73 may be selectively etched by the etchant. In example embodiments, the upper surface of the etched vertical channel portion 73S may be higher than the upper surface of the lower mold layer M1. Since the liner ML includes a material having a selectivity ratio with the channel structure 73, the liner ML may not be etched. The side surfaces of the liner ML and the dielectric structure 76 may be partially exposed by the first wet etching process.

[0082] Reference Fig. 20 , the liner ML may be etched by the second wet etching process. Since the liner ML has an etching selectivity ratio with the channel structure 73, the channel structure 73 may not be etched, and the liner ML may be selectively etched. An upper surface of the etched liner ML may be disposed at a level lower than that of an upper surface of the vertical channel portion 73S. In example embodiments, an upper surface of the liner ML may be disposed at a level higher than that of an upper surface of the lower molding layer M1, but the present disclosure is not limited thereto.

[0083] In example embodiments, the upper insulating structure 81 may be partially etched by an etching process. For example, the second upper insulating layer 81b may include the same material as the liner ML, and a portion of the second upper insulating layer 81b may be etched together with the liner ML.

[0084] In an example embodiment, if Figure 4 As shown, the liner ML and the second upper insulating layer 81b may be etched into a round shape. Figure 5 As shown, the liner ML may be etched such that an upper surface thereof is disposed at a level lower than that of an upper surface of the lower molding layer M1. In addition, when the lower molding layer M1 includes the same material as the liner ML, the lower molding layer M1 may be partially etched.

[0085] In an example embodiment, if Figure 7 As shown in , when the lower mold layer M1 and the upper mold layer M2 include the same material as the liner ML, the upper mold layer M2 may be partially etched.

[0086] In an example embodiment, if Fig.10 As shown in , the liner ML may be replaced by the inner channel structure 73, and the channel structure 73 may include an inner channel structure 874 and an outer channel structure 873. The inner channel structure 874 may include the same material as the outer channel structure 873. However, the inner channel structure 874 may be formed by a physical vapor deposition (PVD) method, while the outer channel structure 873 may be formed by an atomic layer deposition (ALD) method. The outer channel structure 873 may be deposited more densely than the inner channel structure 874. When the second wet etching process is performed, the etching rate of the inner channel structure 874 formed by the PVD method may be different from the etching rate of the outer channel structure 873 formed by the ALD method. Therefore, the inner channel structure 874 may be etched faster, and the upper surface of the inner channel structure 874 may be set at a level lower than the level of the upper surface of the outer channel structure 873.

[0087] Reference Fig.21 , a conductive layer 83p may be formed to cover the upper capping layer 82 and fill the opening at the same time. Figure 2As shown, the conductive layer 83p may include a barrier layer 84 and a metal layer 85. The conductive layer 83p may contact the upper surface of the vertical channel portion 73S and the upper surface of the liner ML. The conductive layer 83p may also partially contact the side surface of the vertical channel portion 73S. The conductive layer 83p may be electrically connected to the bit line 50 through the channel structure 73.

[0088] Refer to Figures 1A to 1C , the conductive layer 83p may be patterned to form a landing pad structure 83. After depositing an insulating material to cover the landing pad structure 83, the insulating material may be planarized to expose the upper surface of the landing pad structure 83, thereby forming an insulating pattern 86. The insulating pattern 86 may be disposed at the same level as that of the landing pad structure 83, and may electrically insulate the landing pad structures 83 from each other. The mold structure MS, the channel structure 73, the dielectric structure 76, the word line 79, the upper insulating structure 81, the upper capping layer 82, the landing pad structure 83, and the insulating pattern 86 may form an upper structure US.

[0089] An information storage structure 87 may be formed on the upper structure US to manufacture the semiconductor device 100. Figures 1A to 1C As described above, the information storage structure 87 may include a first electrode 88a electrically connected to and in contact with the landing pad, a second electrode 88c on the first electrode 88a, and a dielectric layer 88b between the first electrode 88a and the second electrode 88c.

[0090] like Fig. 20 As shown, the second contact portion C2 may be disposed in a space in which the liner ML is etched by a wet etching process. Since the second contact portion C2 is magnetically aligned and disposed, defects in the process may be prevented and reduced compared to a case where an exposure process is performed to form a space in which the second contact portion C2 is disposed. Therefore, the second contact portion C2 having a finer pattern than the first contact portion C1 may be formed, thereby preventing and reducing defects in the semiconductor device 100.

[0091] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit memory device, comprising: a substrate having a bit line extending in a first horizontal direction thereon; a channel structure extending on the bit line, the channel structure comprising a horizontal portion on the bit line and a vertical channel portion extending upward from one end of the horizontal portion; a word line extending opposite to the vertical channel portion and crossing the bit line to extend in a second horizontal direction crossing the first horizontal direction; as well as A landing pad structure is electrically connected to the vertical channel portion, the landing pad structure including a first contact portion contacting an upper surface of the vertical channel portion and a second contact portion protruding downward from a lower surface of the first contact portion.

2. The integrated circuit memory device of claim 1, wherein: The horizontal width of the first contact portion is greater than the horizontal width of the vertical channel portion.

3. The integrated circuit memory device of claim 1, wherein: The second contact portion contacts a side surface of the vertical channel portion.

4. The integrated circuit memory device of claim 1, wherein: An upper region of the vertical channel portion extends between the second contact portion and the word line.

5. The integrated circuit memory device of claim 1 , further comprising: an electrically insulating molding structure extending on the bit line along the second horizontal direction; wherein the molding structure comprises a lower molding layer, an upper molding layer on the lower molding layer, and a liner on a side surface of the lower molding layer; and Wherein, the liner extends between the lower molding layer and the vertical channel portion.

6. The integrated circuit memory device of claim 5, wherein: The second contact portion contacts an upper surface of the liner.

7. The integrated circuit memory device of claim 5, wherein: The vertical channel portion is spaced apart from the lower molding layer.

8. The integrated circuit memory device of claim 5, wherein: A lower surface of the second contact portion is disposed at a higher level than an upper surface of the lower molding layer with respect to an upper surface of the substrate.

9. The integrated circuit memory device of claim 5, wherein: The liner includes at least one of silicon oxide, silicon oxynitride, and hafnium oxide.

10. The integrated circuit memory device of claim 5, wherein: A lower surface of the second contact portion protrudes downward.

11. The integrated circuit memory device of claim 5, wherein: The lower molding layer includes the same material as the upper molding layer and is integrally formed.

12. The integrated circuit memory device of claim 5, wherein: The lower molding layer and the upper molding layer include the same material as the liner; and wherein the lower molding layer has a shape horizontally protruding from a side surface of the upper molding layer.

13. The integrated circuit memory device of claim 5, wherein: The molded structure has a void therein.

14. The integrated circuit memory device of claim 1, further comprising: an upper insulating structure covering upper surfaces of the bit lines and the word lines; and Wherein, the landing pad structure further includes a first protrusion protruding to the upper insulating structure.

15. The integrated circuit memory device of claim 1, wherein: The landing pad structure further includes a second protrusion protruding from a side surface of the second contact portion in a direction away from the word line.

16. The integrated circuit memory device of claim 1, in, Wherein, the channel structure comprises an inner channel structure and an outer channel structure extending on the inner channel structure; wherein the upper surface of the outer channel structure extends at a higher level than the upper surface of the inner channel structure; wherein the first contact portion contacts an upper surface of the outer channel structure; and Wherein, the second contact portion contacts a side surface of the outer channel structure and an upper surface of the inner channel structure.

17. An integrated circuit memory device comprising: a bit line extending in a first horizontal direction; a molding structure extending on the bit line and in a second horizontal direction intersecting the first horizontal direction, the molding structure comprising a molding layer and a liner on a side surface of the molding layer; a channel structure extending on the bit line, the channel structure comprising a horizontal portion on the bit line and a vertical channel portion extending upward from one end of the horizontal portion and extending on a side surface of the liner; a word line extending on the horizontal portion and crossing the bit line to extend in the second horizontal direction; as well as a landing pad structure extending over the vertical channel portion and electrically connected to the channel structure; wherein the upper surface of the vertical channel portion extends at a higher level than the upper surface of the liner; The landing pad structure includes a first contact portion contacting an upper surface of the vertical channel portion, and a second contact portion contacting a side surface of an upper region of the vertical channel portion and an upper surface of the liner.

18. The integrated circuit memory device of claim 17, wherein: The molding structure includes a lower molding layer and an upper molding layer on the lower molding layer; wherein the lower molding layer includes the same material as the liner and is formed integrally; and wherein a portion of the lower molding layer extends at a higher level than a lower surface of the upper molding layer.

19. The integrated circuit memory device of claim 17, wherein: The horizontal width of the second contact portion is the same as the horizontal width of the liner.

20. A semiconductor device comprising: a lower structure including a circuit element; A bit line disposed on the lower structure and extending along a first horizontal direction; a molding structure disposed on the bit line and extending in a second horizontal direction intersecting the first horizontal direction, the molding structure comprising a molding layer and a liner on a side surface of the molding layer; a channel structure disposed on the bit line, wherein the channel structure includes a horizontal portion on the bit line and a vertical channel portion extending upward from one end of the horizontal portion and disposed on a side surface of the liner; a word line disposed on the horizontal portion and crossing the bit line to extend in the second horizontal direction; an upper insulating structure spaced apart from the mold structure in the second horizontal direction and configured to cover the word lines and the bit lines; an upper capping layer configured to cover the molding structure and the upper insulating structure; a landing pad structure disposed on the vertical channel portion, penetrating the upper capping layer, and electrically connected to the channel structure; and an information storage structure extending over the landing pad structure; Wherein, the landing pad structure includes a pad portion on the upper covering layer, a first contact portion in contact with the upper surface of the vertical channel portion, a second contact portion in contact with the side surface of the vertical channel portion and the upper surface of the liner, and a connecting portion between the pad portion and the first contact portion.

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