Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a substrate, a plurality of first lower electrodes are arranged on the substrate, the plurality of first lower electrodes are arranged in an array in a first direction, a second direction and a third direction which are not perpendicular to each other, the outer contour of each first lower electrode is circular, and the first lower electrodes are arranged in the first direction, the second direction and the third direction. The first lower electrodes are located on the substrate, the second lower electrodes are located on the substrate, the outer contour of each second lower electrode comprises a main body and three protruding parts, the main body is circular, and the three protruding parts are arc-shaped and extend outwards from the center of the main body in the fourth direction, the fifth direction and the sixth direction respectively.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor memory device and a manufacturing method thereof. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related memory devices. Summary of the invention

[0003] The present invention provides a semiconductor device, comprising a substrate, a plurality of first lower electrodes located on the substrate, the plurality of first lower electrodes being arranged into an array in a first direction, a second direction and a third direction which are not perpendicular to each other, the outer contour of each of the first lower electrodes being circular, a plurality of second lower electrodes being located on the substrate, the outer contour of the second lower electrodes comprising a main body and three protrusions, wherein the main body is circular, and the three protrusions are arc-shaped, extending outward from the center of the main body along a fourth direction, a fifth direction and a sixth direction respectively.

[0004] The present invention further provides a semiconductor device, including a substrate, a plurality of first lower electrodes and a second lower electrode located on the substrate, the plurality of first lower electrodes being arranged adjacent to each other in an array, wherein from a cross-sectional view, each of the first lower electrodes has an I-shaped profile, and each of the second lower electrodes has a U-shaped profile.

[0005] The present invention further provides a method for manufacturing a semiconductor device, comprising the following steps: providing a substrate, forming a supporting stacking layer located on the substrate, forming a mask layer located on the supporting stacking layer, performing a first patterning step to form a plurality of first grooves in the mask layer, performing a second patterning step to form a plurality of second grooves in the mask layer, wherein each of the second grooves overlaps with a plurality of the first grooves from a top view, and the overlapping portion of each of the first grooves and each of the second grooves is defined as a plurality of third grooves, performing an etching step, using the patterned mask layer as a mask, to form a plurality of first capacitor through holes and a plurality of second capacitor through holes in the supporting stacking layer.

[0006] The present invention is characterized in that, from the top view, the second capacitor through hole OP2 is located in the second area A2, the second lower electrode BE2 in the second capacitor through hole OP2 surrounds the periphery of the first lower electrode BE1 of the plurality of first capacitor through holes OP1, and the shape of the second lower electrode BE2 is different from that of the first lower electrode BE1. Since the second area A2 is adjacent to a blank area (i.e., the third area A3) where no components are formed in the manufacturing process, the component density difference between the two areas is large, and it is easy to be affected by the load effect, resulting in damage to the capacitor structure in the second area A2. In the second area A2, the present invention uses a method of overlapping the first groove R1 and the second groove R2 to produce a second capacitor through hole OP2 with a larger area and a special shape. Therefore, compared with the plurality of first capacitor through holes OP1 located in the first area A1, the second capacitor through hole OP2 has a larger coverage area, and the second capacitor through hole OP2 is composed of three first capacitor through holes OP1 and a central through hole, and its structure is stable and less susceptible to damage caused by the load effect. Therefore, the present invention helps to improve the quality of the capacitor structure located in the edge area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings provide a deeper understanding of the embodiments of the present invention and are incorporated into this specification and become a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figures 1 to 7 A schematic diagram of the steps of a method for manufacturing a semiconductor device in a first embodiment of the present invention is shown, wherein Figures 1 to 7 The upper half is a top view of the semiconductor device, and the lower half is a corresponding cross-sectional view of the semiconductor device;

[0009] Figure 8 Draw Figure 6 A partial enlarged schematic diagram of the steps in FIG.

[0010] Fig. 9 and Fig.10 Schematic cross-sectional structures of semiconductor devices according to two other different embodiments of the present invention are respectively shown.

[0011] The reference numerals are described as follows:

[0012] 100: Substrate

[0013] 110: Support stacking layer

[0014] 111: First support layer

[0015] 112: Second support layer

[0016] 113: Third support layer

[0017] 114: Fourth support layer

[0018] 115: Fifth support layer

[0019] 122: Polysilicon layer

[0020] 124: Oxide layer

[0021] 126: Bottom anti-reflective coating

[0022] 128: Photoresist layer

[0023] 130: Capacitor dielectric layer

[0024] 140: Protrusion

[0025] 142: Main Body

[0026] 200: Range

[0027] 210: Depression (gap)

[0028] 211: Completely fill the structure

[0029] 212: Partially filled structure

[0030] A1: First Area

[0031] A2: Second Area

[0032] A3: The third area

[0033] AE1, AE2, AE3, AE4, AE5, AE6, AE7, AE8, AE9, AE10, AE11, AE12: Arc border

[0034] BE1: First lower electrode

[0035] BE2: Second lower electrode

[0036] C1: First capacitor structure

[0037] C2: Second capacitor structure

[0038] D1: First Direction

[0039] D2: Second direction

[0040] D3: Third direction

[0041] D4: The fourth direction

[0042] D5: The fifth direction

[0043] D6: Sixth Direction

[0044] O: Center point

[0045] OP1: First capacitor through hole

[0046] OP2: Second capacitor through hole

[0047] P: First spacing

[0048] R1: First groove

[0049] R2: Second groove

[0050] R3: The third groove

[0051] SOP1: First support opening

[0052] SOP2: Second support opening

[0053] SNP: Contact Pad (Storage Node Pad)

[0054] SNISO: Insulated Sidewall

[0055] TE: Top electrode layer

[0056] W1: First size

[0057] W2: Second size

[0058] W3: Third Size

[0059] W4: Fourth Size DETAILED DESCRIPTION

[0060] Although specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

[0061] Please refer to Figures 1 to 7 , which is a schematic diagram of the steps of the method for manufacturing a semiconductor device in the first embodiment of the present invention. Figures 1 to 7 The upper half of the figure is a top view of the semiconductor device, while the lower half is a cross-sectional view of the semiconductor device. Figure 1 The upper half is a top view of a semiconductor device. Figure 1 The lower half is a cross-sectional view taken along the section line II'. Figure 1 As shown, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.) or a silicon-on-insulator (SOI) substrate, or other suitable material layers. At least one shallow trench isolation (STI, not shown) is formed in the substrate 100, and a plurality of active areas (AA, not shown) are defined in the substrate 100. In addition, a plurality of gates may be formed in the substrate 100, such as buried gates, wherein the buried gates may be used as buried word lines (BWL, not shown) of semiconductor devices. Since the formation of active areas, shallow trench isolation, buried gates and other structures are well known in the art, they will not be repeated here. Figure 1 The substrate 100 represents a structural layer including the above elements.

[0062] In addition, a plurality of bit lines (not shown, bit line, BL) and a plurality of storage node pads (storage node pads) SNP are formed on the substrate 100. Although the bit lines are not specifically shown in the drawings of the present embodiment, those skilled in the art should be able to easily understand that the bit lines extend in parallel with each other, are electrically isolated from the buried gate located in the substrate 100 by an insulating layer (not shown, such as a silicon oxide-silicon nitride-silicon oxide structure) covering the top surface of the substrate 100, and extend into the active region through a bit line plug (not shown, bit line contact, BLC) formed correspondingly below each bit line to be electrically connected to the substrate 100.

[0063] Wherein, adjacent storage node pads SNP are isolated from each other by an insulating sidewall (storage node contact isolation) SCISO disposed directly above each buried gate. In this way, the storage node pad SNP can be electrically connected to the substrate 100 to receive and transmit a voltage signal from the substrate 100 (such as a transistor component in the substrate 100). In one embodiment, the storage node pad SNP includes, for example, a metal material with a low resistance value such as aluminum (aluminum, Al), titanium (titanium, Ti), copper (copper, Cu) or tungsten (tungsten, W), but is not limited thereto.

[0064] For example Figure 1 As shown, a support stack layer 110 is continuously formed on the substrate 100. Specifically, the support stack layer 110 includes, for example, multiple material layers stacked alternately. In the present embodiment, the support stack layer 110 includes, for example, a first support layer 111 (for example, including silicon nitride or silicon carbonitride), a second support layer 112 (for example, including borophosphosilicate glass (BPSG)), a third support layer 113 (for example, including silicon nitride or silicon carbonitride), a fourth support layer 114 (for example, including silicon oxide), and a fifth support layer 115 (for example, including silicon nitride or silicon carbonitride), etc., which are stacked in sequence from bottom to top, but the present invention is not limited thereto. Preferably, the second support layer 112 and the fourth support layer 114 may have a relatively large thickness, for example, about 5 to 10 times the thickness of the nitride layer (for example, including the first support layer 111, the third support layer 113 or the fifth support layer 115). In this way, the overall thickness of the support layer structure 110 is about 1600 angstroms to 2000 angstroms, but is not limited thereto. It should be understood by those skilled in the art that the specific stacking number of the aforementioned oxide layer and the aforementioned nitride layer is not limited to 1. Figure 1 The numbers shown are limited and can be adjusted to other numbers of layers according to actual needs.

[0065] like Figure 1 As shown, a polysilicon layer 122 and an oxide layer 124 as a mask layer are also formed on the support stack layer 110. Figure 1 The oxide layer 124 has been subjected to a patterning step (such as a photolithography process but not limited thereto) to form a plurality of first grooves R1 located in the oxide layer 124. Figure 1 In the top view of the upper half, a plurality of first grooves R1 are arranged in an array on a plane. More specifically, a plurality of first grooves R1 are arranged along a first direction D1, a second direction D2 and a third direction D3 respectively. The first direction D1, the second direction D2 and the third direction D3 are neither parallel nor perpendicular to each other. Preferably, Figure 1The four adjacent first grooves R1 may be arranged in a diamond shape. That is, the distance from any first groove R1 to the adjacent first groove R1 along the second direction D2 may be equal to the distance from the first groove R1 to another adjacent first groove R1 along the third direction D3, but the present invention is not limited thereto.

[0066] For the convenience of explanation, first Figure 1 A first area A1, a second area A2 and a third area A3 are defined. The first groove R1 is located in the first area A1 and the second area A2, while the third area A3 does not include the first groove R1. The second area A2 is located at the edge of the first area A1 and surrounds or encloses the first area A1, while the third area A3 surrounds or encloses the second area A2. That is, the area near the edge of the array formed by the first grooves R1 is defined as the second area A2, and the area outside the second area A2 that does not include the first groove R1 is defined as the third area A3. In this embodiment, the width of the second area A2 approximately includes 1 to 2 first grooves R1, but the present invention is not limited to this.

[0067] Figure 2 The upper half is a top view of a semiconductor device. Figure 2 The lower half is a cross-sectional view taken along the section line II-II'. Figure 2 As shown, a bottom anti-reflective coating 126 and a photoresist layer 128 are formed to cover the polysilicon layer 122 and the patterned oxide layer 124. Then, a photolithography process is performed to pattern the photoresist layer 128, and a plurality of second grooves R2 are formed in the photoresist layer 128. Figure 2 The top view of the second groove R2 is located in the second area A2. The shape of the second groove R2 can be rectangular, circular, polygonal or other shapes, but the present invention is not limited thereto. Preferably, the shape of the second groove R2 in this embodiment is circular, because according to the applicant's experiment, the structure of the circular second groove R2 is more stable, which is conducive to improving the structural strength of the capacitor structure formed subsequently. It is worth noting that Figure 2 From the top view of FIG. 1 , each second groove R2 overlaps with a plurality of first grooves R1 . More specifically, each second groove R2 is located between three adjacent first grooves R1 and overlaps with three first grooves R1 .

[0068] Figure 3 The upper half is a top view of a semiconductor device. Figure 3 The lower half is a cross-sectional view taken along the section line III-III'. Figure 3As shown, the etching step is then continued to transfer the pattern of the second groove R2 to the material layer below. Specifically, the pattern of the second groove R2 is transferred to the oxide layer 124 below, and the redundant bottom anti-reflective coating 126 and the photoresist layer 128 are removed. As mentioned above, since part of the first groove R1 overlaps with the second groove R2, the overlapping part of the first groove R1 and the second groove R2 is defined as the third groove R3. In other words, at this time, the oxide layer 124 includes a plurality of first grooves R1 and a plurality of third grooves R3 located therein. From the top view, the third groove R3 is located in the second area A2, that is, located at the edge periphery of the array formed by the first grooves R1. In addition, the third groove R3 has a special shape, wherein three arc-shaped protrusions are respectively extended outward from the center point O of the third groove R3 toward three different directions D4, D5, and D6. The directions D4, D5, and D6 here are different from the above-mentioned first direction D1, second direction D2, and third direction D3. Specifically, directions from the center point of the second groove R2 toward the center points of the three first grooves R1 overlapping therewith are defined as directions D4, D5, and D6, respectively, but are not limited thereto.

[0069] Figure 4 The upper half is a top view of a semiconductor device. Figure 4 The lower half is a cross-sectional view along the section line IV-IV'. Figure 4 As shown, the pattern transfer step, such as the etching step, is continued, and the pattern of the first groove R1 and the third groove R3 is transferred to the supporting stack layer 110 below using the oxide layer 124 as a mask. For example, a dry etching process is used to sequentially penetrate the fifth supporting layer 115, the fourth supporting layer 114, the third supporting layer 113, the second supporting layer 112 and the first supporting layer 111, and a plurality of first capacitor through holes OP1 and a plurality of second capacitor through holes OP2 are formed in the supporting stack layer 110. Each of the first capacitor through holes OP1 corresponds to the position of the first groove R1, and each of the second capacitor through holes OP2 corresponds to the position of the third groove R3. In addition, the bottom of each first capacitor through hole OP1 exposes a storage node pad SNP below, and the area of ​​each second capacitor through hole OP2 is larger than that of the first capacitor through hole OP1, so the bottom of each second capacitor through hole OP2 exposes multiple (more than two) storage node pads SNP below.

[0070] The positions of the first capacitor through hole OP1 and the second capacitor through hole OP2 formed here will form multiple capacitor structures in subsequent steps. Among them, the first capacitor through holes OP1 are arranged in an array, and the second capacitor through hole OP2 is located at the periphery of the array formed by the first capacitor through holes OP1. The shape of the second capacitor through hole OP2 is the same as the third groove R3 mentioned above, wherein the second capacitor through hole OP2 has a larger area than the first capacitor through hole OP1, so the capacitor structure subsequently formed in the second capacitor through hole OP2 is more stable. In this embodiment, the second capacitor through hole OP2 can protect the first capacitor through hole OP1 located near the edge.

[0071] Figure 5 The upper half is a top view of a semiconductor device. Figure 5 The lower half is a cross-sectional view taken along the section line V-V'. Figure 5 As shown, a deposition and back-etching process is performed to form a plurality of lower electrodes BE1 in the first capacitor through hole OP1, and a second lower electrode BE2 is formed in the second capacitor through hole OP2. In one embodiment, the manufacturing process of the first lower electrode BE1 and the second lower electrode BE2 includes but is not limited to the following steps. First, an electrode material layer is formed in the first capacitor through hole OP1 and the second capacitor through hole OP2, for example, a metal material with a low resistance value such as titanium nitride, aluminum, titanium, copper or tungsten, preferably including titanium nitride. The electrode material layer may fill each first capacitor through hole OP1 and cover the inner surface and bottom surface of the second capacitor through hole OP2, but does not fill the second capacitor through hole OP2. Then, the excess electrode material layer outside the first capacitor through hole OP1 and the second capacitor through hole OP2 is removed, and a first lower electrode BE1 with an I-shaped cross section is formed in the first capacitor through hole OP1, and a second lower electrode BE2 with a U-shaped cross section is formed in the second capacitor through hole OP2. It can be understood that the first lower electrode BE1 and the second lower electrode BE2 have the same material (both are made of an electrode material layer). The bottom of the second bottom electrode BE2 spans across at least two storage node contact pads SNP.

[0072] In addition, from the top view, Figure 5 As shown in the upper half of the figure, since the first lower electrode BE1 fills each first capacitor through hole OP1, and the first capacitor through hole OP1 has a circular contour, the first lower electrode BE1 also has a circular contour. In addition, since the second lower electrode BE2 does not fill the second capacitor through hole OP2, but covers the side surface of the second capacitor through hole OP2, from the top view, there is still a part of the gap in the middle of the second capacitor through hole OP2 that is not filled by the second lower electrode BE2, and the second lower electrode BE2 in the second capacitor through hole OP2 is formed on the inner surface of the second capacitor through hole OP2, and the outer boundary of the second lower electrode BE2 has three arc-shaped protrusions, which correspond to the three top ends of the triangle (please refer to Figure 5 shape shown).

[0073] Figure 6 The upper half is a top view of a semiconductor device. Figure 6 The lower half is a cross-sectional view taken along the section line VI-VI'. Figure 6 As shown, a wet etching process may then be performed, such as introducing an etchant such as tetramethylammonium hydroxide (TMAH) to remove the remaining fourth support layer 114 and the second support material layer 112. At this time, the first support material layer 111, the third support material layer 113 and the fifth support material layer 115 are left in the support stack layer 110 and are located between each of the first bottom electrodes BE1 and / or the second bottom electrode BE2, which can serve as a structure for stabilizing the bottom electrodes.

[0074] In addition, in order to further increase the support effect between the first lower electrode BE1 and / or the second lower electrode BE2, an etching process may be continued after the wet etching process, and a mask (not shown) may be used to form support openings in the remaining support material layer of the support stack layer 110. The support openings may include openings between the first lower electrode BE1 and the adjacent first lower electrode BE1, which are defined as first support openings SOP1, and openings between the first lower electrode BE1 and the second lower electrode BE2, which are defined as second support openings SOP2. In this embodiment, the shapes of the first support opening SOP1 and the second support opening SOP2 are different, and preferably, the area of ​​the first support opening SOP1 is larger than the area of ​​the second support opening SOP2. The first support opening SOP1 is circular or polygonal, the outer contour of the first support opening SOP1 extends through the adjacent plurality of first lower electrodes BE1 and partially exposes the side walls of the adjacent first lower electrodes BE1, and the outer contour of the second support opening SOP2 extends through a first lower electrode BE1 and an adjacent second lower electrode BE2 and partially exposes the side walls of the first lower electrode BE1 and the second lower electrode BE2. In subsequent steps, the first support opening SOP1 and the second support opening SOP2 will be filled with the capacitor dielectric layer and the upper electrode layer, and used as a support structure between the electrodes, thereby further stabilizing the structure.

[0075] Figure 7 The upper half is a top view of a semiconductor device. Figure 7 The lower half is a cross-sectional view taken along the section line VII-VII'. Figure 7As shown, at least one deposition process is performed to sequentially form a capacitor dielectric layer 130 and an upper electrode layer TE. The capacitor dielectric layer 130 conformally covers the exposed surfaces of the first lower electrode BE1 and the second lower electrode BE2, the fifth support layer 115, and the first support opening SOP1 and the second support opening SOP2, while the upper electrode layer TE covers the capacitor dielectric layer 130 and fills the remaining space between the second lower electrode BE2, and fills the first support opening SOP1 and the second support opening SOP2. Part of the capacitor dielectric layer 130 and the upper electrode layer TE can also be further formed in the space between the first support layer 111 and the third support layer 113, and in the space between the third support layer 1163 and the fifth support layer 115, so as to increase the contact area and improve the capacitance value. In one embodiment, the capacitor dielectric layer 130 includes, for example, a high dielectric constant dielectric material, preferably zirconium oxide-aluminum oxide-zirconium oxide (ZAZ), and the upper electrode layer TE includes, for example, titanium nitride, aluminum, titanium, copper or tungsten and other low resistance metal materials, SiGe and other semiconductor materials or a combination of the above materials, preferably including a multilayer structure of titanium nitride and SiGe, but not limited thereto. It is worth noting that Figure 7 The upper electrode layer TE in the embodiment covers all device surfaces, but in order to facilitate the structural features of this embodiment to be seen from the top view, Figure 7 The top view corresponds to the section line VII-VII' in the cross-sectional view, so the first bottom electrode BE1, the second bottom electrode BE2, the capacitor dielectric layer 130, the top electrode layer TE and other material layers can be seen from the top view.

[0076] At this step, a plurality of capacitor structures have been formed, and the capacitor structures are composed of the first lower electrode BE1 and / or the second lower electrode BE2, the capacitor dielectric layer 130 and the upper electrode layer TE stacked in sequence. More specifically, the capacitor structure composed of the first lower electrode BE1, the capacitor dielectric layer 130 and the upper electrode layer TE can be defined as the first capacitor structure C1, and the capacitor structure composed of the second lower electrode BE2, the capacitor dielectric layer 130 and the upper electrode layer TE can be defined as the second capacitor structure C2. The second capacitor structure C2 is located around the first capacitor structure C1 array, which can protect the peripheral structure of the first capacitor structure C1 array. In other words, the second capacitor structure C2 can be used as a dummy capacitor structure. The first capacitor structure C1 and the capacitor structure C2 serve as storage nodes (SN) of the semiconductor device, wherein each capacitor can be electrically connected to the transistor component (not shown) in the substrate 100 through the storage node pad SNP. Under this configuration, the semiconductor device of the present embodiment can form a dynamic random access memory (DRAM) device, which is composed of at least one transistor element and at least one first capacitor structure C1 to form a memory cell of the smallest component in a dynamic random access memory array to receive voltage information from a bit line and a buried word line (buried gate).

[0077] Before forming the capacitor structure, a contact plug may be formed to connect the capacitor structure. This includes forming an interlayer dielectric layer covering the preceding semiconductor structure, and then forming a contact plug made of a conductive material on the interlayer dielectric layer to electrically connect the capacitor structure. The contact plug may include materials such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, etc., preferably tungsten, but not limited thereto. The above features are well known in the art and will not be elaborated herein.

[0078] In addition, the shapes of the first support opening SOP1 and the second support opening SOP2 of the present invention, as well as the shape of the second bottom electrode BE2, also have characteristics. Figure 8 , Figure 8 A partial enlarged top view of the first supporting opening SOP1 , the second supporting opening SOP2 , the first bottom electrode BE1 , and the second bottom electrode BE2 of the semiconductor device of the present invention is shown. Figure 8 For the above Figure 6 The enlarged schematic diagram of the steps shown can be referred to Figure 6 The range 200 includes the first support opening SOP1, the second support opening SOP2, the first bottom electrode BE1 and the second bottom electrode BE2. Figure 8As shown, from the top view, the first support opening SOP1 is located between the three first lower electrodes BE1, each of the first lower electrodes BE1 presents a circular contour, and part of the boundary of the first support opening SOP1 contacts the side wall of the first lower electrode BE1, while the boundary of the other first support opening SOP1 that does not contact the side wall of the first lower electrode BE1 can be roughly connected to form a circle. In other words, the boundary of the first support opening SOP1 can be composed of six arc boundaries connected to each other, which are respectively defined as arc boundaries AE1, AE2, AE3, AE4, AE5, and AE6. Among them, the arc boundaries AE1, AE3, and AE5 have the same radius of curvature, and the arc boundaries AE2, AE4, and AE6 have the same radius of curvature. In addition, the radius of curvature of the arc boundary AE1 is greater than the radius of curvature of the arc boundary AE2.

[0079] Please continue to refer to Figure 8 From the top view, the second supporting opening SOP2 is located between the first lower electrode BE1 and the second lower electrode BE2, wherein the second lower electrode BE2 may include a main body 142 located in the middle and three protrusions 140 located next to it, wherein the main body 142 is roughly circular, and the protrusions 140 are arc-shaped, and the three protrusions 140 extend outward from the center point O of the main body 142 along directions D4, D5, and D6, respectively.

[0080] As for the second support opening SOP2, it is located between the first lower electrode BE1 and the second lower electrode BE2. The shape of the second support opening SOP2 may be a plurality of shapes composed of circular arcs. Taking the present embodiment as an example, the boundary of the second support opening SOP2 may be composed of six arc boundaries connected to each other, which are respectively defined as arc boundaries AE7, AE8, AE9, AE10, AE11, and AE12. The arc boundaries AE7 and AE11 have the same radius of curvature, while the arc boundaries AE8, AE10, and AE12 have the same radius of curvature. In addition, the radius of curvature of the arc boundary AE7 is greater than the radius of curvature of the arc boundary AE8, and the radius of curvature of the arc boundary AE9 is greater than the radius of curvature of the arc boundary AE7, but it is not limited to this. In addition, the radius of curvature of the arc boundary AE7 may be equal to the radius of curvature of the arc boundary AE1 of the above-mentioned first support opening SOP1, and the radius of curvature of the arc boundary AE8 may be equal to the radius of curvature of the arc boundary AE8 of the above-mentioned first support opening SOP1, but the present invention is not limited to this.

[0081] The boundaries of the first support opening SOP1 and the second support opening SOP2 are composed of a plurality of arc-shaped boundaries. According to the experiment of the applicant, the shape composed of arc-shaped boundaries has a more stable structure. Therefore, it is beneficial to improve the supporting effect of the capacitor structure. However, the present invention is not limited to this, and the shapes of the first support opening SOP1 and the second support opening SOP2 can be adjusted according to the needs.

[0082] In addition, if Figure 8 As shown, the first lower electrode BE1 has a first size (i.e., the diameter of the first lower electrode BE1), the second lower electrode BE2 has a second size W2, a third size W3, and a fourth size W4 in the first direction D1, the second direction D2, and the third direction D3, respectively, and the shortest distance between any two first lower electrodes BE1 is defined as a first spacing P, wherein at least one of the second size W2, the third size W3, and the fourth size W4 is not less than twice the sum of the first size W1 and the first spacing P, that is, taking the second size W2 as an example, the condition of W2 ≥ 2W1 + P is satisfied. The same is true for the remaining third sizes W3 and fourth sizes W4.

[0083] The other features of the first bottom electrode BE1, the second bottom electrode BE2, the first supporting opening SOP1 and the second supporting opening SOP2 can be referred to. Figure 8 It is worth noting that in other embodiments of the present invention, the size, shape, and arrangement of each element can be adjusted according to actual needs, and the present invention is not limited thereto.

[0084] Fig. 9 and Fig.10 Schematic diagrams of cross-sectional structures of semiconductor devices according to two other different embodiments of the present invention are respectively shown. Fig. 9 and Fig.10 With the above Figure 7 The semiconductor device of the first embodiment shown in the figure is compared to highlight the differences between the embodiments. To simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the same parts. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate the comparison between the embodiments. Fig. 9 and Fig.10 As shown, when forming the first bottom electrode BE1, the process parameters can be adjusted so that the first bottom electrode BE1 does not fill the first capacitor through hole OP1, thereby leaving a recess 210 in the first bottom electrode BE1. The recess 210 may be a gap, and when the capacitor dielectric layer 130 is subsequently formed, the capacitor dielectric layer 130 may fill the recess 210 to form a completely filled structure 211 (such as Fig. 9 ), or the capacitor dielectric layer 130 only partially fills the recess 210 to form a partially filled structure 212 (as shown in FIG. Fig.10 As shown), or the capacitor dielectric layer 130 is not filled into the recess 210, but covers the recess 210, so that the recess 210 is retained to form a pore (as shown in FIG. Fig. 9 As shown in FIG. 1 , it is understandable that, with the adjustment of the process parameters, the first bottom electrodes BE1 of different shapes may be combined with each other. Fig. 9 and Fig.10The above various variations are all within the scope of the present invention.

[0085] Based on the above instructions and diagrams, please refer to Figure 1-Figure 8 The present invention provides a semiconductor device, including a substrate 100, a plurality of first lower electrodes BE1 located on the substrate 100, the plurality of first lower electrodes BE1 are arranged in an array in a first direction D1, a second direction D2 and a third direction D3 that are not perpendicular to each other, and the outer contour of each first lower electrode BE1 is circular, a plurality of second lower electrodes BE2 are located on the substrate 100, and the outer contour of the second lower electrode BE2 includes a main body 142 and three protrusions 140, wherein the main body 142 is circular, and the three protrusions 142 are arc-shaped, extending outward from a center O of the main body 142 along a fourth direction D4, a fifth direction D5 and a sixth direction D6, respectively.

[0086] In some embodiments of the present invention, a plurality of second bottom electrodes BE2 are arranged in an array surrounding the first bottom electrodes.

[0087] Some embodiments of the present invention further include a capacitor dielectric layer 130 located on the first lower electrode BE1 and the second lower electrode BE2 , and an upper electrode layer TE located on the capacitor dielectric layer 130 .

[0088] In some embodiments of the present invention, an opening (ie, a second capacitor through hole OP2 ) is further included in each second bottom electrode BE2 , and the capacitor dielectric layer 130 and / or the top electrode layer TE are filled in the opening OP2 .

[0089] In some embodiments of the present invention, a recess 210 is further included in at least one first lower electrode BE1, and the recess 210 may include a void 210, a void partially filled with a capacitor dielectric layer (i.e., a partially filled structure 212), or a fully filled capacitor dielectric layer (i.e., a fully filled structure 211).

[0090] In some embodiments of the present invention, the first lower electrode BE1 has a first size W1, the second lower electrode BE2 has a second size W2, a third size W3 and a fourth size W4 in the first direction D1, the second direction D2 and the third direction D3, respectively, and the shortest distance between any two first lower electrodes BE1 is defined as a first spacing P, wherein at least one of the second size W2, the third size W3 and the fourth size W4 is not less than twice the sum of the first size W1 and the first spacing P.

[0091] In some embodiments of the present invention, a supporting layer (supporting stacking layer 110) is further included, surrounding the first lower electrode BE1 and the second lower electrode BE2, and the supporting layer 110 includes a first supporting opening SOP1 located between the plurality of first lower electrodes BE1, and a second supporting opening SOP2 located between the first lower electrode BE1 and the second lower electrode BE2.

[0092] In some embodiments of the present invention, the area of ​​the second supporting opening SOP2 is smaller than the area of ​​the first supporting opening SOP1.

[0093] In some embodiments of the present invention, the shape of the second supporting opening SOP2 is different from the shape of the first supporting opening SOP1.

[0094] In some embodiments of the present invention, the first supporting opening SOP1 is circular or polygonal, and the outer contour of the first supporting opening SOP1 extends through a plurality of adjacent first lower electrodes BE1 and partially exposes sidewalls of the adjacent first lower electrodes BE1.

[0095] In some embodiments of the present invention, the second supporting opening SOP2 is circular or polygonal, and the outer contour of the second supporting opening SOP2 extends through at least one first lower electrode BE1 and an adjacent second lower electrode BE2 and partially exposes the sidewalls of the first lower electrode BE1 and the second lower electrode BE2.

[0096] In some embodiments of the present invention, the second supporting opening SOP2 partially exposes the sidewall of the body 142 of the second lower electrode BE2 and the sidewall of the at least one protrusion 140 .

[0097] In some embodiments of the present invention, the outer contour of the second bottom electrode BE2 is composed of three first arcs with a first curvature radius and three second arcs with a second curvature radius alternately, wherein the first curvature radius is smaller than the second curvature radius.

[0098] Please refer to Figure 1-Figure 10 The present invention further provides a semiconductor device, including a substrate 100, a plurality of first lower electrodes BE1 and a second lower electrode BE2 located on the substrate 100, and the plurality of first lower electrodes BE1 are arranged adjacent to each other in an array, wherein from the cross-sectional view, each first lower electrode BE1 presents an I-shaped profile, and each second lower electrode BE2 presents a U-shaped profile.

[0099] In some embodiments of the present invention, from a cross-sectional view, the second bottom electrode BE2 is located at one side of the array formed by the first bottom electrodes BE1.

[0100] Some embodiments of the present invention further include a capacitor dielectric layer 130 located on the first lower electrode BE1 and the second lower electrode BE2 , and an upper electrode layer TE located on the capacitor dielectric layer 130 .

[0101] In some embodiments of the present invention, from the cross-sectional view, the second bottom electrode BE2 surrounds and forms an opening OP2, and the opening OP2 is filled with the capacitor dielectric layer 130 and / or the top electrode layer TE.

[0102] In some embodiments of the present invention, from a cross-sectional view, there is also a recess 210 located in at least one first lower electrode BE1, and the recess 210 may include a void 210, a void partially filled with a capacitor dielectric layer (i.e., a partially filled structure 212), or a completely filled capacitor dielectric layer (i.e., a completely filled structure 211).

[0103] In some embodiments of the present invention, from a cross-sectional view, the first bottom electrode BE1 is parallel to the first direction of the substrate ( Fig. 9 The second lower electrode BE2 has a first size W1 in the first direction, and the shortest distance between any two first lower electrodes BE1 in the first direction is defined as a first pitch P, wherein the second size W2 is not less than the sum of twice the first size W1 and the first pitch P.

[0104] In some embodiments of the present invention, a plurality of contact pads SNP are located on the substrate 100, and the contact pads SNP are located between the second bottom electrode BE2 and the substrate 100, wherein the second bottom electrode BE2 contacts the plurality of contact pads SNP (the second bottom electrode BE2 spans over at least two contact pads SNP).

[0105] according to Figures 1 to 7 The present invention provides a method for manufacturing a semiconductor device, comprising providing a substrate 100, forming a support stack layer 110 on the substrate 100, forming a mask layer (including a polysilicon layer 122, an oxide layer 124, a bottom anti-reflective coating 126 and a photoresist layer 128) on the support stack layer 110, and performing a first patterning step ( Figure 1 ), to form a plurality of first grooves R1 in the mask layer, and perform a second patterning step ( Figure 2 As shown), a plurality of second grooves R2 are formed in the mask layer, wherein each second groove R2 overlaps with a plurality of first grooves R1 from a top view, and the overlapping portion of each first groove R1 and each second groove R2 is defined as a plurality of third grooves R3, and an etching step is performed to form a plurality of first capacitor through holes OP1 and a plurality of second capacitor through holes OP2 in the support stack layer 110 using the patterned mask layer as a mask.

[0106] In some embodiments of the present invention, each first capacitor through hole OP1 corresponds to each first groove R1 , and each second capacitor through hole OP2 corresponds to each third groove R3 .

[0107] In some embodiments of the present invention, the subsequent process further includes filling a bottom electrode layer into each of the first capacitor through hole OP1 and the second capacitor through hole OP2 to form a first bottom electrode BE1 and a second bottom electrode BE2.

[0108] In some embodiments of the present invention, from the top view, each first capacitor through hole OP1 is circular, and each second capacitor through hole OP2 includes a main body 142 and three protrusions 140, wherein the main body 142 is circular, and the three protrusions 140 are arc-shaped, respectively distributed in the fourth direction D4, the fifth direction D5 and the sixth direction D6 that are not perpendicular to each other.

[0109] In some embodiments of the present invention, the area of ​​the second capacitor through hole OP2 is three times greater than the area of ​​the first capacitor through hole OP1.

[0110] In some embodiments of the present invention, when forming the first lower electrode BE1 and the second lower electrode BE2, a support opening is also formed in the support stack layer 110, including a first support opening SOP1 located between multiple first lower electrodes BE1, and a second support opening SOP2 located between a first lower electrode BE1 and a second lower electrode BE2, and the area of ​​the first support opening SOP1 is larger than the area of ​​the second support opening SOP2.

[0111] In some embodiments of the present invention, a plurality of contact pads SNP are formed on the substrate 100 , and each first capacitor through hole OP1 corresponds to one contact pad SNP, and each second capacitor through hole OP2 corresponds to a plurality of contact pads SNP.

[0112] The present invention is characterized in that, from the top view, the second capacitor through hole OP2 is located in the second area A2, the second lower electrode BE2 in the second capacitor through hole OP2 surrounds the periphery of the first lower electrode BE1 of the plurality of first capacitor through holes OP1, and the shape of the second lower electrode BE2 is different from that of the first lower electrode BE1. Since the second area A2 is adjacent to a blank area (i.e., the third area A3) where no components are formed in the manufacturing process, the component density difference between the two areas is large, and it is easy to be affected by the load effect, resulting in damage to the capacitor structure in the second area A2. In the second area A2, the present invention uses a method of overlapping the first groove R1 and the second groove R2 to produce a second capacitor through hole OP2 with a larger area and a special shape. Therefore, compared with the plurality of first capacitor through holes OP1 located in the first area A1, the second capacitor through hole OP2 has a larger coverage area, and the second capacitor through hole OP2 is composed of three first capacitor through holes OP1 and a central through hole, and its structure is stable and less susceptible to damage caused by the load effect. Therefore, the present invention helps to improve the quality of the capacitor structure located in the edge area.

[0113] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of first lower electrodes are located on the substrate, the plurality of first lower electrodes are arranged in an array in a first direction, a second direction and a third direction which are not perpendicular to each other, and the outer contour of each of the first lower electrodes is a circle; A plurality of second lower electrodes are located on the substrate, and the outer contour of the second lower electrodes includes a main body and three protrusions, wherein the main body is circular, and the three protrusions are arc-shaped, extending outward from the center of the main body along the fourth direction, the fifth direction and the sixth direction respectively.

2. The semiconductor device according to claim 1, wherein: The plurality of second lower electrodes are arranged around the first lower electrodes to form the array.

3. The semiconductor device according to claim 1, wherein: Also includes: A capacitor dielectric layer, located on the first lower electrode and the second lower electrode; The upper electrode layer is located on the capacitor dielectric layer.

4. The semiconductor device according to claim 3, characterized in that It also includes an opening located in each of the second lower electrodes, wherein the opening is filled with the capacitor dielectric layer and / or the upper electrode layer.

5. The semiconductor device according to claim 3, characterized in that It also includes a recess located in at least one of the first lower electrodes, and the recess may include a void, a void partially filled with the capacitor dielectric layer, or a void completely filled with the capacitor dielectric layer.

6. The semiconductor device according to claim 1, wherein: The first lower electrode has a first size, the second lower electrode has a second size, a third size and a fourth size in the first direction, the second direction and the third direction respectively, the shortest distance between any two of the first lower electrodes is defined as a first spacing, wherein at least one of the second size, the third size and the fourth size is not less than twice the sum of the first size and the first spacing.

7. The semiconductor device according to claim 1, wherein: Also includes: A support layer surrounds the first lower electrode and the second lower electrode, wherein the support layer includes a first support opening located between the plurality of first lower electrodes, and a second support opening located between the first lower electrode and the second lower electrode.

8. The semiconductor device according to claim 7, characterized in that The area of ​​the second supporting opening is smaller than the area of ​​the first supporting opening.

9. The semiconductor device according to claim 7, characterized in that The shape of the second supporting opening is different from the shape of the first supporting opening.

10. The semiconductor device according to claim 7, wherein: The first supporting opening is circular or polygonal, and an outer contour of the first supporting opening extends through a plurality of adjacent first lower electrodes and partially exposes side walls of the adjacent first lower electrodes.

11. The semiconductor device according to claim 7, wherein: The second supporting opening is circular or polygonal, and an outer contour of the second supporting opening extends through at least one of the first lower electrodes and an adjacent second lower electrode, and partially exposes side walls of the first lower electrode and the second lower electrode.

12. The semiconductor device according to claim 11, characterized in that The second supporting opening portion exposes a sidewall of the body of the second lower electrode and a sidewall of at least one of the protrusions.

13. The semiconductor device according to claim 1, wherein: The outer contour of the second lower electrode is composed of three first arcs with a first curvature radius and three second arcs with a second curvature radius alternately, wherein the first curvature radius is smaller than the second curvature radius.

14. A semiconductor device, characterized in that: include: substrate; A plurality of first lower electrodes and a second lower electrode are located on the substrate, and the plurality of first lower electrodes are arranged adjacent to each other in an array, wherein from a cross-sectional view, each of the first lower electrodes has an I-shaped profile, and each of the second lower electrodes has a U-shaped profile.

15. The semiconductor device according to claim 14, characterized in that From the cross-sectional view, the second lower electrode is located on one side of the array formed by the first lower electrodes.

16. The semiconductor device according to claim 14, characterized in that Also includes: A capacitor dielectric layer, located on the first lower electrode and the second lower electrode; The upper electrode layer is located on the capacitor dielectric layer.

17. The semiconductor device according to claim 16, characterized in that From the cross-sectional view, the second lower electrode is surrounded to form an opening, and the capacitor dielectric layer and / or the upper electrode layer are filled in the opening.

18. The semiconductor device according to claim 16, wherein: From the cross-sectional view, it also includes a recess located in at least one of the first lower electrodes, and the recess may include a void, a void partially filled with the capacitor dielectric layer, or a fully filled capacitor dielectric layer.

19. The semiconductor device according to claim 14, characterized in that From the cross-sectional view, the first lower electrode has a first size in a first direction parallel to the substrate, the second lower electrode has a second size in the first direction, and the shortest distance between any two of the first lower electrodes in the first direction is defined as a first spacing, wherein the second size is not less than the sum of twice the first size and the first spacing.

20. The semiconductor device according to claim 14, wherein: A plurality of contact pads are included and located on the substrate. The contact pads are located between the second lower electrode and the substrate, wherein the second lower electrode contacts the plurality of contact pads.

21. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a supporting stack layer on the substrate; forming a mask layer on the supporting stack layer; performing a first patterning step to form a plurality of first grooves in the mask layer; Performing a second patterning step to form a plurality of second grooves in the mask layer, wherein each of the second grooves overlaps with a plurality of the first grooves from a top view, and overlapping portions of each of the first grooves and each of the second grooves are defined as a plurality of third grooves; An etching step is performed to form a plurality of first capacitor through holes and a plurality of second capacitor through holes in the support stack layer using the patterned mask layer as a mask.

22. The method for manufacturing a semiconductor device according to claim 21, characterized in that: Each of the first capacitor through holes corresponds to each of the first grooves, and each of the second capacitor through holes corresponds to each of the third grooves.

23. The method for manufacturing a semiconductor device according to claim 21, characterized in that: The method further includes filling a bottom electrode layer into each of the first capacitor through hole and the second capacitor through hole to form a first bottom electrode and a second bottom electrode.

24. The method for manufacturing a semiconductor device according to claim 21, characterized in that: From the top view, each of the first capacitor through holes is circular, and each of the second capacitor through holes includes a main body and three protrusions, wherein the main body is circular, and the three protrusions are arc-shaped, respectively distributed in the fourth direction, the fifth direction and the sixth direction that are not perpendicular to each other.

25. The method for manufacturing a semiconductor device according to claim 21, characterized in that: An area of ​​the second capacitor through hole is three times greater than an area of ​​the first capacitor through hole.

26. The method for manufacturing a semiconductor device according to claim 23, characterized in that: In the forming of the first lower electrode and the second lower electrode, the method further includes: Support openings are formed in the support stack layer, including first support openings located between the plurality of first lower electrodes, and second support openings located between a first lower electrode and a second lower electrode, wherein an area of ​​the first support opening is greater than an area of ​​the second support opening.

27. The method for manufacturing a semiconductor device according to claim 21, wherein: The method further includes forming a plurality of contact pads on the substrate, wherein each of the first capacitor through holes corresponds to one of the contact pads, and each of the second capacitor through holes corresponds to a plurality of the contact pads.

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