Semiconductor structure and manufacturing method
By forming a cover layer and a patterned protective layer on the surface of the active region during semiconductor manufacturing, the erosion problem caused by wet cleaning is solved, and the protection of the active region and the stability of the equipment are improved.
Patent Information
- Application Number
- CN202411390018.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-01-07
AI Technical Summary
During the semiconductor manufacturing process, the active region during the low-doping drain and high-doping process is eroded due to the consumption of the oxide layer by weak alkaline substances in the wet cleaning solution, resulting in high unevenness and affecting the stability of the equipment.
A cover layer is generated on the surface of the semiconductor substrate, and a patterned protective layer is formed on the surface of the cover layer. Doping processes are performed in different regions respectively to protect the active region by removing the protective layer to avoid erosion by the wet cleaning solution.
Effectively protect the surface of the active area from erosion, maintain high uniformity, improve equipment stability and device yield, and extend service life.
Smart Images
Figure CN119277813A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a manufacturing method. Background Art
[0002] In the manufacture of the active area, when manufacturing the gate structure, it is necessary to first perform a low-doped drain (Lightly Doped Drain, LDD) process on the transistor used to make a low-voltage withstand capability, and then perform a high-doped (High Doped, HD) process on the transistor used to make a high-voltage withstand capability. The low-doped drain process and the high-doped process also include a photolithography process and an ion implantation process, and both require wet cleaning, so the active area will undergo multiple wet cleanings. However, the wet cleaning solution is mixed with weak alkaline substances (such as ammonium hydroxide, with a chemical formula of NH4OH), which will consume the oxide layer exposed above the active area. When the oxide layer is completely consumed, the active area will be exposed and naturally oxidized, and will be consumed by the next wet cleaning, so that the surface of the active area is continuously eroded. This results in a difference in the height of the active area below the polysilicon and the surrounding area, affecting the stability of the device.
[0003] How to provide a method for manufacturing an active region that can protect the active region from being corroded during the doping process is an issue that needs to be solved urgently. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a semiconductor structure and a manufacturing method, which can protect the active area from being corroded during the doping process.
[0005] In order to solve the above problems, the present invention provides an active area manufacturing method, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region, the first region being used to manufacture a transistor with a first voltage resistance, the second region being used to manufacture a transistor with a second voltage resistance, a first gate electrode being formed on the surface of the first region, and a first gate oxide layer being provided at the bottom of the first gate electrode, a second gate electrode being formed on the surface of the second region, and a second gate oxide layer being provided at the bottom of the second gate electrode; generating a covering layer on the surface of the semiconductor substrate; forming a first patterned protective layer on the surface of the covering layer, and performing a first doping process on an exposed region of the first patterned protective layer; removing the first patterned protective layer and retaining the covering layer; forming a second patterned protective layer on the surface of the covering layer, and performing a second doping process on an exposed region of the second patterned protective layer, wherein the exposed region of the first patterned protective layer is located in the first region and the exposed region of the second patterned protective layer is located in the second region, or the exposed region of the first patterned protective layer is located in the second region and the exposed region of the second patterned protective layer is located in the first region; removing the second patterned protective layer.
[0006] In some embodiments, a first gate oxide material layer is formed on the surface of the first region and a second gate oxide material layer is formed on the surface of the second region. Before the step of generating a covering layer on the surface of the semiconductor substrate, the step further includes: removing the first gate oxide material layer and the second gate oxide material layer exposed on the surface of the semiconductor substrate, and the first gate oxide material layer remaining at the bottom of the first gate electrode forms the first gate oxide layer, and the second gate oxide material layer remaining at the bottom of the second gate electrode forms the second gate oxide layer.
[0007] In some embodiments, wet etching is used to remove the first gate oxide material layer and the second gate oxide material layer exposed on the surface of the semiconductor substrate.
[0008] In some embodiments, the material of the first gate electrode and the second gate electrode is polysilicon.
[0009] In some embodiments, the material of the capping layer is silicon oxide.
[0010] In some embodiments, chemical vapor deposition is used to form a capping layer on the surface of the semiconductor substrate.
[0011] In some embodiments, the area exposed by the first patterned protective layer is the area on both sides of the first gate electrode in the first region, and the area exposed by the second patterned protective layer is the area on both sides of the second gate electrode in the second region; or, the area exposed by the first patterned protective layer is the area on both sides of the second gate electrode in the second region, and the area exposed by the second patterned protective layer is the area on both sides of the first gate electrode in the first region.
[0012] In some embodiments, the material of the first patterned protection layer and the second patterned protection layer is photoresist.
[0013] In some embodiments, a wet cleaning process is used to remove the first patterned protection layer and the second patterned protection layer respectively.
[0014] In some embodiments, the step of removing the second patterned protective layer also includes: removing the covering layer to expose the surface of the semiconductor substrate, the first gate structure and the second gate structure, the first gate structure including the first gate electrode and the first gate oxide layer at the bottom thereof, and the second gate structure including the second gate electrode and the second gate oxide layer at the bottom thereof.
[0015] In some embodiments, after the step of removing the second patterned protection layer, the step further includes: forming sidewalls on the sides of the first gate structure and the second gate structure.
[0016] In some embodiments, the material of the sidewall spacer is silicon oxide or silicon nitride.
[0017] In some embodiments, the first doping process is a lightly doped drain process, and the second doping process is a heavily doped process.
[0018] In some embodiments, the lightly doped drain process and the high doping process further include a photolithography process and an ionized metal plasma process.
[0019] In order to solve the above problem, the present invention further provides a semiconductor structure, and the semiconductor structure is manufactured by using the semiconductor structure manufacturing method.
[0020] The above technical scheme generates a covering layer on the surface of a semiconductor substrate including a first region for making a transistor with a first voltage resistance and a second region for making a transistor with a second voltage resistance; forms a first patterned protection layer on the surface of the covering layer, and performs a first doping process on the exposed region of the first patterned protection layer; removes the first patterned protection layer and retains the covering layer; forms a second patterned protection layer on the surface of the covering layer, and performs a second doping process on the exposed region of the second patterned protection layer; removes the second patterned protection layer to protect the surface of the active area from being exposed to the air and corroded during the ionized metal plasma doping and cleaning process, thereby effectively protecting the uniformity of the overall height of the active area, improving the stability of the equipment, increasing the device yield and reliability, and extending the service life.
[0021] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0023] Figure 1 is a flow chart of a semiconductor structure manufacturing method provided by one embodiment of the present invention;
[0024] Figure 2 is a schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention;
[0025] Figure 3 It is a schematic diagram of a device structure formed by the step of removing an oxide layer exposed on the surface of a semiconductor substrate provided by an embodiment of the present invention;
[0026] Figure 4 is a schematic diagram of a device structure formed by the step of generating a covering layer provided in one embodiment of the present invention;
[0027] Figure 5 It is a schematic diagram of a device structure formed by performing a first doping process on an exposed area of a first patterned protective layer provided by an embodiment of the present invention;
[0028] Figure 6is a schematic diagram of a device structure formed by the step of removing the first patterned protective layer provided in one embodiment of the present invention;
[0029] Figure 7 It is a schematic diagram of a device structure formed by performing a second doping process on an exposed area of a second patterned protective layer provided by an embodiment of the present invention;
[0030] Figure 8 is a schematic diagram of a device structure formed by the step of removing the second patterned protective layer provided in one embodiment of the present invention;
[0031] Fig. 9 It is a schematic diagram of a device structure formed by the step of forming sidewalls on the sides of the first gate structure and the second gate structure provided in one embodiment of the present invention. DETAILED DESCRIPTION
[0032] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0033] Please refer to Figures 1 to 9 ,in, Figure 1 is a flow chart of a semiconductor structure manufacturing method provided by one embodiment of the present invention; Figure 2 is a schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention;
[0034] Figure 3 It is a schematic diagram of a device structure formed by the step of removing an oxide layer exposed on the surface of a semiconductor substrate provided by an embodiment of the present invention; Figure 4 is a schematic diagram of a device structure formed by the step of generating a covering layer provided in one embodiment of the present invention; Figure 5 It is a schematic diagram of a device structure formed by performing a first doping process on an exposed area of a first patterned protective layer provided by an embodiment of the present invention; Figure 6 is a schematic diagram of a device structure formed by the step of removing the first patterned protective layer provided in one embodiment of the present invention; Figure 7 It is a schematic diagram of a device structure formed by performing a second doping process on an exposed area of a second patterned protective layer provided by an embodiment of the present invention; Figure 8 is a schematic diagram of a device structure formed by the step of removing the second patterned protective layer provided in one embodiment of the present invention; Fig. 9 It is a schematic diagram of a device structure formed by the step of forming sidewalls on the sides of the first gate structure and the second gate structure provided in one embodiment of the present invention.
[0035] like Figure 1 As shown, the semiconductor structure manufacturing method includes: step S11, providing a semiconductor substrate, the semiconductor substrate includes a first area and a second area, the first area is used to make a transistor with a first voltage resistance, the second area is used to make a transistor with a second voltage resistance, a first gate electrode is formed on the surface of the first area, and a first gate oxide layer is formed at the bottom of the first gate electrode, and a second gate electrode is formed on the surface of the second area, and a second gate oxide layer is formed at the bottom of the second gate electrode; step S12, generating a covering layer on the surface of the semiconductor substrate; step S13, forming a first graphic protection layer on the surface of the covering layer, and performing a first doping process on the exposed area of the first graphic protection layer; step S14, removing the first graphic protection layer, retaining the covering layer, the exposed area of the first graphic protection layer is located in the first area, the exposed area of the second graphic protection layer is located in the second area, or the exposed area of the first graphic protection layer is located in the second area, and the exposed area of the second graphic protection layer is located in the first area; step S15, forming a second graphic protection layer on the surface of the covering layer, and performing a second doping process on the exposed area of the second graphic protection layer; step S16, removing the second graphic protection layer.
[0036] Refer to step S11 and Figure 3 , a semiconductor substrate 11 is provided, the semiconductor substrate 11 includes a first region 111 and a second region 112, the first region 111 is used to make a transistor with a first withstand voltage capability, the second region 112 is used to make a transistor with a second withstand voltage capability, a first gate electrode 13 is formed on the surface of the first region 111, and a first gate oxide layer 12 is formed at the bottom of the first gate electrode 13, a second gate electrode 15 is formed on the surface of the second region 112, and a second gate oxide layer 14 is formed at the bottom of the second gate electrode 15. In this embodiment, the first withstand voltage capability is 5V, and the second withstand voltage capability is 1.5V; the materials of the first gate oxide layer 12 and the second gate oxide layer 14 are both silicon oxide (SiO2); the materials of the first gate electrode 13 and the second gate electrode 15 are polycrystalline silicon. The semiconductor substrate 11 also includes a shallow trench isolation 110 (STI for short). The shallow trench isolation 110 is filled with silicon oxide and is used for isolation of active devices.
[0037] refer to Figure 2 In this embodiment, when forming Figure 3Before the device structure of the semiconductor substrate shown in the figure is formed, a first gate oxide material layer 120 is formed on the surface of the first region 111, and a second gate oxide material layer 140 is formed on the surface of the second region 112, and the materials of the first gate oxide material layer 120 and the second gate oxide material layer 140 are both silicon oxide. Accordingly, before executing the next step, it also includes: removing the first gate oxide material layer 120 and the second gate oxide material layer 140 exposed on the surface of the semiconductor substrate 11, and the first gate oxide material layer 120 remaining at the bottom of the first gate electrode 13 forms the first gate oxide layer 12, and the second gate oxide material layer 140 remaining at the bottom of the second gate electrode 15 forms the second gate oxide layer 14. Then, the structure shown in FIG. 1 is formed. Figure 3 The device structure of the semiconductor substrate is shown.
[0038] In this embodiment, wet etching is used to remove Figure 2 The first gate oxide material layer 120 and the second gate oxide material layer 140 are exposed on the surface of the semiconductor substrate 11 shown in FIG.
[0039] Refer to step S12 and Figure 4 , a capping layer 16 is generated on the surface of the semiconductor substrate 11. Figure 4 As shown, the covering layer 16 is a complete and continuous thin film layer, and the covering layer 16 covers the exposed area of the surface of the semiconductor substrate 11 , the surface of the first gate electrode 13 , and the surface of the second gate electrode 15 .
[0040] Before performing this step, the first gate oxide material layer 120 and the second gate oxide material layer 140 exposed on the surface of the semiconductor substrate 11 have been removed, so that the newly generated cover layer 16 completely and evenly covers the surface of the active area.
[0041] In this embodiment, the material of the cover layer 16 is silicon oxide, which can be formed on the surface of the semiconductor substrate 11 by chemical vapor deposition.
[0042] During the doping process, the active area will undergo multiple wet cleanings. However, the weakly alkaline substances mixed in the wet cleaning solution will consume the oxide layer exposed above the active area, and the thickness of the oxide layer in the active area itself is not enough to protect the active area. When the oxide layer is completely consumed, the active area will be exposed and naturally oxidized, and will be consumed by the next wet cleaning, causing the surface of the active area to be continuously eroded. This step regenerates an oxide layer that meets the thickness requirements on the surface of the semiconductor substrate 11, thereby protecting the active area during the doping process.
[0043] Refer to step S13 and Figure 5A first patterned protective layer 17 is formed on the surface of the cover layer 16, and a first doping process is performed on the exposed area of the first patterned protective layer 17. The first doping process includes a photolithography process, the material of the first patterned protective layer 17 is photoresist, and the first patterned protective layer 17 is obtained by photolithography by imprinting a silicon wafer.
[0044] In this embodiment, the exposed area of the first patterned protection layer 17 is located in the second area 112. Figure 5 As shown, the area exposed by the first patterned protection layer 17 is the area on both sides of the second gate electrode 15 in the second area 112, and the area covered by the first patterned protection layer 17 is the protected area. The withstand voltage of the second gate electrode 15 is 1.5V, and the first doping process is performed on the areas on both sides of the second gate electrode 15.
[0045] In another embodiment, the exposed area of the first patterned protective layer 17 is located in the first area 111, and the exposed area of the first patterned protective layer 17 is the area on both sides of the first gate electrode 13 in the first area 111, that is, the first doping process is first performed on the area on both sides of the first gate electrode 13.
[0046] In this embodiment, the first doping process is a lightly doped drain (LDD) process.
[0047] The lightly doped drain process includes an ionized metal plasma (IMP) process. Through plasma injection, the lightly doped drain process can generate a lightly doped region in the exposed area of the first patterned protective layer 17. The lightly doped region reduces the peak electric field intensity near the drain and weakens the hot carrier effect. When making an N-type transistor, N-type doping is required to increase the number of negatively charged free electrons and perform an N-LDD process. When making a P-type transistor, P-type doping is required to increase the number of positively charged holes and perform a P-LDD process.
[0048] Referring to step S14, the first patterned protection layer 17 is removed, and the cover layer 16 is retained. A photoresist stripping (PR Strip) process is used to remove the first patterned protection layer 17. In this embodiment, a wet cleaning process is used to remove the first patterned protection layer 17.
[0049] The schematic diagram of the device structure after removing the first patterned protective layer 17 is as follows: Figure 6 As shown, Figure 6 The semiconductor structure and Figure 4Similar to the semiconductor structure in FIG. 1 , the surface of the semiconductor substrate 11, the surface of the first gate electrode 13 and the surface of the second gate electrode 15 retain the cover layer 16. In this embodiment, the ionized metal plasma process and the photoresist removal process in the first doping process will consume part of the cover layer 16. Figure 6 and Figure 5 , Figure 6 The thickness of the covering layer 16 is significantly thinned, but the covering layer 16 can still completely cover the surface of the semiconductor substrate 11, the surface of the first gate electrode 13 and the surface of the second gate electrode 15, thereby protecting the surface of the semiconductor substrate 11, the surface of the first gate electrode 13 and the surface of the second gate electrode 15.
[0050] Refer to step S15 and Figure 7 , forming a second patterned protection layer 18 on the surface of the cover layer 16 , and performing a second doping process on the exposed area of the second patterned protection layer 18 .
[0051] The second doping process includes a photolithography process, and the material of the second patterned protective layer 18 is photoresist. The second patterned protective layer 18 is obtained by photolithography by imprinting a silicon wafer. In this embodiment, the exposed area of the second patterned protective layer 18 is located in the first area 111, and the exposed area of the second patterned protective layer 18 is the area on both sides of the first gate electrode 13 in the second area 111, and the area covered by the second patterned protective layer 18 is the protected area. The withstand voltage of the first gate electrode 13 is 5V, and the second doping process is performed in the area on both sides of the first gate electrode 13.
[0052] In another embodiment, the exposed area of the second patterned protective layer 18 is located in the second area 112, and the exposed area of the second patterned protective layer 18 is the area on both sides of the second gate electrode 15 in the second area 112, that is, the second doping process is performed on the area on both sides of the second gate electrode 15.
[0053] In this embodiment, the second doping process is a high doping (HD) process.
[0054] The high doping process includes an ionized metal plasma process, and through plasma injection, the high doping process can generate a high doping area in the exposed area of the second patterned protective layer 18. When making an N-type transistor, N-type doping is required to increase the number of negatively charged free electrons, and an N-HD process is performed; when making a P-type transistor, P-type doping is required to increase the number of positively charged holes, and a P-HD process is performed.
[0055] Refer to step S16 and Figure 8 , remove the second patterned protection layer 18. Use a photoresist stripping (PR Strip) process to remove the second patterned protection layer 18. In this embodiment, use a wet cleaning process to remove the second patterned protection layer 18.
[0056] like Figure 8 As shown, after removing the second patterned protection layer 18, the surface of the semiconductor substrate 11, the surface of the first gate structure and the surface of the second gate structure are still covered with the remaining covering layer 16, the first gate structure includes the first gate electrode 13 and the first gate oxide layer 12 at the bottom thereof, and the second gate structure includes the second gate electrode 15 and the second gate oxide layer 14 at the bottom thereof. In this embodiment, the remaining covering layer 16 cannot completely cover the surface of the semiconductor substrate 11, the surface of the first gate structure and the surface of the second gate structure. In some embodiments, the remaining covering layer 16 can still completely cover the surface of the semiconductor substrate 11, the surface of the first gate structure and the surface of the second gate structure, but the thickness of the covering layer 16 becomes thinner.
[0057] Accordingly, this step also includes removing the capping layer 16 to expose the surface of the semiconductor substrate 11, the first gate structure and the second gate structure, wherein the first gate structure includes the first gate electrode 13 and the first gate oxide layer 12 at the bottom thereof, and the second gate structure includes the second gate electrode 15 and the second gate oxide layer 14 at the bottom thereof, so that the device structure after the doping process is completed returns to Figure 3 In this embodiment, wet etching is used to remove the remaining cover layer 16 .
[0058] In this embodiment, two doping processes are performed when the semiconductor structure is manufactured using the semiconductor structure manufacturing method. In some embodiments, more than two doping processes may be performed when the semiconductor structure is manufactured using the semiconductor structure manufacturing method. After the last doping process is completed, the covering layer 16 is removed.
[0059] In this embodiment, reference Fig. 9 After executing step S16, the step further includes: forming a sidewall 19 on the side of the first gate structure and the second gate structure. That is, after the doping is completed and the cover layer 16 is removed, Figure 3 Based on the device structure shown, a sidewall spacer 19 is formed on the side of the first gate structure and the second gate structure. The first gate structure includes the first gate electrode 13 and the first gate oxide layer 12, and the second gate structure includes the second gate electrode 15 and the second gate oxide layer 14. The material of the sidewall spacer 19 is silicon oxide or silicon nitride.
[0060] Based on the same inventive concept, the present invention also provides a semiconductor structure.
[0061] refer to Figure 3 to Figure 8 , the semiconductor structure is manufactured by a semiconductor structure manufacturing method, and the manufacturing process has the technical characteristics of the semiconductor structure manufacturing method. Specifically comprising: step S11, providing a semiconductor substrate 11, the semiconductor substrate 11 includes a first region 111 and a second region 112, the first region 111 is used to make a transistor with a first voltage resistance, the second region 112 is used to make a transistor with a second voltage resistance, a first gate electrode 13 is formed on the surface of the first region 111, the first gate electrode 13 has a first gate oxide layer 12 at the bottom, a second gate electrode 15 is formed on the surface of the second region 112, and the second gate electrode 15 has a second gate oxide layer 14 at the bottom; step S12, generating a covering layer 16 on the surface of the semiconductor substrate 11; referring to step S13, forming a first patterned protective layer 17 on the surface of the covering layer 16, and forming a first patterned protective layer 17 on the surface of the first patterned protective layer 17; Step S14, removing the first patterned protective layer 17 and retaining the covering layer; Step S15, forming a second patterned protective layer 18 on the surface of the covering layer 16, and performing a second doping process on the exposed area of the second patterned protective layer 18, the exposed area of the first patterned protective layer 17 is located in the first area 111, and the exposed area of the second patterned protective layer 18 is located in the second area 112, or the exposed area of the first patterned protective layer 17 is located in the second area 112, and the exposed area of the second patterned protective layer 18 is located in the first area 111; Step S16, removing the second patterned protective layer 18.
[0062] In this embodiment, the exposed area of the first patterned protective layer 17 is located in the second area 112, and the exposed area of the first patterned protective layer 17 is the area on both sides of the second gate electrode 15 in the second area 112; the exposed area of the second patterned protective layer 18 is the area on both sides of the first gate electrode 13 in the second area 111.
[0063] refer to Figure 2 In this embodiment, when forming Figure 3Before the device structure of the semiconductor substrate shown, a first gate oxide material layer 120 is formed on the surface of the first region 111, and a second gate oxide material layer 140 is formed on the surface of the second region 112, and the materials of the first gate oxide material layer 120 and the second gate oxide material layer 140 are both silicon oxide. Accordingly, before executing the next step, this step also includes: removing the first gate oxide material layer 120 and the second gate oxide material layer 140 exposed on the surface of the semiconductor substrate 11, and the first gate oxide material layer 120 remaining at the bottom of the first gate electrode 13 forms the first gate oxide layer 12, and the second gate oxide material layer 140 remaining at the bottom of the second gate electrode 15 forms the second gate oxide layer 14.
[0064] The above technical scheme generates a covering layer on the surface of a semiconductor substrate including a first region for making a transistor with a first voltage resistance and a second region for making a transistor with a second voltage resistance; forms a first patterned protection layer on the surface of the covering layer, and performs a first doping process on the exposed region of the first patterned protection layer; removes the first patterned protection layer and retains the covering layer; forms a second patterned protection layer on the surface of the covering layer, and performs a second doping process on the exposed region of the second patterned protection layer; removes the second patterned protection layer to protect the surface of the active area from being exposed to the air and corroded during the ionized metal plasma doping and cleaning process, thereby effectively protecting the uniformity of the overall height of the active area, improving the stability of the equipment, increasing the device yield and reliability, and extending the service life.
[0065] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion. The various embodiments in this specification are described in a related manner, and the same and similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.
[0066] The above is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: A semiconductor substrate is provided, the semiconductor substrate comprising a first region and a second region, the first region is used to manufacture a transistor with a first withstand voltage capability, the second region is used to manufacture a transistor with a second withstand voltage capability, a first gate electrode is formed on the surface of the first region, a first gate oxide layer is formed at the bottom of the first gate electrode, a second gate electrode is formed on the surface of the second region, a second gate oxide layer is formed at the bottom of the second gate electrode; generating a capping layer on the surface of the semiconductor substrate; forming a first patterned protective layer on the surface of the cover layer, and performing a first doping process on an exposed area of the first patterned protective layer; removing the first patterned protective layer and retaining the covering layer; forming a second patterned protective layer on the surface of the cover layer, and performing a second doping process on an exposed area of the second patterned protective layer, wherein the exposed area of the first patterned protective layer is located in the first area, and the exposed area of the second patterned protective layer is located in the second area, or the exposed area of the first patterned protective layer is located in the second area, and the exposed area of the second patterned protective layer is located in the first area; The second patterned protection layer is removed.
2. The method according to claim 1, characterized in that A first gate oxide material layer is formed on the surface of the first region and a second gate oxide material layer is formed on the surface of the second region. Before the step of generating a covering layer on the surface of the semiconductor substrate, the step further includes: removing the first gate oxide material layer and the second gate oxide material layer exposed on the surface of the semiconductor substrate, the first gate oxide material layer remaining at the bottom of the first gate electrode forms the first gate oxide layer, and the second gate oxide material layer remaining at the bottom of the second gate electrode forms the second gate oxide layer.
3. The method according to claim 2, characterized in that The first gate oxide material layer and the second gate oxide material layer exposed on the surface of the semiconductor substrate are removed by wet etching.
4. The method according to claim 1, characterized in that: The material of the first gate electrode and the second gate electrode is polysilicon.
5. The method according to claim 1, characterized in that The material of the cover layer is silicon oxide.
6. The method according to claim 1, characterized in that A covering layer is formed on the surface of the semiconductor substrate by chemical vapor deposition.
7. The method according to claim 1, characterized in that The area exposed by the first patterned protection layer is the area on both sides of the first gate electrode in the first region, and the area exposed by the second patterned protection layer is the area on both sides of the second gate electrode in the second region; or, The areas exposed by the first patterned protection layer are areas on both sides of the second gate electrode in the second region, and the areas exposed by the second patterned protection layer are areas on both sides of the first gate electrode in the first region.
8. The method according to claim 1, characterized in that The material of the first patterned protection layer and the second patterned protection layer is photoresist.
9. The method according to claim 8, characterized in that The first patterned protective layer and the second patterned protective layer are removed respectively by a wet cleaning process.
10. The method according to claim 1, characterized in that The step of removing the second patterned protection layer also includes: removing the covering layer to expose the surface of the semiconductor substrate, the first gate structure and the second gate structure, the first gate structure includes the first gate electrode and the first gate oxide layer at the bottom thereof, and the second gate structure includes the second gate electrode and the second gate oxide layer at the bottom thereof.
11. The method according to claim 10, characterized in that After the step of removing the second patterned protection layer, the method further includes: forming sidewalls on the sides of the first gate structure and the second gate structure.
12. The method according to claim 11, characterized in that The material of the sidewall spacer is silicon oxide or silicon nitride.
13. The method according to claim 1, characterized in that The first doping process is a lightly doped drain process, and the second doping process is a heavily doped process.
14. The method according to claim 13, characterized in that The lightly doped drain process and the high doping process also include a photolithography process and an ionized metal plasma process.
15. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the semiconductor structure manufacturing method according to any one of claims 1 to 14.