Monolithic integrated CMOS circuit based on GaN-based epitaxial structure

Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to a monolithic integrated CMOS circuit based on a GaN-based epitaxial structure. According to the circuit, a traditional AlGaN barrier layer with a fixed Al component is replaced by an AlGaN barrier layer formed by regularly stacking AlGaN with a high Al component and (2n-1) layers with different Al components, the Al component of the n AlGaN layer in the middle is the highest value, and the sizes of the Al components of the AlGaN layers from the first layer to the (n-1) layer are regulated and controlled through the difference of the Al components, so that the AlGaN barrier layer with the high Al component is formed. The whole 2DEG concentration suppression between the n AlGaN barrier layer to the (2n-1) AlGaN barrier layer and the GaN channel layer can be realized, so that the enhanced n-FETs with high threshold voltage is realized. For p-FETs under the same epitaxial structure, the overall increase of the Al component of the multi-AlGaN barrier layer is beneficial for improving the concentration of the heterojunction interface 2DHG of the multi-AlGaN barrier layer and the GaN channel layer above the multi-AlGaN barrier layer, so that the enhanced p-FETs with high conduction current density is realized, and the development of a full GaN monolithic power integrated circuit (IC) based on a complementary metal oxide semiconductor (CMOS) is promoted.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a monolithic integrated CMOS circuit based on a GaN-based epitaxial structure. Background Art

[0002] Compared with traditional Si-based devices, GaN power devices have significant advantages in electron saturation velocity, bandgap width, and critical breakdown electric field. For example, the high concentration and high mobility 2DEG at the AlGaN / GaN heterojunction has become a unique feature of GaN power devices. Monolithic integration based on on-chip GaN CMOS not only simplifies circuit design, but also reduces the influence of parasitic inductance, and realizes the most energy-saving and efficient integrated topology with low static power consumption and strong anti-noise capability for the entire power switch system. GaN-based P-channel field effect transistors (FETs) provide the possibility of on-chip CMOS. However, due to the low hole mobility of GaN at room temperature and the difficulty in significantly improving it, and the high ohmic contact resistivity of the device drain and source, the on-current density of GaN p-FETs is much lower than that of the corresponding n-FETs, which is the main obstacle to the current realization of CMOS monolithic integration. At present, in the commonly used commercial enhancement mode p-GaN gate HEMTs power integration epitaxial structure, although the AlGaN barrier layer with high Al content has advantages such as larger bandgap width, larger critical electric field, better thermal conductivity and polarization discontinuity, which can induce higher 2DEG and 2DHG concentrations, the Al content difference of the heterojunction is too high, and the serious thermal and lattice mismatch will cause a large number of defects at the heterojunction interface, deteriorate the interface roughness, and thus reduce the overall device performance and reliability. At the same time, the high concentration of 2DEG p-GaN is difficult to deplete, which leads to the degradation of the HEMTs threshold voltage.

[0003] Therefore, how to realize the advantages of high Al content AlGaN barrier layers and avoid the degradation of device performance caused by high Al content AlGaN barrier layers is one of the key issues in breaking through the bottleneck faced by CMOS-based all-GaN monolithic power integrated epitaxial structure. Summary of the invention

[0004] In view of the above problems, in order to realize GaN monolithic integrated CMOS devices with a high Al content AlGaN barrier layer, avoid the degradation of multi-channel heterojunction interface quality and n-FETs threshold voltage, and at the same time improve the conduction characteristics of p- / n-FETs, and improve the output power and breakdown characteristics of power devices, the present invention proposes a GaN-based epitaxial structure and a monolithic integrated CMOS circuit.

[0005] The technical solution adopted by the present invention is:

[0006] A monolithic integrated CMOS circuit based on a GaN-based epitaxial structure, characterized in that it includes p-FETs and n-FETs, the common structure of the p-FETs and the n-FETs is a substrate 01, a group III nitride buffer layer 02, a GaN channel layer 03 and an AlGaN barrier layer stacked in sequence along a vertical direction, and the AlGaN barrier layer of the p-FETs and the AlGaN barrier layer of the n-FETs are isolated from each other;

[0007] The AlGaN barrier layer of the p-FETs includes 2n-1 AlGaN layers, n≥1, the topmost layer is defined as the first AlGaN layer, the middle layer is the nth layer, and the bottom layer is the 2n-1 layer, that is, the 2n-1 AlGaN layer is in contact with the GaN channel layer 03; a GaN channel layer 05 is provided on the upper surface of the first AlGaN layer, and a P-type heavily doped GaN layer 06 is provided on the upper surface of the GaN channel layer 05; both ends of the upper surface of the P-type heavily doped GaN layer 06 respectively have a p-FETs source ohmic metal 07 and p-FETs drain ohmic metal 08, wherein the p-FETs drain ohmic metal 08 is located on the side close to the n-FETs; a trench gate structure is provided between the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 8, the trench gate structure comprises a gate dielectric 13 and a first gate metal 09, the gate dielectric 13 is located in a groove formed on the upper surface of the P-type heavily doped GaN layer 06, wraps the lower part of the first gate metal 09 and contacts the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08 on both sides respectively;

[0008] The AlGaN barrier layer structure of the n-FETs is the same as that of the p-FETs, and the AlGaN barrier layer also has a GaN channel layer 05 and a P-type heavily doped GaN layer 06 in sequence, the difference being that both sides of the AlGaN layer above the nth layer in the AlGaN barrier layer of the n-FETs are completely etched away, leaving only a portion of the middle gate region, and similarly, both sides of the corresponding GaN channel layer 05 and the P-type heavily doped GaN layer 06 are also etched away; both sides of the upper surface of the nth layer of the AlGaN layer are provided with an n-FETs drain ohmic metal 10 and an n-FETs source ohmic metal 11, wherein the n-FETs drain ohmic metal 10 is located on the side close to the p-FETs; a second gate metal 12 is provided on the upper surface of the P-type heavily doped GaN layer 06 of the n-FETs to form a planar gate;

[0009] The Al component in the AlGaN layer constituting the AlGaN barrier layer is gradual, and the gradual change manner is that the proportion of the Al component gradually increases from the 1st layer to the nth layer, the Al component in the nth AlGaN layer is the highest, and the proportion of the Al component gradually decreases from the nth layer to the 2n-1th layer;

[0010] The p-FETs source ohmic metal 07 is a high-level signal port of the CMOS circuit, the n-FETs source ohmic metal 11 is a low-level signal port of the CMOS circuit, the first gate metal 09 and the second gate metal 12 are connected to form an input-level signal port of the CMOS circuit, and the p-FETs drain ohmic metal 08 and the n-FETs drain ohmic metal 10 are connected to form an output-level signal port of the CMOS circuit.

[0011] Furthermore, the material used for the substrate 01 is one of Si, sapphire and SiC.

[0012] Furthermore, the difference in Al composition between adjacent AlGaN layers is ≤30%.

[0013] Furthermore, the material used for the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08 is any one of Pd / Au / Ni, Ni / Au, and Pd / Ni.

[0014] Furthermore, the material of the first gate metal 09 is any one of Ti / Au, W / Au, Ni / Au, Mo / Au, and Ru.

[0015] Furthermore, the gate dielectric 13 is any one of an oxide layer and an insulating layer.

[0016] Furthermore, the material used for the n-FETs drain ohmic metal 10 and the n-FETs source ohmic metal 11 is any one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al.

[0017] Furthermore, the contact between the second gate metal 12 and the P-type heavily doped GaN layer 06 is an ohmic contact, and the material used for the second gate metal 12 is Ni / Au.

[0018] The beneficial effect of the present invention is that, based on the epitaxial structure of commercial enhanced p-GaN gate HEMTs, the AlGaN barrier layer with a fixed Al component is replaced with an AlGaN barrier layer with a high Al component and 2n-1 layers of AlGaN with different Al components are regularly stacked. Among them, the Al component of the middle nth layer of AlGaN is the highest value, and the difference in Al component between each layer of AlGaN and between the AlGaN barrier layer and the GaN channel layer is ≤30%, which can not only obtain the advantages brought by the high Al component, but also effectively avoid a significant reduction in the quality of the heterojunction interface. At the same time, the Al composition shows a decreasing trend from the nth AlGaN barrier layer to the n-1th AlGaN barrier layer, that is, the Al composition of the first AlGaN barrier layer close to the GaN channel layer is the lowest and is >0%. By regulating the Al composition size of the 1st to n-1th AlGaN layers within the rule that the Al composition difference is ≤30%, the overall 2DEG concentration between the nth to 2n-1th AlGaN barrier layers and the GaN channel layer can be suppressed, thereby realizing enhancement-mode n-FETs with high threshold voltage. In addition, during the preparation of the p-GaN gate structure of n-FETs, etching away the P-type heavily doped GaN layer, GaN channel layer, and the 1st to n-1st AlGaN barrier layers in the gate-drain / gate-source regions not only helps to restore the overall 2DEG concentration between the nth to 2n-1st AlGaN barrier layers and the GaN channel layers, but also can fully utilize the advantage of the highest Al component of the nth AlGaN barrier layer while maintaining the threshold voltage, thereby improving the critical electric field, increasing thermal conductivity, and thus improving the breakdown voltage and high-power output characteristics. In p-FETs, the multi-AlGaN barrier layer with an overall high Al component helps to increase the concentration of 2DHG at the heterojunction interface of the GaN channel layer 05 and the multi-AlGaN barrier layer, thereby increasing the on-current density of p-FETs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the epitaxial structure of the device proposed in the present invention.

[0020] Figure 2 A schematic diagram of the energy band distribution of a reference structure in the epitaxial structure of the device proposed in the present invention.

[0021] Figure 3 This is a schematic diagram of the structure of the device proposed in the present invention after etching out the p-FETs gate groove in the p-FETs region, etching out the P-type heavily doped GaN layer, GaN channel layer and the 1st to n-1th AlGaN barrier layers in the n-FETs gate-drain / gate-source region, and etching out the p-FETs and n-FETs device isolation regions.

[0022] Figure 4Schematic diagram of the change of 2DHG concentration with structural parameters of one of the devices proposed in the present invention

[0023] Figure 5 A schematic diagram of 2DEG concentration distribution of the nth to 2n-1th AlGaN barrier layers after etching all P-type heavily doped GaN layers, GaN channel layers and 1st to n-1th AlGaN barrier layers in the gate-drain / gate-source region of one of the devices proposed in the present invention.

[0024] Figure 6 This is a schematic diagram of the complete structure of the GaN-based CMOS device circuit based on high Al composition, high interface quality and multiple AlGaN barrier layers proposed by the present invention.

[0025] Figure 7 It is a schematic diagram of the topological structure of the CMOS circuit of the present invention. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is described in detail below in conjunction with the attached drawings.

[0027] The present invention provides a GaN-based epitaxial structure and a monolithic integrated CMOS circuit, wherein the preparation method is to first prepare Figure 1 The epitaxial structure shown in Figure 1 The epitaxial structure obtained from the growth direction

[0001] in the middle is from bottom to top, including a substrate 01, a III-nitride buffer layer 02 located above the substrate 01, a GaN channel layer 03 located above the III-nitride buffer layer 02, a multi-AlGaN barrier layer 04 located above the GaN channel layer, a GaN channel layer 05 located above the multi-AlGaN barrier layer 04, and a P-type heavily doped GaN layer 06 located above the GaN channel layer 05.

[0028] The GaN channel layer 05, the multi-AlGaN barrier layer 04 and the GaN channel layer 03 form a multi-layer stacked heterojunction. A 2DHG is formed at the heterojunction interface between the GaN channel layer 05 and the multi-AlGaN barrier layer 04, and a 2DEG is formed at the heterojunction interface between the multi-AlGaN barrier layer 04 and the GaN channel layer 03. The energy band distribution diagram is shown in FIG. Figure 2 shown.

[0029] From left to right along the lateral direction, the surface of the CMOS device includes the p-FETs device region, the isolation region formed by etching or ion implantation between the p-FETs and the n-FETs, and the n-FETs device region. The P-type heavily doped GaN layer 06, the GaN channel layer 05, and the AlGaN 1 barrier layer 04 to the AlGaN n barrier layer 04 in the drain / gate source region of the n-FETs region are etched away, as shown in FIG. Figure 3 2DHG concentration changes as shown in Figure 4 and Figure 5 shown.

[0030] The surface of the p-FETs device is shown from left to right along the lateral direction: a source structure composed of a P-type heavily doped GaN layer 06 and a source metal 07 in the source region of the p-FETs, wherein the source ohmic metal 07 contacts the top of the P-type heavily doped GaN layer 06. A drain structure composed of a P-type heavily doped GaN layer 06 and a drain metal 08 in the drain region of the p-FETs, wherein the other end of the drain ohmic metal 08 on the upper surface of the p-FETs device away from the source structure contacts the top of the P-type heavily doped GaN layer 06. The p-FETs gate structure is etched away partially or entirely of the P-type heavily doped GaN layer 06 outside the drain and source regions, or partially or entirely of the P-type heavily doped GaN layer 06 in the gate region is etched away, and is located on the P-type heavily doped GaN layer 06 or GaN channel layer 05 between the source structure and the drain structure, and the gate structure includes a gate metal 09 deposited on the gate groove and a gate dielectric 13 deposited on the gate groove and on the surface of the P-type heavily doped GaN layer 06 or GaN channel layer 05 between the drain and source, such as Figure 6 shown.

[0031] The surface of the n-FETs device is arranged from left to right along the lateral direction: the source structure composed of the AlGaN n barrier layer 04 in the n-FETs drain region to the AlGaN 2n-1 barrier layer 04 and the drain metal 10, wherein the drain ohmic metal 10 contacts the top of the AlGaN n barrier layer 04 after etching. The drain structure composed of the AlGaN n barrier layer 04 in the n-FETs source region to the AlGaN 2n-1 barrier layer 04 and the source metal 11, wherein the other end of the source ohmic metal 11 away from the upper surface of the HEMTs device of the drain structure contacts the top of the AlGaN n barrier layer left after etching. The n-FETs p-GaN gate structure is located between the n-FETs source structure and the drain structure, and the n-FETs gate structure includes a gate metal 12 deposited on the P-type heavily doped GaN layer 06.

[0032] In the CMOS device, the p-FETs source metal 07 is used as a CMOS circuit to connect the high-level signal V DD The n-FETs source metal 11 is used as the CMOS circuit ground or low level signal GND terminal, the p-FETs drain metal 08 and the n-FETs drain metal 10 are connected together as the output level signal terminal of the CMOS circuit, and the p-FETs gate metal 09 and the n-FETs gate metal 12 are connected together as the input level signal terminal of the CMOS circuit. Figure 7 shown.

[0033] The working principle of a GaN-based epitaxial structure and monolithic integrated CMOS circuit preparation technology proposed by the present invention is:

[0034] The current commercial enhancement mode p-GaN gate HEMTs epitaxial structure has the problem that if the AlGaN barrier layer with too high Al content is used, there will be serious thermal and lattice mismatch, which will cause a large number of defects at the heterojunction interface and deteriorate the interface roughness, thereby reducing the 2DEG, 2DHG mobility, overall device performance and reliability. At the same time, the high concentration of 2DEG p-GaN is difficult to deplete, which will lead to problems such as n-FETs threshold voltage degradation. Figure 6 This is a schematic diagram of the device structure of the present invention. In n-FETs based on p-GaN gate structure, regulating the Al component size of the 1st to n-1st AlGaN layers can help the p-GaN gate to deplete the overall 2DEG concentration between the nth to 2n-1st AlGaN barrier layers and the GaN channel layer below, thereby increasing the gate control capability and threshold voltage of n-FETs. After etching away the 1st to n-1st AlGaN barrier layers in the gate-drain / gate-source region of n-FETs, the nth AlGaN layer with a high Al group can dominate the overall 2DEG concentration, N-channel transport capacity, and high-voltage power performance of n-FETs, and improve the corresponding performance. For p-FETs under the same epitaxial structure, the overall increase in the Al component of the multi-AlGaN barrier layer helps to increase the concentration of 2DHG at the heterojunction interface of the overall multi-AlGaN barrier layer and the upper GaN channel layer, thereby realizing enhanced p-FETs with high on-current density, and promoting the development of all-GaN monolithic power integrated ICs based on CMOS.

Claims

1. A monolithic integrated CMOS circuit based on a GaN-based epitaxial structure, characterized in that: The invention comprises p-FETs and n-FETs, wherein the common structure of the p-FETs and the n-FETs is a substrate (01), a group III nitride buffer layer (02), a GaN channel layer (03) and an AlGaN barrier layer which are stacked in sequence in a vertical direction, and the AlGaN barrier layer of the p-FETs and the AlGaN barrier layer of the n-FETs are isolated from each other; The AlGaN barrier layer of the p-FETs comprises 2n-1 AlGaN layers, where n≥1, and the topmost layer is defined as the first AlGaN layer, the middle layer is the nth layer, and the bottom layer is the 2n-1 layer, that is, the 2n-1 AlGaN layer is in contact with the GaN channel layer (03); a GaN channel layer (05) is provided on the upper surface of the first AlGaN layer, and a P-type heavily doped GaN layer (06) is provided on the upper surface of the GaN channel layer (05); and the upper surfaces of the P-type heavily doped GaN layer (06) respectively have a p-FETs source ohmic metal (07) and a p-FET at both ends of the upper surface. s drain ohmic metal (08), wherein the p-FETs drain ohmic metal (08) is located on the side close to the n-FETs; a groove gate structure is provided between the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08), the groove gate structure comprises a gate dielectric (13) and a first gate metal (09), the gate dielectric (13) is located in a groove formed on the upper surface of the P-type heavily doped GaN layer (06), wraps the lower part of the first gate metal (09) and contacts the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) on both sides respectively; The AlGaN barrier layer structure of the n-FETs is the same as that of the p-FETs, and the AlGaN barrier layer is provided with a GaN channel layer (05) and a P-type heavily doped GaN layer (06) in sequence. Unlike the p-FETs, both sides of the AlGaN layer above the nth layer in the AlGaN barrier layer of the n-FETs are completely etched away, leaving only a portion of the middle gate region. Similarly, both sides of the corresponding GaN channel layer (05) and the P-type heavily doped GaN layer (06) are also etched away; both sides of the upper surface of the nth AlGaN layer are provided with an n-FETs drain ohmic metal (10) and an n-FETs source ohmic metal (11), wherein the n-FETs drain ohmic metal (10) is located on the side close to the p-FETs; and a second gate metal (12) is provided on the upper surface of the P-type heavily doped GaN layer (06) of the n-FETs to form a planar gate; The Al component in the AlGaN layer constituting the AlGaN barrier layer is gradual, and the gradual change manner is that the proportion of the Al component gradually increases from the 1st layer to the nth layer, the Al component in the nth AlGaN layer is the highest, and the proportion of the Al component gradually decreases from the nth layer to the 2n-1th layer; The p-FETs source ohmic metal (07) is a high-level signal port of the CMOS circuit, the n-FETs source ohmic metal (11) is a low-level signal port of the CMOS circuit, the first gate metal (09) and the second gate metal (12) are connected to form an input-level signal port of the CMOS circuit, and the p-FETs drain ohmic metal (8) and the n-FETs drain ohmic metal (10) are connected to form an output-level signal port of the CMOS circuit.

2. The monolithic integrated CMOS circuit based on GaN-based epitaxial structure according to claim 1, characterized in that: The material used for the substrate (01) is one of Si, sapphire and SiC.

3. The monolithic integrated CMOS circuit based on GaN-based epitaxial structure according to claim 1, characterized in that: The Al composition difference between adjacent AlGaN layers is ≤30%.

4. The monolithic integrated CMOS circuit based on GaN-based epitaxial structure according to claim 1, characterized in that: The material used for the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) is any one of Pd / Au / Ni, Ni / Au and Pd / Ni.

5. The monolithic integrated CMOS circuit based on GaN-based epitaxial structure according to claim 1, characterized in that: The material used for the first gate metal (09) is any one of Ti / Au, W / Au, Ni / Au, Mo / Au and Ru.

6. The monolithic integrated CMOS circuit based on GaN-based epitaxial structure according to claim 1, characterized in that: The gate dielectric (13) is any one of an oxide layer and an insulating layer.

7. The monolithic integrated CMOS circuit based on GaN-based epitaxial structure according to claim 1, characterized in that: The material used for the n-FETs drain ohmic metal (10) and the n-FETs source ohmic metal (11) is any one of Ti / Au, Ti / Al / Ni / Au and Ti / Al.

8. The monolithic integrated CMOS circuit based on GaN-based epitaxial structure according to claim 1, characterized in that: The contact between the second gate metal (12) and the P-type heavily doped GaN layer (06) is an ohmic contact, and the material used for the second gate metal (12) is Ni / Au.

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