Quantum logic gate construction method, Dickle2 quantum state preparation method and related device

Abstract

The invention discloses a quantum logic gate construction method, a Dickle2 quantum state preparation method and a related device. The quantum state preparation method comprises the following steps: determining a quantum bit for preparing a Dickle2 quantum state; the plurality of deentanglement quantum logic gates act on quantum bits of which the initial state is a Dickle2 quantum state to obtain a deentanglement quantum circuit, and the action relationship between the deentanglement quantum logic gate and the quantum bits in the next layer of action time sequence is determined by the action relationship between the deentanglement quantum logic gate and the quantum bits in the previous layer of action time sequence; determining an inverse line of the deentanglement quantum line as a target quantum line; and operating the target quantum circuit to prepare the Dickle2 quantum state. Compared with the prior art, according to the Dickle2 quantum state preparation method provided by the invention, the depth of a circuit only needs an O (logn) layer, so that a bit logarithm level preparation scheme of the Dickle2 quantum state can be realized, and the running time of a quantum computer can be effectively compressed.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a method for constructing quantum logic gates, a method for preparing Dickle2 quantum states, and related devices. Background Technology

[0002] Quantum computing is a novel computing paradigm that manipulates quantum information units to perform calculations according to the laws of quantum mechanics. Unlike classical computing, quantum computing follows the laws of quantum mechanics and is a new computing paradigm that can break through the limitations of classical computing power. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have become a key technology under research because of their ability to process mathematical problems more efficiently than ordinary computers; for example, they can accelerate the time to crack RSA keys from hundreds of years to hours.

[0003] The Dickle2 quantum state is a uniform quantum state with only two |1> states and the rest being |0> states. In mathematics, chemistry, and finance, there are many instances where the initial state of the Dickle2 quantum state is needed to solve corresponding problems. How to efficiently prepare the Dickle2 quantum state in quantum computing has become a pressing technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a method for constructing quantum logic gates, a method for preparing Dickle2 quantum states, and related apparatus to solve the technical problems in the prior art, and to achieve efficient preparation of Dickle2 quantum states in quantum computing.

[0005] In a first aspect, the present invention provides a method for constructing unentangled quantum logic gates, the method comprising:

[0006] Obtain the first H gate, the parametric RY gate, and the second H gate that are sequentially applied to each qubit; wherein the angle parameters of the parametric RY gates of the two qubits are opposite numbers;

[0007] A first controlled rotation gate is constructed at both the first and second evolution timings on two qubits. The control bits of the two first controlled rotation gates are on the same qubit. The first evolution timing is the timing between the first H gate and the parametric RY gate, and the second evolution timing is the timing between the parametric RY gate and the second H gate.

[0008] Secondly, the present invention provides a method for preparing a Dickle2 quantum state, the method comprising:

[0009] Determine the qubits used to prepare the Dickle2 quantum state;

[0010] Multiple unentangled quantum logic gates are applied to a qubit whose initial state is Dickle2 to obtain an unentangled quantum circuit. The unentangled quantum logic gates are constructed using the method described in claim 1. In the subsequent layer of the application sequence, the interaction relationship between the unentangled quantum logic gates and the qubits is determined by the interaction relationship between the unentangled quantum logic gates and the qubits in the previous layer of the application sequence.

[0011] The inverse circuit of the deentangled quantum circuit is determined as the target quantum circuit;

[0012] The target quantum circuit is run to prepare the Dickle2 quantum state.

[0013] In the Dickle2 quantum state preparation method described above, preferably, the interaction relationship between the deentangled quantum logic gate and the qubit in the subsequent layer interaction sequence is determined by the interaction relationship between the deentangled quantum logic gate and the qubit in the previous layer interaction sequence, including:

[0014] In each layer of the operation sequence, the qubits are regrouped to form several qubit pairs. Each qubit pair includes a first qubit and a second qubit, with the first qubit being in a lower position than the second qubit.

[0015] In the first layer of operation timing, the qubits from the least significant bit to the most significant bit are grouped sequentially, with each pair of qubits forming a qubit pair, and each qubit pair operating one of the unentangled quantum logic gates;

[0016] In other layers of the operational sequence, several qubits are regrouped according to the interaction relationship between the deentangled quantum logic gate and the qubit in the previous layer of the operational sequence to form a qubit set. The qubits in the qubit set come from the first or second qubit in each qubit pair in the previous layer of the operational sequence that has not evolved to the |0> state. The qubits in the qubit set are grouped sequentially from low to high qubit, and every two qubits form a qubit pair. Each qubit pair operates one deentangled quantum logic gate.

[0017] In the Dickle2 quantum state preparation method described above, preferably, in the first layer of operation timing, the qubits from the least significant bit to the most significant bit are grouped sequentially, with each pair of two adjacent qubits forming a qubit pair, and each qubit pair operating a de-entangled quantum logic gate;

[0018] In other layers of the operational sequence, several qubits are regrouped according to the interaction relationship between the deentangled quantum logic gate and the qubit in the previous layer of the operational sequence to form a qubit set. The qubits in the qubit set come from the first or second qubit in each qubit pair in the previous layer of the operational sequence that has not evolved to the |0> state. The qubits in the qubit set are grouped sequentially from low to high qubit, and every two adjacent qubits form a qubit pair. Each qubit pair operates one of the deentangled quantum logic gates.

[0019] In the Dickle2 quantum state preparation method described above, preferably, the unentangled quantum circuit further includes a second controlled rotation gate acting after each unentangled quantum gate, wherein the control bit of the second controlled rotation gate is the target bit of the first controlled rotation gate, and the target bit of the second controlled rotation gate is the control bit of the first controlled rotation gate.

[0020] In the Dickle2 quantum state preparation method described above, preferably, the first controlled rotation gate is a controlled Z-gate and the second controlled rotation gate is a controlled X-gate.

[0021] In the Dickle2 quantum state preparation method described above, preferably, the target quantum circuit further includes an H-gate acting on all qubits, wherein the H-gate is located after the multi-layer action timing of the entangled quantum logic gate on the qubits.

[0022] Thirdly, the present invention provides a Dickle2 quantum state preparation device, the device comprising:

[0023] The acquisition module is used to determine the qubits used to prepare the Dickle2 quantum state;

[0024] A de-entangled quantum circuit construction module is used to construct de-entangled quantum circuits. Multiple de-entangled quantum logic gates are applied to qubits whose initial state is the Dickle2 quantum state to obtain de-entangled quantum circuits. The interaction relationship between the de-entangled quantum logic gates and qubits in the later layer interaction sequence is determined by the interaction relationship between the de-entangled quantum logic gates and qubits in the previous layer interaction sequence.

[0025] A target quantum circuit construction module is used to determine the inverse circuit of the unentangled quantum circuit as the target quantum circuit;

[0026] The execution module is used to run the target quantum circuit to prepare the Dickle2 quantum state.

[0027] Fourthly, the present invention provides a storage medium storing a computer program, wherein the computer program is configured to implement the aforementioned method when run.

[0028] Fifthly, the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to implement the aforementioned method.

[0029] Compared with existing technologies, the Dickle2 quantum state preparation method provided by this invention only requires O(logn) layers of circuit depth, thereby realizing a logarithmic preparation scheme of Dickle2 quantum states, which can effectively compress the running time of quantum computers. Attached Figure Description

[0030] Figure 1 This is a network block diagram of a quantum circuit construction system provided in an embodiment of this application;

[0031] Figure 2 This is a flowchart illustrating a method for preparing a de-entangled quantum logic gate according to an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of the structure of a deentangled quantum logic gate provided in an embodiment of the present invention;

[0033] Figure 4 This is a flowchart of a method for preparing a Dickle2 quantum state according to an embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram of the structure of a de-entangled quantum circuit provided in an embodiment of the present invention;

[0035] Figure 6 This is a schematic diagram of the structure of a target quantum circuit provided in an embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of another deentangled quantum circuit provided in an embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram of another target quantum circuit provided in an embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of a Dickle2 quantum state preparation device provided in an embodiment of the present invention. Detailed Implementation

[0039] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0040] [Structure of a quantum circuit construction system]

[0041] Figure 1 This is a network block diagram of a quantum circuit construction system provided in an embodiment of this application. The quantum circuit construction system may include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0042] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum circuit construction system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can be wired, wireless communication links, or fiber optic cables.

[0043] Server 120 and client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0044] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 162 (application program 173). The application program 162 (application program 173) may be used to implement a quantum algorithm compiled according to the quantum circuit construction method provided in the embodiments of this application.

[0045] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0046] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum computing.

[0047] The aforementioned classical processing system 160 and quantum processing system 170 can be integrated into a single device or distributed across two different devices. For example, the first device, including the classical processing system 160, runs a classical computer operating system that provides quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum applications using the quantum application development tools and services on the second device and send the quantum program to the second device, including the quantum processing system 170, via the network services. The second device runs a quantum computer operating system, which parses the code of the quantum program and compiles it into instructions that can be recognized and executed by the quantum computer control system. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0048] In the classic silicon-based processing system 160, the units of the classic processor 161 are CMOS transistors. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of these computing units in a silicon chip is sufficient; currently, a classic processor contains tens of thousands of computing units. The sufficient number of computing units and the fixed selectable computing logic of the CMOS transistors, such as AND logic, allow for computational efficiency through a combination of numerous CMOS transistors and limited logic functions.

[0049] Unlike the logic units in the classical processing system 160, the basic computational unit of the quantum processor 171 in the quantum processing system 170 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logic functions. Given the limited number of qubits and the diverse logic functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logic function combinations to achieve computational effects.

[0050] Based on these differences, the design of logical functions applied to qubits (including the design of whether qubits are used and the design of the efficiency of each qubit's use) is crucial to improving the computational performance of quantum computers and requires specialized design. The aforementioned design considerations for qubits are technical issues that ordinary computing devices do not need to address.

[0051] [Methods for Constructing Unentangled Quantum Logic Gates]

[0052] In the embodiments provided by the present invention, a de-entangled quantum logic gate is provided. This entangled quantum logic gate is used to realize controlled rotation operation between two entangled qubits, and the quantum states of the two qubits are switched between the |01> state and the |10> state.

[0053] Reference Figure 2 As shown, the present invention also provides a method for constructing a de-entangled quantum logic gate, wherein the constructed de-entangled quantum logic gate refers to... Figure 3 As shown, the construction method includes:

[0054] S101: Determine two qubits and obtain the first H gate, the parametric RY gate, and the second H gate that are sequentially applied to each qubit; wherein, the angle parameter of the parametric RY gate of the two qubits takes the opposite value, and the absolute value of the angle parameter of the parametric RY gate is jointly determined by the quantum state amplitude value of each qubit.

[0055] S102: A first controlled rotation gate is constructed at both the first and second evolution timings on the two qubits. Preferably, the first controlled rotation gate is a controlled Z gate, and the control bits of the two first controlled rotation gates are on the same qubit. The first evolution timing is the timing between the first H gate and the parametric RY gate, and the second evolution timing is the timing between the parametric RY gate and the second H gate.

[0056] [Dickle2 quantum state preparation method]

[0057] The Dickle2 quantum state is a uniform quantum state with only two |1> states and the rest being |0> states. The embodiments provided in this invention assume that the initial state of a certain unentangled quantum circuit is the Dickle2 quantum state to be prepared; therefore, by unentanglementing the Dickle2 quantum state, the target quantum state can be evolved to |0> states. n The above steps are classical processing procedures for quantum circuits of the state, which can be implemented using a quantum simulator.

[0058] Furthermore, the inverse circuit of the above-mentioned unentangled quantum circuit can be constructed to obtain the target quantum circuit. The target quantum circuit is then run and applied to the initial state |0> nThis allows for the fabrication of Dickle2 quantum states on real quantum chips by placing them on qubits of the state.

[0059] In one feasible implementation, refer to Figure 4 As shown, this invention provides a method for preparing a Dickle2 quantum state, comprising the following steps:

[0060] Step S201: Determine the qubits to be used to prepare the Dickle2 quantum state.

[0061] The number of qubits corresponding to a Dickle2 quantum state can be predetermined, depending on the number of qubits supported by the quantum device. Generally, it is less than or equal to the number of qubits supported. When the number of qubits supported by the quantum device is relatively large, the number of qubits required for preparation can be selected as appropriate.

[0062] Step S202: Multiple unentangled quantum logic gates are applied to a qubit initially in the Dickle2 quantum state to obtain an unentangled quantum circuit. The unentangled quantum circuit is used to evolve the Dickle2 quantum state into |0> n The unentangled quantum logic gates are constructed using the aforementioned method, wherein the interaction relationship between the unentangled quantum logic gates and qubits in the later layer of the interaction sequence is determined by the interaction relationship between the unentangled quantum logic gates and qubits in the previous layer of the interaction sequence.

[0063] In a de-entangled quantum circuit, each de-entangled quantum logic gate acts on two preset qubits. These two qubits can be two adjacent qubits or two qubits at positions separated by a gap, depending on the circuit configuration. No limitation is made here. Along the action sequence, multiple de-entangled quantum logic gates are distributed in multiple layers. Each layer of de-entangled quantum logic gates includes at least one de-entangled quantum logic gate, and the de-entangled quantum logic gates in the same layer all act on the same action sequence.

[0064] In deentangled quantum circuits, deentangled quantum logic gates play a role in deentangled two qubits. After the deentangled quantum circuit passes through two qubits, the deentanglement of these two qubits is completed. After each layer of deentangled quantum logic gates, some qubits in the target quantum state become mutually deentangled until all layers have passed, resulting in an approximate |0> n state.

[0065] Step S203: Determine the inverse circuit of the deentangled quantum circuit as the target quantum circuit. The target quantum circuit has a target quantum logic gate, which is determined based on the deentangled quantum logic gate. Specifically, the interaction relationship between the target quantum logic gate and the qubit in the previous layer's interaction timing is determined by the interaction relationship between the target quantum logic gate and the qubit in the next layer's interaction timing.

[0066] The number of target quantum logic gates in a target quantum circuit is the same as the number of unentangled quantum logic gates in a deentangled quantum circuit, while the execution timing of multiple target quantum logic gates is the opposite of that of multiple deentangled quantum logic gates.

[0067] The target quantum circuit is obtained by reverse engineering the de-entangled quantum circuit. In the target quantum circuit, each target quantum logic gate acts on two preset qubits. These two qubits can be two qubits in adjacent positions or two qubits in positions separated by a gap. Since the Dickle2 state is a symmetric quantum state, the pairs of qubits can be freely set. At the same time, the maximum number of parallel executable quantum gate pairs must be satisfied to efficiently complete the de-entanglement. Along the action sequence, the multiple target quantum logic gates are distributed in multiple layers. Each layer of target quantum logic gates includes at least one target quantum logic gate. The target quantum logic gates in the same layer of target quantum logic gates all act on the same action sequence.

[0068] In the target quantum circuit, the target quantum logic gate functions to generate a predetermined entangled state between two qubits, with the initial state being |0> n After each layer of target quantum logic gate, some of the qubits in the state become entangled with each other until all the action sequences are completed, resulting in the Dickle2 quantum state.

[0069] Step S204: Run the target quantum circuit to prepare the Dickle2 quantum state. In the specific preparation process, first obtain the target quantum circuit, and then run the quantum operation corresponding to the target quantum circuit on the quantum chip to prepare the Dickle2 quantum state.

[0070] Based on the Dickle2 quantum state preparation method provided in the above embodiments, the circuit depth only needs to be O(logn) layers, thereby realizing the qubit logarithmic preparation scheme of Dickle2 quantum state, which can effectively compress the running time of quantum computer.

[0071] Furthermore, the specific method for determining the interaction relationship between the deentangled quantum logic gate and the qubit in the later layer's interaction timing from the interaction relationship between the deentangled quantum logic gate and the qubit in the previous layer's interaction timing is as follows:

[0072] Each qubit within a deentangled quantum circuit needs to be uniquely identified; therefore, each qubit is assigned a unique number to distinguish different qubits. In the embodiments provided by this invention, the qubits within the deentangled quantum circuit are numbered sequentially from the least significant bit to the most significant bit. For example, referring to... Figure 5 As shown, the unentangled quantum circuit has 8 qubits, which are numbered sequentially from 1 to 8. Qubit 1 is located at the top of the diagram, which is also the lowest qubit, and qubit 8 is located at the bottom of the diagram, which is also the highest qubit.

[0073] In each layer of the interaction sequence, the qubits are regrouped to form several qubit pairs. Each qubit pair includes a first qubit and a second qubit, with the first qubit being in a lower position than the second qubit. In each layer of the interaction sequence, each qubit pair is subjected to a deentangled quantum logic gate.

[0074] In the first layer of operation, the qubits are grouped sequentially from the least significant bit to the most significant bit, with each pair of qubits forming a qubit pair. These two qubits can be two adjacent qubits or two qubits at positions separated by a gap. Preferably, each pair of two adjacent qubits forms a qubit pair. Each qubit pair is subjected to a deentanglement quantum logic gate, thereby deentanglement of the two qubits. After the deentanglement quantum logic gate is applied to the two qubits, the deentanglement of the two qubits is completed, and the first or second qubit is evolved into the |0> state.

[0075] In other layers of the interaction sequence, several qubits are regrouped according to the interaction relationship between the deentangled quantum logic gate and the qubit in the previous layer of the interaction sequence to form a qubit set. The qubits in the qubit set come from the first or second qubit in each qubit pair in the previous layer of the interaction sequence that has not evolved to the |0> state. The qubits in the qubit set are grouped sequentially from the least significant bit to the most significant bit, and every two qubits form a qubit pair. These two qubits can be two qubits in adjacent positions or two qubits in positions that are separated by a gap. Preferably, every two adjacent qubits form a qubit pair, and each qubit pair is subjected to a deentangled quantum logic gate.

[0076] After each layer of deentangled quantum logic gates, some qubits in the target quantum state become unentangled with each other until, after all the interaction sequences, the initial approximate state |0> is obtained. n state.

[0077] The deentanglement quantum circuit provided by this invention can directly deentangle the first layer. The number of qubits, half the number of qubits remaining after the second layer of deentanglement. By continuing in this way, all entanglement can eventually be completed, and the depth of the line only needs to be O(logn) layers.

[0078] In one feasible implementation, refer to Figure 5 As shown, an example of a deentangled quantum circuit with 8 qubits will be used for illustration:

[0079] In the first layer of the interaction sequence, every two adjacent qubits are grouped into four qubit pairs, namely [1,2], [3,4], [5,6] and [7,8]. Each qubit pair is subjected to an unentangled quantum logic gate, which limits the second qubit in the qubit pair to evolve into an approximate |0> state. That is, qubits 2, 4, 6 and 7 are in an approximate |0> state after being interacted.

[0080] After the first layer of interaction, the amplitude is approximately present in qubits 1, 3, 5, and 7. At this point, in the second layer of interaction, the remaining qubits are regrouped. This time, there are two qubit pairs, [1,3] and [5,7]. Each qubit pair is subjected to a deentanglement quantum logic gate, which limits the second qubit in the qubit pair to evolve into an approximate |0> state. That is, after qubits 3 and 7 are interacted, they are in an approximate |0> state.

[0081] After the second layer of interaction, the amplitude exists only on qubits 1 and 5. At this point, in the third layer of interaction, it is only necessary to apply the deentanglement quantum logic gate on qubits 1 and 5 to completely collapse the quantum states on qubits 1 and 5 into the |0> state.

[0082] For n qubits, let's first assume they are powers of 2, that is, n = 2. m Where m is a positive integer, in the first layer of the action sequence, each qubit is grouped, and the qubit pairs are: [1,2],[3,4],[5,6]......[2 m -1,2 m ].

[0083] If the second qubit in a constrained qubit pair evolves into an approximate |0> state, then after the first layer of interaction timing, the remaining qubits with amplitude are qubits 1, 3, up to 2. m -1 qubit, in the second layer of the timing sequence, these remaining qubits are regrouped to obtain the following qubit pairs: [1,3],[5,7]......[2 m -3,2 m-1].

[0084] In this way, until the last layer, only two qubits remain to be grouped, requiring a total of m = logn layers of pairing.

[0085] When considering n qubits that are not exponents of 2, the highest-order qubit is not grouped during the first layer of operation. It is only during the second layer of operation that the highest-order qubit is included in the grouping.

[0086] The following example uses 7 qubits:

[0087] Reference Figure 7 As shown, in the first layer of the interaction sequence, there are three qubit pairs: [1,2], [3,4], [5,6], and the remaining qubit number 7 is not grouped.

[0088] In the second layer of the timing sequence, qubit 7 is included in the grouping range, and the qubit pair is two: [1,3], [5,7].

[0089] In the third layer of the interaction sequence, the qubit pair is [1,5].

[0090] In the embodiments provided by this invention, the specific method for determining the interaction relationship between the target quantum logic gate and the qubit in the previous layer's interaction timing sequence of the target quantum circuit from the interaction relationship between the target quantum logic gate and the qubit in the next layer's interaction timing sequence is as follows:

[0091] Each qubit within the target quantum circuit needs to be uniquely identified; therefore, each qubit is assigned a unique number to distinguish different qubits. In the embodiments provided by this invention, the qubits within the target quantum circuit are numbered sequentially from the least significant bit to the most significant bit. For example, referring to... Figure 6 As shown, the target quantum circuit has 8 qubits, which are numbered sequentially from 1 to 8. Qubit 1 is located at the top of the diagram, which is also the lowest qubit, and qubit 8 is located at the bottom of the diagram, which is the highest qubit. This is the same as the numbering of the unentangled quantum circuit.

[0092] In each layer of the interaction sequence, the qubits are regrouped to form several qubit pairs. Different qubit pairs contain different qubits. Each qubit pair includes a first qubit and a second qubit. The first qubit is in a lower position than the second qubit. In each layer of the interaction sequence, each qubit pair is interacted with a target quantum logic gate.

[0093] In the final layer of the interaction sequence, the qubits from the least significant bit to the most significant bit are grouped sequentially, with each pair of adjacent qubits forming a qubit pair. In the final layer of the interaction sequence, each pair of adjacent qubits is interacted with a target quantum logic gate. Since the target quantum circuit is derived by reverse engineering from the deentangled quantum circuit, the qubit pairs interacted by the target quantum logic gate in the final layer of the interaction sequence are the same as the qubit pairs interacted by the deentangled quantum logic gate in the first layer of the interaction sequence of the deentangled quantum circuit.

[0094] In other layers of interaction, several qubits are regrouped according to the interaction relationship between the target quantum logic gate and the qubits in the next layer of interaction, forming a qubit set. Within each qubit set, the qubits are grouped sequentially from the least significant bit to the most significant bit, forming qubit pairs. This can be derived from deentangled quantum circuits. For example, in the penultimate layer of interaction, the qubit pair interacting with the target quantum logic gate is the same as the qubit pair interacting with the deentangled quantum logic gate in the second layer of interaction of the deentangled quantum circuit. This process is repeated to obtain the qubit pairs for all interaction times of the target quantum circuit.

[0095] After each layer of target quantum logic gate, some of the qubits in the initial state become entangled with each other until the Dickle2 quantum state is obtained after all the interaction sequences.

[0096] In one feasible implementation, refer to Figure 6 As shown, an example of a target quantum circuit with 8 qubits will be used for illustration:

[0097] In the final layer of the timing sequence, every two adjacent qubits are grouped into four qubit pairs, namely [1,2], [3,4], [5,6] and [7,8], and each qubit pair is acted upon by a target quantum logic gate.

[0098] In the penultimate layer of the interaction sequence, there are two qubit pairs, [1,3] and [5,7], and each qubit pair is interacted with a conjugate transpose of a unitary matrix (the target quantum logic gate).

[0099] In the first layer of the interaction sequence, the target quantum logic gate is applied to qubits 1 and 5.

[0100] For n qubits, let's first assume they are powers of 2, that is, n = 2. m Where m is a positive integer, in the last layer of the action sequence, each qubit is grouped, and the qubit pairs are: [1,2],[3,4],[5,6]......[2m -1,2 m ].

[0101] In the penultimate engagement sequence, the qubits are rearranged to obtain the following qubit pairs: [1,3],[5,6]......[2 m -3,2 m -1].

[0102] By analogy with the first layer of timing, only two qubits remain to be grouped, requiring a total of m = logn layers of pairing.

[0103] When considering n qubits that are not exponents of 2, the highest-order qubits are not grouped in the last layer of the operational sequence.

[0104] The following example uses 7 qubits:

[0105] Reference Figure 8 As shown, in the last layer of the timing sequence, there are three qubit pairs: [1,2], [3,4], [5,6], and the remaining qubit number 7 is not grouped.

[0106] In the penultimate layer of the timing sequence, qubit 7 is included in the grouping range, and the qubit pair is two: [1,3], [5,7].

[0107] In the first layer of the interaction sequence, the qubit pair is [1,5].

[0108] The quantum state preparation method provided in the above embodiments requires only O(logn) layers of circuit depth, thereby realizing a logarithmic preparation scheme for Dickle2 quantum states, which can effectively compress the running time of quantum computers.

[0109] Furthermore, the deentangled quantum circuit also includes a second controlled rotation gate acting after each deentangled quantum gate. The control bit of the second controlled rotation gate is the target bit of the first controlled rotation gate, and the target bit of the second controlled rotation gate is the control bit of the first controlled rotation gate. Preferably, the second controlled rotation gate is a controlled X gate. Figure 5 For example, the control bits of the first controlled rotating gate are qubits 1, 3, 5, and 7, and the target bits are qubits 2, 4, 6, and 8. The control bits of the second controlled rotating gate are qubits 2, 4, 6, and 8, and the target bits are qubits 1, 3, 5, and 7.

[0110] First, we assume we have n = 2. m The state of each qubit is:

[0111]

[0112] The first step is in [1,2],[3,4],[5,6]......[2 m -1,2 m An unentangled quantum logic gate is applied to the qubit [1,2], [3,4], [5,6], ..., [2]. Then a second controlled rotation gate is applied to the qubit [1,2], [3,4], [5,6], ..., [2]. m -1,2 m The quantum state at this point becomes:

[0113]

[0114] Thus, the preparation of quantum states with m layers as the final circuit was completed.

[0115] In the embodiments provided by the present invention, the target quantum circuit further includes an H gate acting on all qubits, wherein the H gate is located after the multi-layer action timing of the entangled quantum logic gates on the qubits.

[0116] [Structure of the Dickle2 quantum state preparation device]

[0117] See Figure 9 As shown, the preparation apparatus includes:

[0118] The acquisition module is used to determine the qubits for preparing the Dickle2 quantum state.

[0119] The unentangled quantum circuit construction module is used to construct unentangled quantum circuits. Multiple unentangled quantum logic gates are applied to qubits with an initial state of Dickle2 to obtain unentangled quantum circuits. The interaction relationship between the unentangled quantum logic gates and qubits in the later layer interaction sequence is determined by the interaction relationship between the unentangled quantum logic gates and qubits in the previous layer interaction sequence.

[0120] Specifically, a method for constructing unentangled quantum logic gates is used to determine unentangled quantum logic gates. Multiple unentangled quantum logic gates are applied to qubits initially in the Dickle2 quantum state to obtain unentangled quantum circuits. These unentangled quantum circuits are used to evolve the Dickle2 quantum state into |0> n state.

[0121] The target quantum circuit construction module is used to determine the inverse circuit of the unentangled quantum circuit as the target quantum circuit.

[0122] In this context, the inverse of the unentangled quantum circuit is the target quantum circuit. The number of target quantum logic gates in the target quantum circuit is the same as the number of unentangled quantum logic gates in the unentangled quantum circuit. However, the execution timing of multiple target quantum logic gates is the opposite of that of multiple unentangled quantum logic gates. Multiple target quantum logic gates act on an initial state |0> nThe Dickle2 quantum state can be evolved from the qubit of the state.

[0123] The execution module is used to run the target quantum circuit to prepare the Dickle2 quantum state.

[0124] The operating module is a quantum system capable of running quantum circuits. For example, a quantum hardware system including a quantum processor and a quantum measurement and control system with communication connection is a system. The quantum processor refers to a quantum chip, and the quantum measurement and control system is used to provide analog signals to implement the quantum logic gates in the quantum circuit. The analog signals act on the quantum chip to realize the operation of the quantum circuit.

[0125] [Structure of storage media]

[0126] This invention also provides a storage medium storing a computer program, wherein the computer program is configured to implement the steps in any of the above method embodiments when running.

[0127] Specifically, in this embodiment, the storage medium can be configured to store a computer program for implementing the following steps:

[0128] Step S201: Determine the qubits to be used to prepare the Dickle2 quantum state.

[0129] Step S202: Multiple deentangled quantum logic gates are applied to a qubit whose initial state is the Dickle2 quantum state to obtain a deentangled quantum circuit. The deentangled quantum logic gates are constructed using the method of claim 1. In the latter layer of the interaction sequence, the interaction relationship between the deentangled quantum logic gates and the qubits is determined by the interaction relationship between the deentangled quantum logic gates and the qubits in the former layer of the interaction sequence.

[0130] Step S203: Determine the inverse of the unentangled quantum circuit as the target quantum circuit.

[0131] Step S204: Run the target quantum circuit to prepare the Dickle2 quantum state.

[0132] Structure of electronic devices

[0133] This invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to implement the steps in any of the above method embodiments.

[0134] Specifically, the aforementioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the aforementioned processor, and the input / output device is connected to the aforementioned processor.

[0135] Specifically, in this embodiment, the processor described above can be configured to implement the following steps via a computer program:

[0136] Step S201: Determine the qubits to be used to prepare the Dickle2 quantum state.

[0137] Step S202: Multiple deentangled quantum logic gates are applied to a qubit whose initial state is the Dickle2 quantum state to obtain a deentangled quantum circuit. The deentangled quantum logic gates are constructed using the method of claim 1. In the latter layer of the interaction sequence, the interaction relationship between the deentangled quantum logic gates and the qubits is determined by the interaction relationship between the deentangled quantum logic gates and the qubits in the former layer of the interaction sequence.

[0138] Step S203: Determine the inverse of the unentangled quantum circuit as the target quantum circuit.

[0139] Step S204: Run the target quantum circuit to prepare the Dickle2 quantum state.

[0140] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A method for constructing a de-entangled quantum logic gate, characterized in that: The method comprises: Obtaining a first H gate, a parameter-containing RY gate, and a second H gate acting on each quantum bit in sequence; wherein the angle parameters of the parameter-containing RY gates of the two quantum bits are opposite numbers; A first controlled rotary gate is constructed at the first evolutionary timing and the second evolutionary timing on the two quantum bits, and the control bits of the two first controlled rotary gates are on the same quantum bit, wherein the first evolutionary timing is the timing between the first H gate and the parameter-containing RY gate, and the second evolutionary timing is the timing between the parameter-containing RY gate and the second H gate.

2. A method for preparing Dickle2 quantum state, characterized in that: The method comprises: Determine the quantum bits used to prepare the Dickle2 quantum state; A plurality of disentanglement quantum logic gates act on a quantum bit whose initial state is a Dickle2 quantum state to obtain a disentanglement quantum circuit, wherein the disentanglement quantum logic gate is constructed by the method of claim 1, wherein the action relationship between the disentanglement quantum logic gate and the quantum bit in the latter layer of action sequence is determined by the action relationship between the disentanglement quantum logic gate and the quantum bit in the previous layer of action sequence; Determining the inverse circuit of the deentangled quantum circuit as the target quantum circuit; The target quantum circuit is run to prepare the Dickle2 quantum state.

3. The Dickle2 quantum state preparation method according to claim 2, characterized in that: The action relationship between the de-entanglement quantum logic gate and the quantum bit in the latter action sequence is determined by the action relationship between the de-entanglement quantum logic gate and the quantum bit in the previous action sequence, including: In each layer of action sequence, the qubits are regrouped to form a plurality of qubit pairs, each of which includes a first qubit and a second qubit, and the first qubit is at a lower position than the second qubit; In the first layer of action sequence, the qubits are grouped in sequence from the lowest bit to the highest bit, and every two qubits form a qubit pair, and each qubit pair acts on one of the de-entanglement quantum logic gates; In other layers of action sequences, a number of the quantum bits are regrouped according to the action relationship between the de-entanglement quantum logic gate and the quantum bits in the previous layer of action sequence to form a quantum bit set, the quantum bits in the quantum bit set come from the first quantum bit or the second quantum bit that has not evolved to the |0> state in the quantum bit pair in each previous layer of action sequence, the quantum bits in the quantum bit set are grouped in sequence from low to high, every two quantum bits form a quantum bit pair, and each quantum bit pair is acted upon by a de-entanglement quantum logic gate.

4. The Dickle2 quantum state preparation method according to claim 3, characterized in that: In the first layer of action sequence, the qubits from the lowest bit to the highest bit are grouped in sequence, and every two adjacent qubits form a qubit pair, and each qubit pair acts on one of the de-entanglement quantum logic gates; In other layers of action sequences, a number of the quantum bits are regrouped according to the action relationship between the de-entanglement quantum logic gate and the quantum bits in the previous layer of action sequence to form a quantum bit set, the quantum bits in the quantum bit set come from the first quantum bit or the second quantum bit that has not evolved to the |0> state in the quantum bit pair in each previous layer of action sequence, the quantum bits in the quantum bit set are grouped in sequence from low to high, every two adjacent quantum bits form a quantum bit pair, and each quantum bit pair is acted upon by one of the de-entanglement quantum logic gates.

5. The Dickle2 quantum state preparation method according to claim 2, characterized in that: The de-entanglement quantum circuit also includes a second controlled rotary gate acting after each of the de-entanglement quantum gates, the control bit of the second controlled rotary gate is the target bit of the first controlled rotary gate, and the target bit of the second controlled rotary gate is the control bit of the first controlled rotary gate.

6. The Dickle2 quantum state preparation method according to claim 5, characterized in that: The first controlled revolving door is a controlled Z-door, and the second controlled revolving door is a controlled X-door.

7. The Dickle2 quantum state preparation method according to claim 2, characterized in that: The target quantum circuit further comprises an H gate acting on all quantum bits, wherein the H gate is located after the multi-layer action sequence of the entangled quantum logic gate on the quantum bits.

8. A Dickle2 quantum state preparation device, characterized in that: The device comprises: The acquisition module is used to determine the quantum bits for preparing the Dickle2 quantum state; A de-entanglement quantum circuit construction module is used to construct a de-entanglement quantum circuit, wherein a plurality of de-entanglement quantum logic gates act on a quantum bit whose initial state is a Dickle2 quantum state to obtain a de-entanglement quantum circuit, wherein the action relationship between the de-entanglement quantum logic gate and the quantum bit in the latter layer of action sequence is determined by the action relationship between the de-entanglement quantum logic gate and the quantum bit in the previous layer of action sequence; A target quantum circuit construction module, used to determine the inverse circuit of the deentangled quantum circuit as the target quantum circuit; An operation module is used to operate the target quantum circuit to prepare the Dickle2 quantum state.

9. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to implement the method according to any one of claims 1 to 7 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to execute the computer program to implement the method according to any one of claims 1 to 7.

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