Test mode control circuit, control method and memory

Abstract

The embodiment of the invention provides a test mode control circuit, a control method and a memory, in the circuit, an address processing circuit is used for sampling mode register address information based on a mode register write signal to obtain a mode register address signal under the condition that an enable signal is in an enable state; decoding the mode register address signal to obtain a target address signal; the delay circuit is used for carrying out delay processing on the mode register write signal to obtain a shift mode register write signal; the sampling latch circuit is used for sampling and latching the operation code information based on the shift mode register write signal under the condition that the enable signal is in an enable state to obtain a target operation code signal; and the test circuit is used for performing logic processing on the target operation code signal, the shift mode register write signal and the target address signal, and generating and outputting a corresponding test signal. According to the embodiment of the invention, the delay can be reduced, and each command can work normally during the test mode.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a test mode control circuit, a control method and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements for data transmission speed when manufacturing and using computers and other equipment. In order to obtain faster data transmission speed, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.

[0003] In the fourth generation of Double Data Rate 4 (DDR4) and its previous Synchronous Dynamic Random Access Memory (SDRAM) technology, Design For Test (DFT) is limited by external pin (PIN) information and needs to issue two Mode Register Write (MRW) commands to generate test signals. However, the delay time between the two MRW commands is long, and other commands between the two MRW commands cannot work properly. Summary of the invention

[0004] Embodiments of the present disclosure provide a test mode control circuit, a control method, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a test mode control circuit, including:

[0006] an address processing circuit, configured to receive a mode register write signal, mode register address information and an enable signal, sample the mode register address information based on the mode register write signal to obtain a mode register address signal when the enable signal is in an enabled state, and decode the mode register address signal to obtain a target address signal; the enable signal indicates whether the mode is in a test mode;

[0007] A delay circuit, used for receiving the mode register write signal, delaying the mode register write signal, and obtaining a shift mode register write signal;

[0008] a sampling latch circuit, configured to receive the shift mode register write signal, the operation code information and the enable signal, and to sample and latch the operation code information based on the shift mode register write signal when the enable signal is in an enabled state, so as to obtain a target operation code signal;

[0009] The test circuit is used to receive the target operation code signal, the shift mode register write signal and the target address signal, and perform logic processing on the target operation code signal, the shift mode register write signal and the target address signal to generate and output a corresponding test signal.

[0010] In some embodiments, the test mode control circuit further includes a command decoding circuit, wherein:

[0011] The command decoding circuit is used to receive a mode register write command and a chip select signal, and decode the command information in the mode register write command based on the chip select signal to generate the mode register write signal;

[0012] The mode register write command lasts for two clock cycles of the clock signal. In the first clock cycle, the mode register write command includes the command information and the mode register address information. In the second clock cycle, the mode register write command includes the operation code information and the key information.

[0013] In some embodiments, the operation code information includes an N-bit operation code, the sampling latch circuit includes N first sampling sub-circuits, and the target operation code signal includes an N-bit target operation code, where N is an integer greater than 0, wherein:

[0014] The i-th first sampling sub-circuit is used to receive the enable signal, the shift mode register write signal and the i-th operation code, and when the enable signal is in an enabled state, sample the i-th operation code according to the shift mode register write signal to obtain the i-th target operation code;

[0015] Here, i is an integer greater than 0 and less than or equal to N.

[0016] In some embodiments, the mode register address information includes M-bit address data, the test mode control circuit includes S test circuits, M is an integer greater than 0, S is an integer greater than 0 and less than or equal to 2M, the target address signal includes S target address sub-signals, the S target address sub-signals correspond to the test circuits one by one, and the target address sub-signal indicates whether the corresponding test circuit is selected; each of the test circuits includes N test sub-circuits, and the test signal includes N test sub-signals, wherein:

[0017] The i-th test sub-circuit is used to receive the i-th target operation code, the shift mode register write signal and the corresponding target address sub-signal; perform logic processing according to the i-th target operation code and the corresponding target address sub-signal to generate the i-th sampling input signal, and perform logic processing according to the shift mode register write signal and the target address sub-signal to generate a sampling signal; perform sampling processing on the i-th sampling input signal according to the sampling signal to generate and output the i-th test sub-signal.

[0018] In some embodiments, the target address sub-signal includes at least one target address selection signal, and the i-th test sub-circuit includes a first logic circuit, a second logic circuit, a third logic circuit and a first latch circuit, wherein:

[0019] The first logic circuit is used to receive the at least one target address selection signal and generate an address enable signal according to the at least one target address selection signal; wherein, when the at least one target address selection signal is in a preset level state, the address enable signal is in an enabled state;

[0020] The second logic circuit is used to receive the i-th target operation code and the address enable signal, and generate the i-th sampling input signal according to the i-th target operation code and the address enable signal; wherein, when the address enable signal is in an enabled state, the level state of the i-th sampling input signal is the same as the level state of the i-th target operation code;

[0021] The third logic circuit is used to receive the shift mode register write signal and the address enable signal, and generate the sampling signal according to the shift mode register write signal and the address enable signal; when the address enable signal is in an enabled state, the level state of the sampling signal is the same as the level state of the shift mode register write signal;

[0022] The first latch circuit is used to receive the i-th sampling input signal and the sampling signal, and perform sampling processing on the i-th sampling input signal according to the sampling signal to generate the i-th test sub-signal.

[0023] In some embodiments, the first logic circuit includes a NAND gate, the second logic circuit includes a first NOT gate and a first NOR gate, and the third logic circuit includes a second NOT gate and a second NOR gate; wherein:

[0024] The input end of the NAND gate is used to receive the at least one target address selection signal, and the output end of the NAND gate is connected to the second input end of the first NOR gate and the first input end of the second NOR gate respectively; the output end of the NAND gate is used to output the address enable signal;

[0025] The input end of the first NOT gate is used to receive the i-th target operation code; the output end of the first NOT gate is connected to the first input end of the first NOR gate; the output end of the first NOR gate is used to output the i-th sampling input signal;

[0026] The input end of the second NOT gate is used to receive the shift mode register write signal; the output end of the second NOT gate is connected to the second input end of the second NOR gate; and the output end of the second NOR gate is used to output the sampling signal.

[0027] In some embodiments, the first latch circuit includes a second sampling subcircuit and a driving circuit, and the driving circuit includes an even number of third NOT gates, wherein:

[0028] The input end of the second sampling sub-circuit is used to receive the i-th sampling input signal, the clock end of the second sampling sub-circuit is used to receive the sampling signal, the output end of the second sampling sub-circuit is connected to the driving circuit, and the output end of the driving circuit is used to output the i-th test sub-signal.

[0029] In some embodiments, the i-th test sub-circuit is also used to receive the enable signal, and when the enable signal is in an enabled state, performs logical processing on the i-th target operation code, the shift mode register write signal and the target address signal to generate and output the i-th test sub-signal; when the enable signal is in a disabled state, the i-th test sub-signal is not output.

[0030] In some embodiments, the driving circuit also includes a first AND gate, wherein the first input terminal of the first AND gate is used to receive the enable signal, the second input terminal of the first AND gate is connected to the output terminal of the last of the third NOT gates, and the output terminal of the first AND gate is used to output the i-th test sub-signal.

[0031] In some embodiments, the first sampling subcircuit includes a D flip-flop, and the second sampling subcircuit includes a latch.

[0032] In some embodiments, the delay circuit is also used to receive the enable signal, and when the enable signal is in the enabled state, the mode register write signal is delayed so that the delay time of the shift mode register write signal compared to the mode register write signal is greater than or equal to one of the clock cycles and less than two of the clock cycles.

[0033] In some embodiments, the delay circuit comprises a shift register; wherein:

[0034] The shift register is used to receive the clock signal and the mode register write signal, and shift the mode register write signal based on the clock signal to delay the mode register write signal by one clock cycle to obtain the shift mode register write signal.

[0035] In some embodiments, the test mode control circuit further includes an enable signal generating circuit, wherein:

[0036] The enable signal generating circuit is used to continuously receive multiple key information and corresponding multiple mode register write signals in multiple mode register write commands, and generate and output the enable signal according to the multiple key information and corresponding multiple mode register write signals.

[0037] In some embodiments, the enable signal generating circuit includes a test mode start circuit and a second latch circuit; wherein:

[0038] The test mode start circuit is used to continuously receive the plurality of key information and the corresponding plurality of mode register write signals in the plurality of mode register write commands, and decode the corresponding key information in response to each mode register write signal to generate a plurality of key decoding signals; and generate a test mode start signal when the plurality of key decoding signals are respectively the same as a plurality of preset values;

[0039] The second latch circuit is used to receive the test mode start signal, latch the test mode start signal, and generate and output the enable signal.

[0040] In a second aspect, an embodiment of the present disclosure provides a control method, including:

[0041] receiving a mode register write signal, mode register address information and an enable signal through an address processing circuit, sampling the mode register address information based on the mode register write signal to obtain a mode register address signal when the enable signal is in an enabled state, and decoding the mode register address signal to obtain a target address signal; the enable signal indicates whether it is in a test mode;

[0042] receiving the mode register write signal through a delay circuit, delaying the mode register write signal, and obtaining a shift mode register write signal;

[0043] Receiving the shift mode register write signal, the operation code information and the enable signal through a sampling latch circuit, sampling and latching the operation code information based on the shift mode register write signal when the enable signal is in an enabled state, and obtaining a target operation code signal;

[0044] The target operation code signal, the shift mode register write signal and the target address signal are received by the test circuit, and the target operation code signal, the shift mode register write signal and the target address signal are logically processed to generate and output a corresponding test signal.

[0045] In a third aspect, an embodiment of the present disclosure provides a memory, which at least includes a test mode control circuit as described in any one of the first aspects.

[0046] The embodiments of the present disclosure provide a test mode control circuit, a control method and a memory, wherein the test mode control circuit comprises: an address processing circuit, which is used to receive a mode register write signal, a mode register address information and an enable signal, and when the enable signal is in an enabled state, the mode register address information is sampled based on the mode register write signal to obtain the mode register address signal, and the mode register address signal is decoded to obtain a target address signal; the enable signal indicates whether it is in a test mode; a delay circuit, which is used to receive the mode register write signal, and delay the mode register write signal to obtain a shift mode register write signal; a sampling latch circuit, which is used to receive the shift mode register write signal, an operation code information and an enable signal, and when the enable signal is in an enabled state, the operation code information is sampled and latched based on the shift mode register write signal to obtain a target operation code signal; and a test circuit, which is used to receive a target operation code signal, a shift mode register write signal and a target address signal, and logically processes the target operation code signal, the shift mode register write signal and the target address signal to generate and output a corresponding test signal. In this way, based on the test mode control circuit provided in this embodiment, when the circuit is in test mode, only one mode register write command is needed to generate and output a test signal, thereby not only reducing delays, shortening the test mode operation time, and saving command resources, but also ensuring that other commands can operate normally during the test mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of the structure of a test mode control circuit;

[0048] Figure 2 A signal timing diagram Figure 1 ;

[0049] Figure 3 A signal timing diagram Figure 2 ;

[0050] Figure 4 A schematic diagram of the structure of a test mode control circuit provided in an embodiment of the present disclosure Figure 1 ;

[0051] Figure 5 A schematic diagram of the structure of a test mode control circuit provided in an embodiment of the present disclosure Figure 2 ;

[0052] Figure 6 A schematic diagram of the structure of an address processing circuit provided in an embodiment of the present disclosure;

[0053] Figure 7 A schematic diagram of the composition structure of a first sampling sub-circuit provided in an embodiment of the present disclosure;

[0054] Figure 8 A schematic diagram of the structure of a test subcircuit provided in an embodiment of the present disclosure Figure 1 ;

[0055] Fig. 9 A signal timing diagram provided for an embodiment of the present disclosure Figure 1 ;

[0056] Fig.10 A schematic diagram of the structure of a test subcircuit provided in an embodiment of the present disclosure Figure 2 ;

[0057] Fig.11 A schematic diagram of the structure of a test subcircuit provided in an embodiment of the present disclosure Figure 3 ;

[0058] Fig.12 A schematic diagram of the structure of a delay circuit provided by an embodiment of the present disclosure;

[0059] Fig.13 A schematic diagram of the structure of a test mode control circuit provided in an embodiment of the present disclosure Figure 3 ;

[0060] Fig.14 A schematic diagram of the structure of an enable signal generating circuit provided in an embodiment of the present disclosure;

[0061] Fig.15 A detailed structural diagram of an enable signal generating circuit provided in an embodiment of the present disclosure;

[0062] Fig.16 A signal timing diagram provided for an embodiment of the present disclosure Figure 2 ;

[0063] Fig.17 A detailed structural diagram of a test mode control circuit provided in an embodiment of the present disclosure;

[0064] Fig.18 A signal timing diagram provided for an embodiment of the present disclosure Figure 3 ;

[0065] Fig.19 A flow chart of a control method provided by an embodiment of the present disclosure;

[0066] Fig. 20 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0069] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0070] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0071] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0072] Static Random Access Memory (SRAM);

[0073] Dynamic Random Access Memory (DRAM);

[0074] Synchronous Dynamic Random Access Memory (SDRAM);

[0075] Double Data Rate SDRAM (DDR SDRAM);

[0076] Double Data Rate (DDR);

[0077] The fourth generation of double data rate (Double Data Rate 4, DDR4);

[0078] The fifth generation of double data rate (Double Data Rate 5, DDR5);

[0079] Design for Test (DFT);

[0080] Mode Register Write (MRW);

[0081] Mode Register Address (MRA);

[0082] Operation code (Operand, OP);

[0083] Chip Select (CS);

[0084] Command / Address (CA);

[0085] Command (CMD);

[0086] Read (RD);

[0087] First Input First Output (FIFO);

[0088] Mode Register Read (MRR);

[0089] Data (DQ);

[0090] Row Address Strobe (RAS);

[0091] Column Address Strobe (CAS);

[0092] Write Enable (WE);

[0093] D flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF);

[0094] High level (High, H);

[0095] Low level (Low, L);

[0096] Valid level (Valid, V);

[0097] Test mode (TEST MODE).

[0098] In the field of integrated circuit testing technology, the testability design can be used to implement the testing of various dimensions of integrated circuit chips. Figure 1 , which shows a schematic diagram of the composition structure of a test mode control circuit. Figure 1 As shown, the test mode control circuit 10 includes an enable signal generating circuit 11, a positioning circuit 12 and a test circuit 13. The enable signal generating circuit 11 may include a first latch subcircuit 111, a second latch subcircuit 112, a third latch subcircuit 113 and a fourth latch subcircuit 114. The specific connection relationship is detailed in Figure 1 .like Figure 1 As shown, the enable signal generating circuit 11 is used to receive the first enable signal TMSET and generate the enable signal TM_EN; the positioning circuit 12 is used to receive the enable signal TM_EN and the operation code information OP, so as to locate the specific test circuit 13, and then the test circuit 13 generates the test signal TM_SIGNAL.

[0099] like Figure 1 As shown, the first latch subcircuit 111 can be represented by DFTKEY_0, the second latch subcircuit 112 can be represented by DFTKEY_1, the third latch subcircuit 113 can be represented by DFTKEY_2, the fourth latch subcircuit 114 can be represented by SR_LATCH, the positioning circuit 12 can be represented by MASTER&SLAVE, and the test circuit 13 can be represented by DFT_UNIT.

[0100] Table 1 shows some commands of DDR4. Among them, CKE represents the clock signal, CS_n represents the chip select signal, ACT_n represents the activation signal, RAS_n represents the row address strobe pulse signal, CAS_n represents the column address strobe pulse signal, WE_n represents the write enable signal, and A0-A16 represents the address information. In Table 1, the command signal can be decoded according to the CS_n signal and the WE_n / A14 signal, and the operation code information OP is carried in A0-A13. It should be noted that the commands in DDR4 are all single-cycle commands (1-cycle commands), that is, the command will only be sent when the chip select signal is in a low state.

[0101] Table 1

[0102] CKE CS_n ACT_n RAS_n / A16 CAS_n / A15 WE_n / A14 A0-A13

[0103] It should be noted that Figure 1 The detailed information of the circuit and the input and output signals are omitted in the figure, which is only a brief circuit block diagram. Specifically, for the first latch sub-circuit 111, TMKEY is generated by the Guard Key0 signal. <0> Signal; For the second latch sub-circuit 112, it is generated by the Guard Key1 signal TMKEY <1> For the third latch sub-circuit 113, it is generated by Guard Key2 signal TMKEY <2> Here, each Guard Key signal can be obtained by decoding the operation code information OP. <0> After the signal, TMKEY <0> The signal is transmitted to the second latch sub-circuit 112, and TMKEY is generated according to the Guard Key1 signal only when the Guard Key0 signal is valid. <1> signal; and so on, TMKEY <1> The signal is transmitted to the third latch sub-circuit 113, and TMKEY is generated according to the Guard Key2 signal only when the Guard Key1 signal is valid. <2> Signal, that is, the enable signal TM_EN is generated through three Guard Key signals (Guard Key0 signal, Guard Key1 signal and Guard Key2 signal).

[0104] It should also be noted that the test circuit 13 includes a plurality of test sub-circuits, and the operation code information may include an 8-bit operation code OP <0> To OP <7> , multiple test sub-circuits correspond to each opcode in the opcode information OP<7:0>. After entering the test mode according to the enable signal TM_EN, in order to meet the number of test signals TM_SIGNAL required for chip design work, in the positioning circuit 12, it is necessary to first latch the opcode information OP<7:0> through the slave command (SLAVE_CMD, SLAVE command), and then use the master command (MASTER_CMD, MASTER command) to locate the specific test sub-circuit in the test circuit 13, and combine the opcode information OP<7:0> carried by the SLAVE command to enable a specific test signal TM_SIGNAL. Among them, the SLAVE command and the MASTER command are both MRW commands.

[0105] Since the commands in DDR4 are all single-cycle commands and the external pin information is limited, in the previous technology, due to the limitation of external pin information, it is necessary to issue a SLAVE command to latch the 8-bit operation code information OP<7:0>, and then issue a MASTER command, and use the operation code information OP<7:0> carried by the SLAVE command to decode and locate the specific test sub-circuit in the corresponding test circuit 13 to enable a specific test signal TM_SIGNAL.

[0106] based on Figure 1 The test mode control circuit 10 shown in FIG. 1 has a corresponding signal timing as shown in FIG. Figure 2 As shown. Figure 2 As shown, TMKEY <0> Signal, TMKEY <1> Signals and TMKEY <2> There is a certain delay time between the signals; the operation code information OP carried by SLAVE_CMD can be represented by SLAVE_OP, specifically SLAVE_OP<7:0>; the address of the test circuit 13 can be represented by TM_UNIT_ADDR. For example, Figure 2 As shown, the address of a test circuit 13 is TMSRAF0 / 3 / 6T<7:0>. In addition, an MRR command may be issued between SLAVE_CMD and MASTER_CMD, but the MRR command cannot work normally.

[0107] Figure 3 A signal timing diagram is shown. Figure 2 , specifically a control timing diagram of the MRW command specified in a standard. Figure 3 As shown, the time between two adjacent MRW commands is represented by tMRW, and the time between the MRW command and the next valid command (VALID) is represented by tMRD.

[0108] In DDR4, the MRW command is a single-cycle command, and two single-cycle MRW commands are required to generate a test signal. The DDR4 standard stipulates that the interval between two consecutive MRW commands is 8tck, where tck represents the clock cycle of the system clock signal. In DDR5, the MRW command is a two-cycle command. When using a two-cycle MRW command to generate a test signal, the circuit applied to DDR4 is no longer suitable. Table 2 shows the information of the command / address signal in DDR5.

[0109] Table 2

[0110]

[0111] In Table 2, CS_n represents a chip select signal, CA0-CA13 represent command / address signals, CW represents a control signal, High / H represents a high level state, Low / L represents a low level state, and V represents a valid level state.

[0112] In the design of the test mode control circuit 10, after entering the test mode through three consecutive Guard Key signals, two commands need to be issued, namely the SLAVE command and the MASTER command, that is, at least 16 tcks are required to enable the test signal TM_SIGNAL. At the same time, after entering the test mode, in order to reduce power consumption, the chip will turn off the circuit used to generate the internal clock (which can be represented by PDL). The clock signal generated by this circuit is used to control the read command (such as MRR command) and other signals inside the chip. If this circuit is turned off, no clock signal for the read command is generated, which will stop the working clock signal of the FIFO structure from flipping. In this way, if the controller sends commands such as MRR between the SLAVE command and the MASTER command, these commands will not work properly, and the data cannot be correctly read out and sent to the DQ end.

[0113] Based on this, the embodiment of the present disclosure provides a test mode control circuit, which includes: an address processing circuit for sampling the mode register address information based on the mode register write signal to obtain the mode register address signal when the enable signal is in the enable state, and decoding the mode register address signal to obtain the target address signal; the enable signal indicates whether it is in the test mode; the delay circuit is used to delay the mode register write signal to obtain the shift mode register write signal; the sampling latch circuit is used to sample and latch the operation code information based on the shift mode register write signal when the enable signal is in the enable state to obtain the target operation code signal; the test circuit is used to perform logical processing on the target operation code signal, the shift mode register write signal and the target address signal to generate and output the corresponding test signal. In this way, based on the test mode control circuit provided by this embodiment, when the circuit is in the test mode, only one mode register write command is needed to generate and output the test signal, thereby not only reducing the delay, shortening the test mode operation time, saving command resources, but also ensuring that other commands can work normally during the test mode.

[0114] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0115] In one embodiment of the present disclosure, see Figure 4 , which shows a schematic diagram of the composition structure of a test mode control circuit provided by an embodiment of the present disclosure Figure 1 .like Figure 4 As shown, the test mode control circuit 20 may include:

[0116] The address processing circuit 21 is used to receive a mode register write signal, mode register address information and an enable signal, and when the enable signal is in an enabled state, the mode register address information is sampled based on the mode register write signal to obtain a mode register address signal, and the mode register address signal is decoded to obtain a target address signal; the enable signal indicates whether it is in a test mode;

[0117] The delay circuit 22 is used to receive the mode register write signal, delay the mode register write signal, and obtain the shift mode register write signal;

[0118] The sampling latch circuit 23 is used to receive the shift mode register write signal, the operation code information and the enable signal, and when the enable signal is in the enabled state, the operation code information is sampled and latched based on the shift mode register write signal to obtain the target operation code signal;

[0119] The test circuit 24 is used to receive the target operation code signal, the shift mode register write signal and the target address signal, and perform logic processing on the target operation code signal, the shift mode register write signal and the target address signal to generate and output a corresponding test signal.

[0120] It should be noted that, in this embodiment, the test mode control circuit 20 can be applied to a memory. The memory can be, for example, SRAM, DRAM, SDRAM, DDR SDRAM, etc., without specific limitation. In addition, this embodiment specifically relates to a circuit related to the testability design operation control in an integrated circuit, and can be applied to a control circuit of the testability design in a DRAM chip, without specific limitation.

[0121] In this embodiment, the mode register write signal is represented by MRW, the mode register address information is represented by MRA, the enable signal is represented by TM_EN, the shift mode register write signal is represented by MRW_SHIFT, the operation code information is represented by OP, and the test signal is represented by TM_SIGNAL.

[0122] For example, the specific implementation of the embodiment of the present disclosure is described in detail by taking the mode register address information including 8-bit address data as an example. In this case, the mode register address information can be recorded as MRA<7:0>, where MRA<7:0> is MRA <0> to MRA <7> A total of 8 bits of address data are written in a combined manner.

[0123] In this embodiment, the enable signal is used to indicate whether the chip to which the test mode control circuit 20 belongs is in the test mode, and whether the control mode control circuit 20 enters the test mode to work is determined according to whether the enable signal is in the enabled state or the disabled state. If the enable signal is in the enabled state, the test mode control circuit 20 can be placed in the test mode to output the test signal; if the enable signal is in the disabled state, the test mode control circuit 20 can be placed in the test mode and not output the test signal (or output an invalid test signal); that is, only when the enable signal is in the enabled state, the test mode control circuit 20 will work normally and generate and output the test signal.

[0124] like Figure 4As shown, in the test mode control circuit 20, the target address signal is obtained through the address processing circuit 21, the shift mode register write signal is obtained through the delay circuit 22, and the target operation code signal is obtained through the sampling latch circuit 23. The test circuit 24 performs logical processing on the target operation code signal, the shift mode register write signal and the target address signal to generate and output a corresponding test signal, so that the test signal can be obtained by using a mode register write command, which reduces the delay, shortens the test mode operation time, saves command resources, and eliminates the risk of other commands failing to work during the enabling of the test mode.

[0125] exist Figure 4 Based on Figure 5 , which shows a schematic diagram of the composition structure of a test mode control circuit provided by an embodiment of the present disclosure Figure 2 .like Figure 5 As shown, in some embodiments, the test mode control circuit 20 may further include a command decoding circuit 25, wherein:

[0126] The command decoding circuit 25 is used to receive a mode register write command and a chip select signal, and decode the command information in the mode register write command based on the chip select signal to generate a mode register write signal; wherein the mode register write command lasts for two clock cycles of the clock signal, in the first clock cycle, the mode register write command includes command information and mode register address information, and in the second clock cycle, the mode register write command includes operation code information and key information.

[0127] Here, the clock signal refers to the system clock signal, and its clock cycle can be represented by tck. The period of the chip select signal is two clock cycles, represented by 2tck; in the first clock cycle, the chip select signal is in the first level state, and in the second clock cycle, the chip select signal is in the second level state. Among them, the first level state can be a low level state (logic 0), and the second level state can be a high level state (logic 1).

[0128] In this embodiment, the mode register write command may be a command / address signal. As shown in Table 2 above, MRA0-MAR7 represent the mode register address information, OP0-OP7 represent the operation code information, and the key information may include CA8, CA9, CA11, and CA12. When the chip select signal is in the first level state (Low), CA0-CA4 is the command information. When CA0-CA4 meets the level state shown in Table 2 and CS_n is Low, the command information is decoded to obtain the mode register write signal.

[0129] In this embodiment, the mode register address information received by the address processing circuit 21 and the operation code information received by the sampling latch circuit 23 are carried by the same mode register write command.

[0130] For the address processing circuit 21, see Figure 6 , which shows a schematic diagram of the structure of an address processing circuit provided by an embodiment of the present disclosure, such as Figure 6 As shown, in some embodiments, the address processing circuit 21 may include an address latch circuit 211 and an address decoding circuit 212, wherein:

[0131] The address latch circuit 211 is used to receive a mode register write signal, mode register address information and an enable signal, and when the enable signal is in an enabled state, sample the mode register address information based on the mode register write signal to generate a mode register address signal;

[0132] The address decoding circuit 212 is used to receive the mode register address signal and decode the mode register address signal to obtain a target address signal.

[0133] It should be noted that, in the address processing circuit 21, the mode register address information needs to be latched as a mode register address signal first, and then the mode register address signal is decoded into a target address signal. Among them, the address latch circuit 211 is represented by MRA LATCH, which can be implemented by devices such as latches or triggers; the address decoding circuit 212 is represented by MRADEC, which can be implemented by a combination of logic gates, and the specific decoding method can refer to the relevant technology.

[0134] In some embodiments, the operation code information may include an N-bit operation code, the sampling latch circuit 23 may include N first sampling sub-circuits 231, and the target operation code signal may include an N-bit target operation code, where N is an integer greater than 0, wherein:

[0135] The i-th first sampling sub-circuit 231 is used to receive the enable signal, the shift mode register write signal and the i-th operation code, and when the enable signal is in the enabled state, sample the i-th operation code according to the shift mode register write signal to obtain the i-th target operation code;

[0136] Here, i is an integer greater than 0 and less than or equal to N.

[0137] It should be noted that when the operation code information includes N bits (or N) of operation codes, the sampling latch circuit 23 correspondingly includes N first sampling sub-circuits 231, and each first sampling sub-circuit 231 samples each bit of the N-bit operation code to obtain the corresponding target operation code to form a target operation code signal.

[0138] Exemplarily, as shown in Table 2, the operation code information includes 8-bit operation codes from OP0 to OP7. At this time, the operation code information can be specifically represented by OP<7:0>. This embodiment takes N=8 as an example, but is not limited thereto. When the operation code information includes an 8-bit operation code, there are 8 first sampling sub-circuits 231 for sampling each bit of the operation code in OP<7:0> respectively.

[0139] In addition, when the operation code information includes an 8-bit operation code, the target operation code signal also includes an 8-bit target operation code, and each bit of the target operation code corresponds to a test signal.

[0140] In some embodiments, for the first sampling subcircuit 231, see Figure 7 , which shows a schematic diagram of the composition structure of a first sampling sub-circuit provided by an embodiment of the present disclosure. Figure 7 As shown, the first sampling subcircuit 231 may include a D flip-flop 2311; wherein:

[0141] The D flip-flop 2311 is used to receive the shift mode register write signal and the i-th operation code, and to sample and process the i-th operation code based on the shift mode register write signal to obtain the i-th target operation code.

[0142] It should be noted that the D flip-flop 2311 is an information storage device with a memory function and two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits and is also an important unit circuit in digital logic circuits. Here, the D flip-flop has two stable states, namely "0" and "1", and can flip from one stable state to another stable state under the action of the signal received at the clock end.

[0143] It should also be noted that the D flip-flop 2311 may include a clock terminal (CK), an input terminal (D), and an output terminal (Q); in addition, it may also include a set terminal (SET) and a reset terminal (RST), etc., but they are not shown in the figure. Here, the clock terminal of the D flip-flop 2311 is used to receive a shift mode register write signal, the input terminal of the D flip-flop 2311 is used to receive the i-th operation code, and the output terminal of the D flip-flop 2311 is used to output the i-th target operation code.

[0144] Here, the first sampling subcircuit 231 may also be a latch or other device with a sampling function, that is, the i-th operation code may be sampled and processed by the latch to obtain the i-th target operation code, and no specific limitation is made to this.

[0145] In some embodiments, the mode register address information includes M-bit address data, the test mode control circuit 20 includes S test circuits 24, M is an integer greater than 0, and S is an integer greater than 0 and less than or equal to 2. M The target address signal includes S target address sub-signals, the S target address sub-signals correspond to the test circuits 24 one by one, and the target address sub-signals indicate whether the corresponding test circuit is selected; each test circuit 24 may include N test sub-circuits 241, and the test signal may include N test sub-signals. Figure 8 , which shows a schematic diagram of the composition structure of a test sub-circuit provided in an embodiment of the present disclosure Figure 1 ,like Figure 8 As shown, the i-th test sub-circuit 241 is used to receive the i-th target operation code, the shift mode register write signal and the corresponding target address sub-signal; perform logic processing according to the i-th target operation code and the corresponding target address sub-signal to generate the i-th sampling input signal, and perform logic processing according to the shift mode register write signal and the target address sub-signal to generate the sampling signal; perform sampling processing on the i-th sampling input signal according to the sampling signal, and generate and output the i-th test sub-signal.

[0146] It should be noted that the target address sub-signal is used to locate the test circuit 24. When the mode register address information includes M-bit address data, each address data has two level states, high level and low level, and thus when decoding, at most 2 M Decoding results, corresponding to up to 2 M Taking Table 2 as an example, M = 8, the mode register address information is MRA<7:0>, and MRA<7:0> is sampled and decoded. The output target address sub-signal can have at most 2 to the power of 8 (2 8 ) types, each target address sub-signal corresponds to a test circuit 24, that is, there can be at most 2 8 Here, the number of target address sub-signals and test circuits 24 is the same and is less than or equal to 2. 8 There is no limitation on the number of target address sub-signals and test circuits 24, which can be set according to the actual situation of the circuit.

[0147] It should also be noted that, in this embodiment, the target operation code signal includes an 8-bit target operation code as an example, and the corresponding test circuit 24 includes 8 test sub-circuits 241. In addition, for the test sub-circuits 241 in the test circuit 24, only the received target operation codes are different, and the other received signals and circuit structures are the same, that is, different test sub-circuits 241 are used to receive different target operation codes and obtain different test sub-signals.

[0148] After locating the specific test circuit 24 according to the target address sub-signal, the test circuit 24 includes 8 test sub-circuits 241, and each test sub-circuit 241 corresponds to a target opcode. In other words, each test circuit 24 receives an 8-bit target opcode, transmits it to the corresponding test sub-circuit 241, and generates a corresponding test sub-signal; illustratively, if the target address sub-signal has two conditions and a 2-bit target opcode is required, a total of 4 test sub-signals will be generated and output, so that specific test sub-signals can be enabled according to the actual situation through the required target opcode, making the circuit structure simple.

[0149] In some embodiments, Figure 8 As shown, the target address signal includes S target address sub-signals, each target address sub-signal includes at least one target address selection signal, and the i-th test sub-circuit 241 may include a first logic circuit 2411, a second logic circuit 2412, a third logic circuit 2413 and a first latch circuit 2414, wherein:

[0150] The first logic circuit 2411 is used to receive at least one target address selection signal, and generate an address enable signal according to the at least one target address selection signal; wherein, when the at least one target address selection signal is in a preset level state, the address enable signal is in an enabled state;

[0151] The second logic circuit 2412 is used to receive the i-th target operation code and the address enable signal, and generate the i-th sampling input signal according to the i-th target operation code and the address enable signal; wherein, when the address enable signal is in an enabled state, the level state of the i-th sampling input signal is the same as the level state of the i-th target operation code;

[0152] The third logic circuit 2413 is used to receive the shift mode register write signal and the address enable signal, and generate a sampling signal according to the shift mode register write signal and the address enable signal; when the address enable signal is in an enabled state, the level state of the sampling signal is the same as the level state of the shift mode register write signal;

[0153] The first latch circuit 2414 is used to receive the i-th sampling input signal and the sampling signal, perform sampling processing on the i-th sampling input signal according to the sampling signal, and generate the i-th test sub-signal.

[0154] It should be noted that if Figure 8As shown, exemplarily, the target address sub-signal includes three target address selection signals, namely MRA20, MRA53 and MRA76; wherein MRA20 represents the target address selection signal decoded from MRA<2:0> in the mode register address information MRA<7:0>, MRA53 represents the target address selection signal decoded from MRA<5:3> in the mode register address information MRA<7:0>, and MRA76 represents the target address selection signal decoded from MRA<7:6> in the mode register address information MRA<7:0>. That is, the 8-bit mode register address information MRA<7:0> is split into MRA<2:0>, MRA<5:3> and MRA<7:6>, i.e., a combination of 3 bits, 3 bits and 2 bits, and after respectively decoding MRA<2:0>, MRA<5:3> and MRA<7:6>, 3 corresponding target address selection signals are obtained respectively to form a set of target address sub-signals.

[0155] After the mode register address signal is generated by the address latch circuit, the mode register address signal is decoded by the address decoding circuit to obtain the target address signal. Exemplarily, when the target address sub-signal includes three target address selection signals, namely, MRA20, MRA53 and MRA76, all of the three target address selection signals are set to a high level state (logic 1) to locate the test circuit 24. It can be understood that if the mode register address information MRA<7:0> is split and at least one target address selection signal is generated, the test circuit 24 is located by setting all the target address selection signals in one of the S target address sub-signals to a high level state (logic 1); if the mode register address information MRA<7:0> is not split, the obtained target address sub-signal is set to a high level state (logic 1) to locate the test circuit 24.

[0156] It can be seen that in this embodiment, the mode register address information MRA<7:0> can be split to generate at least one target address selection signal, but the splitting method of the mode register address information MRA<7:0> is not limited, and the above splitting method is only an example; or, the mode register address information MRA<7:0> may not be split, and it may be directly decoded to obtain the target address sub-signal, and there is no specific limitation on this. It can be understood that splitting the mode register address information MRA<7:0> to generate at least one target address selection signal can save the area of ​​the address processing circuit 21, which is beneficial to circuit design and saves costs.

[0157] Regarding the specific composition of the test sub-circuit 241, in some embodiments, as Figure 8As shown, the first logic circuit 2411 may include a NAND gate U1, the second logic circuit 2412 may include a first NOT gate U2 and a first NOR gate U3, and the third logic circuit 2413 may include a second NOT gate U4 and a second NOR gate U5; wherein:

[0158] The input end of the NAND gate U1 is used to receive at least one target address selection signal, and the output end of the NAND gate U1 is connected to the second input end of the first NOR gate U3 and the first input end of the second NOR gate U5 respectively; the output end of the NAND gate U1 is used to output an address enable signal;

[0159] The input end of the first NOT gate U2 is used to receive the i-th target operation code; the output end of the first NOT gate U2 is connected to the first input end of the first NOR gate U3; the output end of the first NOR gate U3 is used to output the i-th sampling input signal;

[0160] The input end of the second NOT gate U4 is used to receive the shift mode register write signal; the output end of the second NOT gate U4 is connected to the second input end of the second NOR gate U5; the output end of the second NOR gate U5 is used to output the sampling signal.

[0161] It should be noted that, by way of example, Figure 8 In the embodiment, the input end of the NAND gate U1 is used to receive three target address selection signals, namely MRA20, MRA53 and MRA76.

[0162] Among them, the input end of the first NOT gate U2 serves as the first input end of the second logic circuit 2412, for receiving the i-th target operation code; the second input end of the first NOR gate U3 serves as the second input end of the second logic circuit 2412, for receiving the address enable signal; the output end of the first NOR gate U3 serves as the output end of the second logic circuit 2412, for outputting the i-th sampling input signal; the input end of the second NOR gate U4 serves as the first input end of the third logic circuit 2413, for receiving the shift mode register write signal; the first input end of the second NOR gate U5 serves as the second input end of the third logic circuit 2413, for receiving the address enable signal; the output end of the second NOR gate U5 serves as the output end of the third logic circuit 2413, for outputting the sampling signal.

[0163] Furthermore, in some embodiments, Figure 8 As shown, the first latch circuit 2414 may include a second sampling subcircuit U6 and a driving circuit U7. The driving circuit U7 may include an even number of third NOT gates a1, wherein:

[0164] The input end of the second sampling subcircuit U6 is used to receive the i-th sampling input signal, the clock end of the second sampling subcircuit U6 is used to receive the sampling signal, the output end of the second sampling subcircuit U6 is connected to the driving circuit U7, and the output end of the driving circuit U7 is used to output the i-th test sub-signal.

[0165] In some embodiments, Figure 8 As shown, the second sampling subcircuit U6 may include a latch a2.

[0166] It should be noted that in the embodiment of the present disclosure, for latch a2, it may include a control terminal (CK), an input terminal (D), and an output terminal (Q); in addition, it may also include a set terminal (SET) and a reset terminal (RST), etc., but they are not shown in the figure. In addition, when the sampling signal input by the control terminal is at a high level, the sampling signal samples the i-th sampling input signal to generate the i-th test sub-signal.

[0167] In addition, the second sampling sub-circuit U6 may also receive the i-th sampling input signal and the sampling signal through a D flip-flop to implement sampling, but this is not specifically limited.

[0168] It should also be noted that, in the embodiment of the present disclosure, the driving circuit U7 can be composed of two third NOT gates a1, or four, or six, eight, etc., third NOT gates a1 connected in series, which is not specifically limited in the embodiment of the present disclosure. Figure 8 In the embodiment, the specific implementation of the embodiment of the present disclosure is described in detail by taking the driving circuit U7 consisting of two third NOT gates a1 as an example.

[0169] Here, because the driving circuit U7 includes an even number of third NOT gates a1, the signal output from the output end of the second sampling sub-circuit U6 is delayed. In addition, the delay time between the signal input to the driving circuit U7 and the i-th test sub-signal output is related to the specific number of the third NOT gates a1 in the driving circuit U7. The number of the third NOT gates a1 in the driving circuit U7 is different, and the delay time between the signal input to the driving circuit U7 and the i-th test sub-signal output is different. In this way, the embodiment of the present disclosure can determine the specific number of the third NOT gates a1 in the driving circuit U7 according to the required delay time.

[0170] Alternatively, in this embodiment, the first NOR gate U3 and the second NOR gate U5 may be replaced by OR gates, and devices for inverting processing may be added to the control end and output end of the latch a2 to achieve corresponding functions, which is not specifically limited here.

[0171] based on Figure 8 The test subcircuit 241 shown in FIG. Fig. 9 As shown. Fig. 9As shown, when MRA20, MRA53 and MRA76 are all in high level state, the generated address enable signal is in low level state; the i-th sampling input signal is obtained by performing an OR-NO logic operation on the inverted i-th target opcode and the address enable signal; the sampling signal is obtained by performing an OR-NO logic operation on the inverted shift mode register write signal and the address enable signal; then the i-th sampling input signal is sampled and processed according to the sampling signal to generate the i-th test sub-signal. Here, the i-th target opcode is also in high level state; in addition, the mode register write signal is shifted to obtain the shift mode register write signal. It can be seen that the mode register write signal and the i-th target opcode are not synchronized in timing, and the i-th target opcode cannot be sampled, while the shift mode register write signal after shifting is synchronized in timing with the i-th target opcode, and the i-th target opcode can be sampled.

[0172] exist Figure 8 Based on Fig.10 , which shows a schematic diagram of the composition structure of a test sub-circuit provided in an embodiment of the present disclosure Figure 2 ,like Fig.10 As shown, in some embodiments, the i-th test sub-circuit 241 is also used to receive an enable signal, and when the enable signal is in an enabled state, the i-th target operation code, the shift mode register write signal and the target address signal are logically processed to generate and output the i-th test sub-signal; when the enable signal is in a disabled state, the i-th test sub-signal is not output.

[0173] It should be noted that the test sub-circuit 241 controls whether to generate a test sub-signal according to whether the enable signal is in an enabled state or a disabled state; specifically, if the enable signal is in an enabled state, the test sub-circuit 241 can be controlled to output the test sub-signal; if the enable signal is in a disabled state, the test sub-circuit 241 does not output the i-th test sub-signal (or outputs an invalid test signal).

[0174] Furthermore, in some embodiments, Fig.10 As shown, the driving circuit U7 may further include a first AND gate a3, a first input terminal of the first AND gate a3 being used to receive an enable signal, a second input terminal of the first AND gate a3 being connected to an output terminal of the last third NOT gate a1, and an output terminal of the first AND gate a3 being used to output the i-th test sub-signal.

[0175] It should be noted that, for the test sub-circuit 241, the input of the enable signal can be implemented not only through the first AND gate a3, but also through other methods, which are not specifically limited.

[0176] In another implementation, Figure 8Based on Fig.11 , which shows a schematic diagram of the composition structure of a test sub-circuit provided in an embodiment of the present disclosure Figure 3 ,like Fig.11 As shown, the first NOR gate U3 and the second NOR gate U5 include three input terminals, wherein: the third input terminal of the first NOR gate U3 is used to receive the inverted signal of the enable signal, and the third input terminal of the second NOR gate U5 is used to receive the inverted signal of the enable signal.

[0177] It should be noted that, in the embodiment of the present disclosure, the second logic circuit 2412 may further include a fourth NOT gate U8, and the third logic circuit 2413 may further include a fifth NOT gate U9. The input end of the fourth NOT gate U8 is used to receive an enable signal, and the output end of the fourth NOT gate U8 is connected to the third input end of the first NOR gate U3; similarly, the input end of the fifth NOT gate U9 is used to receive an enable signal, and the output end of the fifth NOT gate U9 is connected to the third input end of the second NOR gate U5.

[0178] In some embodiments, the delay circuit 22 is also used to receive an enable signal, and when the enable signal is in an enabled state, the mode register write signal is delayed so that the delay time of the shift mode register write signal compared to the mode register write signal is greater than or equal to one clock cycle and less than two clock cycles.

[0179] It should be noted that in the embodiment of the present disclosure, the delay circuit 22 can also determine whether to delay the mode register write signal according to whether the enable signal is in an enabled state or a disabled state; specifically, if the enable signal is in an enabled state, the delay circuit 22 generates a shift mode register write signal; if the enable signal is in a disabled state, the delay circuit 22 does not generate a shift mode register write signal.

[0180] Specifically, in the first clock cycle of the clock signal, the command information in the mode register write command is decoded based on the chip select signal to generate a mode register write signal; in the second clock cycle of the clock signal, the mode register write command includes the operation code information, and the sampling latch circuit samples and latches the operation code information based on the shift mode register write signal to obtain the target operation code signal, so the timing of the mode register write signal and the target operation code signal differs by at least one clock cycle. When the delay circuit 22 makes the delay time of the shift mode register write signal compared to the mode register write signal greater than or equal to one clock cycle and less than two clock cycles, the timing of the shift mode register write signal and the target operation code signal can be synchronized, and then the test signal is generated and output through the test circuit 24. Here, timing synchronization refers to the simultaneous change of the level states of the shift mode register write signal and the target operation code signal. Among them, the "timing synchronization" and "simultaneous" described in the embodiments of the present disclosure refer to the timing deviation being within a preset accuracy range.

[0181] Further, see Fig.12 , which shows a schematic diagram of the composition structure of a delay circuit provided by an embodiment of the present disclosure, such as Fig.12 As shown, in some embodiments, the delay circuit 22 may include a shift register 221; wherein:

[0182] The shift register 221 is used to receive the clock signal and the mode register write signal, and shift the mode register write signal based on the clock signal to delay the mode register write signal by one clock cycle to obtain a shifted mode register write signal.

[0183] It should be noted that the shift register 221 may be a D flip-flop or a D latch or other devices with a sampling function, which is not specifically limited.

[0184] In some embodiments, in the second clock cycle of the clock signal, the mode register write command also includes key information. Figure 5 Based on Fig.13 , which shows a schematic diagram of the composition structure of a test mode control circuit provided by an embodiment of the present disclosure Figure 3 .like Fig.13 As shown, the test mode control circuit 20 may further include an enable signal generating circuit 26, wherein:

[0185] The enable signal generating circuit 26 is used to continuously receive multiple key information and corresponding multiple mode register write signals in multiple mode register write commands, and generate and output an enable signal according to the multiple key information and the corresponding multiple mode register write signals.

[0186] Taking Table 2 as an example, the key information may be the four pin information of CA8, CA9, CA11 and CA12 corresponding to the high level state of the CS_n signal. As shown in Table 2, when the CS_n signal is in the high level state, the command / address signal is in the valid level state (V) for the valid bits, such as CA8, CA9, CA11, CA12 and CA13, etc., and the valid bits can be fully utilized as key bits, and the pin information of the valid bits can be used as key information. It can be understood that when the number of bits included in the key information is more, the security is higher, and there is no limitation on the specific number of bits of the key information.

[0187] It should also be noted that in the embodiments of the present disclosure, the key information included in multiple mode register write commands is the same. When certain conditions are met, an enable signal can be generated to actively enter the test mode, which can prevent attacks or misoperations from entering the test mode.

[0188] In addition, in DDR4, at most two pin information of A12 and A13 can be used as key information; while in DDR5, the four pin information of CA8, CA9, CA11 and CA12 corresponding to the high level state of the CS_n signal can be used as key information. In this way, the key information is changed from the original 2-bit key information to 4-bit key information, and the number of bits included in the key information is increased, thereby enhancing security.

[0189] In some embodiments, for the enable signal generating circuit 26, see Fig.14 , which shows a schematic diagram of the structure of an enable signal generating circuit provided by an embodiment of the present disclosure. Fig.14 As shown, the enable signal generating circuit 26 may include a test mode starting circuit 261 and a second latch circuit 262; wherein:

[0190] The test mode start circuit 261 is used to continuously receive multiple key information and corresponding multiple mode register write signals in multiple mode register write commands, and decode the corresponding key information in response to each mode register write signal to generate multiple key decoding signals; when the multiple key decoding signals are respectively the same as multiple preset values, generate a test mode start signal;

[0191] The second latch circuit 262 is used to receive the test mode start signal, latch the test mode start signal, and generate and output an enable signal.

[0192] When the plurality of key decoding signals are respectively identical to the plurality of preset values, in this case, the enable signal is in an enable state, and the mode control circuit 20 is in a test mode.

[0193] Furthermore, if Fig.14As shown, the test mode startup circuit 261 may include a first startup subcircuit b1, a second startup subcircuit b2 and a third startup subcircuit b3, wherein:

[0194] The first start sub-circuit b1 is used to receive the first enable signal TMSET and generate a first key decoding signal TMKEY <0> The second start sub-circuit b2 is used to receive the first key decoding signal TMKEY <0> signal, generating a second key decoding signal TMKEY <1> signal, the third start sub-circuit b3 is used to receive the second key decoding signal TMKEY <1> Signal, generates a test mode start signal.

[0195] It should be noted that if Fig.14 As shown, the first start sub-circuit b1 is represented by DFTKEY_0, the second start sub-circuit b2 is represented by DFTKEY_1, the third start sub-circuit b3 is represented by DFTKEY_2, the second latch circuit 262 is represented by SR_LATCH; the test mode start signal is represented by TMKEY <2> Indicates that the enable signal is represented by TM_EN.

[0196] It should also be noted that Fig.14 Some signals are omitted. Fig.14 For further refinement, see Fig.15 , which is a detailed structural diagram of an enable signal generating circuit provided by an embodiment of the present disclosure. Fig.15 As shown in (a) in FIG. 1 , a first enable signal TMSET is generated according to the key information CA<8,9,11,12>, the control signal CW and the MRW command; Fig.15 As shown in (b), the first key decoding signal TMKEY is generated according to the operation code information OP<7:0> carried by the first MRW command after the first enable signal TMSET is generated and the first enable signal TMSET. <0> ;like Fig.15 As shown in (c) of FIG. 1 , according to the operation code information OP<7:0> carried by the second MRW command after the first enable signal TMSET is generated, the first key decoding signal TMKEY <0> and the first enable signal TMSET to generate a second key decoding signal TMKEY <1> ;like Fig.15 As shown in (d) in FIG. 1 , according to the operation code information OP<7:0> carried by the third MRW command after the first enable signal TMSET is generated, the second key decoding signal TMKEY <1> and the first enable signal TMSET to generate a test mode start signal TMKEY <2> ;like Fig.15 As shown in (e), the test mode start signal TMKEY <2> A latching process is performed to generate an enable signal TM_EN.

[0197] exist Fig.15In the figure, DEC1 and DEC2 represent decoding circuits for decoding received signals, wherein DEC1 is used to decode key information CA<8,9,11,12> and control signal CW, and DEC2 is used to decode operation code information OP<7:0> carried by MRW command; VDD represents a high level signal, and VSS represents a low level signal; GuardKey0 signal is a signal obtained by decoding operation code information OP<7:0> carried by the first MRW command after the first enable signal TMSET is generated. Similarly, Guard Key1 signal is a signal obtained by decoding operation code information OP<7:0> carried by the second MRW command after the first enable signal TMSET is generated, and Guard Key2 signal is a signal obtained by decoding operation code information OP<7:0> carried by the third MRW command after the first enable signal TMSET is generated.

[0198] When the MRW command satisfies the key information CA<8,9,11,12>, the first enable signal TMSET can be generated. That is, the first enable signal TMSET is the MRW command that satisfies the key information CA<8,9,11,12>. This MRW command is a test mode entry command. However, whether the test mode can be entered depends on whether the corresponding operation code information OP<7:0> in three consecutive MRW commands meet the preset decoding requirements. First key decoding signal TMKEY <0> , the second key decoding signal TMKEY <1> And the test mode start signal TMKEY <2> All need to be generated according to the first enable signal TMSET, that is, three consecutive first enable signals TMSET are generated based on three consecutive MRW commands that satisfy the corresponding key information CA<8,9,11,12>, which can prevent accidental entry into the test mode and improve security.

[0199] In the disclosed embodiment, three consecutive Guard Key signals (Guard Key0 signal, Guard Key1 signal and Guard Key2 signal) can be generated through three consecutive MRW commands, and the enable signal TM_EN can be generated through three consecutive Guard Key signals. In addition, in the test mode control circuit 20, the mode register address information received by the address processing circuit 21 and the operation code information received by the sampling latch circuit 23 are carried by the same MRW command, that is, obtained according to the fourth MRW command after the first enable signal TMSET is generated; that is, the test mode is entered through the first three MRW commands, and which test circuit 24 generates and outputs the corresponding test signal is determined by the fourth MRW command.

[0200] based on Fig.15The enable signal generating circuit 26 shown, Fig.16 is the corresponding signal timing diagram. Fig.16 As shown, TMKEY <0> Signal, TMKEY <1> Signals and TMKEY <2> There is a certain delay time between the signals. Specifically, when the first rising edge of the TMSET signal arrives, the TMKEY <0> The signal switches to high level; when the second rising edge of the TMSET signal arrives, TMKEY <1> The signal switches to high level; when the third rising edge of the TMSET signal arrives, TMKEY <2> The signal switches to high level; by <2> The signal is latched to generate the TM_EN signal. The rising edge of the TM_EN signal is determined by TMKEY <2> After the rising edge of the signal is generated and the TM_EN signal remains at a high level, the test mode control circuit 20 enters the test.

[0201] The disclosed embodiment provides a test mode control circuit, which includes: an address processing circuit for sampling mode register address information based on a mode register write signal to obtain a mode register address signal when an enable signal is in an enabled state, and decoding the mode register address signal to obtain a target address signal; an enable signal indicates whether it is in a test mode; a delay circuit for delaying the mode register write signal to obtain a shift mode register write signal; a sampling latch circuit for sampling and latching the operation code information based on the shift mode register write signal when the enable signal is in an enabled state to obtain a target operation code signal; and a test circuit for performing logical processing on the target operation code signal, the shift mode register write signal and the target address signal to generate and output a corresponding test signal. In this way, only one mode register write command is needed to generate and output a test signal, thereby reducing delay, while ensuring that each command can work normally during the test mode, and utilizing the multi-bit key information carried by the mode register write command to improve security.

[0202] In another embodiment of the present disclosure, based on the above embodiment, the test mode control circuit 20 is further refined. Fig.17 Detailed structural diagram of a test mode control circuit provided by an embodiment of the present disclosure. Fig.17As shown, the test mode control circuit 20 may include an address processing circuit 21, a delay circuit 22, a sampling latch circuit 23, a test circuit 24, a command decoding circuit 25, an enable signal generating circuit 26 and an initial enable signal generating circuit 27; wherein, illustratively, there are S test circuits 24, respectively represented by 24-1, 24-2, 24-3, 24-4, ..., 24-S, and each test circuit 24 includes 8 test sub-circuits 241. In addition, the specific composition structure of the test sub-circuit 241 can refer to the aforementioned embodiment and will not be described in detail here. For specific connection relationships, see Fig.17 .

[0203] It should be noted that the address processing circuit 21 can be represented by MRA DEC, the delay circuit 22 can be represented by CMDSHIFT, the sampling latch circuit 23 can be represented by LATCH, the test circuit 24 can be represented by DFT UNIT, the command decoding circuit 25 can be represented by CMD DEC, the enable signal generating circuit 26 can be represented by TEST MODE ENTRY, and the initial enable signal generating circuit 27 can be represented by TM_GEN.

[0204] In addition, the chip select signal can be represented by CS_n, the command / address signal can be represented by CA, the mode register write signal can be represented by MRW, the first enable signal can be represented by TMSET, the enable signal can be represented by TM_EN, the mode register address information can be represented by MRA, the shift mode register write signal can be represented by MRW_SHIFT, the operation code information can be represented by OP, and the test signal can be represented by TM_SIGNAL. Here, the command / address signal is CA<13:0>, the mode register address information is MRA<7:0>, and the operation code information is OP<7:0>, and no specific limitation is made.

[0205] Here, the command decoding circuit 25 is used to receive the CA<13:0> signal and the CS_n signal to generate the MRW signal; it can be understood that the command included in the CA<13:0> signal can be a mode register write command. In addition, the key information received by the initial enable signal generating circuit 27 can be the four pin information of CA8, CA9, CA11 and CA12 corresponding to the high level state of the CS_n signal, which is not specifically limited.

[0206] It should also be noted that the mode register address information <7:0> includes 8-bit address data, and the test mode control circuit 20 may include S test circuits 24, where S is greater than 0 and less than or equal to 2. MThe target address signal includes S target address sub-signals, the S target address sub-signals correspond to the test circuits 24 one by one, and the target address sub-signals indicate whether the corresponding test circuit 24 is selected; the target address sub-signals include at least one target address selection signal, and here the target address sub-signals include three target address selection signals such as MRA20, MRA53 and MRA76 as an example, but it is not specifically limited.

[0207] Each test circuit 24 includes eight test sub-circuits 241, each test sub-circuit 241 corresponds to one target operation code. Fig.17 The test circuit 24 receives the target operation code signal OP<7:0>, which means that there are 8 test sub-circuits 241 in the test circuit 24 that perform logic processing on each bit of the target operation code signal OP<7:0>, generate and output corresponding test signals. Fig.17 It is shown for convenience only.

[0208] It should also be noted that the sampling latch circuit 23 also includes eight first sampling sub-circuits, each of which corresponds to an operation code bit in the operation code information OP<7:0> and generates a corresponding target operation code.

[0209] It can be understood that an important difference between DDR5 and DDR4 is the different working mode of the command interface. In DDR4 and its previous SDRAM technology, the command and address signal pins are independent of each other; in DDR5, the command and address signals are combined into a CA bus. Many commands require two clock cycles to complete. The CA signal is sampled in the first clock cycle when the chip select signal is in a low state as command parsing, and the CA signal is sampled at the next clock rising edge for address use. Therefore, using the MRA information of the first clock cycle of the MRW command, the MRW command is shifted and then sampled for the OP and other information of the next clock cycle, which is equivalent to the SLAVE command + MASTER command mode in the related art. This design utilizes the characteristics of two-cycle (i.e., clock cycle) commands to fully utilize the CA information within two cycles. Only one MRW command is needed to enable the TM_SIGNAL signal. On the one hand, the original 2-bit key bit is changed to a 4-bit key bit, increasing the number of key bits to improve security; on the other hand, the original two-level command (SLAVE command and MASTER command) latching is now required. Only one MRW command is needed to enable the maximum number of TM_SIGNAL signals required for the chip to work, thereby reducing latency and eliminating the drawback that the commands during the interval between the SLAVE command and the MASTER command in the original design will not work properly.

[0210] based on Fig.17 The test mode control circuit 20 shown, Fig.18 The following is the corresponding signal timing diagram. Fig.18 As shown, after entering the test mode through three Guard Key signal sequences, the controller sends an MRW command. Due to the characteristics of the CA bus, the MRW signal is parsed out from the CA[4:0] information in the first clock cycle through the CS_n signal. The MRW signal samples and latches the MRA<7:0> information of the same clock cycle, and the decoding makes the target address selection signal MRA20 / 53 / 76 valid, and the index is located at the corresponding TM_UNIT unit (i.e., the test subcircuit 241) position.

[0211] It should be noted that if Fig.18 As shown, the MRW signal parsed in the first clock cycle is shifted and delayed by 1tck to obtain the MRW_SHIFT signal, which is to match the OP<7:0> information of the CS_n signal in the second clock cycle, and then the MRW_SHIFT signal is used to sample the OP<7:0> information as the input signal of the SR latch (i.e., the aforementioned second sampling subcircuit U6) inside the TM_UNIT (i.e., the test subcircuit 241), enabling the corresponding TM_SIGNAL signal to be valid. It can be understood that the OP<7:0> information can enable up to 8 TM_SIGNAL signals at the same time.

[0212] exist Fig.18 There is no requirement for the duration of "Test Mode Entry Sequence", which indicates the process of entering the test mode through three Guard Key signal sequences, namely, three MRW commands, and the MRW signal is obtained according to the fourth MRW command.

[0213] In addition, Fig.18 In the figure, the CK_t signal represents the clock signal. In the first clock cycle of the CK_t signal, the CS_n signal is in a low level state; in the second clock cycle of the CK_t signal, the CS_n signal is in a high level state. The clock cycle tck refers to one cycle of the clock signal CK_t.

[0214] The disclosed embodiment provides a test mode control circuit, specifically related to the circuit related to the testability design operation control in the integrated circuit. The original testability design is limited by the external pin information, and the test mode is enabled by combining the SLAVE command with the MASTER command. In this embodiment, a new testability design control circuit is proposed based on the CA bus. On the one hand, it can make full use of the effective information of all CA pins in the two-cycle MRW command, enhance security and reduce delay; on the other hand, it eliminates the disadvantage that the command originally designed during the interval between the SLAVE command and the MASTER command will not work normally.

[0215] In another embodiment of the present disclosure, see Fig.19, which shows a flow chart of a control method provided by an embodiment of the present disclosure. Fig.19 As shown, the method may include:

[0216] S301. Receive a mode register write signal, mode register address information and an enable signal through an address processing circuit. When the enable signal is in an enabled state, sample the mode register address information based on the mode register write signal to obtain a mode register address signal, and decode the mode register address signal to obtain a target address signal.

[0217] S302 , receiving a mode register write signal through a delay circuit, performing delay processing on the mode register write signal, and obtaining a shift mode register write signal.

[0218] S303, receiving the shift mode register write signal, the operation code information and the enable signal through the sampling latch circuit, and when the enable signal is in the enabled state, sampling and latching the operation code information based on the shift mode register write signal to obtain the target operation code signal.

[0219] S304, receiving the target operation code signal, the shift mode register write signal and the target address signal through the test circuit, and performing logic processing on the target operation code signal, the shift mode register write signal and the target address signal to generate and output a corresponding test signal.

[0220] It should be noted that, in the embodiment of the present disclosure, the enable signal indicates whether it is in the test mode.

[0221] In the embodiment of the present disclosure, the method is specifically a testability design operation control method in an integrated circuit, and the method is applied to the test mode control circuit 20 in the above embodiment. For details not disclosed in the embodiment of the present disclosure, please refer to the description of the above embodiment for understanding.

[0222] The disclosed embodiment provides a control method, which utilizes the transmission characteristics of the two-cycle MRW command and fully utilizes the CA information within the two cycles, thereby reducing delays, shortening the test mode operation time, saving command resources, and eliminating the risk of other commands failing to work during the test mode enablement.

[0223] In another embodiment of the present disclosure, see Fig. 20 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Fig. 20 As shown, the memory 40 may include the test mode control circuit 20 described in any one of the aforementioned embodiments.

[0224] In some embodiments, the memory 40 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., which are not specifically limited here.

[0225] In the disclosed embodiment, for the memory 40, the address processing circuit is used to obtain the target address signal; the delay circuit is used to obtain the shift mode register write signal; the sampling latch circuit is used to obtain the target operation code signal; and the test circuit is used to generate and output the corresponding test signal. In this way, only one mode register write command is needed to generate and output the test signal, thereby reducing the delay, shortening the test mode operation time, and saving command resources; at the same time, it is ensured that other commands can work normally during the test mode.

[0226] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0227] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0228] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0229] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0230] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0231] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0232] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A test mode control circuit, characterized in that: include: an address processing circuit, configured to receive a mode register write signal, mode register address information and an enable signal, sample the mode register address information based on the mode register write signal to obtain a mode register address signal when the enable signal is in an enabled state, and decode the mode register address signal to obtain a target address signal; the enable signal indicates whether the mode is in a test mode; A delay circuit, used for receiving the mode register write signal, delaying the mode register write signal, and obtaining a shift mode register write signal; a sampling latch circuit, configured to receive the shift mode register write signal, the operation code information and the enable signal, and to sample and latch the operation code information based on the shift mode register write signal when the enable signal is in an enabled state, so as to obtain a target operation code signal; The test circuit is used to receive the target operation code signal, the shift mode register write signal and the target address signal, and perform logic processing on the target operation code signal, the shift mode register write signal and the target address signal to generate and output a corresponding test signal.

2. The test mode control circuit according to claim 1, characterized in that: The test mode control circuit also includes a command decoding circuit, wherein: The command decoding circuit is used to receive a mode register write command and a chip select signal, and decode the command information in the mode register write command based on the chip select signal to generate the mode register write signal; The mode register write command lasts for two clock cycles of the clock signal. In the first clock cycle, the mode register write command includes the command information and the mode register address information. In the second clock cycle, the mode register write command includes the operation code information and the key information.

3. The test mode control circuit according to claim 1, characterized in that: The operation code information includes an N-bit operation code, the sampling latch circuit includes N first sampling sub-circuits, and the target operation code signal includes an N-bit target operation code, where N is an integer greater than 0, wherein: The i-th first sampling sub-circuit is used to receive the enable signal, the shift mode register write signal and the i-th operation code, and when the enable signal is in an enabled state, sample the i-th operation code according to the shift mode register write signal to obtain the i-th target operation code; Here, i is an integer greater than 0 and less than or equal to N.

4. The test mode control circuit according to claim 3, characterized in that: The mode register address information includes M-bit address data, the test mode control circuit includes S test circuits, M is an integer greater than 0, and S is an integer greater than 0 and less than or equal to 2. M The target address signal includes S target address sub-signals, the S target address sub-signals correspond to the test circuits one by one, and the target address sub-signals indicate whether the corresponding test circuit is selected; each test circuit includes N test sub-circuits, and the test signal includes N test sub-signals, wherein: The i-th test sub-circuit is used to receive the i-th target operation code, the shift mode register write signal and the corresponding target address sub-signal; perform logic processing according to the i-th target operation code and the corresponding target address sub-signal to generate the i-th sampling input signal, and perform logic processing according to the shift mode register write signal and the target address sub-signal to generate a sampling signal; perform sampling processing on the i-th sampling input signal according to the sampling signal to generate and output the i-th test sub-signal.

5. The test mode control circuit according to claim 4, characterized in that: The target address sub-signal includes at least one target address selection signal, and the i-th test sub-circuit includes a first logic circuit, a second logic circuit, a third logic circuit and a first latch circuit, wherein: The first logic circuit is used to receive the at least one target address selection signal and generate an address enable signal according to the at least one target address selection signal; wherein, when the at least one target address selection signal is in a preset level state, the address enable signal is in an enabled state; The second logic circuit is used to receive the i-th target operation code and the address enable signal, and generate the i-th sampling input signal according to the i-th target operation code and the address enable signal; wherein, when the address enable signal is in an enabled state, the level state of the i-th sampling input signal is the same as the level state of the i-th target operation code; The third logic circuit is used to receive the shift mode register write signal and the address enable signal, and generate the sampling signal according to the shift mode register write signal and the address enable signal; when the address enable signal is in an enabled state, the level state of the sampling signal is the same as the level state of the shift mode register write signal; The first latch circuit is used to receive the i-th sampling input signal and the sampling signal, and perform sampling processing on the i-th sampling input signal according to the sampling signal to generate the i-th test sub-signal.

6. The test mode control circuit according to claim 5, characterized in that: The first logic circuit includes a NAND gate, the second logic circuit includes a first NOT gate and a first NOR gate, and the third logic circuit includes a second NOT gate and a second NOR gate; wherein: The input end of the NAND gate is used to receive the at least one target address selection signal, and the output end of the NAND gate is connected to the second input end of the first NOR gate and the first input end of the second NOR gate respectively; the output end of the NAND gate is used to output the address enable signal; The input end of the first NOT gate is used to receive the i-th target operation code; the output end of the first NOT gate is connected to the first input end of the first NOR gate; the output end of the first NOR gate is used to output the i-th sampling input signal; The input end of the second NOT gate is used to receive the shift mode register write signal; the output end of the second NOT gate is connected to the second input end of the second NOR gate; and the output end of the second NOR gate is used to output the sampling signal.

7. The test mode control circuit according to claim 5, characterized in that: The first latch circuit includes a second sampling subcircuit and a driving circuit, and the driving circuit includes an even number of third NOT gates, wherein: The input end of the second sampling sub-circuit is used to receive the i-th sampling input signal, the clock end of the second sampling sub-circuit is used to receive the sampling signal, the output end of the second sampling sub-circuit is connected to the driving circuit, and the output end of the driving circuit is used to output the i-th test sub-signal.

8. The test mode control circuit according to claim 7, characterized in that: The i-th test sub-circuit is further used to receive the enable signal, and when the enable signal is in an enabled state, perform logic processing on the i-th target operation code, the shift mode register write signal and the target address signal to generate and output the i-th test sub-signal; When the enable signal is in a disabled state, the i-th test sub-signal is not output.

9. The test mode control circuit according to claim 8, characterized in that: The driving circuit also includes a first AND gate, a first input end of the first AND gate is used to receive the enable signal, a second input end of the first AND gate is connected to the output end of the last third NOT gate, and an output end of the first AND gate is used to output the i-th test sub-signal.

10. The test mode control circuit according to claim 7, characterized in that: The first sampling sub-circuit includes a D flip-flop, and the second sampling sub-circuit includes a latch.

11. The test mode control circuit according to claim 2, characterized in that: The delay circuit is also used to receive the enable signal, and when the enable signal is in the enabled state, delay the mode register write signal so that the delay time of the shift mode register write signal compared to the mode register write signal is greater than or equal to one clock cycle and less than two clock cycles.

12. The test mode control circuit according to claim 11, characterized in that: The delay circuit comprises a shift register; wherein: The shift register is used to receive the clock signal and the mode register write signal, and shift the mode register write signal based on the clock signal to delay the mode register write signal by one clock cycle to obtain the shift mode register write signal.

13. The test mode control circuit according to claim 2, characterized in that: The test mode control circuit further includes an enable signal generating circuit, wherein: The enable signal generating circuit is used to continuously receive multiple key information and corresponding multiple mode register write signals in multiple mode register write commands, and generate and output the enable signal according to the multiple key information and corresponding multiple mode register write signals.

14. The test mode control circuit according to claim 13, characterized in that: The enable signal generating circuit comprises a test mode starting circuit and a second latch circuit; wherein: The test mode start circuit is used to continuously receive the plurality of key information and the corresponding plurality of mode register write signals in the plurality of mode register write commands, and decode the corresponding key information in response to each mode register write signal to generate a plurality of key decoding signals; and generate a test mode start signal when the plurality of key decoding signals are respectively the same as a plurality of preset values; The second latch circuit is used to receive the test mode start signal, latch the test mode start signal, and generate and output the enable signal.

15. A control method, characterized in that: include: receiving a mode register write signal, mode register address information and an enable signal through an address processing circuit, sampling the mode register address information based on the mode register write signal to obtain a mode register address signal when the enable signal is in an enabled state, and decoding the mode register address signal to obtain a target address signal; the enable signal indicates whether it is in a test mode; receiving the mode register write signal through a delay circuit, delaying the mode register write signal, and obtaining a shift mode register write signal; Receiving the shift mode register write signal, the operation code information and the enable signal through a sampling latch circuit, sampling and latching the operation code information based on the shift mode register write signal when the enable signal is in an enabled state, and obtaining a target operation code signal; The target operation code signal, the shift mode register write signal and the target address signal are received by the test circuit, and the target operation code signal, the shift mode register write signal and the target address signal are logically processed to generate and output a corresponding test signal.

16. A memory, characterized in that: The method comprises the test mode control circuit as claimed in any one of claims 1 to 14.

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