Method and device for testing effective channel length of MOS (Metal Oxide Semiconductor) tube

Abstract

The invention provides a method and a device for testing the effective channel length of an MOS (Metal Oxide Semiconductor) tube, and belongs to the technical field of semiconductor manufacturing. The method is applied to an MOS tube test structure, the MOS tube test structure comprises a plurality of MOS units, each MOS unit comprises a substrate, a source electrode, a drain electrode and a grid electrode, the source electrode and the drain electrode are arranged on the substrate, the grid electrode is located between the source electrode and the drain electrode, and an isolation oxide layer is arranged between the substrate and the grid electrode; wherein all the MOS units share one substrate, the lengths of the grid electrodes of all the MOS units are different, and every two adjacent MOS units share the source electrode or the drain electrode. During testing, the effective channel length can be tested by only one group of testing structure units, so that the testing efficiency is greatly improved, and the space occupied by the testing structure is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for testing an effective channel length of a MOS tube, a device for testing an effective channel length of a MOS tube, a machine-readable storage medium and an electronic device. Background Art

[0002] MOS is the abbreviation of MOSFET, which is Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

[0003] Testkey (TSK) is a test structure mainly used to monitor whether the chip manufacturing process is healthy, whether the device performance is normal, and whether the test results of various device parameters meet the standards.

[0004] The existing Testkey test structure only includes one MOS unit, that is, a substrate, a source, a drain and a gate. Therefore, when using the existing Testkey test structure to test the effective channel length of a MOS tube, multiple TSKs of MOS of different sizes are required to complete the test, which takes up a lot of test structure space. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a MOS tube effective channel length testing method, a MOS tube effective channel length testing device, a machine-readable storage medium and an electronic device. The MOS tube effective channel length testing method only needs one set of test structure units to test the effective channel length, which greatly improves the test efficiency. At the same time, each MOS unit shares a substrate, and two adjacent MOS units share a source or a drain, so that the MOS tube test structure is greatly reduced, and the space occupied by the test structure is reduced.

[0006] In order to achieve the above-mentioned object, the first aspect of the present application provides a MOS tube effective channel length test method, which is applied to a MOS tube test structure, wherein the MOS tube test structure comprises: a plurality of MOS units, each MOS unit comprises a substrate, a source, a drain and a gate, the source and the drain are respectively arranged on the substrate, the gate is located between the source and the drain, and an isolation oxide layer is arranged between the substrate and the gate; wherein each MOS unit shares a substrate, each MOS unit has a different gate length, and two adjacent MOS units share a source or a drain; the MOS tube effective channel length test method comprises:

[0007] Applying a voltage signal to the MOS unit in the MOS tube test structure according to a preset voltage application scheme;

[0008] Acquiring parameter information of a MOS unit in the MOS tube test structure under the voltage signal;

[0009] Based on the parameter information, an effective channel length is obtained.

[0010] In the embodiment of the present application, the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme;

[0011] The preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to any MOS unit in the MOS tube test structure;

[0012] The preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS tube test structure, and applying different gate voltages to all MOS units in the MOS tube test structure.

[0013] In the embodiment of the present application, the step of obtaining parameter information of a MOS unit in the MOS tube test structure under the voltage signal includes:

[0014] Obtaining a first drain current, where the first drain current is a drain current of a corresponding MOS unit at different gate voltages under the preset first voltage application scheme;

[0015] A second drain current is obtained, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

[0016] In the embodiment of the present application, obtaining the effective channel length based on the parameter information includes:

[0017] Based on the first drain current and the first fixed drain voltage, a total resistance is obtained, wherein the total resistance is the sum of the channel resistance, the lightly doped region resistance and the source and drain region resistance;

[0018] Based on the second drain current, the second fixed drain voltage and the total resistance, a first linear function is obtained, wherein the first linear function is a linear function of the ratio of the drain voltage to the drain current as the gate length changes;

[0019] Determining a channel length error based on an intersection point of the first linear function;

[0020] Based on the theoretical channel length and the channel length error, an effective channel length is obtained.

[0021] In the embodiment of the present application, the first linear function is:

[0022]

[0023] R sd is the source-drain resistance, R LDD is the resistance of the lightly doped region, R channel is the channel resistance, L poly is the gate length, ΔL is the difference between the mask channel length and the effective channel length, W is the channel width, c OX is the gate capacitance, μ n is the electron mobility, V gs is the gate voltage, V t is the threshold voltage, V ds is the second fixed drain voltage, I ds is the second drain current.

[0024] In the embodiment of the present application, it also includes:

[0025] Based on the channel length error, a sum of the source and drain region resistance and the lightly doped region resistance is obtained;

[0026] The channel resistance is obtained based on the sum of the source and drain region resistance and the lightly doped region resistance and the total resistance.

[0027] In the embodiment of the present application, gate electrodes are respectively provided at both ends of the gate.

[0028] In a second aspect, the present application provides a MOS tube effective channel length test device for the above-mentioned MOS tube test structure, which is applied to the MOS tube test structure. The MOS tube test structure includes a plurality of MOS units, each of which includes a substrate, a source, a drain and a gate. The source and the drain are respectively arranged on the substrate, the gate is located between the source and the drain, and an isolation oxide layer is arranged between the substrate and the gate; wherein each MOS unit shares a substrate, each MOS unit has a different gate length, and two adjacent MOS units share a source or a drain; the MOS tube effective channel length test device includes:

[0029] A signal applying module, used for applying a voltage signal to the MOS unit in the MOS tube test structure according to a preset voltage application scheme;

[0030] A parameter acquisition module, used to acquire parameter information of the MOS unit in the MOS tube test structure under the voltage signal;

[0031] The testing module is used to obtain the effective channel length based on the parameter information.

[0032] In an embodiment of the present application, the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme; the preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to any MOS unit in the MOS tube test structure; the preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to all MOS units in the MOS tube test structure.

[0033] In the embodiment of the present application, the parameter acquisition module includes:

[0034] A first acquisition unit, configured to acquire a first drain current, wherein the first drain current is a drain current of a corresponding MOS unit under different gate voltages under the preset first voltage application scheme;

[0035] The second acquisition unit is used to acquire a second drain current, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

[0036] In the embodiment of the present application, the test module includes:

[0037] a first calculation unit, configured to obtain a total resistance based on the first drain current and the first fixed drain voltage, wherein the total resistance is the sum of a channel resistance, a lightly doped region resistance, and a source-drain region resistance;

[0038] a second calculation unit, configured to obtain a first linear function based on the second drain current, the second fixed drain voltage and the total resistance, wherein the first linear function is a linear function of a ratio of a drain voltage to a drain current varying with a gate length;

[0039] A first determining unit, configured to determine a channel length error based on an intersection point of the first linear function;

[0040] The third calculation unit is used to obtain an effective channel length based on the theoretical channel length and the channel length error.

[0041] In the embodiment of the present application, it also includes:

[0042] A second determining unit, configured to obtain a sum of a source-drain region resistance and a lightly doped region resistance based on the channel length error;

[0043] The resistance calculation module is used to obtain the channel resistance based on the sum of the source and drain region resistance and the lightly doped region resistance and the total resistance.

[0044] A third aspect of the present application provides an electronic device, the electronic device comprising:

[0045] at least one processor;

[0046] a memory connected to the at least one processor;

[0047] The memory stores instructions that can be executed by the at least one processor, and the at least one processor implements the above-mentioned MOS tube effective channel length test method by executing the instructions stored in the memory.

[0048] A fourth aspect of the present application provides a machine-readable storage medium having instructions stored thereon, which, when executed by a processor, configures the processor to execute the above-mentioned MOS tube effective channel length test method.

[0049] Through the above technical solution, a voltage signal is applied to the MOS unit in the MOS tube test structure according to a preset voltage application scheme; parameter information of the MOS unit in the MOS tube test structure under the voltage signal is obtained; and the effective channel length is obtained based on the parameter information. Since a MOS tube test structure includes multiple MOS units, only one group of test structure units is needed to test the effective channel length during testing, which greatly improves the test efficiency. At the same time, each MOS unit shares a substrate, and two adjacent MOS units share a source or drain, which greatly reduces the MOS tube test structure and reduces the space occupied by the test structure.

[0050] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0052] Figure 1 A schematic diagram of a process flow of a MOS tube test structure method according to an embodiment of the present application is schematically shown;

[0053] Figure 2 A schematic diagram of a process flow of a method for testing an effective channel length of a MOS tube according to an embodiment of the present application is shown;

[0054] Figure 3 A schematic diagram of the structure of a MOS tube effective channel length testing device according to an embodiment of the present application is shown;

[0055] Figure 4The internal structure diagram of a computer device according to an embodiment of the present application is schematically shown.

[0056] Description of Reference Numerals

[0057] 410 - signal application module; 420 - parameter acquisition module; 430 - test module; A01 - processor; A02 - network interface; A03 - internal memory; A04 - display screen; A05 - input device; A06 - non-volatile storage medium; B01 - operating system; B02 - computer program. DETAILED DESCRIPTION

[0058] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0059] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0060] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0061] Please see Figure 1 , Figure 1 A schematic flow chart of a MOS tube test structure method according to an embodiment of the present application is schematically shown. This embodiment provides a MOS tube test structure, including: a plurality of MOS units, each MOS unit including a substrate, a source, a drain and a gate, the source and the drain are respectively arranged on the substrate, the gate is located between the source and the drain, and an isolation oxide layer is arranged between the substrate and the gate; wherein each MOS unit shares a substrate, each MOS unit has a different gate length, and two adjacent MOS units share a source or a drain.

[0062] In this embodiment, the gate lengths of the MOS units are different, so that MOS units of different sizes can be obtained. The above-mentioned source, drain and gate can be manufactured according to the manufacturing process of the MOS device, which will not be repeated here. The arrangement of the above-mentioned multiple MOS units can be arranged in order from short to long or from long to short according to the gate length, or can be arranged in any way. Two adjacent MOS units can share a source or a drain, such as Figure 1 As shown, the MOS unit with a gate length of L1 and the MOS unit with a gate length of L2 share a drain, and the MOS unit with a gate length of L2 and the MOS unit with a gate length of L3 share a source. A plurality of substrate electrodes may be disposed on the substrate.

[0063] When the MOS tube test structure in this embodiment is used to test the effective channel length of the MOS tube, the drain voltage is first fixed in the MOS tube test structure, and different voltages are applied to the gate of any MOS unit to measure the source-drain current under different gate voltages, thereby obtaining the channel resistance, the lightly doped region resistance, and the sum of the source-drain region resistance. Then, the drain voltage is fixed again, and the drain current of different gate lengths under different gate voltages is measured to obtain a linear function of the ratio of the drain voltage to the drain current and the gate length. The linear function of the ratio of the drain voltage to the drain current and the gate length is a plurality of linear straight lines, and the plurality of linear straight lines intersect at a point. The ratio of the drain voltage to the drain current corresponding to this point is the sum of the source-drain region resistance and the lightly doped region resistance, and the corresponding channel length is the channel length error. Specifically, the gate length corresponding to the sum of the source-drain region resistance and the lightly doped region resistance can be obtained, and the gate length is the channel length error, and then the corresponding channel length can be calculated by the theoretical channel length and the channel length error. At the same time, after obtaining the sum of the source-drain region resistance and the lightly doped region resistance, the channel resistance can be further obtained according to the sum of the channel resistance, the lightly doped region resistance and the source-drain region resistance.

[0064] In the above implementation process, since a MOS tube test structure includes multiple MOS units, only one group of test structure units is needed to test the effective channel length during testing, which greatly improves the test efficiency. At the same time, each MOS unit shares a substrate, and two adjacent MOS units share a source or drain, which greatly reduces the MOS tube test structure and reduces the space occupied by the test structure. At the same time, the MOS tube test structure can be used to test the sum of the source, drain and lightly doped region series resistance, the channel resistance and the effective channel length on a MOS tube test structure at the same time, further improving the test efficiency. The test structure can also be used to test MOS units with different gate lengths to verify the influence of the gate length on the MOS. The number of MOS units placed in the test structure can be flexibly adjusted to adjust the calculation precision and accuracy. By adjusting the space of each MOS unit in the test structure, the influence of dense areas and sparse areas on the performance of MOS devices can be verified.

[0065] In some embodiments, gate electrodes are respectively disposed at both ends of the gate.

[0066] In this embodiment, electrodes may be provided at the upper and lower ends of the gate respectively for testing the gate resistance, so as to implement MOS gate resistance testing on the MOS tube test structure, thereby testing the gate resistance of the MOS in actual working state.

[0067] Please see Figure 2 , Figure 2 The flowchart of a method for testing the effective channel length of a MOS tube according to an embodiment of the present application is schematically shown. This embodiment provides a method for testing the effective channel length of a MOS tube based on the above-mentioned MOS tube test structure, comprising the following steps:

[0068] Step 210: applying a voltage signal to the MOS unit in the MOS tube test structure according to a preset voltage application scheme;

[0069] In this embodiment, the test method can be to pre-establish a program on a test machine, and to implement the MOS tube effective channel length test through the program execution. The above-mentioned preset voltage application scheme can be pre-set, and specifically, when applying, the voltage application scheme can be implemented by controlling the voltage on and off of each MOS unit.

[0070] Wherein, in order to be able to quickly test the effective channel length, the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme;

[0071] The preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to any MOS unit in the MOS tube test structure;

[0072] The preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS tube test structure, and applying different gate voltages to all MOS units in the MOS tube test structure.

[0073] In this embodiment, by applying the first voltage application scheme, the drain current under different gate voltages can be measured, and then the sum of the channel resistance, the lightly doped region resistance and the source-drain region resistance can be obtained; by applying the second voltage application scheme, the drain current under different gate voltages and different gate lengths can be measured to obtain a linear function of the ratio of the drain voltage to the drain current and the gate length. The first voltage application scheme and the second voltage application scheme can be applied at a certain interval to ensure that reliable parameter information can be obtained.

[0074] Step 220: Obtain parameter information of the MOS unit in the MOS tube test structure under the voltage signal;

[0075] In this embodiment, the parameter information includes drain currents at different gate voltages.

[0076] In some embodiments, the step of obtaining parameter information of a MOS unit in the MOS tube test structure under the voltage signal comprises the following steps:

[0077] First, a first drain current is obtained, where the first drain current is a drain current of a corresponding MOS unit at different gate voltages under the preset first voltage application scheme;

[0078] In this embodiment, the voltage can be obtained by measuring the drain current of the corresponding MOS unit after applying the first voltage application scheme.

[0079] Then, a second drain current is obtained, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

[0080] In this embodiment, the voltage can be obtained by measuring the drain current of each MOS unit after applying the second voltage application scheme.

[0081] Step 230: Based on the parameter information, obtain the effective channel length.

[0082] In some embodiments, obtaining the effective channel length based on the parameter information comprises the following steps:

[0083] First, based on the first drain current and the first fixed drain voltage, a total resistance is obtained, where the total resistance is the sum of the channel resistance, the lightly doped region resistance, and the source and drain region resistance;

[0084] In this embodiment, by calculating the ratio of the first fixed drain voltage to the first drain current, the result obtained is actually the sum of the channel resistance, the lightly doped region resistance and the source-drain region resistance.

[0085] Then, based on the second drain current, the second fixed drain voltage and the total resistance, a first linear function is obtained, where the first linear function is a linear function of the ratio of the drain voltage to the drain current as the gate length changes;

[0086] In this embodiment, the first linear function is a plurality of linear lines, each of which represents a linear line showing that the ratio of the drain voltage to the drain current varies with the gate length under a voltage difference between the gate voltage and the threshold voltage.

[0087] Wherein, the first linear function is:

[0088]

[0089] R sd is the source-drain resistance, R LDD is the resistance of the lightly doped region, R channel is the channel resistance, L poly is the mask channel length, i.e., the gate length, ΔL is the difference between the mask channel length and the effective channel length, W is the channel width, c OX is the gate capacitance, μ n is the electron mobility, V gs is the gate voltage, V t is the threshold voltage; V ds is the drain voltage, i.e., the second fixed drain voltage, I ds is the channel current, ie, the second drain current.

[0090] Then, based on the intersection point of the first linear function, a channel length error is determined;

[0091] In this embodiment, the multiple linear lines intersect at a point, and the ratio of the drain voltage to the drain current corresponding to this point is the sum of the lightly doped region resistance and the source-drain region resistance. Then, the channel length corresponding to this point is the channel length error.

[0092] Finally, based on the theoretical channel length and the channel length error, the effective channel length is obtained.

[0093] In this embodiment, the corresponding channel length can be calculated by calculating the difference between the theoretical channel length and the channel length error.

[0094] In the above implementation process, a voltage signal is applied to the MOS unit in the MOS tube test structure according to a preset voltage application scheme; parameter information of the MOS unit in the MOS tube test structure under the voltage signal is obtained; and the effective channel length is obtained based on the parameter information. Since a MOS tube test structure includes multiple MOS units, only one group of test structure units is needed to test the effective channel length during testing, which greatly improves the test efficiency. At the same time, each MOS unit shares a substrate, and two adjacent MOS units share a source or drain, which greatly reduces the MOS tube test structure and reduces the space occupied by the test structure.

[0095] In some embodiments, it also includes:

[0096] Firstly, based on the channel length error, the sum of the source and drain region resistance and the lightly doped region resistance is obtained;

[0097] Then, the channel resistance is obtained based on the sum of the source and drain region resistance and the lightly doped region resistance and the total resistance.

[0098] In this embodiment, the sum of the source-drain region resistance and the lightly doped region resistance is actually a constant. After obtaining the sum of the source-drain region resistance and the lightly doped region resistance, the sum of the source-drain region resistance and the lightly doped region resistance can be subtracted from the total resistance to further obtain the channel resistance, thereby achieving simultaneous testing of the channel resistance and the effective channel length on a MOS tube test structure, further improving the test efficiency.

[0099] Figure 2 FIG. 1 is a flow chart of a method for testing the effective channel length of a MOS tube in one embodiment. It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0100] This embodiment provides a MOS tube effective channel length test device for the above MOS tube test structure. Figure 3 , Figure 3The schematic diagram of the structure of a MOS tube effective channel length test device according to an embodiment of the present application is schematically shown. The MOS tube effective channel length test device includes a signal application module 410, a parameter acquisition module 420 and a test module 430, wherein:

[0101] A signal applying module 410, configured to apply a voltage signal to the MOS unit in the MOS tube test structure according to a preset voltage application scheme;

[0102] A parameter acquisition module 420, used to acquire parameter information of the MOS unit in the MOS tube test structure under the voltage signal;

[0103] The testing module 430 is used to obtain the effective channel length based on the parameter information.

[0104] The preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme; the preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to any MOS unit in the MOS tube test structure; the preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to all MOS units in the MOS tube test structure.

[0105] Wherein, the parameter acquisition module includes:

[0106] A first acquisition unit, configured to acquire a first drain current, wherein the first drain current is a drain current of a corresponding MOS unit under different gate voltages under the preset first voltage application scheme;

[0107] The second acquisition unit is used to acquire a second drain current, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

[0108] Wherein, the test module includes:

[0109] a first calculation unit, configured to obtain a total resistance based on the first drain current and the first fixed drain voltage, wherein the total resistance is the sum of a channel resistance, a lightly doped region resistance, and a source-drain region resistance;

[0110] a second calculation unit, configured to obtain a first linear function based on the second drain current, the second fixed drain voltage and the total resistance, wherein the first linear function is a linear function of a ratio of a drain voltage to a drain current varying with a gate length;

[0111] A first determining unit, configured to determine a channel length error based on an intersection point of the first linear function;

[0112] The third calculation unit is used to obtain an effective channel length based on the theoretical channel length and the channel length error.

[0113] Among them, it also includes:

[0114] A second determining unit, configured to obtain a sum of a source-drain region resistance and a lightly doped region resistance based on the channel length error;

[0115] The resistance calculation module is used to obtain the channel resistance based on the sum of the source and drain region resistance and the lightly doped region resistance and the total resistance.

[0116] The MOS tube effective channel length test device includes a processor and a memory. The signal application module 410, the parameter acquisition module 420 and the test module 430 are all stored in the memory as program units. The processor executes the program units stored in the memory to implement the MOS tube effective channel length test.

[0117] The processor includes a kernel, which retrieves the corresponding program unit from the memory. One or more kernels can be set, and the coordinated optimization of distributed resources in the power control area can be achieved by adjusting kernel parameters.

[0118] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0119] An embodiment of the present invention provides a machine-readable storage medium on which a program is stored. When the program is executed by a processor, the MOS tube effective channel length test method is implemented.

[0120] An embodiment of the present invention provides a processor, which is used to run a program, wherein the MOS tube effective channel length testing method is executed when the program is running.

[0121] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 4As shown. The computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05 and a memory (not shown in the figure) connected through a system bus. Among them, the processor A01 of the computer device is used to provide computing and control capabilities. The memory of the computer device includes an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 in the non-volatile storage medium A06. The network interface A02 of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor A01, a MOS tube effective channel length test method is implemented. The display screen A04 of the computer device can be a liquid crystal display or an electronic ink display, and the input device A05 of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0122] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0123] In one embodiment, the MOS tube effective channel length test device provided by the present application can be implemented in the form of a computer program. The computer program can be used in Figure 4 The memory of the computer device can store various program modules constituting the MOS tube effective channel length test device, for example, Figure 3 The signal application module 410, parameter acquisition module 420 and test module 430 are shown. The computer program composed of various program modules enables the processor to execute the steps of the file system calling method of each embodiment of the present application described in this specification.

[0124] Figure 4 The computer device shown can be Figure 3 In the MOS transistor effective channel length testing device shown, the signal applying module 410 executes step 210 , the parameter acquiring module 420 executes step 220 , and the testing module 430 executes step 230 .

[0125] The embodiment of the present application provides a device, which includes a processor, a memory, and a program stored in the memory and executable on the processor, and is applied to a MOS tube test structure, wherein the MOS tube test structure includes a plurality of MOS units, each of which includes a substrate, a source, a drain, and a gate, wherein the source and the drain are respectively arranged on the substrate, the gate is located between the source and the drain, and an isolation oxide layer is arranged between the substrate and the gate; wherein each MOS unit shares a substrate, each MOS unit has a different gate length, and two adjacent MOS units share a source or a drain; and when the processor executes the program, the following steps are implemented:

[0126] Applying a voltage signal to the MOS unit in the MOS tube test structure according to a preset voltage application scheme;

[0127] Acquiring parameter information of a MOS unit in the MOS tube test structure under the voltage signal;

[0128] Based on the parameter information, an effective channel length is obtained.

[0129] In one embodiment, the preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme;

[0130] The preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to any MOS unit in the MOS tube test structure;

[0131] The preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS tube test structure, and applying different gate voltages to all MOS units in the MOS tube test structure.

[0132] In one embodiment, the obtaining parameter information of the MOS unit in the MOS tube test structure under the voltage signal includes:

[0133] Obtaining a first drain current, where the first drain current is a drain current of a corresponding MOS unit at different gate voltages under the preset first voltage application scheme;

[0134] A second drain current is obtained, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

[0135] In one embodiment, obtaining the effective channel length based on the parameter information includes:

[0136] Based on the first drain current and the first fixed drain voltage, a total resistance is obtained, wherein the total resistance is the sum of the channel resistance, the lightly doped region resistance and the source and drain region resistance;

[0137] Based on the second drain current, the second fixed drain voltage and the total resistance, a first linear function is obtained, wherein the first linear function is a linear function of the ratio of the drain voltage to the drain current as the gate length changes;

[0138] Determining a channel length error based on an intersection point of the first linear function;

[0139] Based on the theoretical channel length and the channel length error, an effective channel length is obtained.

[0140] In one embodiment, the first linear function is:

[0141]

[0142] R sd is the source-drain resistance, R LDD is the resistance of the lightly doped region, R channel is the channel resistance, L poly is the gate length, ΔL is the difference between the mask channel length and the effective channel length, W is the channel width, c OX is the gate capacitance, μ n is the electron mobility, V gs is the gate voltage, V t is the threshold voltage, V ds is the second fixed drain voltage, I ds is the second drain current.

[0143] In one embodiment, it further includes:

[0144] Based on the channel length error, a sum of the source and drain region resistance and the lightly doped region resistance is obtained;

[0145] The channel resistance is obtained based on the sum of the source and drain region resistance and the lightly doped region resistance and the total resistance.

[0146] In one embodiment, gate electrodes are respectively disposed at two ends of the gate.

[0147] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0148] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0149] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0150] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0151] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0152] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0153] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0154] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0155] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A method for testing the effective channel length of a MOS tube, characterized in that: Applied to a MOS tube test structure, the MOS tube test structure comprises a plurality of MOS units, each MOS unit comprises a substrate, a source, a drain and a gate, the source and the drain are respectively arranged on the substrate, the gate is located between the source and the drain, and an isolation oxide layer is arranged between the substrate and the gate; wherein each MOS unit shares a substrate, each MOS unit has a different gate length, and two adjacent MOS units share a source or a drain; the MOS tube effective channel length test method comprises: Applying a voltage signal to the MOS unit in the MOS tube test structure according to a preset voltage application scheme; Acquiring parameter information of a MOS unit in the MOS tube test structure under the voltage signal; Based on the parameter information, an effective channel length is obtained.

2. The MOS tube effective channel length testing method according to claim 1, characterized in that: The preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme; The preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS tube test structure, and applying a different gate voltage to any MOS unit in the MOS tube test structure; The preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS tube test structure, and applying different gate voltages to all MOS units in the MOS tube test structure.

3. The MOS tube effective channel length testing method according to claim 2, characterized in that: The obtaining parameter information of the MOS unit in the MOS tube test structure under the voltage signal includes: Obtaining a first drain current, where the first drain current is a drain current of a corresponding MOS unit at different gate voltages under the preset first voltage application scheme; A second drain current is obtained, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

4. The MOS tube effective channel length testing method according to claim 3, characterized in that: The obtaining of the effective channel length based on the parameter information comprises: Based on the first drain current and the first fixed drain voltage, a total resistance is obtained, wherein the total resistance is the sum of the channel resistance, the lightly doped region resistance and the source and drain region resistance; Based on the second drain current, the second fixed drain voltage and the total resistance, a first linear function is obtained, wherein the first linear function is a linear function of the ratio of the drain voltage to the drain current as the gate length changes; Determining a channel length error based on an intersection point of the first linear function; Based on the theoretical channel length and the channel length error, an effective channel length is obtained.

5. The method for testing the effective channel length of a MOS tube according to claim 4, characterized in that: The first linear function is: R sd is the source-drain resistance, R LDD is the resistance of the lightly doped region, R channel is the channel resistance, L poly is the gate length, ΔL is the difference between the mask channel length and the effective channel length, W is the channel width, c OX is the gate capacitance, μ n is the electron mobility, V gs is the gate voltage, V t is the threshold voltage, V ds is the second fixed drain voltage, I ds is the second drain current.

6. The method for testing the effective channel length of a MOS tube according to claim 4, characterized in that: Also includes: Based on the channel length error, a sum of the source and drain region resistance and the lightly doped region resistance is obtained; The channel resistance is obtained based on the sum of the source and drain region resistance and the lightly doped region resistance and the total resistance.

7. The MOS tube effective channel length testing method according to claim 1, characterized in that: Gate electrodes are respectively arranged at two ends of the gate.

8. A MOS tube effective channel length test device, characterized in that: Applied to a MOS tube test structure, the MOS tube test structure includes a plurality of MOS units, each MOS unit includes a substrate, a source, a drain and a gate, the source and the drain are respectively arranged on the substrate, the gate is located between the source and the drain, and an isolation oxide layer is arranged between the substrate and the gate; wherein each MOS unit shares a substrate, each MOS unit has a different gate length, and two adjacent MOS units share a source or a drain; the MOS tube effective channel length test device includes: A signal applying module, used for applying a voltage signal to the MOS unit in the MOS tube test structure according to a preset voltage application scheme; A parameter acquisition module, used to acquire parameter information of the MOS unit in the MOS tube test structure under the voltage signal; The testing module is used to obtain the effective channel length based on the parameter information.

9. The MOS tube effective channel length testing device according to claim 8, characterized in that: The preset voltage application scheme includes a preset first voltage application scheme and a preset second voltage application scheme; the preset first voltage application scheme is: applying a first fixed drain voltage to all MOS units in the MOS tube test structure, and applying different gate voltages to any MOS unit in the MOS tube test structure; the preset second voltage application scheme is: applying a second fixed drain voltage to all MOS units in the MOS tube test structure, and applying different gate voltages to all MOS units in the MOS tube test structure.

10. The MOS tube effective channel length testing device according to claim 9, characterized in that: The parameter acquisition module includes: A first acquisition unit, configured to acquire a first drain current, wherein the first drain current is a drain current of a corresponding MOS unit under different gate voltages under the preset first voltage application scheme; The second acquisition unit is used to acquire a second drain current, where the second drain current is the drain current of each MOS unit at different gate voltages under the preset second voltage application scheme.

11. The MOS tube effective channel length testing device according to claim 10, characterized in that: The test module includes: a first calculation unit, configured to obtain a total resistance based on the first drain current and the first fixed drain voltage, wherein the total resistance is the sum of a channel resistance, a lightly doped region resistance, and a source-drain region resistance; a second calculation unit, configured to obtain a first linear function based on the second drain current, the second fixed drain voltage and the total resistance, wherein the first linear function is a linear function of a ratio of a drain voltage to a drain current varying with a gate length; A first determining unit, configured to determine a channel length error based on an intersection point of the first linear function; The third calculation unit is used to obtain an effective channel length based on the theoretical channel length and the channel length error.

12. The MOS tube effective channel length testing device according to claim 11, characterized in that: Also includes: A second determining unit, configured to obtain a sum of a source-drain region resistance and a lightly doped region resistance based on the channel length error; The resistance calculation module is used to obtain the channel resistance based on the sum of the source and drain region resistance and the lightly doped region resistance and the total resistance.

13. An electronic device, characterized in that: The electronic device includes: at least one processor; a memory connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor implements the MOS tube effective channel length testing method according to any one of claims 1 to 7 by executing the instructions stored in the memory.

14. A machine-readable storage medium having instructions stored thereon, characterized in that: When the instruction is executed by a processor, the processor is configured to execute the MOS transistor effective channel length testing method according to any one of claims 1 to 7.

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