SOI wafer and preparation method thereof

Abstract

The invention provides an SOI wafer and a preparation method thereof, and the preparation method of the SOI wafer comprises the steps: providing a silicon crystal ingot grown through a Czochralski method, and enabling the crystal growth direction to be 1t; 100 gt; or lt; 110gt, 110gt; or lt; 111gt, 111gt; the silicon crystal ingot is processed to obtain a crystal bar with the target diameter, the crystal bar is cut into sections to obtain crystal sections, and the section cutting direction is lt; 100 gt; or lt; 110gt, 110gt; ; carrying out slicing treatment on one crystal section, controlling the cutting angle to be theta 1, carrying out grinding and polishing treatment to obtain a first silicon wafer as a device wafer, and enabling the value of theta 1 to be-0.05 to 0.05 degrees; carrying out slicing treatment on the other crystal segment, and carrying out grinding and polishing treatment to obtain a second silicon wafer as a support chip; and bonding the device sheet and the support sheet into a whole to obtain the SOI wafer. According to the SOI wafer obtained by the preparation method of the SOI wafer provided by the invention, the surface roughness and the number of surface particles are remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an SOI wafer and a preparation method thereof. Background Art

[0002] Silicon on insulator (SOI) technology has become one of the mainstream products in most electronic materials fields. With the rapid development of new energy vehicles, the integration of automotive-grade SOI material on-board chips has gradually increased. Therefore, the market demand for high-quality SOI is getting higher and higher. How to further improve the quality of the device layer of SOI materials has become an important trend in current development;

[0003] In SOI technology, the silicon crystal layer is isolated by an insulator layer, which can effectively reduce parasitic capacitance, increase the speed of the device, and reduce power consumption. One of the well-known methods is to use direct hydrophilic bonding of silicon and silicon oxide or silicon dioxide wafers, and then use physical and chemical methods to thin the top silicon to the required thickness. This technology can reduce the problems of injection damage and insufficient thickness of the top silicon film faced in the SIMOX (Separation by Implanted Oxygen) process.

[0004] The main principle of silicon-silicon dioxide bonding technology is to use the chemical reaction between silicon and silicon dioxide to achieve bonding. In practical applications, it is usually necessary to achieve bonding between silicon and silicon dioxide by controlling the reaction conditions and contact mode under a certain temperature and pressure. At the same time, in order to improve the bonding quality and reliability, the material also needs to be pre-treated by surface treatment and cleaning.

[0005] The quality of the SOI device layer is the key to the performance in the back-end processing. Poor device layer quality will lead to problems such as lithography overlay failure, increased threshold voltage, leakage current, etc., thus affecting the device's process manufacturing and performance. In order to improve the roughness of the device layer and the number of defects in the SOI substrate, it is usually necessary to achieve this through pre-bonding process optimization and post-bonding heat treatment, but process adjustments often cause other problems. Summary of the invention

[0006] The object of the present invention is to provide a SOI wafer and a method for preparing the same, so as to solve one or more problems in the prior art.

[0007] In order to solve the above problems, the present invention provides a method for preparing an SOI wafer, which is characterized by comprising:

[0008] Provide silicon ingots grown by Czochralski method, the crystal growth direction is <100> or <110> or <111> <111> , processing the silicon ingot to obtain a crystal rod of a target diameter, and cutting the crystal rod into segments to obtain crystal segments, wherein the cutting direction is <100> or <110> ;

[0009] Slicing one of the crystal segments, controlling the cutting angle to be θ1, and grinding and polishing to obtain a first silicon wafer as a device wafer, wherein the value of θ1 is -0.05° to 0.05°;

[0010] Slicing the other crystal segment, and grinding and polishing the wafer to obtain a second silicon wafer as a support wafer; and

[0011] Thermally oxidize at least one of the device wafer and the support wafer to obtain a buried oxide layer, and bond the device wafer and the support wafer together through the buried oxide layer to obtain an SOI wafer.

[0012] Optionally, in the method for preparing the SOI wafer, when slicing another of the wafer segments to obtain the support sheet, the cutting angle is controlled to be θ2, and the value of θ2 is -0.5° to 0.5°.

[0013] Optionally, in the method for preparing the SOI wafer, the device wafer has a thickness of 500-800 μm.

[0014] Optionally, in the method for preparing the SOI wafer, the support sheet has a thickness of 500-800 μm.

[0015] Optionally, in the method for preparing the SOI wafer, the buried oxide layer has a thickness of 0.01-1 μm.

[0016] Optionally, in the method for preparing the SOI wafer, if the device wafer is thermally oxidized to form the buried oxide layer, the thickness of the buried oxide layer formed on the surface of the device wafer is less than 0.4 μm.

[0017] Optionally, in the method for preparing the SOI wafer, the method further includes: performing a thinning and planarization process on the SOI wafer so that the thickness of the device wafer is 0.01-0.5 μm.

[0018] Optionally, in the method for preparing the SOI wafer, before performing thinning and planarization processes on the SOI wafer, the method further includes: performing heat treatment to strengthen the SOI wafer.

[0019] Optionally, in the method for preparing the SOI wafer, after the device wafer and the support wafer are ground and polished, the method further includes: cleaning the device wafer and the support wafer.

[0020] The present invention also provides an SOI wafer, which is prepared by the preparation method as described in any of the preceding items, and the number of particles on the surface of the SOI wafer is less than 10 in a light scattering channel with a size greater than or equal to 65 nm.

[0021] In summary, the method for preparing an SOI wafer provided by the present invention comprises: providing a silicon ingot grown by a Czochralski method, wherein the crystal growth direction is <100> or <110> or <111> <111> , processing the silicon ingot to obtain a crystal rod of a target diameter, and cutting the crystal rod into segments to obtain crystal segments, wherein the cutting direction is <100> or <110> ; Slice one of the crystal segments, control the cutting angle to θ1, and grind and polish to obtain a first silicon wafer as a device wafer, and the value of θ1 is -0.05° to 0.05°; slice another crystal segment, grind and polish to obtain a second silicon wafer as a support wafer; and thermally oxidize at least one of the device wafer and the support wafer to obtain a buried oxide layer, and bond the device wafer and the support wafer together through the buried oxide layer to obtain an SOI wafer. The SOI wafer obtained by the preparation method of the SOI wafer provided by the present invention has significantly reduced surface roughness and the number of surface particles. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of steps formed on the silicon surface along the cutting angle direction;

[0023] Figure 2 A flow chart of a method for preparing an SOI wafer provided by an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of the angle between the cutting surface and the growth surface in an embodiment of the present invention;

[0025] Figure 4 Schematic diagram of the positional relationship between the cutting surface and the growth surface in an embodiment of the present invention;

[0026] Figure 5 This is a surface particle diagram of comparative example 1 in the embodiment of the present invention;

[0027] Figure 6 This is a scanning electron microscope image of comparative example 1 in an embodiment of the present invention;

[0028] Figure 7 This is a surface roughness diagram of comparative example 1 in the embodiment of the present invention;

[0029] Figure 8 This is a surface particle diagram of comparative example 2 in the embodiment of the present invention;

[0030] Fig. 9 This is a scanning electron microscope image of comparative example 2 in the embodiment of the present invention;

[0031] Fig.10 This is a surface roughness diagram of comparative example 2 in the embodiment of the present invention;

[0032] Fig.11 This is a surface particle diagram of comparative example 3 in the embodiment of the present invention;

[0033] Fig.12 This is a scanning electron microscope image of comparative example 3 in the embodiment of the present invention;

[0034] Fig.13 This is a surface roughness diagram of comparative example 3 in the embodiment of the present invention;

[0035] The descriptions of the reference numerals are as follows:

[0036] 10-growth surface; 20-cutting surface; 30-shallow pit. DETAILED DESCRIPTION

[0037] The technical personnel of this application have found that after bonding the device wafer and the support wafer to form an SOI wafer, a flattening process is generally performed on the SOI wafer. The flattening process is a high-temperature heat treatment. At high temperatures, the surface silicon atoms will migrate to reach the lowest energy state. Driven by this mechanism, the silicon surface will appear flatter. On the other hand, please refer to Figure 1 In order to achieve the lowest energy state, the silicon surface often forms steps along the cutting angle direction, and the step width W decreases with the increase of the cutting angle of the silicon wafer surface. The silicon surface with wider steps has fewer hole defects. Therefore, the device wafer with a smaller cutting angle has a flatter surface and fewer defects after high-temperature flattening heat treatment.

[0038] In view of this, the present invention provides a method for preparing an SOI wafer. When slicing a crystal segment to form a device wafer, the slicing angle is controlled so that the surface roughness and the number of surface particles of the final SOI wafer can be reduced.

[0039] The following is a further detailed description of the SOI wafer and the method for preparing the same proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0040] See also Figure 2 The present invention provides a method for preparing a SOI wafer, comprising the following steps:

[0041] S1, providing a silicon ingot, wherein the silicon ingot is passed through a crystal <100> or <110> or <111> <111> The silicon crystal ingot is grown in a direction, the silicon crystal ingot is processed to obtain a crystal rod of a target diameter, and the crystal rod is segmented to obtain crystal segments, and the segmentation direction is <100> or <110> ;

[0042] S2, slicing one of the crystal segments, controlling the cutting angle to be θ1, and grinding and polishing to obtain a first silicon wafer as a device wafer, wherein the value of θ1 is -0.05° to 0.05°;

[0043] S3, slicing the other crystal segment, and grinding and polishing the same to obtain a second silicon wafer as a support wafer; and

[0044] S4, thermally oxidizing at least one of the device wafer and the support wafer to obtain a buried oxide layer, and bonding the device wafer and the support wafer together through the buried oxide layer to obtain an SOI wafer.

[0045] The method for preparing the SOI wafer provided in the embodiment of the present invention is described in further detail below.

[0046] First, execute step S1, which specifically includes the following three steps:

[0047] S11, providing a silicon ingot, wherein the silicon ingot is passed through a crystal <100> or <110> or <111> <111> The silicon ingot is preferably grown by a Czochralski method, and other methods known in the art may also be used;

[0048] S12, processing the silicon crystal ingot to obtain a crystal rod of a target diameter, for example, performing edge rolling and other processing on the silicon crystal ingot to obtain a crystal rod of a target diameter;

[0049] S13: cutting the crystal rod into segments to obtain crystal segments, and the cutting direction is <100> or <110> By obtaining different crystal segments, they are used to obtain device wafers and support wafers respectively, and the cutting directions of different crystal segments should be the same.

[0050] Next, step S2 is performed to slice one of the crystal segments, control the cutting angle to be θ1, and obtain a first silicon wafer through grinding and polishing. The first silicon wafer is used as a device wafer, wherein the value of θ1 is -0.05° to 0.05°, for example, -0.05°, 0, 0.05°, etc. Preferably, the thickness of the obtained device wafer is 500-800 μm, for example, 500 μm, 600 μm, 700 μm, 800 μm, etc.

[0051] Please note that, see Figure 3 The cutting angle θ is the angle between the cutting surface 20 and the growth surface 10 when the crystal segment is sliced. For example, if the silicon ingot is cut along the crystal <110> The cutting angle θ is the angle between the cutting plane 20 and the cutting plane 20 when slicing the crystal segment. <110> The angle between the faces, Figure 2 As shown in FIG. 1 , the growth surface 10 is <100> In addition, the specific value of the cutting angle θ can be positive or negative. If a positive value indicates that the cutting surface 20 is located in the clockwise direction of the growth surface 10, then a negative value indicates that the cutting surface 20 is located in the counterclockwise direction of the growth surface 10. For example, see Figure 4 If the cutting surface 20 with a cutting angle θ of 0.05° is located in the clockwise direction of the growth surface 10, then the cutting surface 20 with a cutting angle of -0.05° is located in the counterclockwise direction of the growth surface 10, that is, the cutting surface 20 with a cutting angle of 0.05° and the cutting surface 20 with a cutting angle of -0.05° are symmetrical about the growth surface 10.

[0052] Preferably, after the device wafer is ground and polished, the device wafer is also cleaned to remove surface particles.

[0053] Next, step S3 is performed to slice another of the crystal segments, and grind and polish the slices to obtain a second silicon wafer, which is used as a support wafer.

[0054] When slicing another crystal segment to obtain the support sheet, the cutting angle can be controlled to be θ2, and the value of θ2 is -0.5° to 0.5°, for example, -0.5°, 0, 0.5°, etc. Preferably, the thickness of the obtained support sheet is 500-800 μm, for example, 500 μm, 600 μm, 700 μm, 800 μm, etc.

[0055] Preferably, after the support sheet is ground and polished, the device sheet is also cleaned to remove surface particles.

[0056] Then, step S4 is executed, and step S4 specifically includes the following steps:

[0057] S41, thermally oxidizing at least one of the device wafer and the support wafer to obtain a buried oxide layer; that is, only the device wafer or the support wafer may be thermally oxidized, or both may be thermally oxidized, and the thickness of the buried oxide layer formed by thermal oxidation is preferably 0.01-1 μm. If the device wafer is thermally oxidized to form the buried oxide layer, the thickness of the buried oxide layer formed on the surface of the device wafer is less than 0.4 μm, so as to avoid the thermal oxidation time being too long and affecting its surface flatness;

[0058] S42, bonding the device wafer and the support wafer together through the buried oxide layer to obtain an SOI wafer.

[0059] Optionally, the manufacturing method provided by the embodiment of the present invention further comprises: performing a thinning and flattening process on the SOI wafer. Preferably, the device wafer has a thickness of 0.01-0.5 μm through the thinning and flattening process.

[0060] Preferably, before the SOI wafer is subjected to the thinning and planarization process, the SOI wafer is subjected to heat treatment for strengthening. Optionally, the edge of the SOI wafer is also subjected to chamfering treatment.

[0061] The embodiment of the present invention also provides an SOI wafer, which is prepared by the method for preparing an SOI wafer provided by the embodiment of the present invention. The surface roughness and the number of surface particles of the SOI wafer obtained by the method for preparing an SOI wafer provided by the embodiment of the present invention are significantly reduced, and the number of particles on the surface of the SOI wafer is less than 10 in a light scattering channel with a size greater than or equal to 65nm.

[0062] The SOI wafer and the preparation method thereof provided in the embodiments of the present invention are illustrated below with reference to several comparative examples.

[0063] [Comparative Example 1]

[0064] Provide silicon ingots grown by Czochralski method, with the crystal growth direction being <100> , grind the edge of the ingot to the target diameter, and cut it into sections in the direction of <110> .

[0065] A crystal segment is provided, and the crystal segment is sliced, and the slicing angle θ1 is 0.03°. The final silicon wafer is obtained by subsequent grinding, polishing and cleaning, and the thickness is selected to be 780um, which is used as a device wafer.

[0066] Another crystal segment is provided, and the crystal segment is sliced, and the slicing angle θ2 is -0.29°. The final silicon wafer is obtained through subsequent grinding, polishing and cleaning, and the thickness is selected to be 780um, which is used as a support sheet.

[0067] The device wafer is subjected to dry oxygen oxidation and wet oxygen oxidation to obtain a buried oxide layer, and the buried oxide layer has a thickness of 250 nm.

[0068] The device wafer and the support wafer are bonded, and after bonding, heat treatment is performed for reinforcement, and thinning and flattening processes are performed to obtain an SOI wafer with the required top silicon thickness, which is 100nm.

[0069] The quality of the prepared SOI wafer surface was observed by scanning electron microscope, atomic force microscope and surface particle detector. Figure 5 to Figure 7 The observation results are: surface roughness 0.222nm (30X30μm), the number of surface particles (LLS65) is 6, and there are no obvious defects under scanning electron microscope.

[0070] [Comparative Example 2]

[0071] Provide silicon ingots grown by Czochralski method, with the crystal growth direction being <100> , grind the edge of the ingot to the target diameter, and cut it into sections in the direction of <110> .

[0072] A crystal segment is provided, and the crystal segment is sliced, and the slicing angle θ1 is 0.06°. The final silicon wafer is obtained by subsequent grinding, polishing and cleaning, and the thickness is selected to be 780um, which is used as a device wafer.

[0073] Another crystal segment is provided, and the crystal segment is sliced, and the slicing angle θ2 is -0.29°. The final silicon wafer is obtained through subsequent grinding, polishing and cleaning, and the thickness is selected to be 780um, which is used as a support sheet.

[0074] The device wafer is subjected to dry oxygen oxidation and wet oxygen oxidation to obtain a buried oxide layer, and the buried oxide layer has a thickness of 250 nm.

[0075] The device wafer and the support wafer are bonded, and after bonding, heat treatment is performed for reinforcement, and thinning and flattening processes are performed to obtain an SOI wafer with the required top silicon thickness, which is 100nm.

[0076] The quality of the prepared SOI wafer surface was observed by scanning electron microscope, atomic force microscope and surface particle detector. Figure 8 to Figure 10 The observation results are: surface roughness 0.318nm (30×30μm), the number of surface particles (LLS65) is 94, and 30 shallow pits appear under the scanning electron microscope. It can be understood that LLS65 means that the size of the light scattering channel is 65nm.

[0077] [Comparative Example 3]

[0078] Provide silicon ingots grown by Czochralski method, with the crystal growth direction being <100> , grind the edge of the ingot to the target diameter, and cut it into sections. <110> ;

[0079] A crystal segment is provided, and the crystal segment is sliced, and the angle θ1 of the slice is 0.18°. The final silicon wafer is obtained by grinding, polishing and cleaning, and the thickness is selected to be 780um, which is used as a device wafer;

[0080] Another crystal segment is provided, and the crystal segment is sliced, and the angle θ2 of the slice is -0.28°. After subsequent grinding, polishing and cleaning, a final silicon wafer is obtained, and the thickness is selected to be 780um, which is used as a support sheet.

[0081] The device wafer is subjected to dry oxygen oxidation and wet oxygen oxidation to obtain a SOI buried oxide layer, and the buried oxide layer has a thickness of 250 nm.

[0082] The device wafer and the support wafer are bonded, and after bonding, heat treatment is performed to strengthen and thinning and flattening processes are performed to obtain an SOI wafer with the required top silicon thickness, which is 100nm.

[0083] The prepared SOI wafer is observed by scanning electron microscope, atomic force microscope and surface particle detector to reflect the quality of the SOI wafer surface. Figure 11 to Figure 13 The observation results are: surface roughness 0.321nm (30X30μm), the number of surface particles (LLS65) is 106, and 30 shallow pits appear under the scanning electron microscope.

[0084] It can be seen from the above three comparative examples that compared with comparative examples 2 and 3, since in comparative example 1, the value of θ1 is in the range of -0.05° to 0.05°, the surface roughness of comparative example 1 is significantly reduced relative to comparative examples 2 and 3, and the number of surface particles (LLS65) is less than 10.

[0085] In summary, the method for preparing an SOI wafer provided in an embodiment of the present invention comprises: providing a silicon ingot grown by a Czochralski method, wherein the crystal growth direction is <100> or <110> or <111> <111> , processing the silicon ingot to obtain a crystal rod of a target diameter, and cutting the crystal rod into segments to obtain crystal segments, wherein the cutting direction is <100> or <110> ; Slice one of the crystal segments, control the cutting angle to θ1, and grind and polish to obtain a first silicon wafer as a device wafer, and the value of θ1 is -0.05° to 0.05°; slice another crystal segment, and grind and polish to obtain a second silicon wafer as a support wafer; and thermally oxidize at least one of the device wafer and the support wafer to obtain a buried oxide layer, and bond the device wafer and the support wafer together through the buried oxide layer to obtain an SOI wafer. The SOI wafer obtained by the method for preparing the SOI wafer provided by the embodiment of the present invention has significantly reduced surface roughness and the number of surface particles.

[0086] It should be noted that, although the present invention has been disclosed as a preferred embodiment, any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention by using the technical content disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a SOI wafer, characterized in that: include: Provide a silicon ingot, the silicon ingot is passed through a crystal along <100> or <110> or <111> The silicon crystal ingot is grown in a direction, the silicon crystal ingot is processed to obtain a crystal rod of a target diameter, and the crystal rod is segmented to obtain crystal segments, and the segmentation direction is <100> or <110> ; Slicing one of the crystal segments, controlling the cutting angle to be θ1, and grinding and polishing to obtain a first silicon wafer as a device wafer, wherein the value of θ1 is -0.05° to 0.05°; Slicing the other crystal segment, and grinding and polishing the same to obtain a second silicon wafer as a support wafer; as well as, Thermally oxidize at least one of the device wafer and the support wafer to obtain a buried oxide layer, and bond the device wafer and the support wafer together through the buried oxide layer to obtain an SOI wafer.

2. The method for preparing an SOI wafer according to claim 1, wherein: When another crystal segment is sliced ​​to obtain the support sheet, the cutting angle is controlled to be θ2, and the value of θ2 is -0.5° to 0.5°.

3. The method for preparing an SOI wafer according to claim 1, wherein: The device sheet has a thickness of 500-800 μm.

4. The method for preparing an SOI wafer according to claim 1, wherein: The support sheet has a thickness of 500-800 μm.

5. The method for preparing an SOI wafer according to claim 1, wherein: The thickness of the buried oxide layer is 0.01-1 μm.

6. The method for preparing an SOI wafer according to claim 1, wherein: If the device wafer is thermally oxidized to form the buried oxide layer, the buried oxide layer formed on the surface of the device wafer has a thickness of less than 0.4 μm.

7. The method for preparing an SOI wafer according to claim 1, wherein: The method further includes performing thinning and planarization processes on the SOI wafer.

8. The method for preparing an SOI wafer according to claim 1, wherein: Before performing thinning and planarization processes on the SOI wafer, the method further includes: performing thermal treatment to strengthen the SOI wafer.

9. The method for preparing an SOI wafer according to claim 1, wherein: After the device wafer and the support wafer are subjected to grinding and polishing treatment, the method further comprises: cleaning the device wafer and the support wafer.

10. An SOI wafer, characterized in that: The SOI wafer is prepared by the preparation method according to any one of claims 1 to 9, and the number of particles on the surface of the SOI wafer is less than 10 in a light scattering channel with a size greater than or equal to 65 nm.

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