Control circuit for three-level topology circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of electronics, in particular to a control circuit for a three-level topology circuit, a chip and electronic equipment. The control circuit comprises a current sampling circuit, a voltage sampling circuit, a current loop integrator, a first modulation signal generation circuit and a second modulation signal generation circuit. According to the control circuit provided by the invention, firstly, an inductive current signal is collected, which is equivalent to an average current signal in a sampling circuit, so that the sampling precision of the inductive current signal is higher, and meanwhile, a voltage loop is designed, which is equivalent to a double-loop control circuit adopting a current loop and a voltage loop, so that the sampling precision of the inductive current signal is improved. The control precision of the three-level topology circuit is improved, and the stability of the three-level topology circuit is further improved. Besides, the two paths of pulse width modulation signals are generated through the two paths of sawtooth wave signals with the phase difference of 180 degrees, the three-level topology circuit can be controlled to achieve natural and smooth switching within the full duty ratio range, and the stability of the three-level topology circuit is further improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a control circuit, a chip and an electronic device for a three-level topology circuit. Background Art

[0002] The three-level topology circuit is a hybrid topology composed of transistors, inductors and capacitors. The three-level topology circuit can be used as a power converter in fast charging equipment applications and has been widely used in consumer electronics such as mobile phones and tablets. The three-level topology structure uses the flying capacitor voltage clamping effect to make the switching stress of the transistor under normal operation only half of the input power supply voltage. Then, the on-resistance and switching loss can be reduced by selecting lower voltage devices, thereby improving the fast charging efficiency.

[0003] In the related art, the peak current or valley current of the transistor in the three-level topology circuit is mainly sampled, and then each transistor is controlled according to the collected peak current or valley current of the transistor by using a current loop. However, after the input voltage or output voltage of the three-level topology circuit changes, the duty cycle of the control signal used to control each transistor will also change; for example, after the input voltage or output voltage changes, the duty cycle of the three-level topology circuit changes from greater than 50% to less than 50%, which will make it difficult to sample the peak current or valley current of the transistor, or cause the sampling accuracy of the peak current or valley current of the transistor to decrease, thereby causing the control accuracy of the three-level topology circuit to decrease, thereby affecting the stability of the three-level topology circuit. Summary of the invention

[0004] The present application provides a control circuit, a chip and an electronic device for a three-level topology circuit, which are used to solve the technical problem in the related art that the control accuracy of the three-level topology circuit is low, thereby affecting the stability of the three-level topology circuit.

[0005] In a first aspect, the present application provides a control circuit for a three-level topology circuit, wherein the three-level topology circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a first inductor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are sequentially connected in series between a power supply and a ground terminal, the first capacitor is connected in parallel at both ends of the second transistor and the third transistor, the first end of the first inductor is connected to a midpoint between the second transistor and the third transistor, the second end of the first inductor is a voltage output terminal, and the voltage output terminal is used to output a discharge voltage;

[0006] The control circuit comprises: a current sampling circuit, a voltage sampling circuit, a current loop integrator, a first modulation signal generating circuit and a second modulation signal generating circuit;

[0007] The sampling end of the current sampling circuit is connected to the two ends of the first inductor, and the output end of the current sampling circuit is connected to the inverting input end of the current loop integrator; the sampling end of the voltage sampling circuit is connected to the voltage output end, and the output end of the voltage sampling circuit is connected to the non-inverting input end of the current loop integrator; the output end of the current loop integrator is respectively connected to the input ends of the first modulation signal generating circuit and the second modulation signal generating circuit;

[0008] The current sampling circuit is used to sample the inductor current signal on the first inductor; the voltage sampling circuit is used to sample the discharge voltage signal on the voltage output terminal and convert the discharge voltage signal into a first current signal; the current loop integrator is used to integrate the inductor current signal and the first current signal to obtain a first voltage signal;

[0009] The first modulation signal generating circuit is used to receive a first sawtooth wave signal, and generate a first pulse width modulation signal according to the first sawtooth wave signal and the first voltage signal; the second modulation signal generating circuit is used to receive a second sawtooth wave signal, and generate a second pulse width modulation signal according to the second sawtooth wave signal and the first voltage signal; the phase difference between the first sawtooth wave signal and the second sawtooth wave signal is 180°;

[0010] The first pulse width modulation signal is used to control the on and off of the first transistor and the fourth transistor; the second pulse width modulation signal is used to control the on and off of the second transistor and the third transistor.

[0011] In a possible design, the current sampling circuit includes a first resistor, a second capacitor, and a first signal amplifier;

[0012] The first end of the first resistor is connected to the first end of the first inductor, the second end of the first resistor is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the second end of the first inductor; the first end of the first resistor and the second end of the second capacitor are sampling ends of the current sampling circuit;

[0013] The first end of the second capacitor is connected to the non-inverting input end of the first signal amplifier, the second end of the second capacitor is connected to the inverting input end of the first signal amplifier, and the output end of the first signal amplifier is the output end of the current sampling circuit.

[0014] In one possible design, the voltage sampling circuit includes a second resistor, a third resistor, and a voltage loop integrator;

[0015] The first end of the second resistor is the sampling end of the voltage sampling circuit, the first end of the second resistor is connected to the voltage output end, the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded;

[0016] The first end of the second resistor is also connected to the inverting input end of the voltage loop integrator. The non-inverting input end of the voltage loop integrator is used to receive a reference voltage signal. The output end of the voltage loop integrator is the output end of the voltage sampling circuit. The output end of the voltage loop integrator is connected to the non-inverting input end of the current loop integrator.

[0017] In a possible design, the voltage sampling circuit further includes a fourth resistor and a third capacitor;

[0018] A first end of the fourth resistor is connected to the output end of the voltage loop integrator, a second end of the fourth resistor is connected to a first end of the third capacitor, and a second end of the third capacitor is grounded.

[0019] In one possible design, the control circuit for the three-level topology circuit further includes a fifth resistor and a fourth capacitor;

[0020] A first end of the fifth resistor is connected to the output end of the current loop integrator, a second end of the fifth resistor is connected to a first end of the fourth capacitor, and a second end of the fourth capacitor is grounded.

[0021] In a possible design, the first modulation signal generating circuit includes a first comparator and a first SR trigger; the non-inverting input terminal of the first comparator is used to receive the first sawtooth wave signal, the inverting input terminal of the first comparator is connected to the output terminal of the current loop integrator, and the output terminal of the first comparator is connected to the reset input terminal of the first SR trigger; the set input terminal of the first SR trigger is used to receive the first clock signal;

[0022] The first comparator is used to compare the first sawtooth wave signal with the first voltage signal and generate a first trigger signal according to the comparison result; the first SR trigger is used to generate the first pulse width modulation signal according to the first trigger signal;

[0023] The second modulation signal generating circuit comprises a second comparator and a second SR flip-flop; the non-inverting input terminal of the second comparator is used to receive the second sawtooth wave signal, the inverting input terminal of the second comparator is connected to the output terminal of the current loop integrator, and the output terminal of the second comparator is connected to the reset input terminal of the second SR flip-flop; the set input terminal of the second SR flip-flop is used to receive a second clock signal; the phase difference between the first clock signal and the second clock signal is 180°;

[0024] The second comparator is used to compare the second sawtooth wave signal with the first voltage signal and generate a second trigger signal according to the comparison result; the second SR trigger is used to generate the second pulse width modulation signal according to the second trigger signal.

[0025] In a possible design, a sawtooth wave generating circuit is further included; the sawtooth wave generating circuit is used to generate the first sawtooth wave signal and the second sawtooth wave signal with a phase difference of 180°.

[0026] In a possible design, the sawtooth wave generating circuit includes a second signal amplifier, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a sixth resistor, a fifth capacitor, a sixth capacitor, a first switch tube and a second switch tube;

[0027] The non-inverting input terminal of the second signal amplifier is used to receive the sampling voltage signal, the inverting input terminal of the second signal amplifier is connected to the first terminal of the sixth resistor, and the second terminal of the sixth resistor is grounded; the output terminal of the second signal amplifier is connected to the control electrode of the fifth transistor, the first electrode of the fifth transistor is connected to the first terminal of the sixth resistor, the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor, and the first electrode of the sixth transistor is used to receive the second voltage signal;

[0028] The control electrode of the seventh transistor is connected to the control electrode of the sixth transistor, the first electrode of the seventh transistor is also used to receive the second voltage signal, the second electrode of the seventh transistor is connected to the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, the first electrode of the first switch tube is connected to the first end of the fifth capacitor, the second electrode of the first switch tube is grounded, and the control electrode of the first switch tube is used to receive the first clock signal; the first end of the fifth capacitor is a first sawtooth wave signal output end, used to output the first sawtooth wave signal;

[0029] The control electrode of the eighth transistor is connected to the control electrode of the seventh transistor, the first electrode of the eighth transistor is also used to receive the second voltage signal, the second electrode of the eighth transistor is connected to the first end of the sixth capacitor, the second end of the sixth capacitor is grounded, the first electrode of the second switch tube is connected to the first end of the sixth capacitor, the second electrode of the second switch tube is grounded, and the control electrode of the second switch tube is used to receive the second clock signal; the first end of the sixth capacitor is a second sawtooth wave signal output end, which is used to output the second sawtooth wave signal.

[0030] In a second aspect, the present application further provides a chip, comprising a control circuit for a three-level topology circuit as described in any one of the above items.

[0031] In a third aspect, the present application further provides an electronic device, comprising a control circuit for a three-level topology circuit as described in any one of the above items; or comprising a chip as described above.

[0032] The control circuit for the three-level topology circuit provided by the first aspect above includes a current sampling circuit, a voltage sampling circuit, a current loop integrator, a first modulation signal generating circuit and a second modulation signal generating circuit. Among them, the current sampling circuit is used to sample the inductor current signal on the first inductor; the voltage sampling circuit is used to sample the discharge voltage signal on the voltage output terminal and convert the discharge voltage signal into a first current signal; the current loop integrator is used to integrate the inductor current signal and the first current signal to obtain a first voltage signal; the first modulation signal generating circuit is used to receive the first sawtooth wave signal and generate a first pulse width modulation signal according to the first sawtooth wave signal and the first voltage signal; the second modulation signal generating circuit is used to receive the second sawtooth wave signal and generate a second pulse width modulation signal according to the second sawtooth wave signal and the first voltage signal; the phase difference between the first sawtooth wave signal and the second sawtooth wave signal is 180°. Finally, the first pulse width modulation signal is used to control the conduction and disconnection of the first transistor and the fourth transistor, and the second pulse width modulation signal is used to control the conduction and disconnection of the second transistor and the third transistor. It can be seen that the control circuit provided in the present application first collects the inductor current signal, which is equivalent to the average current signal in the sampling circuit, so that the sampling accuracy of the inductor current signal is higher. At the same time, a voltage loop is designed, which is equivalent to a dual-loop control circuit of a current loop and a voltage loop, thereby improving the control accuracy of the three-level topology circuit and thus improving the stability of the three-level topology circuit.

[0033] In addition, according to the control circuit provided in the present application, two sawtooth wave signals with a phase difference of 180° are compared with the first voltage signal output by the current loop integrator, thereby generating two pulse width modulation signals with a phase difference of 180°. The two pulse width modulation signals with a phase difference of 180° can control the three-level topology circuit to achieve natural and smooth switching within the full duty cycle range, thereby further improving the stability of the three-level topology circuit.

[0034] The beneficial effects provided in the above-mentioned other aspects and the possible designs of the above-mentioned other aspects can be referred to the beneficial effects brought about by the above-mentioned first aspect and the possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0036] Figure 1 A schematic diagram of a common three-level topology circuit structure provided in an embodiment of the present application;

[0037] Figure 2 One of the structural schematic diagrams of the control circuit for the three-level topology circuit provided in the embodiment of the present application;

[0038] Figure 3 The second structural schematic diagram of the control circuit for the three-level topology circuit provided in the embodiment of the present application;

[0039] Figure 4 The third structural schematic diagram of the control circuit for a three-level topology circuit provided in an embodiment of the present application;

[0040] Figure 5 A fourth structural schematic diagram of a control circuit for a three-level topology circuit provided in an embodiment of the present application;

[0041] Figure 6 A schematic diagram of the structure of a current sampling circuit provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of the sawtooth wave generating circuit structure provided in an embodiment of the present application;

[0043] Figure 8 This is a schematic diagram of a process of generating a trigger signal according to a sawtooth wave signal and a first voltage signal in an embodiment of the present application;

[0044] Fig. 9 A schematic diagram of the waveforms of various signals when the control circuit provided in an embodiment of the present application is working. DETAILED DESCRIPTION

[0045] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0046] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0047] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0048] The transistor in the present application is a three-terminal transistor, and its three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor.

[0049] The three-level topology circuit is a hybrid topology architecture composed of transistors, inductors and capacitors. When working normally, the voltage on the capacitor is half of the supply voltage, which makes the three-level topology circuit very suitable for applications with high input voltage and high output power. At present, the three-level topology circuit has been well applied in existing DC / DC converters. Some three-level DC / DC converters not only reduce the switching stress, but also greatly reduce the size of the filter and improve the dynamic characteristics of the converter.

[0050] In the related art, the peak current or valley current of the transistor in the three-level topology circuit is mainly sampled, and then each transistor is controlled by using a current loop according to the peak current or valley current of the transistor collected. However, after the input voltage or output voltage of the three-level topology circuit changes, the duty cycle of the control signal used to control each transistor will also change, which will make it difficult to sample the peak current or valley current of the transistor, or cause the sampling accuracy of the peak current or valley current of the transistor to decrease, thereby causing the control accuracy of the three-level topology circuit to decrease, thereby affecting the stability of the three-level topology circuit. In addition, the related art also uses a voltage-mode control method to control the three-level topology circuit, and the use of the voltage-mode control method will introduce LC conjugate poles in the loop, which will also affect the stability of the three-level topology circuit.

[0051] In order to overcome the defects in the above-mentioned related technologies, the present application provides a control circuit for a three-level topology circuit. First, in order to overcome the technical problems in the related technologies that the sampling of the peak current or valley current of the sampling transistor is difficult and the accuracy is low, a current loop is designed to collect the inductor current signal, which is equivalent to the average current signal in the sampling circuit, so that the sampling accuracy of the inductor current signal is higher; at the same time, a voltage loop is designed, which is equivalent to a dual-loop control circuit of a current loop and a voltage loop, thereby improving the control accuracy of the three-level topology circuit, and thereby improving the stability of the three-level topology circuit.

[0052] In addition, according to the control circuit provided in the present application, two sawtooth wave signals with a phase difference of 180° are compared with the first voltage signal output by the current loop integrator, thereby generating two pulse width modulation signals with a phase difference of 180°. The two pulse width modulation signals with a phase difference of 180° can control the three-level topology circuit to achieve natural and smooth switching within the full duty cycle range, thereby further improving the stability of the three-level topology circuit.

[0053] Figure 1 A common three-level topology circuit structure diagram provided in the embodiment of the present application is shown in FIG. Figure 1As shown, the three-level topology circuit includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first capacitor C1 and a first inductor L1. The first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 are sequentially connected in series between the power supply and the ground terminal GND, the first capacitor C1 is connected in parallel to both ends of the second transistor Q2 and the third transistor Q3, the first end of the first inductor L1 is connected to the middle point of the second transistor Q2 and the third transistor Q3, and the second end of the first inductor L1 is a voltage output terminal, which is used to output a discharge voltage Vout.

[0054] Specifically, the first electrode of the first transistor Q1 is used to connect to the power supply, thereby receiving the power supply voltage Vin, the second electrode of the first transistor Q1 is connected to the first electrode of the second transistor Q2, the second electrode of the second transistor Q2 is connected to the first electrode of the third transistor Q3, the second electrode of the third transistor Q3 is connected to the first electrode of the fourth transistor Q4, and the second electrode of the fourth transistor Q4 is grounded GND. The first end of the first capacitor C1 is connected to the first electrode of the second transistor Q2, and the second end of the first capacitor C1 is connected to the first electrode of the fourth transistor Q4. The first end of the first inductor L1 is connected to the second electrode of the second transistor Q2, and the second end of the first inductor L1 is used to output the discharge voltage Vout. During normal operation, after the voltage on the first capacitor C1 is stable, the voltage value on the first capacitor C1 is half of the power supply voltage Vin, that is, the operating voltage on the control electrode and the second electrode of each transistor is half of the power supply voltage Vin, so that lower voltage devices can be used to reduce on-resistance and switching loss, thereby improving the working efficiency of the circuit.

[0055] It should be noted that Figure 1 This is only a common three-level topology circuit provided in this embodiment, and its purpose is to assist in explaining the control circuit provided in this application. This does not mean that the control circuit provided in this application can only be applied to Figure 1 It can be understood that the control circuit provided in the present application can be applied to a variety of common three-level topology circuits and deformation circuits based on the three-level topology circuits.

[0056] Figure 2 One of the structural schematic diagrams of the control circuit for the three-level topology circuit provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, the control circuit for the three-level topology circuit includes: a current sampling circuit 20 , a voltage sampling circuit 21 , a current loop integrator GM_I, a first modulation signal generating circuit 22 and a second modulation signal generating circuit 23 .

[0057] Among them, the sampling end of the current sampling circuit 20 is connected to the two ends of the first inductor L1, and the output end of the current sampling circuit 20 is connected to the inverting input end of the current loop integrator GM_I; the sampling end of the voltage sampling circuit 21 is connected to the voltage output end, and the output end of the voltage sampling circuit 21 is connected to the non-inverting input end of the current loop integrator GM_I; the output end of the current loop integrator GM_I is respectively connected to the input ends of the first modulation signal generating circuit 22 and the second modulation signal generating circuit 23.

[0058] Among them, the current sampling circuit 20 is used to sample the inductor current signal IL_SNS on the first inductor L1; the voltage sampling circuit 21 is used to sample the discharge voltage signal Vout on the voltage output end and convert the discharge voltage signal Vout into the first current signal COMP_V; the current loop integrator GM_I is used to integrate the inductor current signal IL_SNS and the first current signal COMP_V to obtain the first voltage signal COMP_I.

[0059] Among them, the first modulation signal generating circuit 22 is used to receive the first sawtooth wave signal VRAMP1, and generate the first pulse width modulation signal PWM1 according to the first sawtooth wave signal VRAMP1 and the first voltage signal COMP_I; the second modulation signal generating circuit 23 is used to receive the second sawtooth wave signal VRAMP2, and generate the second pulse width modulation signal PWM2 according to the second sawtooth wave signal VRAMP2 and the first voltage signal COMP_I; the phase difference between the first sawtooth wave signal VRAMP1 and the second sawtooth wave signal VRAMP2 is 180°.

[0060] The first pulse width modulation signal PWM1 is used to control the on and off of the first transistor Q1 and the fourth transistor Q4; the second pulse width modulation signal PWM2 is used to control the on and off of the second transistor Q2 and the third transistor Q3.

[0061] For details, see Figure 1 As shown, the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 include duty cycle information, and the first transistor Q1 and the fourth transistor Q4 are controlled to be turned on and off according to the duty cycle information in the first pulse width modulation signal PWM1, and the states of the first transistor Q1 and the fourth transistor Q4 need to be controlled to be mutually exclusive, for example, when the first transistor Q1 is controlled to be turned on according to the duty cycle information, the fourth transistor Q4 is controlled to be turned off at the same time. Correspondingly, the second transistor Q12 and the third transistor Q3 are controlled to be turned on and off according to the duty cycle information in the second pulse width modulation signal PWM2, and the states of the second transistor Q2 and the third transistor Q3 need to be controlled to be mutually exclusive, for example, when the second transistor Q2 is controlled to be turned on according to the duty cycle information, the third transistor Q3 is controlled to be turned off at the same time.

[0062] Through the above analysis, it can be known that the control circuit provided in the present application first collects the inductor current signal IL_SNS on the first inductor L1 through the current sampling circuit 20, and the inductor current signal IL_SNS is equivalent to the average current in the circuit. Therefore, this is equivalent to the average current signal in the sampling circuit, so that the sampling accuracy of the inductor current signal is higher.

[0063] At the same time, the control circuit of this embodiment designs a voltage loop, and integrates the inductor current signal IL_SNS and the first current signal COMP_V through the current loop integrator GM_I, and obtains the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 according to the first voltage signal COMP_I after the integration. This is equivalent to using a dual-loop control circuit of a current loop and a voltage loop, thereby improving the control accuracy of the three-level topology circuit, and further improving the stability of the three-level topology circuit.

[0064] In addition, according to the control circuit provided in the present application, two sawtooth wave signals with a phase difference of 180° are compared with the first voltage signal output by the current loop integrator, thereby generating two pulse width modulation signals with a phase difference of 180°. The two pulse width modulation signals with a phase difference of 180° can control the three-level topology circuit to achieve natural and smooth switching within the full duty cycle range, thereby further improving the stability of the three-level topology circuit.

[0065] Please continue to see Figure 2 As shown, in some embodiments, the control circuit for the three-level topology circuit includes a first sawtooth wave generating circuit 301 and a second sawtooth wave generating circuit 302. The first sawtooth wave generating circuit 301 is used to generate the first sawtooth wave signal VRAMP1, and the second sawtooth wave generating circuit 302 is used to generate the second sawtooth wave signal VRAMP2; and the phase difference between the generated first sawtooth wave signal VRAMP1 and the second sawtooth wave signal VRAMP2 is 180°.

[0066] Figure 6 For a schematic diagram of the structure of the current sampling circuit provided in the embodiment of the present application, please refer to Figure 6As shown, the current sampling circuit 20 includes a first resistor R1, a second capacitor C2 and a first signal amplifier AMP1; the first end of the first resistor R1 is connected to the first end of the first inductor L1, the second end of the first resistor R2 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second end of the first inductor L1; the first end of the first resistor R1 and the second end of the second capacitor C2 are sampling ends of the current sampling circuit 20. The first end of the second capacitor C2 is connected to the non-inverting input end of the first signal amplifier AMP1, the second end of the second capacitor C2 is connected to the inverting input end of the first signal amplifier AMP1, and the output end of the first signal amplifier AMP1 is the output end of the current sampling circuit 20, which is used to output the inductor current signal IL_SNS.

[0067] The first resistor R1 and the second capacitor C2 form an inductor current sampling network, and the first signal amplifier AMP1 is used to perform signal amplification processing on the sampled inductor current. Since the time constant formed by the first resistor R1 and the second capacitor C2 is much larger than the switching cycle of each transistor in the three-level topology circuit, the voltage difference across the second capacitor C2 can represent the product of the inductor current and the inductor parasitic resistance DCR. At the same time, the first signal amplifier AMP1 can adjust the inductor current signal IL_SNS by gain amplification.

[0068] It should be noted that the inductor current signal IL_SNS output by the first signal amplifier AMP1 represents the average current on the first inductor L1, which can be specifically expressed in the following form:

[0069]

[0070] In the above formula (1), K1 is the gain coefficient of the first signal amplifier AMP1, IL represents the instantaneous current on the first inductor L1, and R DCR represents the parasitic resistance of the first inductor L1, L1 represents the inductance of the first inductor, R 1 Represents the resistance of the first resistor, C 2 represents the capacitance value of the second capacitor, s represents the transfer function, and the transfer function sthreshold includes a zero point and a pole.

[0071] The above formula (1) contains the pole 1 / (R 1 *C 2 ) and the left half plane zero point R DCR / L1, can be achieved by optimizing the parameter R 1 and C 2 The value of makes the left half plane zero and pole cancel each other out, so that the inductor current signal IL_SNS can be expressed as: IL_SNS = K*IL*R DCR .

[0072] In this embodiment, the sampled inductor current signal IL_SNS is injected into the current loop integrator GM_I through the current sampling circuit 20, so that the first voltage signal COMP_I output by the current loop integrator GM_I can be characterized as a superposition of a DC voltage and an AC voltage signal. The DC voltage represents the duty cycle state, and the AC voltage represents the inductor ripple current information. The inductor ripple current component can change the high-frequency gain in the current sampling by adjusting the first resistor R1 and the second capacitor C2, thereby improving the loop stability and transient response capability.

[0073] Please continue to see Figure 2 As shown, the voltage sampling circuit 21 of this embodiment includes a second resistor R2, a third resistor R3 and a voltage loop integrator GM_V; the first end of the second resistor R2 is the sampling end of the voltage sampling circuit 21, the first end of the second resistor R2 is connected to the voltage output end, the second end of the second resistor R2 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is grounded GND. The first end of the second resistor R2 is also connected to the inverting input end of the voltage loop integrator GM_V, the positive input end of the voltage loop integrator GM_V, the positive input end of the voltage loop integrator GM_V is used to receive the reference voltage signal Vref, the output end of the voltage loop integrator GM_V is the output end of the voltage sampling circuit 21, and the output end of the voltage loop integrator GM_V is connected to the non-inverting input end of the current loop integrator GM_I.

[0074] Generally, in order to stabilize the output discharge voltage VOUT near the target voltage value, the reference voltage signal Vref can be set equal to the target voltage value. In this embodiment, the second resistor R2 and the third resistor R3 can be two resistors with the same resistance value. Therefore, the voltage input to the inverting input terminal of the voltage loop integrator GM_V is half of the discharge voltage VOUT, and accordingly, the reference voltage signal Vref can be set to half of the target voltage value.

[0075] In some embodiments, the voltage sampling circuit 21 further includes a fourth resistor R4 and a third capacitor C3; a first end of the fourth resistor R4 is connected to the output end of the voltage loop integrator GM_V, a second end of the fourth resistor R4 is connected to the first end of the third capacitor C3, and a second end of the third capacitor C3 is grounded GND. In this embodiment, the third capacitor C3 and the output impedance of the voltage loop integrator GM_V form a low-frequency main pole of the loop, and the fourth resistor R4 and the third capacitor C3 form a left half plane zero of the loop compensation, thereby improving the stability of the control circuit.

[0076] Figure 3 The second structural diagram of the control circuit for the three-level topology circuit provided in the embodiment of the present application is shown in FIG. Figure 3As shown, in some embodiments, the control circuit also includes a fifth resistor R5 and a fourth capacitor C4; the first end of the fifth resistor R5 is connected to the output end of the current loop integrator GM_I, the second end of the fifth resistor R5 is connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is grounded.

[0077] The main pole of the inner current loop of the control circuit is composed of the output impedance of the current loop integrator GM_I and the fourth capacitor C4, and the fifth resistor R5 and the fourth capacitor C4 form a left half plane zero point for improving the loop stability of the inner current loop, thereby improving the stability of the control circuit.

[0078] Please continue to see Figure 3 As shown, in some embodiments, there is a seventh capacitor C7 at the voltage output end, and the seventh capacitor C7 is used to perform filtering to eliminate the ripple signal at the voltage output end.

[0079] Figure 4 The third structural diagram of the control circuit for the three-level topology circuit provided in the embodiment of the present application is shown in FIG. Figure 4 As shown, the first modulation signal generating circuit 22 of the present embodiment includes a first comparator CMP1 and a first SR flip-flop SR1; the non-inverting input terminal of the first comparator CMP1 is used to receive the first sawtooth wave signal VRAMP1, the inverting input terminal of the first comparator CMP1 is connected to the output terminal of the current loop integrator GM_I, and the output terminal of the first comparator CMP1 is connected to the reset input terminal of the first SR flip-flop SR1; the set input terminal of the first SR flip-flop SR1 is used to receive the first clock signal f PWM The first comparator CMP1 is used to compare the first sawtooth wave signal VRAMP1 with the first voltage signal COMP_I and generate a first trigger signal according to the comparison result; the first SR trigger SR1 is used to generate a corresponding first pulse width modulation signal PWM1 according to the first trigger signal.

[0080] Correspondingly, the second modulation signal generating circuit 23 in this embodiment includes a second comparator CMP2 and a second SR flip-flop SR2; the non-inverting input terminal of the second comparator CMP2 is used to receive the second sawtooth wave signal VRAMP2, the inverting input terminal of the second comparator CMP2 is connected to the output terminal of the current loop integrator GM_I, and the output terminal of the second comparator CMP2 is connected to the reset input terminal of the second SR flip-flop SR2; the set input terminal of the second SR flip-flop SR2 is used to receive the second clock signal f PWM _180°. Among them, the first clock signal f PWM _0° and the second clock signal f PWMThe second comparator CMP2 is used to compare the second sawtooth wave signal VRAMP2 with the first voltage signal COMP_I and generate a second trigger signal according to the comparison result; the second SR trigger SR2 is used to generate a second pulse width modulation signal PWM2 according to the second trigger signal.

[0081] It can be understood that, in some embodiments, the first sawtooth wave signal VRAMP1 and the second sawtooth wave signal VRAMP2 can be generated by the above-mentioned first sawtooth wave generating circuit 301 and the second sawtooth wave generating circuit 302 respectively. In other embodiments, the first sawtooth wave signal VRAMP1 and the second sawtooth wave signal VRAMP2 can also be generated by a sawtooth wave generating circuit, which is not limited here.

[0082] Figure 5 The fourth structural diagram of the control circuit for the three-level topology circuit provided in the embodiment of the present application is shown in FIG. Figure 5 As shown, in some embodiments, the control circuit of this embodiment further includes a sawtooth wave generating circuit 300, which is used to generate the first sawtooth wave signal VRAMP1 and the second sawtooth wave signal VRAMP2 with a phase difference of 180°, and make the first sawtooth wave signal VRAMP1 and the second sawtooth wave signal VRAMP2 have the same waveform.

[0083] Figure 7 For a schematic diagram of the sawtooth wave generating circuit structure provided in the embodiment of the present application, please refer to Figure 7As shown, the sawtooth wave generating circuit includes a second signal amplifier AMP2, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a sixth resistor R6, a fifth capacitor C5, a sixth capacitor C6, a first switch tube M1 and a second switch tube M2. The in-phase input terminal of the second signal amplifier AMP2 is used to receive a sampled voltage signal. Specifically, the sampled voltage signal in this embodiment is K*Vin. The inverting input terminal of the second signal amplifier AMP2 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is grounded GND; the output terminal of the second signal amplifier AMP2 is connected to the control electrode of the fifth transistor Q5, the first electrode of the fifth transistor Q5 is connected to the first end of the sixth resistor R6, the second electrode of the fifth transistor Q5 is connected to the second electrode of the sixth transistor Q6, and the first electrode of the sixth transistor Q6 is also used to receive a second voltage signal, and the second voltage signal is used to provide the required working voltage to the first electrode of the sixth transistor Q6. The control electrode of the seventh transistor Q7 is connected to the control electrode of the sixth transistor Q6, the first electrode of the seventh transistor Q7 is also used to receive the second voltage signal, the second electrode of the seventh transistor Q7 is connected to the first end of the fifth capacitor C5, the second end of the fifth capacitor C5 is grounded, the first electrode of the first switch tube M1 is connected to the first end of the fifth capacitor C5, the second electrode of the first switch tube M1 is grounded, and the control electrode of the first switch tube M1 is used to receive the first clock signal f PWM _0°; The first end of the fifth capacitor C5 is the first sawtooth wave signal output end, which is used to output the first sawtooth wave signal VRAMP1. Among them, the control electrode of the eighth transistor Q8 is connected to the control electrode of the seventh transistor Q7, the first electrode of the eighth transistor Q8 is also used to receive the second voltage signal, the second electrode of the eighth transistor Q8 is connected to the first end of the sixth capacitor C6, the second end of the sixth capacitor C6 is grounded GND, the first electrode of the second switch tube M2 is connected to the first end of the sixth capacitor C6, the second electrode of the second switch tube M2 is grounded GND, and the control electrode of the second switch tube M2 is used to receive the second clock signal f PWM _180°; the first end of the sixth capacitor C6 is the second sawtooth wave signal output end, which is used to output the second sawtooth wave signal VRAMP2.

[0084] Among them, each device in the two-way sawtooth wave generating circuit of this embodiment is designed with devices of the same specifications and parameters, so that the slope gain of the two-way sawtooth wave signals generated is the same, that is, the waveforms of the two-way sawtooth wave signals generated are the same, and they only differ in phase by 180°, so that the duty cycles of the two-way sawtooth wave signals obtained are the same.

[0085] Figure 8 FIG. 1 is a schematic diagram of a process of generating a trigger signal according to a sawtooth wave signal and a first voltage signal in an embodiment of the present application. Figure 8As shown, in this embodiment, the working process of the first comparator CMP1 is taken as an example. The first comparator CMP1 compares the first sawtooth wave signal VRAMP1 and the first voltage signal COMP_I to generate a corresponding first trigger signal, which is specifically a CLK signal. Specifically, when the voltage value of the first voltage signal COMP_I is less than the first sawtooth wave signal VRAMP1, a low level signal is generated, and when the voltage value of the first voltage signal COMP_I is greater than the first sawtooth wave signal VRAMP1, a high level signal is generated. Finally, the first SR trigger SR1 is triggered according to the CLK trigger signal and the first clock signal f PWM _0°generates a first pulse width modulation signal PWM1.

[0086] It can be understood that, in the sawtooth wave generating circuit in this embodiment, the input sampling voltage signal K*Vin is proportional to the voltage Vin provided by the power supply, and then through the design of the current mirror circuit, the seventh transistor Q7 and the eighth transistor Q8 respectively form two current mirrors with the same current, thereby making the waveforms of the generated two sawtooth wave signals the same.

[0087] Fig. 9 For a schematic diagram of the waveforms of various signals when the control circuit provided in the embodiment of the present application is working, please refer to Fig. 9 As shown, Fig. 9 (a) shows the waveform diagram of each signal in the control circuit when the duty cycle is greater than 0.5. Fig. 9 (b) shows a waveform diagram of each signal in the control circuit when the duty cycle is greater than 0.5. Taking the case where the duty cycle is greater than 0.5 as an example, when there are two clock signals and sawtooth wave signals with a phase difference of 180°, four transistor drive signals are generated according to the two pulse width modulation signals generated. The four transistor drive signals are Q1_ON, Q2_ON, Q3_ON and Q4_ON, respectively. Q1_ON, Q2_ON, Q3_ON and Q4_ON are used to control the on and off of the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4. Among them, Fig. 9 IL in FIG. 1 is a waveform diagram of the instantaneous current on the first inductor L1 in the three-level topology circuit.

[0088] According to the control circuit provided in this embodiment, two sawtooth wave signals with a phase difference of 180° are compared with the first voltage signal COMP_I to generate a first pulse width modulation signal PWM1 and a second pulse width modulation signal PWM2; the three-level topology circuit is controlled according to the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2, so that the three-level topology circuit can switch smoothly at each duty cycle, thereby ensuring the stability of the circuit during operation.

[0089] An embodiment of the present application further provides a chip, which includes the control circuit for the three-level topology circuit as described above.

[0090] An embodiment of the present application further provides an electronic device, which includes the control circuit for the three-level topology circuit as described above; or the electronic device includes the chip as described above.

[0091] It can be understood that the chips and electronic devices provided in other embodiments have the same technical effects as the above-mentioned control circuit, and will not be described in detail here.

[0092] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A control circuit for a three-level topology circuit, the three-level topology circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a first inductor, the first transistor, the second transistor, the third transistor and the fourth transistor are sequentially connected in series between a power supply and a ground terminal, the first capacitor is connected in parallel to both ends of the second transistor and the third transistor, the first end of the first inductor is connected to the middle point of the second transistor and the third transistor, the second end of the first inductor is a voltage output terminal, and the voltage output terminal is used to output a discharge voltage; It is characterized in that The control circuit comprises: a current sampling circuit, a voltage sampling circuit, a current loop integrator, a first modulation signal generating circuit and a second modulation signal generating circuit; The sampling end of the current sampling circuit is connected to the two ends of the first inductor, and the output end of the current sampling circuit is connected to the inverting input end of the current loop integrator; the sampling end of the voltage sampling circuit is connected to the voltage output end, and the output end of the voltage sampling circuit is connected to the non-inverting input end of the current loop integrator; the output end of the current loop integrator is respectively connected to the input ends of the first modulation signal generating circuit and the second modulation signal generating circuit; The current sampling circuit is used to sample the inductor current signal on the first inductor; the voltage sampling circuit is used to sample the discharge voltage signal on the voltage output terminal and convert the discharge voltage signal into a first current signal; the current loop integrator is used to integrate the inductor current signal and the first current signal to obtain a first voltage signal; The first modulation signal generating circuit is used to receive a first sawtooth wave signal, and generate a first pulse width modulation signal according to the first sawtooth wave signal and the first voltage signal; the second modulation signal generating circuit is used to receive a second sawtooth wave signal, and generate a second pulse width modulation signal according to the second sawtooth wave signal and the first voltage signal; the phase difference between the first sawtooth wave signal and the second sawtooth wave signal is 180°; The first pulse width modulation signal is used to control the on and off of the first transistor and the fourth transistor; the second pulse width modulation signal is used to control the on and off of the second transistor and the third transistor.

2. The control circuit for a three-level topology circuit according to claim 1, characterized in that: The current sampling circuit includes a first resistor, a second capacitor and a first signal amplifier; The first end of the first resistor is connected to the first end of the first inductor, the second end of the first resistor is connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the second end of the first inductor; the first end of the first resistor and the second end of the second capacitor are sampling ends of the current sampling circuit; The first end of the second capacitor is connected to the non-inverting input end of the first signal amplifier, the second end of the second capacitor is connected to the inverting input end of the first signal amplifier, and the output end of the first signal amplifier is the output end of the current sampling circuit.

3. The control circuit for a three-level topology circuit according to claim 1 or 2, characterized in that: The voltage sampling circuit includes a second resistor, a third resistor and a voltage loop integrator; The first end of the second resistor is the sampling end of the voltage sampling circuit, the first end of the second resistor is connected to the voltage output end, the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded; The first end of the second resistor is also connected to the inverting input end of the voltage loop integrator. The non-inverting input end of the voltage loop integrator is used to receive a reference voltage signal. The output end of the voltage loop integrator is the output end of the voltage sampling circuit. The output end of the voltage loop integrator is connected to the non-inverting input end of the current loop integrator.

4. The control circuit for a three-level topology circuit according to claim 3, characterized in that: The voltage sampling circuit also includes a fourth resistor and a third capacitor; A first end of the fourth resistor is connected to the output end of the voltage loop integrator, a second end of the fourth resistor is connected to a first end of the third capacitor, and a second end of the third capacitor is grounded.

5. The control circuit for a three-level topology circuit according to claim 1 or 2, characterized in that: Also includes a fifth resistor and a fourth capacitor; A first end of the fifth resistor is connected to the output end of the current loop integrator, a second end of the fifth resistor is connected to a first end of the fourth capacitor, and a second end of the fourth capacitor is grounded.

6. The control circuit for a three-level topology circuit according to claim 1 or 2, characterized in that: The first modulation signal generating circuit includes a first comparator and a first SR trigger; the non-inverting input terminal of the first comparator is used to receive the first sawtooth wave signal, the inverting input terminal of the first comparator is connected to the output terminal of the current loop integrator, and the output terminal of the first comparator is connected to the reset input terminal of the first SR trigger; The set input terminal of the first SR trigger is used to receive a first clock signal; The first comparator is used to compare the first sawtooth wave signal with the first voltage signal, and generate a first trigger signal according to the comparison result; The first SR trigger is used to generate the first pulse width modulation signal according to the first trigger signal; The second modulation signal generating circuit includes a second comparator and a second SR trigger; the non-inverting input terminal of the second comparator is used to receive the second sawtooth wave signal, the inverting input terminal of the second comparator is connected to the output terminal of the current loop integrator, and the output terminal of the second comparator is connected to the reset input terminal of the second SR trigger; The set input terminal of the second SR flip-flop is used to receive a second clock signal; The phase difference between the first clock signal and the second clock signal is 180°; The second comparator is used to compare the second sawtooth wave signal with the first voltage signal, and generate a second trigger signal according to the comparison result; The second SR trigger is used to generate the second pulse width modulation signal according to the second trigger signal.

7. The control circuit for a three-level topology circuit according to claim 6, characterized in that: It also includes a sawtooth wave generating circuit; the sawtooth wave generating circuit is used to generate the first sawtooth wave signal and the second sawtooth wave signal with a phase difference of 180°.

8. The control circuit for a three-level topology circuit according to claim 7, characterized in that: The sawtooth wave generating circuit includes a second signal amplifier, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a sixth resistor, a fifth capacitor, a sixth capacitor, a first switch tube and a second switch tube; The non-inverting input terminal of the second signal amplifier is used to receive the sampling voltage signal, the inverting input terminal of the second signal amplifier is connected to the first terminal of the sixth resistor, and the second terminal of the sixth resistor is grounded; the output terminal of the second signal amplifier is connected to the control electrode of the fifth transistor, the first electrode of the fifth transistor is connected to the first terminal of the sixth resistor, the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor, and the first electrode of the sixth transistor is used to receive the second voltage signal; The control electrode of the seventh transistor is connected to the control electrode of the sixth transistor, the first electrode of the seventh transistor is also used to receive the second voltage signal, the second electrode of the seventh transistor is connected to the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, the first electrode of the first switch tube is connected to the first end of the fifth capacitor, the second electrode of the first switch tube is grounded, and the control electrode of the first switch tube is used to receive the first clock signal; the first end of the fifth capacitor is a first sawtooth wave signal output end, used to output the first sawtooth wave signal; The control electrode of the eighth transistor is connected to the control electrode of the seventh transistor, the first electrode of the eighth transistor is also used to receive the second voltage signal, the second electrode of the eighth transistor is connected to the first end of the sixth capacitor, the second end of the sixth capacitor is grounded, the first electrode of the second switch tube is connected to the first end of the sixth capacitor, the second electrode of the second switch tube is grounded, and the control electrode of the second switch tube is used to receive the second clock signal; the first end of the sixth capacitor is a second sawtooth wave signal output end, which is used to output the second sawtooth wave signal.

9. A chip, characterized in that: The invention comprises a control circuit for a three-level topology circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a control circuit for a three-level topology circuit as claimed in any one of claims 1 to 8; or comprises a chip as claimed in claim 9.

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