Continuous data receiving and processing method, device, medium and system based on cyclic RAM (Random Access Memory)

Abstract

The invention discloses a continuous data receiving and processing method, device, medium and system based on a cyclic RAM, and belongs to the field of spaceflight measurement and control communication, and the method comprises the steps: a PS unit and a PL unit of a ZYNQ chip in the system are connected through an AXI bus; and the received data Ch1 RecvData to ChNRecvData are interconnected with the PL unit by using an SPI (Serial Peripheral Interface) bus. The PL unit stores the received data into a DataRAM, the packet length is stored into a LenRAM, and enqueue pointer counting of the PL unit is updated; and the PS unit reads the LenRAM according to the counting difference value of the in-queue and out-queue pointers in a timed query mode, and reads data in the DataRAM according to the numerical value of the LenRAM for subsequent processing. The invention provides a solution which is simple in software implementation and improves the quantity of different data types stored at the receiving end at the same time.

Description

Technical Field

[0001] The present invention relates to the field of aerospace measurement and control communications, and more specifically, to a method, device, medium and system for receiving and processing continuous data based on cyclic RAM. Background Art

[0002] As a new generation of fully programmable system-on-chip (APSOC), ZYNQ perfectly integrates the software programmability of the processor with the hardware programmability of the FPGA, and has high flexibility and scalability to adapt to different application requirements. In recent years, ZYNQ has been increasingly used as a main control chip in the hardware design of the aerospace measurement and control field.

[0003] With the development of measurement and control technology, the receiving end needs to process more and more data patterns at higher and higher rates. The receiving end needs to receive a complete data packet before it can perform subsequent parsing and processing. In current system applications, most application scenarios store the received data in the local cache RAM or FIFO of the ZYNQ chip programmable logic (PL unit). After receiving a complete data packet, the data is parsed and processed through an interrupt or a timed query of the ZYNQ chip processor (PS unit). When the receiving end receives data from multiple hardware devices at the same time, it usually uses a ping-pong cache. For example, if 2 different types of data are received at the same time, they are stored in 2 RAMs or FIFOs; if 3 different types of data are received at the same time, they are stored in 3 RAMs or FIFOs; and so on, there are as many different types of data as there are stored in RAMs or FIFOs.

[0004] The above scheme has certain limitations, mainly in that different types of data have different lengths and different transmission intervals. The receiving end needs to define the size of the receiving end's cache RAM or FIFO based on the largest data length, so as to maximize the cache ping-pong function and make each cache RAM or FIFO used. Taking the ZYNQ chip 7Z045 as an example, the total number of RAM resources inside the 7Z045 is 545 36Kbit RAM units. Assuming that the length of the received data packet is 8Byte to 256KByte, since the size of the RAM needs to be defined based on the maximum length of the received data packet, the minimum storage capacity of a single RAM at the receiving end must reach 256KByte. Receiving 1 type of data requires 57 36Kbit RAM units, receiving 4 different types of data requires 228 36Kbit RAM units, and receiving 10 different types of data requires 570 36Kbit RAM units, which has exceeded the total number of 545 RAM resources inside the single ZYNQ chip 7Z045. The above calculation only calculates the amount of RAM resources required for the first-level storage of received data at the receiving end. In actual use, the post-processing will also occupy a large amount of RAM resources.

[0005] The above solution is simple to implement, but as the number of data types simultaneously received by the first stage increases, firstly, the resource usage of the first-stage RAM will be greatly increased, squeezing the RAM resources required for the subsequent processing; secondly, as the uneven length of the received data packets increases, for example, when the length of a certain type of data further increases, the number of data types simultaneously received by the first stage will be further compressed; thirdly, the extensive use of RAM resources will inevitably bring about the problem of timing convergence within the PL unit. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method, device, medium and system for receiving and processing continuous data based on cyclic RAM. Without increasing the system hardware cost and the limited RAM resources of the existing ZYNQ chip, the number of data types that can be stored simultaneously at the receiving end can be increased, the complexity of software design implementation can be reduced, and the reliability of the system can be effectively improved.

[0007] The object of the present invention is achieved through the following solutions:

[0008] A method for receiving and processing continuous data based on a cyclic RAM is based on a ZYNQ chip PS unit, a ZYNQ chip PL unit, and receiving data Ch1_Recv_Data to receiving data ChN_Recv_Data, and performs the following steps:

[0009] Step S1, connecting the PS unit of the ZYNQ chip to the PL unit, the connection includes connecting using an AXI bus; receiving data Ch1_Recv_Data to ChN_Recv_Data and interconnecting with the PL unit of the ZYNQ chip, the interconnection includes interconnecting using an SPI bus;

[0010] Step S2, using the PL unit to receive data from the received data Ch1_Recv_Data to the received data ChN_Recv_Data, storing the data in Data_RAM, storing the data packet length in Len_RAM, and updating the PL unit queue pointer count; the PS unit reads Len_RAM according to the difference between the queue pointer counts through a timed query method;

[0011] Step S3, according to the read Len_RAM length value, read the data of corresponding length in Data_RAM for subsequent processing.

[0012] Furthermore, the ZYNQ chip includes a Xilinx-7Z045 device or a domestically produced device FMQ-7Z045.

[0013] Furthermore, the PL unit includes: a packet-level RAM module and an enqueue pointer counting module, the packet-level RAM module consists of data Data_RAM and length Len_RAM; wherein Data_RAM is defined according to a capacity of 1MByte and occupies 228 36Kbit RAM units; Len_RAM is defined according to a capacity of 8KByte and occupies 2 36Kbit RAM units; a total of 230 36Kbit RAM units are occupied.

[0014] Further, in step S2, the use of the PL unit to receive data from the received data Ch1_Recv_Data to the received data ChN_Recv_Data specifically includes sub-steps: the PL unit receives data through the SPI bus, the received data Ch1_Recv_Data to ChN_Recv_Data, and the packet length ranges from 8Byte to 256KByte.

[0015] Further, in step S2, the updating of the PL unit queue pointer count specifically includes the following sub-steps:

[0016] The number of received data packets is accumulated and counted using the queue pointer counting module of the PL unit. The counter bit width of the queue pointer counting module is selected to be 64 bits. Each time the length Len_RAM is written, the counter performs an increment operation.

[0017] Furthermore, the PS unit includes a timing query function module, a receiving data processing function module and a dequeue pointer counting function module, wherein the dequeue pointer counting function adopts a 64-bit counting form. Each time the timing interval arrives, the dequeue pointer counting function is called to determine whether there is a new data packet in the PL unit packet-level RAM that needs to be read by comparing the difference between the in-queue and out-queue pointer counts, and the data packet is handed over to the receiving data processing function module for subsequent processing.

[0018] A method for receiving and processing continuous data based on a cyclic RAM is based on a ZYNQ chip PS unit and a ZYNQ chip PL unit. The ZYNQ chip PS unit is connected to the PL unit, and also includes a PL unit receiving data processing flow: the PL unit receiving data processing flow enters an initial state after power-on reset is completed, and monitors whether a new data packet arrives. If so, it enters a current data packet reception completion judgment flow, otherwise it continues to monitor; in the current data packet reception completion judgment flow, if so, it enters an update queue pointer count state, otherwise it continues to judge; after the queue pointer count is updated, it returns to the initial state.

[0019] A method for receiving and processing continuous data based on a cyclic RAM is based on a ZYNQ chip PS unit and a ZYNQ chip PL unit. The ZYNQ chip PS unit and the PL unit are connected, and also includes a PS unit receiving data processing flow: the PS unit receiving data processing flow enters an initial state after power-on reset is completed, monitors whether the timing query time has arrived, otherwise continues to monitor, if yes, then turns to a read queue pointer count state, after reading the queue pointer count value, enters a flow of judging whether the queue pointer counts are equal, if yes, it means that no new data packet has arrived for this query, and returns to the initial state; otherwise, it means that a new data packet has arrived for this query, and enters a state of reading Len_RAM value;

[0020] After reading the Len_RAM value, enter the process of judging whether the length value corresponding to Len_RAM is reached by reading Data_RAM. If yes, enter the state of updating the dequeue pointer count, otherwise continue to judge. After the dequeue pointer count is updated, return to the process of judging whether the in-queue pointer count is equal.

[0021] A continuous data receiving and processing device based on cyclic RAM comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, any of the above methods is executed.

[0022] A computer-readable storage medium stores a computer program, wherein the computer program executes any of the above methods when loaded by a processor.

[0023] A continuous data receiving and processing system based on cyclic RAM comprises the device as described above.

[0024] The beneficial effects of the present invention include:

[0025] (1) The solution of the present invention increases the number of different data types that can be stored simultaneously at the receiving end, and uses a cyclic RAM continuous storage method. On the one hand, it effectively improves the utilization rate of RAM resources and avoids defining each RAM according to the maximum length of all received data packets, which can effectively reduce the occupancy of RAM space; on the other hand, when the dynamic balance of the received data packet length range occurs, the data types that can be received simultaneously can be greatly increased.

[0026] (2) The scheme of the present invention reduces the complexity of software design and improves the data processing capability of the PS unit at the later stage. By adopting the packet-level RAM (data RAM + length RAM) method, the continuously input data can be restored into data packets one by one, and the data packets and the corresponding data packet lengths are recorded in the RAM. Through the handshake method of in-and-out queue pointer counting, on the one hand, the PS unit can effectively and smoothly process multiple data packets with very small continuous packet lengths; on the other hand, since the data packets and the data packet lengths are stored in the RAM, it is convenient for the later stage to have the ability to obtain the same data multiple times, which has certain advantages when recovering from the error site. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0028] Figure 1 The figure is a schematic diagram of a method for receiving and processing continuous data based on cyclic RAM according to an embodiment of the present invention.

[0029] Figure 2 for Figure 1 Implementation schematic diagram.

[0030] Figure 3 for Figure 2 Flowchart of data receiving and processing by PL unit.

[0031] Figure 4 for Figure 2 Flowchart of data receiving and processing by PS unit. DETAILED DESCRIPTION

[0032] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0033] The specific implementation process of the present invention is as follows:

[0034] like Figure 1 As shown, the present invention provides a method for receiving and processing continuous data based on cyclic RAM, comprising: a ZYNQ chip PS unit, a ZYNQ chip PL unit and received data Ch1_Recv_Data to received data ChN_Recv_Data. The ZYNQ chip PS unit and the PL unit are connected using an AXI bus; the received data Ch1_Recv_Data to ChN_Recv_Data are interconnected with the ZYNQ chip PL unit using an SPI bus.

[0035] like Figure 2 As shown, the ZYNQ chip uses the imported Xilinx-7Z045 device or the corresponding domestically produced device FMQ-7Z045.

[0036] The PL unit includes a packet-level RAM module and an enqueue pointer counting module. The packet-level RAM module consists of Data_RAM and Len_RAM. Data_RAM is defined as 1MByte capacity and occupies 228 36Kbit RAM units; Len_RAM is defined as 8KByte capacity and occupies 2 36Kbit RAM units; a total of 230 36Kbit RAM units are occupied.

[0037] Figure 2 In the example, the PL unit receives data through the SPI bus, which are: received data Ch1_Recv_Data~ChN_Recv_Data, and the packet length ranges from 8Byte to 256KByte. Continuously storing 8Byte data packets, a maximum of 131072 packets can be stored (equivalent to storing 131072 different types of single data packet length data); continuously storing 256Byte data packets, a maximum of 4096 packets can be stored (equivalent to storing 4096 different types of single data packet length data); continuously storing 4KByte data packets, a maximum of 256 packets can be stored (equivalent to storing 256 different types of single data packet length data); continuously storing 256KByte data packets, a maximum of 4 packets can be stored (equivalent to storing 4 different types of single data packet length data). It can be seen that when using continuous RAM storage, the number of data packet types stored in a single packet is linearly inversely proportional to the size of the data packet; the smaller the data packet length, the more obvious the advantage of continuous RAM storage. However, the fixed RAM usage method defined according to the maximum data packet length will cause a large waste of RAM resources when the length of the received data packet is small.

[0038] Figure 2 In the PL unit, the main function of the queue pointer counting module is to accumulate and count the number of received data packets. The counter bit width of the queue pointer counting module is selected as 64 bits. Each time the length Len_RAM is written, the counter performs an increment operation.

[0039] Figure 2 In the PS unit, the timing query function, the receiving data processing function and the dequeue pointer counting function are composed of the timing query function, the receiving data processing function and the dequeue pointer counting function, in which the dequeue pointer counting function adopts the 64-bit counting form. Every time the timing interval arrives, the dequeue pointer counting function is called to compare the difference between the in-queue pointer count and the out-queue pointer count to determine whether there is a new data packet in the PL unit packet level RAM that needs to be read, and then hand it over to the receiving data processing function for subsequent processing.

[0040] like Figure 3 As shown, the data receiving process in the PL unit enters the initial state after the power-on reset is completed. Monitor whether there is a new data packet arriving, and if so, enter the process of judging whether the current data packet has been received. In the process of judging whether the current data packet has been received, if yes, enter the state of updating the queue pointer count; after the queue pointer count is updated, return to the initial state.

[0041] like Figure 4 As shown, the data receiving processing flow in the PS unit enters the initial state after the power-on reset is completed. Monitor whether the scheduled query time has arrived. If so, enter the read queue pointer count state. After reading the queue pointer count value, enter the equal judgment process of the queue pointer counts. If so, it means that there is no new data packet arriving for this query, and return to the initial state; otherwise, it means that there is a new data packet arriving for this query, and enter the read Len_RAM value state. After reading the Len_RAM value, enter the judgment process of whether the reading Data_RAM reaches the length value corresponding to Len_RAM. If so, enter the update dequeue pointer count state; after the dequeue pointer count is updated, return to the equal judgment process of the queue pointer counts. By using the above-mentioned queue pointer count cycle comparison, multiple data packets in the PL unit package-level RAM can be taken away at one time through a scheduled query and handed over to the subsequent receiving data processing function, which can effectively improve the efficiency of PS reading data.

[0042] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0043] Example 1

[0044] A method for receiving and processing continuous data based on a cyclic RAM is based on a ZYNQ chip PS unit, a ZYNQ chip PL unit, and receiving data Ch1_Recv_Data to receiving data ChN_Recv_Data, and performs the following steps:

[0045] Step S1, connecting the PS unit of the ZYNQ chip to the PL unit, the connection includes connecting using an AXI bus; receiving data Ch1_Recv_Data to ChN_Recv_Data and interconnecting with the PL unit of the ZYNQ chip, the interconnection includes interconnecting using an SPI bus;

[0046] Step S2, using the PL unit to receive data from the received data Ch1_Recv_Data to the received data ChN_Recv_Data, storing the data in Data_RAM, storing the data packet length in Len_RAM, and updating the PL unit queue pointer count; the PS unit reads Len_RAM according to the difference between the queue pointer counts through a timed query method;

[0047] Step S3, according to the read Len_RAM length value, read the data of corresponding length in Data_RAM for subsequent processing.

[0048] Example 2

[0049] Based on Example 1, the ZYNQ chip includes a Xilinx-7Z045 device or a domestically produced device FMQ-7Z045.

[0050] Example 3

[0051] On the basis of Example 1, the PL unit includes: a packet-level RAM module and an enqueue pointer counting module, the packet-level RAM module consists of data Data_RAM and length Len_RAM; wherein Data_RAM is defined according to a capacity of 1MByte and occupies 228 36Kbit RAM units; Len_RAM is defined according to a capacity of 8KByte and occupies 2 36Kbit RAM units; a total of 230 36Kbit RAM units are occupied.

[0052] Example 4

[0053] On the basis of Example 1, in step S2, the PL unit is used to receive data from received data Ch1_Recv_Data to received data ChN_Recv_Data, specifically including sub-steps: the PL unit receives data through the SPI bus, the received data Ch1_Recv_Data to ChN_Recv_Data, and the packet length ranges from 8Byte to 256KByte.

[0054] Example 5

[0055] Based on Embodiment 1, in step S2, the updating of the PL unit queue pointer count specifically includes the following sub-steps:

[0056] The number of received data packets is accumulated and counted using the queue pointer counting module of the PL unit. The counter bit width of the queue pointer counting module is selected to be 64 bits. Each time the length Len_RAM is written, the counter performs an increment operation.

[0057] Example 6

[0058] Based on Example 1, the PS unit includes a timing query function module, a receiving data processing function module and a dequeue pointer counting function module, wherein the dequeue pointer counting function adopts a 64-bit counting form. Each time the timing interval arrives, the dequeue pointer counting function is called, and by comparing the difference between the in-queue and out-queue pointer counts, it is determined whether there is a new data packet in the PL unit packet-level RAM that needs to be read, and the data packet is handed over to the receiving data processing function module for subsequent processing.

[0059] Example 7

[0060] A method for receiving and processing continuous data based on a cyclic RAM is based on a ZYNQ chip PS unit and a ZYNQ chip PL unit. The ZYNQ chip PS unit is connected to the PL unit, and also includes a PL unit receiving data processing flow: the PL unit receiving data processing flow enters an initial state after power-on reset is completed, and monitors whether a new data packet arrives. If so, it enters a current data packet reception completion judgment flow, otherwise it continues to monitor; in the current data packet reception completion judgment flow, if so, it enters an update queue pointer count state, otherwise it continues to judge; after the queue pointer count is updated, it returns to the initial state.

[0061] Example 8

[0062] A method for receiving and processing continuous data based on a cyclic RAM is based on a ZYNQ chip PS unit and a ZYNQ chip PL unit. The ZYNQ chip PS unit and the PL unit are connected, and also includes a PS unit receiving data processing flow: the PS unit receiving data processing flow enters an initial state after power-on reset is completed, monitors whether the timing query time has arrived, otherwise continues to monitor, if yes, then turns to a read queue pointer count state, after reading the queue pointer count value, enters a flow of judging whether the queue pointer counts are equal, if yes, it means that no new data packet has arrived for this query, and returns to the initial state; otherwise, it means that a new data packet has arrived for this query, and enters a state of reading Len_RAM value;

[0063] After reading the Len_RAM value, enter the process of judging whether the length value corresponding to Len_RAM is reached by reading Data_RAM. If yes, enter the state of updating the dequeue pointer count, otherwise continue to judge. After the dequeue pointer count is updated, return to the process of judging whether the in-queue pointer count is equal.

[0064] Example 9

[0065] A continuous data receiving and processing device based on cyclic RAM includes a processor and a memory, wherein a computer program is stored in the memory. When the computer program is loaded by the processor, the method described in any one of Embodiments 1 to 8 is executed.

[0066] Example 10

[0067] A computer-readable storage medium stores a computer program, and when the computer program is loaded by a processor, the method described in any one of Embodiments 1 to 8 is executed.

[0068] Embodiment 11

[0069] A continuous data receiving and processing system based on cyclic RAM includes the device described in Example 9.

[0070] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0071] According to one aspect of an embodiment of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations.

[0072] As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

Claims

1. A method for receiving and processing continuous data based on cyclic RAM, characterized in that: Based on the ZYNQ chip PS unit, the ZYNQ chip PL unit, and the received data Ch1_Recv_Data to the received data ChN_Recv_Data, the following steps are performed: Step S1, connecting the PS unit of the ZYNQ chip to the PL unit, the connection includes connecting using an AXI bus; receiving data Ch1_Recv_Data to ChN_Recv_Data and interconnecting with the PL unit of the ZYNQ chip, the interconnection includes interconnecting using an SPI bus; Step S2, using the PL unit to receive data from the received data Ch1_Recv_Data to the received data ChN_Recv_Data, storing the data in Data_RAM, storing the data packet length in Len_RAM, and updating the PL unit queue pointer count; the PS unit reads Len_RAM according to the difference between the queue pointer counts through a timed query method; Step S3, according to the read Len_RAM length value, read the data of corresponding length in Data_RAM for subsequent processing.

2. The method for receiving and processing continuous data based on cyclic RAM according to claim 1, characterized in that: The ZYNQ chip includes a Xilinx-7Z045 device or a domestically produced FMQ-7Z045 device.

3. The method for receiving and processing continuous data based on cyclic RAM according to claim 1, characterized in that: The PL unit includes: a packet-level RAM module and an enqueue pointer counting module, the packet-level RAM module consists of data Data_RAM and length Len_RAM; wherein Data_RAM is defined according to 1MByte capacity and occupies 228 36Kbit RAM units; Len_RAM is defined according to 8KByte capacity and occupies 2 36Kbit RAM units; a total of 230 36Kbit RAM units are occupied.

4. The method for receiving and processing continuous data based on cyclic RAM according to claim 1, characterized in that: In step S2, the PL unit is used to receive data from the received data Ch1_Recv_Data to the received data ChN_Recv_Data, which specifically includes sub-steps: the PL unit receives data through the SPI bus, and the received data Ch1_Recv_Data to ChN_Recv_Data have a packet length ranging from 8 Byte to 256 KByte.

5. The method for receiving and processing continuous data based on cyclic RAM according to claim 3, characterized in that: In step S2, the updating of the PL unit queue pointer count specifically includes the following sub-steps: The number of received data packets is accumulated and counted using the queue pointer counting module of the PL unit. The counter bit width of the queue pointer counting module is selected to be 64 bits. Each time the length Len_RAM is written, the counter performs an increment operation.

6. The method for receiving and processing continuous data based on cyclic RAM according to claim 1, characterized in that: The PS unit includes a timing query function module, a receiving data processing function module and a dequeue pointer counting function module, wherein the dequeue pointer counting function adopts a 64-bit counting form. Each time the timing interval arrives, the dequeue pointer counting function is called to determine whether there is a new data packet in the PL unit packet-level RAM that needs to be read by comparing the difference between the in-queue and out-queue pointer counts, and hand it over to the receiving data processing function module for subsequent processing.

7. A method for receiving and processing continuous data based on cyclic RAM, characterized in that: Based on the ZYNQ chip PS unit and the ZYNQ chip PL unit, the ZYNQ chip PS unit is connected to the PL unit and also includes the PL unit receiving data processing flow: the PL unit receiving data processing flow enters the initial state after the power-on reset is completed, and monitors whether there is a new data packet arriving. If so, it enters the current data packet reception completion judgment flow, otherwise it continues to monitor; in the current data packet reception completion judgment flow, if so, it enters the update queue pointer count state, otherwise it continues to judge; after the queue pointer count is updated, it returns to the initial state.

8. A method for receiving and processing continuous data based on cyclic RAM, characterized in that: Based on the ZYNQ chip PS unit and the ZYNQ chip PL unit, the ZYNQ chip PS unit is connected to the PL unit, and also includes the PS unit receiving data processing flow: the PS unit receiving data processing flow enters the initial state after the power-on reset is completed, monitors whether the timing query time has arrived, otherwise continues to monitor, if yes, then turns to the read queue pointer count state, after reading the queue pointer count value, enters the queue pointer count and whether the equal judgment flow is entered, if yes, it means that no new data packet has arrived for this query, and returns to the initial state; Otherwise, it means that a new data packet has arrived for this query, and the state of reading Len_RAM value has been entered; After reading the Len_RAM value, enter the process of judging whether the length value corresponding to Len_RAM is reached by reading Data_RAM. If yes, enter the state of updating the dequeue pointer count, otherwise continue to judge. After the dequeue pointer count is updated, return to the process of judging whether the in-queue pointer count is equal.

9. A continuous data receiving and processing device based on cyclic RAM, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 1 to 8 is executed.

10. A computer-readable storage medium, characterized in that: A computer program is stored in a readable storage medium, and when the computer program is loaded by a processor, the method according to any one of claims 1 to 8 is executed.

11. A continuous data receiving and processing system based on cyclic RAM, characterized in that: Comprising the device as claimed in claim 9.

Images