Semiconductor device, manufacturing method thereof, and memory system

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and a memory system, and the semiconductor device comprises a memory array structure which comprises a memory array; the high-voltage device integrated structure comprises a high-voltage device peripheral circuit of the storage array, and the high-voltage device peripheral circuit comprises a plurality of high-voltage semiconductor devices; the low-voltage device integration structure comprises a low-voltage device peripheral circuit of the storage array, and the low-voltage device peripheral circuit comprises a plurality of low-voltage semiconductor devices; in the first direction, the storage array structure is located between the high-voltage device integration structure and the low-voltage device integration structure and connected with the high-voltage device integration structure and the low-voltage device integration structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] In recent years, the development of memory has been particularly rapid. The main feature of memory is that it can retain stored information for a long time without power supply, and has the advantages of high integration, fast access speed, easy erasure and rewriting, etc. Therefore, it has been widely used in many fields such as microcomputers and automatic control.

[0003] As the manufacturing process of memory becomes more and more difficult, how to reduce the difficulty of memory manufacturing has become an urgent problem to be solved. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, and a storage system to reduce the difficulty of manufacturing the semiconductor device.

[0005] In a first aspect, the present application provides a semiconductor device, the semiconductor device comprising:

[0006] A storage array structure, including a storage array;

[0007] A high-voltage device integrated structure, including a high-voltage device peripheral circuit of the memory array, wherein the high-voltage device peripheral circuit includes a plurality of high-voltage semiconductor devices; and

[0008] A low-voltage device integrated structure, including a low-voltage device peripheral circuit of the storage array, wherein the low-voltage device peripheral circuit includes a plurality of low-voltage semiconductor devices;

[0009] Wherein, in the first direction, the storage array structure is located between the high-voltage device integrated structure and the low-voltage device integrated structure, and is connected to the high-voltage device integrated structure and the low-voltage device integrated structure.

[0010] In some embodiments, the storage array structure includes a storage area, and the storage array structure includes:

[0011] a stacking structure stacked along the first direction; and

[0012] A plurality of channel structures, located in the storage area and penetrating the stack structure along the first direction, the channel structure comprising a first channel connection end and a second channel connection end located at opposite sides of the stack structure in the first direction, the first channel connection end being close to the high voltage device integrated structure, and the second channel connection end being close to the low voltage device integrated structure;

[0013] The high-voltage device peripheral circuit is connected to the first channel connection terminal;

[0014] The low voltage device peripheral circuit is connected to the second channel connection terminal.

[0015] In some embodiments, the storage array structure further includes:

[0016] A common source is located on a side of the stack structure away from the high-voltage device integrated structure in the first direction, and the second channel connection ends of the plurality of channel structures extend into the common source, and the common source is connected to the low-voltage device peripheral circuit.

[0017] In some embodiments, the storage array structure further includes:

[0018] The connecting wire is located at a side of the common source away from the stacking structure and connects the common source and the peripheral circuit of the low-voltage device.

[0019] In some embodiments, the memory array structure further includes a first bonding layer, which is located on a side of the connecting wire away from the stacking structure and includes a first bonding contact connected to the connecting wire;

[0020] The low voltage device integrated structure further includes a second bonding layer, the second bonding layer includes a second bonding contact connected to the peripheral circuit of the low voltage device, and the second bonding contact is bonded to the first bonding contact.

[0021] In some embodiments, the storage array structure further includes:

[0022] The first through-array connection contact extends along the first direction and connects the high-voltage device peripheral circuit and the low-voltage device peripheral circuit.

[0023] In some embodiments, the memory array structure further includes a peripheral region and a step region adjacent to the memory region in a second direction, the second direction intersecting the first direction;

[0024] The first through-array connection contacts are located in the peripheral area and / or the step area.

[0025] In some embodiments, the storage array structure further includes:

[0026] a third bonding layer, located between the stacked structure and the high-voltage device integrated structure, and comprising a third bonding contact connected to the first channel connection end;

[0027] The high-voltage device integrated structure further includes a fourth bonding layer, wherein the fourth bonding layer includes a fourth bonding contact connected to the peripheral circuit of the high-voltage device, and the fourth bonding contact is bonded to the third bonding contact.

[0028] In some embodiments, the storage array structure further includes a step region adjacent to the storage region in a second direction, the second direction intersecting the first direction;

[0029] The stacked structure comprises a plurality of gate layers spaced apart along the first direction, wherein the plurality of gate layers respectively form a plurality of step surfaces in the step region;

[0030] The storage array structure also includes: multiple gate contact structures, located in the step area and respectively connected to the multiple gate layers, the multiple gate contact structures have a first contact end close to the high-voltage device integrated structure, and the first contact ends of the multiple gate contact structures are connected to the high-voltage device peripheral circuit.

[0031] In some embodiments, the memory array structure further includes: an isolation layer, at least a portion of which is located in the step region, and in the first direction, the isolation layer is located on a side of the stack structure away from the high-voltage device integrated structure;

[0032] Wherein, in the first direction, the gate contact structure further has a second contact end arranged opposite to the first contact end, and in the first direction, the second contact end protrudes from the stacking structure and extends into the isolation layer.

[0033] In some embodiments, the memory array structure further includes a peripheral area, and the memory array structure further includes:

[0034] A second through-array connection pad is located in the peripheral area and extends along the first direction;

[0035] The low voltage device integrated structure includes a pad portion, and the second through array connection contact connects the pad portion and the high voltage device peripheral circuit; or,

[0036] The high-voltage device integrated structure includes a pad portion, and a second through-array connection contact connects the pad portion and the low-voltage device peripheral circuit.

[0037] In some embodiments, the high-voltage semiconductor device includes a first transistor, the first transistor including a first gate insulating layer;

[0038] The low voltage semiconductor device includes a second transistor, the second transistor includes the second gate insulating layer, and the thickness of the second gate insulating layer is smaller than the thickness of the first gate insulating layer.

[0039] In a second aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0040] forming a memory array on the first semiconductor layer;

[0041] forming a high-voltage device peripheral circuit of the memory array on the second semiconductor layer, wherein the high-voltage device peripheral circuit includes a plurality of high-voltage semiconductor devices;

[0042] Disposing the high-voltage device peripheral circuit between the second semiconductor layer and the memory array in the first direction, so that the first semiconductor layer is located on a side of the memory array away from the second semiconductor layer, and connecting the memory array and the high-voltage device peripheral circuit;

[0043] forming a low-voltage device peripheral circuit of the memory array on the third semiconductor layer, wherein the low-voltage device peripheral circuit includes a plurality of low-voltage semiconductor devices;

[0044] removing at least a portion of the first semiconductor layer; and

[0045] The low voltage device peripheral circuit is disposed between the third semiconductor layer and the memory array in the first direction, and the memory array and the low voltage device peripheral circuit are connected.

[0046] In some embodiments, forming a memory array on the first semiconductor layer includes:

[0047] The step of forming a memory array on the first semiconductor layer comprises:

[0048] forming a stacked layer stacked along the first direction on the first semiconductor layer, the stacked layer comprising a plurality of sacrificial layers spaced apart along the first direction;

[0049] forming a channel structure penetrating the stacked layer along the first direction in a first region of the first semiconductor layer, the channel structure comprising a first channel connecting end and a second channel connecting end located at opposite sides of the stacked layer in the first direction, the second channel connecting end extending into the first semiconductor layer; and

[0050] Replacing the multiple sacrificial layers of the stacked layer with multiple gate layers to form a stacked structure, wherein the first channel connection end and the second channel connection end of the channel structure are located at opposite sides of the stacked structure in the first direction;

[0051] The connecting the storage array and the high voltage device peripheral circuit comprises:

[0052] Disposing the high-voltage device peripheral circuit close to the first channel connection end in the first direction, and connecting the first channel connection end of the channel structure with the high-voltage device peripheral circuit;

[0053] The connecting the storage array and the low voltage device peripheral circuit comprises:

[0054] The low voltage device peripheral circuit is arranged close to the second channel connection end in the first direction, and the second channel connection end of the channel structure and the low voltage device peripheral circuit are connected.

[0055] In some embodiments, removing at least a portion of the first semiconductor layer comprises:

[0056] removing a portion of the first semiconductor layer located in the first region;

[0057] The method further comprises: after removing the portion of the first semiconductor layer located in the first region, exposing the second channel connection end of the channel structure; and

[0058] A common source is formed on a side of the second channel connection end away from the stack structure, and the second channel connection end of the channel structure extends into the common source and contacts the common source.

[0059] In some embodiments, the method further comprises:

[0060] providing the first semiconductor layer; and

[0061] pre-burying a common source layer in the first semiconductor layer;

[0062] The forming of a channel structure penetrating the stacked layers along the first direction in the first region of the first semiconductor layer includes: extending the second channel connecting end of the channel structure into the common source layer and contacting the common source layer.

[0063] In some embodiments, removing at least a portion of the first semiconductor layer further comprises: thinning a surface of the first semiconductor layer away from the stacked structure to expose the common source layer;

[0064] The method also includes: removing the portion of the common source layer outside the first region and retaining the portion of the common source layer in the first region, the remaining common source layer constitutes a common source, and the second channel connection end of the channel structure extends into the common source and contacts the common source.

[0065] In some embodiments, after forming the common source, the method further includes:

[0066] A connecting wire is formed on a side of the common source away from the stacking structure in the first direction, and the connecting wire is connected to the common source.

[0067] In some embodiments, connecting the storage array with the low voltage device peripheral circuit includes:

[0068] forming a first bonding layer on a side of the connecting wire away from the stacking structure in the first direction, the first bonding layer comprising a first bonding contact connected to the connecting wire;

[0069] forming a second bonding layer on a side of the low voltage device peripheral circuit away from the third semiconductor layer, the second bonding layer comprising a second bonding contact connected to the low voltage device peripheral circuit; and

[0070] The first bonding contact and the second bonding contact are bonded.

[0071] In some embodiments, the method further comprises:

[0072] forming a first through array connection contact extending along the first direction on the first semiconductor layer; and

[0073] The first through-array connection contacts are used to connect the high-voltage device peripheral circuit and the low-voltage device peripheral circuit.

[0074] In some embodiments, forming a first through array connection contact on the first semiconductor layer includes:

[0075] forming the first through array connection contact in the second region of the first semiconductor layer, the second region is arranged adjacent to the first region in a second direction, the stacking structure is located in the first region and the second region, and the second direction intersects the first direction; and / or,

[0076] The first through array connection pads are formed in a third region of the first semiconductor layer, and the third region is adjacent to the stacking structure in the second direction.

[0077] In some embodiments, the method further comprises:

[0078] forming a third bonding layer on a side of the stacked layer away from the first semiconductor layer, wherein the third bonding layer includes a third bonding contact connected to the first channel connection end;

[0079] forming a fourth bonding layer on a side of the high-voltage device peripheral circuit away from the second semiconductor layer, the fourth bonding layer comprising a fourth bonding contact connected to the high-voltage device peripheral circuit; and

[0080] The third bonding contact is bonded to the fourth bonding contact.

[0081] In some embodiments, the method further comprises:

[0082] forming a plurality of gate contact structures in a second region of the first semiconductor layer, the plurality of gate contact structures being respectively connected to the plurality of sacrificial layers, the gate contact structures having a first contact end away from the first semiconductor layer, the second region being adjacent to the first region along a second direction, and the second direction intersecting the first direction; and

[0083] The high-voltage device peripheral circuit is arranged close to the first contact end, and the first contact ends of a plurality of gate contact structures are connected to the high-voltage device peripheral circuit.

[0084] In some embodiments, forming a plurality of gate contact structures in the second region further comprises:

[0085] Extending the second contact end of the gate contact structure into the first semiconductor layer, the second contact end and the first contact end being arranged opposite to each other in the first direction;

[0086] The removing at least a portion of the first semiconductor layer comprises:

[0087] removing a portion of the first semiconductor layer located in the second region;

[0088] The method further includes: forming an isolation layer on a side of the second contact end away from the stack structure, wherein the second contact end of the gate contact structure extends into the isolation layer.

[0089] In some embodiments, the method further comprises:

[0090] forming a second through array connection contact in a third region of the first semiconductor layer, the third region being disposed adjacent to the stacked structure in the second direction, the second direction intersecting the first direction; and

[0091] A pad portion is formed on a side of the third semiconductor layer away from the low-voltage device peripheral circuit, and the second through-array connection contact connects the pad portion and the high-voltage device peripheral circuit; or,

[0092] A pad portion is formed on a side of the second semiconductor layer away from the high-voltage device peripheral circuit, and the second through-array connection contact connects the pad portion and the low-voltage device peripheral circuit.

[0093] In some embodiments, the high-voltage device peripheral circuit of the memory array formed on the second semiconductor layer includes:

[0094] forming a first transistor including a first gate insulating layer on the second semiconductor layer;

[0095] The low-voltage device peripheral circuit of the memory array formed on the third semiconductor layer includes:

[0096] A second transistor including a second gate insulating layer is formed on the third semiconductor layer, wherein the thickness of the second gate insulating layer is less than the thickness of the first gate insulating layer.

[0097] In a third aspect, the present application provides a storage system, the storage system comprising:

[0098] A memory, comprising the semiconductor device according to any of the above embodiments; and

[0099] The controller is connected to the memory and is used to control the memory.

[0100] In some embodiments of the present application, the high-voltage device peripheral circuit of the storage array is formed on the second conductor layer, so that the high-voltage device peripheral circuit of the storage array is integrated into a high-voltage device integrated structure, and the process window of multiple high-voltage semiconductor devices of the high-voltage device peripheral circuit is increased, thereby reducing the manufacturing difficulty of the high-voltage device peripheral circuit of the storage array. Moreover, the low-voltage device peripheral circuit of the storage array is formed on the third semiconductor layer, so that the low-voltage device peripheral circuit of the storage array is integrated into a low-voltage device integrated structure, and the process window of multiple low-voltage semiconductor devices of the low-voltage device peripheral circuit is increased, thereby reducing the manufacturing difficulty of the low-voltage device peripheral circuit. The manufacturing difficulty of the high-voltage device peripheral circuit and the low-voltage device peripheral circuit is reduced, so that the manufacturing difficulty of the semiconductor device is reduced.

[0101] In addition, the memory array is connected to the high-voltage device peripheral circuit, at least a portion of the first semiconductor layer is removed, and the memory array is connected to the low-voltage device peripheral circuit. In this way, the high-voltage device peripheral circuit and the low-voltage device peripheral circuit are respectively connected to opposite sides of the memory array, simplifying the manufacturing process of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;

[0103] Figures 2 to 8 A schematic diagram of a process for manufacturing a semiconductor device according to some embodiments of the present application;

[0104] Figures 9 and 10 A schematic diagram of a process for manufacturing semiconductor devices according to other embodiments of the present application;

[0105] Fig.11 A block diagram of a storage system according to some embodiments of the present application;

[0106] Fig.12 A block diagram of a storage system according to some other embodiments of the present application;

[0107] Fig.13 A block diagram of an electronic device according to some embodiments of the present application.

[0108] Reference numerals:

[0109] 100, semiconductor device; 200, memory; 300, controller; 400, storage system; 500, electronic device; 600, host;

[0110] 1', initial storage array structure; 1, storage array structure; 1a, storage area; 1b, step area; 1c, peripheral area;

[0111] 01, first semiconductor layer; 01a, first region; 01b, second region; 01c, third region; 113, dielectric layer;

[0112] 11, storage array; 111, stacking structure; 112, stacking layer;

[0113] 12, channel structure; 12a, first channel connection end; 12b, second channel connection end; 121, channel layer; 122, blocking layer; 123, charge trapping layer; 124, tunneling layer;

[0114] Common source; 131, common source layer;

[0115] 142, a first connecting wire; 141, a second connecting wire;

[0116] First bonding layer; 1511, first bonding contact; 152, third bonding layer; 1521, third bonding contact;

[0117] 161, sacrificial layer; 162, gate layer; 162a, step surface; 163, gate dielectric layer;

[0118] 17, gate contact structure; 17a, first contact end; 17b, second contact end; 171, gate contact penetration portion; 172, gate contact portion; 173, gate contact insulating portion;

[0119] 18, isolation layer;

[0120] 191, first through-array connection contact; 1911, first conductive connection portion; 1912, first insulating portion; 192, second through-array connection contact; 1921, second conductive connection portion; 1922, second insulating portion;

[0121] 2, high-voltage device integrated structure; 21, high-voltage device peripheral circuit; 211, high-voltage semiconductor device; 2111, first transistor; 2112, first gate insulating layer; 212, first page buffer circuit; 213, string driving circuit; 22, fourth bonding layer; 221, fourth bonding contact; 02, second semiconductor layer;

[0122] 3', initial low voltage device integrated structure; 3, low voltage device integrated structure; 31, low voltage device peripheral circuit; 311, low voltage semiconductor device; 3111, second transistor; 3112, second gate insulating layer; 312, second page buffer circuit; 313, connection contact; 3131, first connection contact; 3132, second connection contact; 32, second bonding layer; 321, second bonding contact; 03, third semiconductor layer;

[0123] 4, pad portion; 41, first pad portion; 42, second pad portion; 5, insulating layer;

[0124] z, first direction; x, second direction. DETAILED DESCRIPTION

[0125] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0126] Figure 1 Schematic diagram of a method for manufacturing a semiconductor device according to some embodiments of the present application. Figure 1 As shown, the method comprises the following steps:

[0127] S101: forming a memory array on the first semiconductor layer;

[0128] S102: forming a high-voltage device peripheral circuit of a memory array on the second semiconductor layer, wherein the high-voltage device peripheral circuit includes a plurality of high-voltage semiconductor devices;

[0129] S103: arranging the high-voltage device peripheral circuit between the second semiconductor layer and the memory array in the first direction, so that the first semiconductor layer is located on a side of the memory array away from the second semiconductor layer, and connecting the memory array and the high-voltage device peripheral circuit;

[0130] S104: forming a low-voltage device peripheral circuit of a storage array on the third semiconductor layer, wherein the low-voltage device peripheral circuit includes a plurality of low-voltage semiconductor devices;

[0131] S105: removing at least a portion of the first semiconductor layer; and

[0132] S106: Disposing the low-voltage device peripheral circuit between the third semiconductor layer and the memory array in the first direction, and connecting the memory array and the low-voltage device peripheral circuit.

[0133] In some embodiments of the present application, the high-voltage device peripheral circuit of the memory array is formed on the second semiconductor layer, so that the high-voltage device peripheral circuit of the memory array is integrated into a high-voltage device integrated structure, and the process window of multiple high-voltage semiconductor devices of the high-voltage device peripheral circuit is increased, thereby reducing the difficulty of manufacturing the high-voltage device peripheral circuit of the memory array. In addition, the low-voltage device peripheral circuit of the memory array is formed on the third semiconductor layer, so that the low-voltage device peripheral circuit of the memory array is integrated into a low-voltage device integrated structure, and the process window of multiple low-voltage semiconductor devices of the low-voltage device peripheral circuit is increased, thereby reducing the difficulty of manufacturing the low-voltage device peripheral circuit.

[0134] In addition, the memory array is connected to the high-voltage device peripheral circuit, at least a portion of the first semiconductor layer is removed, and the memory array is connected to the low-voltage device peripheral circuit. In this way, the high-voltage device peripheral circuit and the low-voltage device peripheral circuit are respectively connected to opposite sides of the memory array, simplifying the manufacturing process of the semiconductor device.

[0135] Figures 2 to 8 The following is a schematic diagram of the process of manufacturing the semiconductor device of some embodiments of the present application. Figure 1 , Figures 2 to 8 The manufacturing methods of semiconductor devices according to some embodiments of the present application are described in detail.

[0136] First, refer to Figure 2 and Figure 3 As shown, the above step S101 is performed to form a memory array on the first semiconductor layer.

[0137] In some embodiments, Figure 2 As shown, the first semiconductor layer 01 includes a first region 01a, a second region 01b and a third region 01c. The first region 01a and the second region 01b are adjacently arranged in the second direction x, and the third region 01c is adjacently arranged to the first region 01a. The first region 01a is used to form a storage array. The second region 01b is used to form a step. The third region 01c is arranged around the first region 01a.

[0138] Exemplarily, in the second direction x, there are two first regions 01a and two second regions 01b, the two second regions 01b are adjacent to each other, the two first regions 01a are located on opposite sides of the two second regions 01b, and the third region 01c is arranged around the first region 01a, but is not limited thereto.

[0139] Exemplarily, the material of the first semiconductor layer 01 includes but is not limited to a single element semiconductor material (such as silicon or polysilicon), a III-V compound semiconductor material, a II-VI compound semiconductor material, an organic semiconductor material or other semiconductor materials known in the art.

[0140] In some embodiments, forming a memory array on the first semiconductor layer includes: forming a stacked layer 112 stacked along a first direction z on the first semiconductor layer 01, the stacked layer 112 being located in the first region 01a and the second region 01b. The second direction x intersects the first direction z.

[0141] Exemplarily, two stacked layers 112 are disposed on the first semiconductor layer 01 along the second direction x at intervals, but the invention is not limited thereto, and the number of the stacked layer 112 may also be one.

[0142] Exemplarily, the second direction x is perpendicular to the first direction z, but is not limited thereto.

[0143] In some embodiments, one stacked layer 112 includes a plurality of sacrificial layers 161 and a plurality of gate dielectric layers 163 alternately arranged along a first direction z.

[0144] Exemplarily, the sacrificial layer 161 and the gate dielectric layer 163 are both formed by a thin film deposition process, including but not limited to a chemical vapor deposition process (CVD), a plasma enhanced chemical vapor deposition process (PCVD), an atomic layer deposition process (ALD), or a combination thereof.

[0145] Exemplarily, the material of the sacrificial layer 161 includes, but is not limited to, silicon nitride. The material of the gate dielectric layer 163 includes, but is not limited to, silicon oxide.

[0146] In some embodiments, Figure 2 As shown, forming a storage array on the first semiconductor layer also includes: forming a channel structure 12 that penetrates the stacked layer 112 along a first direction z in a first region 01a of the first semiconductor layer 01, the channel structure 12 includes a first channel connection end 12a and a second channel connection end 12b located on opposite sides of the stacked layer 112 in the first direction z, and the second channel connection end 12b extends into the first semiconductor layer 01.

[0147] In some embodiments, a first region 01a is provided with a plurality of channel structures 12, each channel structure 12 penetrates the stacked layer 112 and extends into the first semiconductor layer 01. Each channel structure 12 includes a blocking layer 122, a charge trapping layer 123, a tunneling layer 124, and a channel layer 121 arranged sequentially from the outside to the inside. The channel layer 121 is used to transport charges. The first channel connection end 12a and the second channel connection end 12b are two opposite parts of the channel layer 121 in the first direction z.

[0148] In some embodiments, the blocking layer 122 , the charge trapping layer 123 , the tunneling layer 124 , and the channel layer 121 all extend into the first semiconductor layer 01 .

[0149] Exemplarily, the blocking layer 122, the charge trapping layer 123 and the tunneling layer 124 may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. The material of the channel layer 121 includes but is not limited to polysilicon. The space inside the channel layer 121 is filled with a channel filling layer, and the material of the channel filling layer includes but is not limited to silicon oxide or silicon oxynitride.

[0150] In some embodiments, Figure 3 As shown, forming a memory array on the first semiconductor layer further includes: replacing the multiple sacrificial layers 161 of the stacked layer 112 with multiple gate layers 162 to form a stacked structure 111. The stacked structure 111 and the channel structure 12 constitute a memory array 11, and the memory array 11 is located in the first area 01a. The stacked structure 111 is located in the first area 01a and the second area 01b, and is adjacent to the third area 01c.

[0151] In some embodiments, the plurality of sacrificial layers 161 are replaced by a plurality of gate layers 162 via gate line gaps (not shown). The plurality of gate layers 162 form a plurality of step surfaces 162a in the second region 01b.

[0152] Exemplarily, when the number of the stacked layers 112 is two, the number of the stacked structures 111 is also two.

[0153] Exemplarily, the material of the gate layer 162 includes, but is not limited to, metals, and the metals include, but are not limited to, tungsten, cobalt, copper, nickel, and combinations thereof.

[0154] In some embodiments, the first channel connection end 12 a and the second channel connection end 12 b of the channel structure 12 are located at opposite sides of the stack structure 111 in the first direction z.

[0155] In some embodiments, Figure 2 As shown, the method further includes: forming a dielectric layer 113 in the second region 01 b and the third region 01 c of the first semiconductor layer 01 .

[0156] In some embodiments, the dielectric layer 113 covers the stacked layer 112 in the second region 01 b and fills the entire third region 01 c .

[0157] Exemplarily, the above-mentioned thin film deposition process is used to form the dielectric layer 113. The material of the dielectric layer 113 includes but is not limited to silicon nitride, silicon oxide, silicon oxynitride or any combination thereof.

[0158] In some embodiments, Figure 2 As shown, the method further includes: forming a plurality of gate contact structures 17 in the second region 01b of the first semiconductor layer 01, wherein at least a portion of the gate contact structures 17 penetrates a portion of the dielectric layer 113, and the plurality of gate contact structures 17 are respectively connected to the plurality of sacrificial layers 161. The gate contact structure 17 has a first contact end 17a away from the first semiconductor layer 01.

[0159] It should be noted that if Figure 3 As shown, after the multiple sacrificial layers 161 are replaced with multiple gate layers 162 , the multiple gate contact structures 17 are respectively connected to the multiple gate layers 162 .

[0160] Exemplarily, in the stack structure 111 , the plurality of gate contact structures 17 are connected to the plurality of gate layers 162 one-to-one.

[0161] In some embodiments, Figure 2 As shown, the method further includes: making the gate contact structure 17 penetrate the stacked layer 112, and making the second contact end 17b of the gate contact structure 17 extend into the first semiconductor layer 01, and the second contact end 17b and the first contact end 17a are arranged opposite to each other in the first direction z. Through this design, the gate contact hole provided with the gate contact structure 17 and the channel hole provided with the channel structure 12 can be formed by one photomask and the same etching process, thereby reducing the etching times of deep holes and shallow holes, reducing the number of photomasks required for manufacturing semiconductor devices, and reducing the cost of manufacturing semiconductor devices.

[0162] In some embodiments, the gate contact structure 17 includes a gate contact penetration portion 171 and a gate contact portion 172, and the gate contact penetration portion 171 and the gate contact portion 172 both extend along the first direction z and are connected. The gate contact penetration portion 171 penetrates the stacked layer 112 along the first direction z. The gate contact portion 172 penetrates the dielectric layer 113 along the first direction z, and one end of the gate contact portion 172 close to the gate contact penetration portion 171 is connected to the gate contact penetration portion 171 and contacts the sacrificial layer 161.

[0163] In some embodiments, the size of the gate contact portion 172 along the first direction x is greater than the size of the gate contact penetration portion 171 along the first direction x, so that the gate contact portion 172 can contact the corresponding gate layer 162 to connect the gate contact portion 172 to the corresponding gate layer 162 .

[0164] Exemplarily, one end of the gate contact penetration portion 171 away from the gate contact portion 172 is the second contact end 17b. One end of the gate contact portion 172 away from the gate contact penetration portion 171 is the first contact end 17a.

[0165] Exemplarily, the material of the gate contact penetration portion 171 and the gate contact portion 172 includes, but is not limited to, metal, and the metal includes, but is not limited to, tungsten, cobalt, copper, nickel, and combinations thereof.

[0166] In some embodiments, the gate contact structure 17 further includes a gate contact insulating portion 173. The gate contact insulating portion 173 covers the sidewalls and bottom wall of the gate contact penetration portion 171, and the bottom wall of the gate contact penetration portion 171 is embedded in the first semiconductor layer 01. The gate contact insulating portion 173 also covers the sidewalls of the gate contact portion 172.

[0167] It should be noted that if Figure 3 As shown, the gate contact insulating portion 173 on the sidewall of the gate contact penetration portion 171 isolates the gate contact penetration portion 171 from the gate layer 162 it penetrates. One end of the gate contact portion 172 close to the gate contact penetration portion 171 is also in contact with the gate layer 162 .

[0168] Exemplarily, the material of the gate contact insulating portion 173 includes, but is not limited to, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0169] Exemplarily, the gate contact portions 172 of the plurality of gate contact structures 17 are respectively connected to the plurality of step surfaces 162 a of the plurality of gate layers 162 in a one-to-one manner, but the present invention is not limited thereto.

[0170] In some other embodiments, the gate contact structure 17 may also include a gate contact portion 172 instead of a gate contact penetration portion 171 .

[0171] In some embodiments, Figure 2 As shown, the method further includes: forming a first through array connection contact 191 extending along a first direction z on the first semiconductor layer 01 , wherein the first through array connection contact 191 extends into the first semiconductor layer 01 .

[0172] It should be noted that, when the high voltage device peripheral circuit 21 and the low voltage device peripheral circuit 31 are respectively integrated on different semiconductor layers, the first through array connection contact 191 is used to connect the high voltage device peripheral circuit 21 and the low voltage device peripheral circuit 31 .

[0173] Exemplarily, the first through-array connection contact 191 penetrates the dielectric layer 113 along the first direction z and extends into the first semiconductor layer 01 .

[0174] In some embodiments, forming a first through array connection pad 191 extending along a first direction z on the first semiconductor layer 01 includes:

[0175] A first through array connection contact 191 is formed in the second region 01 b of the first semiconductor layer 01 ; and / or a first through array connection contact 191 is formed in the third region 01 c of the first semiconductor layer 01 .

[0176] For example, Figure 2 As shown, a first through array connection contact 191 is formed in the third region 01 c of the first semiconductor layer 01 , and the first through array connection contact 191 is disposed adjacent to the channel structure 12 .

[0177] In other embodiments, a first through-array connection contact 191 is formed in the second region 01b of the first semiconductor layer 01, and the first through-array connection contact 191 is spaced apart from the gate contact structure 17; or, a first through-array connection contact 191 is formed in both the third region 01c and the second region 01b of the first semiconductor layer 01.

[0178] In some embodiments, the first through-array connection contact 191 includes a first conductive connection portion 1911 and a first insulating portion 1912, the first conductive connection portion 1911 extends along the first direction z, the first insulating portion 1912 covers the side walls and bottom walls of the first conductive connection portion 1911, and the bottom wall of the first conductive connection portion 1911 is embedded in the first semiconductor layer 01.

[0179] Exemplarily, the material of the first conductive connection part 1911 includes but is not limited to metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel and a combination thereof. The material of the first insulating part 1912 includes but is not limited to silicon nitride, silicon oxide and a combination thereof. 。

[0180] In some embodiments, the method further includes: forming a second through array connection contact 192 in the third region 01 c of the first semiconductor layer 01 .

[0181] In some embodiments of the present application, the second through-array connection pad 192 is used to connect at least one of the high-voltage device peripheral circuit 21 and the low-voltage device peripheral circuit 31 to an external circuit.

[0182] Exemplarily, the second through-array connection contact 192 penetrates the dielectric layer 113 and extends into the first semiconductor layer 01 .

[0183] It should be noted that if Figure 4 As shown, when the first through-array connection contact 191 is also disposed in the third region 01c, the spacing between the second through-array connection contact 192 and the channel structure 12 is greater than the spacing between the first through-array connection contact 191 and the channel structure 12. With this design, the spacing between the first through-array connection contact 191 and the channel structure 12 is smaller, thereby shortening the length of the wire connecting the first through-array connection contact 191 and the channel structure 12.

[0184] In some embodiments, the second through array connection pad 192 includes a second conductive connection portion 1921 and a second insulating portion 1922. The second conductive connection portion 1921 extends along the first direction z, the second insulating portion 1922 covers the sidewall and bottom wall of the second conductive connection portion 1921, and the bottom wall of the second conductive connection portion 1921 is embedded in the first semiconductor layer 01.

[0185] Exemplarily, the material of the second conductive connection part 1921 includes but is not limited to metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel and a combination thereof. The material of the second insulating part 1922 includes but is not limited to silicon nitride or silicon oxide. 。

[0186] In some embodiments, Figure 2 As shown, the method further includes: forming a first connecting wire 142 on a side of the plurality of gate contact structures 17 away from the first semiconductor layer 01, the first connecting wire 142 being connected to the first contact ends 17a of at least two gate contact structures 17, and the at least two gate contact structures 17 connected to the first connecting wire 142 being respectively connected to at least two gate layers 162 located in the at least two stacked structures 111 and arranged in the same layer. With this design, by applying a voltage to one first connecting wire 142, at least two gate layers 162 located in the two second regions 01b and arranged in the same layer can be controlled, thereby simplifying the wiring of the semiconductor device.

[0187] Exemplarily, one first connecting wire 142 is connected to the first contact ends 17 a of two gate contact structures 17 .

[0188] In some embodiments, Figure 2As shown, the method further includes: forming a third bonding layer 152 on a side of the stacked layer 112 away from the first semiconductor layer 01 , the third bonding layer 152 including a third bonding contact 1521 connected to the first channel connection terminal 12 a .

[0189] In some embodiments, the third bonding layer 152 includes a plurality of third bonding contacts 1521 , which are respectively connected to the first channel connection end 12a of the channel structure 12 , the first connection wire 142 , the first through-array connection contact 191 , and the second through-array connection contact 192 .

[0190] Exemplarily, the material of the third bonding contact 1521 includes metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel, and combinations thereof.

[0191] It should be noted that, through the above step S101 and other steps, the Figure 3 The initial memory array structure 1' is shown.

[0192] Next, refer to Figure 5 As shown, the above step S102 is performed to form a high-voltage device peripheral circuit of the memory array on the second semiconductor layer, and the high-voltage device peripheral circuit includes a plurality of high-voltage semiconductor devices.

[0193] In some embodiments, the high-voltage device peripheral circuit 21 integrates multiple high-voltage semiconductor devices 211 that control the storage array 11 to increase the process window of the multiple high-voltage semiconductor devices 211 while reducing the manufacturing difficulty of the high-voltage device peripheral circuit 21 that controls the storage array 11.

[0194] The high-voltage device peripheral circuit 21 includes a first page buffer (PB) circuit 212 and a string driver (SD) circuit 213. The first page buffer circuit 212 and the string driver circuit 213 each include at least one high-voltage semiconductor device 211. The first page buffer circuit 212 is used to connect to the channel structure 12. The string driver circuit 213 is used to connect to multiple gate contact structures 17, so that the string driver circuit 213 can load a driving signal to multiple gate layers 162.

[0195] Exemplarily, the high-voltage semiconductor device 211 includes but is not limited to semiconductor devices such as transistors and capacitors, wherein the transistor includes but is not limited to a planar transistor (Planar Field Effect Transistor), a fin field effect transistor (Fin Field Effect Transistor) and a gate-all-around field effect transistor (Gate-All-Around Field Effect Transistor).

[0196] Exemplarily, the material of the second semiconductor layer 02 includes but is not limited to a single semiconductor material (such as silicon or polysilicon), a III-V compound semiconductor material, a II-VI compound semiconductor material, an organic semiconductor material or other semiconductor materials known in the art.

[0197] In some embodiments, the high-voltage device peripheral circuit 21 of the memory array 11 formed on the second semiconductor layer 02 includes: a first transistor 2111 including a first gate insulating layer 2112 formed on the second semiconductor layer 02 .

[0198] Exemplarily, the first transistor 2111 is selected from at least one of a P-type transistor and an N-type transistor.

[0199] Exemplarily, the material of the first gate insulating layer 2112 includes, but is not limited to, at least one of silicon nitride and silicon oxide.

[0200] In some embodiments, the method further includes: forming a fourth bonding layer 22 on a side of the high-voltage device peripheral circuit 21 away from the second semiconductor layer 02 , the fourth bonding layer 22 including a fourth bonding contact 221 connected to the high-voltage device peripheral circuit 21 .

[0201] In some embodiments, the fourth bonding layer 22 includes a plurality of fourth bonding contacts 221 , and the plurality of fourth bonding contacts 221 are respectively connected to the first page buffer circuit 212 and the string driving circuit 213 .

[0202] Exemplarily, the material of the fourth bonding contact 221 includes metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel, and combinations thereof.

[0203] It should be noted that, through the above step S102 and other steps, Figure 5 The high voltage device integrated structure 2 is shown.

[0204] Next, refer to Figure 6 As shown, the above step S103 is performed: the high-voltage device peripheral circuit 21 is arranged between the second semiconductor layer 02 and the storage array 11 in the first direction z, so that the first semiconductor layer 01 is located on the side of the storage array 11 away from the second semiconductor layer 02, and the storage array 11 and the high-voltage device peripheral circuit 21 are connected.

[0205] In some embodiments, the above-mentioned setting of the high-voltage device peripheral circuit 21 between the second semiconductor layer 02 and the storage array 11 in the first direction z so that the first semiconductor layer 01 is located on the side of the storage array 11 away from the second semiconductor layer 02 includes: flipping the initial storage array structure 1', setting the initial storage array structure 1' above the high-voltage device integrated structure 2, and the first semiconductor layer 01 of the initial storage array structure 1' is located on the side of the stacking structure 111 away from the high-voltage device integrated structure 2.

[0206] It should be noted that after the initial memory array structure 1 ′ is disposed above the high-voltage device integrated structure 2 , the high-voltage device peripheral circuit 21 is disposed close to the first contact terminal 17 a and the first channel connection terminal 12 a .

[0207] In some embodiments, connecting the memory array 11 and the high-voltage device peripheral circuit 21 includes: bonding the fourth bonding contact 221 and the third bonding contact 1521 .

[0208] In some embodiments, the fourth bonding contact 221 is bonded to the third bonding contact 1521, so that the first channel connection terminal 12a of the channel structure 12 is connected to the high-voltage device peripheral circuit 21, the first contact terminals 17a of the multiple gate contact structures 17 are connected to the high-voltage device peripheral circuit 21, and the first through-array connection contact 191 and the second through-array connection contact 192 are connected to the high-voltage device peripheral circuit 21.

[0209] In some embodiments, the first channel connection terminal 12 a of the channel structure 12 is connected to the first page buffer circuit 212 of the high-voltage device peripheral circuit 21 , and the first contact terminal 17 a of the gate contact structure 17 is connected to the string driving circuit 213 .

[0210] It should be noted that, through the above step S103 , the connection between the storage array 11 and the high-voltage device peripheral circuit 21 is achieved.

[0211] In some embodiments, reference Figure 7 As shown, the above step S104 is performed to form a low-voltage device peripheral circuit 31 of the memory array 11 on the third semiconductor layer 03 . The low-voltage device peripheral circuit 31 includes a plurality of low-voltage semiconductor devices 311 .

[0212] In some embodiments of the present application, the low-voltage device peripheral circuit 31 integrates multiple low-voltage semiconductor devices 311 of the storage array 11 to increase the process window of the multiple low-voltage semiconductor devices 311 while reducing the manufacturing difficulty of the low-voltage device peripheral circuit 31 of the storage array 11.

[0213] The low voltage device peripheral circuit 31 includes a second page buffer circuit 312 , and the second page buffer circuit 312 includes at least one or more low voltage semiconductor devices 311 . The second page buffer circuit 312 is used to connect to the channel structure 12 .

[0214] By way of example, the low voltage semiconductor device 311 includes but is not limited to transistors and capacitors, etc. The transistors include but are not limited to planar transistors, fin field effect transistors and all-around gate transistors.

[0215] Exemplarily, the material of the third semiconductor layer 03 includes but is not limited to a single semiconductor material (such as silicon or polysilicon), a III-V compound semiconductor material, a II-VI compound semiconductor material, an organic semiconductor material or other semiconductor materials known in the art.

[0216] In some embodiments, a low-voltage device peripheral circuit 31 of a storage array 11 is formed on a third semiconductor layer 03 , including: a second transistor 3111 including a second gate insulating layer 3112 is formed on the third semiconductor layer 03 , and the thickness of the second gate insulating layer 3112 is less than the thickness of the first gate insulating layer 2112 .

[0217] Exemplarily, the second transistor 3111 includes but is not limited to a P-type transistor or an N-type transistor.

[0218] Exemplarily, the material of the second gate insulating layer 3112 includes, but is not limited to, at least one of silicon nitride and silicon oxide.

[0219] In some embodiments, Figure 7 As shown, the method further includes: forming a plurality of connection contacts 313 on the third semiconductor layer 03 , wherein the plurality of connection contacts 313 extend along the first direction z and are spaced apart from the low-voltage device peripheral circuit 31 .

[0220] In some embodiments, the plurality of connection contacts 313 include adjacently arranged first connection contacts 3131 and second connection contacts 3132. The first connection contacts 3131 are connected to the low voltage device peripheral circuit 31. The second connection contacts 3132 are used to connect to the second through array connection contacts 192 described above.

[0221] Exemplarily, the material of the connection contact 313 includes metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel, and combinations thereof.

[0222] In some embodiments, Figure 3 As shown, the method further includes: forming a second bonding layer 32 on a side of the low voltage device peripheral circuit 31 away from the third semiconductor layer 03 , the second bonding layer 32 including a second bonding contact 321 connected to the low voltage device peripheral circuit 31 .

[0223] In some embodiments, the second bonding layer 32 includes a plurality of second bonding contacts 321 , and the plurality of second bonding contacts 321 are respectively connected to the low-voltage device peripheral circuit 31 and the plurality of connection contacts 313 .

[0224] It should be noted that, through the above step S104 and other steps, Figure 7 The initial low voltage device integrated structure 3' is shown.

[0225] It should also be noted that the above step S104 can also be performed after step S102 and before step S103.

[0226] In some embodiments, Figure 3 The initial storage array structure shown is connected to Figure 5 After the high voltage device integrated structure 2 is shown, please refer to Figure 6 As shown, the above step S105 is performed: removing at least a portion of the first semiconductor layer 01 .

[0227] In some embodiments of the present application, at least a portion of the first semiconductor layer 01 is removed to facilitate connecting the low-voltage device integrated structure 3 to a side of the stacked structure 111 away from the high-voltage device integrated structure 2 .

[0228] In some embodiments, removing at least a portion of the first semiconductor layer 01 includes: removing a portion of the first semiconductor layer 01 located in the first region 01 a .

[0229] Exemplarily, an etching process is used to remove the portion of the first semiconductor layer 01 located in the first region 01a to form a first semiconductor layer opening (not shown). The etching process includes but is not limited to wet etching or dry etching.

[0230] In some embodiments, after removing the portion of the first semiconductor layer 01 located in the first region 01 a , the method further includes: exposing the second channel connection end 12 b of the channel structure 12 .

[0231] Exemplarily, an etching process is used to remove the blocking layer 122 , the charge trapping layer 123 , and the tunneling layer 124 covering the second channel connection end 12 b , so as to expose the channel layer 121 .

[0232] In some embodiments, Figure 6 As shown, the method further includes: forming a common source 13 on a side of the second channel connection end 12b away from the stack structure 111, and the second channel connection end 12b of the channel structure 12 extends into the common source 13 and contacts the common source 13. The common source 13 is connected to multiple second channel connection ends 12b of multiple channel structures 12.

[0233] Exemplarily, at least two channel structures 12 of a storage region 1 a are connected to a common source 13 .

[0234] Exemplarily, the material of the common source 13 includes but is not limited to conductive materials, and the conductive materials include but are not limited to metals and polysilicon. The metals include but are not limited to tungsten, cobalt, copper, nickel and combinations thereof. Specifically, the material of the common source 13 includes polysilicon.

[0235] In some embodiments, Figure 6 As shown, removing at least part of the first semiconductor layer further includes: removing the part of the first semiconductor layer 01 located in the second area 01b.

[0236] In some embodiments, after removing the portion of the first semiconductor layer 01 located in the second region 01 b , the method further includes: exposing the second contact end 17 b of the gate contact structure 17 .

[0237] Exemplarily, an etching process is used to remove the gate contact insulating portion 173 covering the second contact end 17 b of the gate contact structure 17 .

[0238] In some embodiments, Figure 6 As shown, the method further includes: forming an isolation layer 18 on a side of the second contact end 17b away from the stack structure 111, and the second contact end 17b of the gate contact structure 17 extends into the isolation layer 18. Through this design, the second contact ends 17b of the plurality of gate contact structures 17 are insulated from each other, and it is convenient to connect with the peripheral circuit through the second contact end 17b of the gate contact structure 17, thereby simplifying the wiring design of the semiconductor device.

[0239] Exemplarily, the material of the isolation layer 18 includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof.

[0240] In some embodiments, removing at least a portion of the first semiconductor layer further includes: removing a portion of the first semiconductor layer 01 located in the third region 01 c .

[0241] In some embodiments, after removing the portion of the first semiconductor layer 01 located in the third region 01 c , the method further includes: exposing the first conductive connection portion 1911 of the first through array connection pad 191 , and exposing the second conductive connection portion 1921 of the second through array connection pad 192 .

[0242] Illustratively, an etching process is used to remove the first insulating portion 1912 covering one end of the first conductive connection portion 1911 away from the stack structure 111 , and an etching process is used to remove the second insulating portion 1922 covering one end of the second conductive connection portion 1921 away from the stack structure 111 .

[0243] In some embodiments, the method further includes: forming an isolation layer 18 on a side of the first through array connection pad 191 and the second through array connection pad 192 away from the stack structure 111 .

[0244] It should be noted that, after removing the portions of the first semiconductor layer 01 located in the first region 01a, the second region 01b and the third region 01c, an isolation layer 18 is formed at the location where the first semiconductor layer 01 is removed, and then a portion of the isolation layer 18 is removed to form a common source 13 at the location where the isolation layer 18 is removed.

[0245] In some embodiments, Figure 6 As shown, after forming the common source 13 , the method further includes: forming a second connecting wire 141 on a side of the common source 13 away from the stacking structure 111 in the first direction z, and the second connecting wire 141 is connected to the common source 13 .

[0246] Exemplarily, one second connecting wire 141 is connected to at least two common sources 13 to reduce the number of wirings for transmitting signals to the at least two common sources 13 and simplify the wiring design of the semiconductor device.

[0247] Exemplarily, the material of the second connecting wire 141 includes metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel and a combination thereof.

[0248] In some embodiments, Figure 6 As shown, the method further includes: forming a first bonding layer 151 on a side of the second connecting wire 141 away from the stacking structure 111 in the first direction z, the first bonding layer 151 including a first bonding contact 1511 connected to the second connecting wire 141 .

[0249] In some embodiments, the first bonding layer 151 includes a plurality of first bonding contacts 1511 , and the plurality of first bonding contacts 1511 are respectively connected to the second connection wires 141 , the first through-array connection contacts 191 , and the second through-array connection contacts 192 .

[0250] It should be noted that, through the above step S105 and other steps, Figure 6 The memory array structure 1 is shown, and the memory array structure 1 is connected to the high-voltage device integrated structure 2 .

[0251] It should also be noted that the storage array structure 1 includes adjacently arranged storage areas 1a, step areas 1b, and peripheral areas 1c, the storage area 1a corresponds to the first area 01a of the first semiconductor layer 01, the step area 1b corresponds to the second area 01b of the first semiconductor layer 01, the peripheral area 1c corresponds to the third area 01c of the first semiconductor layer 01, and the peripheral area 1c is arranged around the storage area 1a. The channel structure 12 is arranged in the storage area 1a. The gate contact structure 17 is arranged in the step area 1b. The first through-array connection contact 191 and the second through-array connection contact 192 are both arranged in the peripheral area 1c.

[0252] Finally, please refer to Figure 8 As shown, step S106 is performed: the low-voltage device peripheral circuit is disposed between the third semiconductor layer and the memory array in the first direction, and the memory array and the low-voltage device peripheral circuit are connected.

[0253] In some embodiments, disposing the low-voltage device peripheral circuit between the third semiconductor layer and the storage array in the first direction includes: flipping the above-mentioned initial low-voltage device integrated structure 3', disposing the initial low-voltage device integrated structure 3' on the side of the storage array structure 1 away from the high-voltage device integrated structure 2, so that the low-voltage device peripheral circuit 31 is disposed close to the second channel connection terminal 12b in the first direction z.

[0254] In some embodiments, connecting the memory array with the peripheral circuit of the low voltage device includes: bonding the first bonding contact 1511 and the second bonding contact 321 .

[0255] In some embodiments of the present application, by bonding the first bonding contact 1511 and the second bonding contact 321, the second channel connection end 12b of the channel structure 12 is connected to the low-voltage device peripheral circuit 31, the first through-array connection contact 191 is connected to the high-voltage device peripheral circuit 21 and the low-voltage device peripheral circuit 31, and the second through-array connection contact 192 is connected to the second connection contact 3132. Since the second through-array connection contact 192 is connected to the second connection contact 3132, the second through-array connection contact 192 is connected to the second connection contact 3132 and the high-voltage device peripheral circuit 21.

[0256] In some embodiments, please refer to Figure 8 As shown, the method further includes: forming a pad portion 4 on a side of the third semiconductor layer 03 away from the low voltage device peripheral circuit 31 , and connecting the pad portion 4 and the high voltage device peripheral circuit 21 with the second through array connection contact 192 .

[0257] In some embodiments, the plurality of pad portions 4 include a first pad portion 41 and a second pad portion 42 that are spaced apart. The first pad portion 41 is connected to the first connection pad 3131, so that the first pad portion 41 is connected to the low-voltage device peripheral circuit 31. The second pad portion 42 is connected to the second connection pad 3132, so that the second pad portion 42 is connected to the high-voltage device peripheral circuit 21 through the second connection pad 3132 and the second through-array connection pad 192.

[0258] Exemplarily, the material of the pad portion 4 includes metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel, and combinations thereof.

[0259] In some embodiments, Figure 8 As shown, before forming the pad portion 4 on the side of the third semiconductor layer 03 away from the low-voltage device peripheral circuit 31, the method further includes: thinning the surface of the third semiconductor layer 03 away from the low-voltage device peripheral circuit 31 to expose a plurality of connection contacts 313; and

[0260] An insulating layer 5 is formed on a side of the thinned third semiconductor layer 03 away from the low-voltage device peripheral circuit 31 .

[0261] In some embodiments, forming the pad portion 4 on a side of the third semiconductor layer 03 away from the low-voltage device peripheral circuit 31 includes: removing a portion of the insulating layer 5 to form an insulating layer opening; and

[0262] A pad portion 4 is formed in the insulating layer opening.

[0263] In some other embodiments, the method further includes: forming a pad portion 4 on a side of the second semiconductor layer 02 away from the high voltage device peripheral circuit 21 , and connecting the pad portion 4 and the low voltage device peripheral circuit 31 through the second through array connection contact 192 .

[0264] It should be noted that, in some embodiments of the present application, through the above step S106 and other steps, Figure 8 The low-voltage device integrated structure 3 is shown, and the low-voltage device integrated structure 3 is connected to a side of the storage array structure 1 away from the high-voltage device integrated structure 2 .

[0265] In other embodiments, referring to Fig. 9 Before forming the memory array on the first semiconductor layer, the method further includes: providing a first semiconductor layer 01 ; and pre-burying a common source layer 131 in the first semiconductor layer 01 .

[0266] In some other embodiments, pre-embedding the common source layer 131 in the first semiconductor layer 01 includes:

[0267] A groove (not shown) is formed on the surface of the first semiconductor layer 01 , the groove extending in the thickness direction of the first semiconductor layer 01 ; and the common source layer 131 is filled in the groove.

[0268] In some other embodiments, the material of the common source layer 131 is different from the material of the first semiconductor layer 01 .

[0269] Exemplarily, the material of the common source layer 131 includes, but is not limited to, a conductive material. The conductive material includes, but is not limited to, metals and polysilicon. The metal includes, but is not limited to, tungsten, cobalt, copper, nickel, and combinations thereof. Specifically, the material of the common source layer 131 includes polysilicon.

[0270] In some other embodiments, forming a channel structure penetrating the stacked layer along the first direction in the first region of the stacked layer includes: extending the second channel connection end 12 b of the channel structure into the common source layer 131 and contacting the common source layer 131 .

[0271] In some other embodiments, the channel structure formed in the first region of the stacked layer along the first direction and penetrating the stacked layer includes: forming a channel hole (not shown) penetrating the stacked layer and extending into the common source layer 131; forming a functional layer in the channel hole, removing the functional layer at the bottom of the channel hole, and forming a groove; and forming a channel layer 121 in the groove, wherein the channel layer 121 at the bottom of the groove contacts the common source layer 131. The functional layer includes the blocking layer 122, the charge trapping layer 123, and the tunneling layer 124 arranged from the outside to the inside.

[0272] In some other embodiments, forming a plurality of gate contact structures 17 in the second region 01 b of the first semiconductor layer 01 further includes: extending the gate contact structures 17 into the common source layer 131 .

[0273] In other embodiments, Fig.10 After the initial memory array structure 1 ′ is connected to the high-voltage device integrated structure 2 , the above-mentioned removal of at least part of the first semiconductor layer 01 further includes: thinning the surface of the first semiconductor layer 01 away from the stacking structure 111 to expose the common source layer 131 .

[0274] In other embodiments, after exposing the common source layer 131, the method further includes: removing the portion of the common source layer 131 located outside the first region 01a, and retaining the portion of the common source layer 131 located in the first region 01a, the remaining common source layer 131 constitutes the common source 13, and the second channel connection end 12b of the channel structure 12 extends into the common source 13 and contacts the common source 13.

[0275] In other embodiments of the present application, by pre-burying the common source layer 131 in the first semiconductor layer 01 and extending the second channel connection end 12b of the channel structure 12 into the common source layer 131 while forming the channel structure 12, the damage to the channel structure 12 caused by etching to expose the second channel connection end 12b of the channel structure 12 is improved.

[0276] It should be noted that by Fig. 9 The multiple sacrificial layers 163 of the semiconductor structure shown are replaced by multiple gate layers 162 to obtain Fig.10 The initial memory array structure 1' is shown.

[0277] The following combination Figure 8 A semiconductor device manufactured by using the above-mentioned method for manufacturing a semiconductor device will be described in detail.

[0278] The semiconductor device 100 includes a storage array structure 1, a high voltage device integrated structure 2 and a low voltage device integrated structure 3. In a first direction z, the storage array structure 1 is located between the high voltage device integrated structure 2 and the low voltage device integrated structure 3, and the storage array structure 1 is connected to both the high voltage device integrated structure 2 and the low voltage device integrated structure 3.

[0279] The memory array structure 1 includes a memory area 1a, a step area 1b and a peripheral area 1c. The step area 1b and the peripheral area 1c are adjacent to the memory area 1a in a second direction x, wherein the second direction x intersects with the first direction z.

[0280] Exemplarily, the memory array structure 1 includes two memory areas 1a and two step areas 1b, the two step areas 1b are adjacently arranged, the two memory areas 1a are located on opposite sides of the two step areas 1b, and the peripheral area 1c is arranged around the two memory areas 1a, but is not limited thereto.

[0281] Exemplarily, the second direction x is perpendicular to the first direction z, but is not limited thereto.

[0282] The memory array structure 1 includes a memory array 11 , and the memory array 11 includes a stacking structure 111 stacked along a first direction z and a plurality of channel structures 12 .

[0283] A stacked structure 111 includes a plurality of gate layers 162 and a plurality of gate dielectric layers 163 alternately arranged along a first direction z. The plurality of gate layers 162 of a stacked structure 111 are arranged at intervals along the first direction z. The plurality of gate layers 162 form a plurality of step surfaces 162a in the step region 1b.

[0284] Exemplarily, the storage array structure 1 includes at least two stacked structures 111 disposed at intervals.

[0285] Exemplarily, the material of the gate layer 162 includes, but is not limited to, metal, and the metal includes, but is not limited to, tungsten, cobalt, copper, nickel, and combinations thereof. The material of the gate dielectric layer 163 includes, but is not limited to, silicon oxide.

[0286] A plurality of channel structures 12 are located in the storage area 1a and penetrate the stacked structure 111 along the first direction z. The channel structure 12 includes a first channel connection end 12a and a second channel connection end 12b located on opposite sides of the stacked structure 111 in the first direction z. The first channel connection end 12a is close to the high-voltage device integrated structure 2 and connected to the high-voltage device integrated structure 2. The second channel connection end 12b is close to the low-voltage device integrated structure 3 and connected to the low-voltage device integrated structure 3.

[0287] Exemplarily, each channel structure 12 includes a blocking layer, a charge trapping layer, a tunneling layer and a channel layer arranged in sequence from the outside to the inside. The channel layer is used to transport the required charges. The first channel connection end 12a and the second channel connection end 12b are two opposite parts of the channel layer in the first direction z.

[0288] Exemplarily, the blocking layer, the charge trapping layer and the tunneling layer may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. The material of the channel layer includes, but is not limited to, polysilicon. The space inside the channel layer is filled with a channel filling layer, and the material of the channel filling layer includes, but is not limited to, silicon oxide or silicon oxynitride.

[0289] In some embodiments, the storage array structure 1 also includes a common source 13, which is located on a side of the stacking structure 111 away from the high-voltage device integrated structure 2 in the first direction z, and the second channel connection ends 12b of the multiple channel structures 12 extend into the common source 13, and the common source 13 is connected to the low-voltage device peripheral circuit 31.

[0290] Exemplarily, one common source 13 is connected to the second channel connection ends 12 b of at least two channel structures 12 .

[0291] Exemplarily, the material of the common source 13 includes but is not limited to conductive materials, and the conductive materials include but are not limited to metals and polysilicon. The metals include but are not limited to tungsten, cobalt, copper, nickel and combinations thereof. Specifically, the material of the common source 13 includes polysilicon.

[0292] The memory array structure 1 further includes a second connecting wire 141 . The second connecting wire 141 is located on a side of the common source 13 away from the stacking structure 111 and connects the common source 13 and the low-voltage device peripheral circuit 31 .

[0293] Exemplarily, a second connecting wire 141 is connected to at least two common sources 13, and the second connecting wire 141 is connected to the low-voltage device peripheral circuit 31 to reduce the number of wirings transmitting signals to at least two common sources 13 and simplify the wiring design of the semiconductor device.

[0294] Exemplarily, the material of the second connecting wire 141 includes metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel and a combination thereof.

[0295] The memory array structure 1 further includes a dielectric layer 113 . The dielectric layer 113 is located in the step region 1 b and the peripheral region 1 c . The dielectric layer 113 covers the stacked structure 111 in the step region 1 b and fills the peripheral region 1 c .

[0296] Exemplarily, the material of the dielectric layer 113 includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof.

[0297] The memory array structure 1 further includes a plurality of gate contact structures 17, which are located in the step region 1b and penetrate the dielectric layer 113, and the plurality of gate contact structures 17 are respectively connected to the plurality of gate layers 162. The plurality of gate contact structures 17 have first contact ends 17a close to the high-voltage device integrated structure 2, and the first contact ends 17a of the plurality of gate contact structures are connected to the high-voltage device peripheral circuit 21.

[0298] In some embodiments, the storage array structure 1 also includes a first connecting wire 142, which is connected to the first contact ends 17a of at least two gate contact structures 17, and the at least two gate contact structures 17 connected to the first connecting wire 142 are respectively connected to at least two gate layers 162 located in the same layer and arranged in at least two stacked structures 111.

[0299] The gate contact structure 17 also has a second contact end 17b disposed opposite to the first contact end 17a in the first direction z. The plurality of gate contact structures 17 respectively penetrate the stack structure 111 , and the first contact end 17a and the second contact end 17b of the gate contact structure 17 are respectively located at opposite sides of the stack structure 111 .

[0300] In some embodiments, the gate contact structure 17 includes a gate contact penetration portion and a gate contact portion, and the gate contact penetration portion and the gate contact portion both extend along the first direction z and are connected. The gate contact penetration portion penetrates the stacked structure 111 along the first direction z. The gate contact portion penetrates the dielectric layer 113 along the first direction z, and one end of the gate contact portion close to the gate contact penetration portion is connected to the gate contact penetration portion 171 and contacts the gate layer 162.

[0301] In some embodiments, a dimension of the gate contact portion along the first direction x is greater than a dimension of the gate contact penetration portion along the first direction x, so that the gate contact portion can contact and connect with the corresponding gate layer.

[0302] Exemplarily, one end of the gate contact penetration portion away from the gate contact portion is the second contact end 17b. One end of the gate contact portion away from the gate contact penetration portion is the first contact end 17a.

[0303] Exemplarily, the materials of the gate contact penetration portion and the gate contact portion include, but are not limited to, metals, and the metals include, but are not limited to, tungsten, cobalt, copper, nickel, and combinations thereof.

[0304] In some embodiments, the gate contact structure 17 further includes a gate contact insulating portion. The gate contact insulating portion covers the sidewalls of the gate contact through portion. The gate contact insulating portion also covers the sidewalls of the gate contact portion.

[0305] The memory array structure 1 further includes an isolation layer 18, at least part of which is located in the step region 1b, and in the first direction, the isolation layer 18 is located on a side of the stack structure 111 away from the high-voltage device integrated structure 2. In the first direction z, the second contact end 17b protrudes from the stack structure 111 and extends into the isolation layer 18.

[0306] Exemplarily, the material of the isolation layer 18 includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, or any combination thereof.

[0307] The memory array structure 1 further includes a first through-array connection contact 191. The first through-array connection contact 191 extends along a first direction z, penetrates the dielectric layer 113 and extends into the isolation layer 18. The first through-array connection contact 191 connects the high-voltage device peripheral circuit 21 and the low-voltage device peripheral circuit 31.

[0308] In some embodiments, the first through-array connection pads 191 are located in the peripheral region 1 c and / or the step region 1 b .

[0309] Exemplarily, the first through array connection pad 191 is located in the peripheral area 1c, but not limited thereto, the first through array connection pad 191 may also be located in the step area 1b, or the first through array connection pad 191 may also be located in the peripheral area 1c and the step area 1b.

[0310] In some embodiments, the first through-array connection contact 191 includes a first conductive connection portion and a first insulating portion, the first conductive connection portion extends along a first direction z, the first insulating portion covers the side wall of the first conductive connection portion, and the bottom wall of the first conductive connection portion is embedded in the isolation layer 18 .

[0311] Exemplarily, the material of the first conductive connection portion includes but is not limited to metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel and a combination thereof. The material of the first insulating portion includes but is not limited to silicon nitride or silicon oxide. 。

[0312] The memory array structure 1 further includes a second through-array connection contact 192 , which is located in the peripheral region 1 c and extends along the first direction z.

[0313] In some embodiments, the second through-array connection contacts 192 extend along the first direction z, penetrate the dielectric layer 113 and extend into the isolation layer 18 .

[0314] In some embodiments, when the first through-array connection contact 191 is also disposed in the peripheral region 1 c , the spacing between the second through-array connection contact 192 and the channel structure 12 is greater than the spacing between the first through-array connection contact 191 and the channel structure 12 .

[0315] In some embodiments, the second through array connection pad 192 includes a second conductive connection portion extending along the first direction z and a second insulating portion covering the sidewall of the second conductive connection portion, and a bottom wall of the second conductive connection portion embedded in the isolation layer 18 .

[0316] Exemplarily, the material of the second conductive connection portion includes but is not limited to metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel and a combination thereof. The material of the second insulating portion includes but is not limited to silicon nitride or silicon oxide. 。

[0317] The memory array structure 1 further includes a first bonding layer 151, which is located on a side of the second connection wire 141 away from the stacking structure 111. The first bonding layer 151 includes a plurality of first bonding contacts 1511, which are respectively connected to the second connection wire 141, the first through-array connection contact 191, and the second through-array connection contact 192.

[0318] The memory array structure 1 further includes a third bonding layer 152, which is located between the stacked structure 111 and the high-voltage device integrated structure 2. The third bonding layer 152 includes a plurality of third bonding contacts 1521, which are respectively connected to the first channel connection end 12a of the channel structure 12, the first connection wire 142, the first through-array connection contact 191, and the second through-array connection contact 192.

[0319] The high-voltage device integrated structure 2 includes a second semiconductor layer 02 and a high-voltage device peripheral circuit 21 of a memory array 11 located on the second semiconductor layer 02. The high-voltage device peripheral circuit 21 includes a plurality of high-voltage semiconductor devices 211.

[0320] In some embodiments, the high-voltage device peripheral circuit 21 includes a first page buffer circuit 212 and a string drive circuit 213, and the first page buffer circuit 212 and the string drive circuit 213 each include at least one high-voltage semiconductor device 211. The first page buffer circuit 212 is used to connect to the channel structure 12. The string drive circuit 213 is used to connect to multiple gate contact structures 17, so that the string drive circuit 213 can load signals to multiple gate layers 162.

[0321] In some embodiments, the high-voltage semiconductor device 211 includes a first transistor 2111 including a first gate insulating layer 2112 .

[0322] In some embodiments, the high-voltage device integrated structure 2 further includes a fourth bonding layer 22, which is located on a side of the high-voltage device peripheral circuit 21 away from the second semiconductor layer 02. The fourth bonding layer 22 includes a plurality of fourth bonding contacts 221, which are connected to the high-voltage device peripheral circuit 21 and bonded to the third bonding contacts 1521.

[0323] Exemplarily, the plurality of fourth bonding contacts 221 are respectively connected to the first page buffer circuit 212 and the string driving circuit 213 .

[0324] Since the fourth bonding contact 221 is connected to the high-voltage device peripheral circuit 21, the plurality of third bonding contacts 1521 are respectively connected to the first channel connection terminal 12a of the channel structure 12, the first connection wire 142, the first through-array connection contact 191, and the second through-array connection contact 192, the first connection wire 142 is connected to the first contact terminal 17a of the gate contact structure 17, and the fourth bonding contact 221 is bonded to the third bonding contact 1521. Therefore, the high-voltage device peripheral circuit 21 is connected to the first channel connection terminal 12a, the first contact terminal 17a of the gate contact structure 17, the first through-array connection contact 191, and the second through-array connection contact 192.

[0325] The low voltage device integrated structure 3 includes a third semiconductor layer 03 and a low voltage device peripheral circuit 31 of a memory array 11 located on the third semiconductor layer 03. The low voltage device peripheral circuit 31 includes a plurality of low voltage semiconductor devices 311.

[0326] In some embodiments, the low voltage device peripheral circuit 31 includes a second page buffer circuit 312, and the second page buffer circuit 312 includes at least one or more low voltage semiconductor devices 311. The second page buffer circuit 312 is used to connect with the channel structure 12.

[0327] By way of example, the low voltage semiconductor device 311 includes but is not limited to transistors and capacitors, etc. The transistors include but are not limited to planar transistors, fin field effect transistors and all-around gate transistors.

[0328] In some embodiments, the low voltage semiconductor device 311 includes a second transistor 3111 , the second transistor 3111 includes a second gate insulating layer 3112 , and the thickness of the second gate insulating layer 3112 is less than the thickness of the first gate insulating layer 2112 .

[0329] The low voltage device integrated structure 3 also includes a second bonding layer 32, which is located on the side of the low voltage device peripheral circuit 31 away from the third semiconductor layer 03, and the second bonding layer 32 includes a second bonding contact 321 connected to the low voltage device peripheral circuit 31, and the second bonding contact 321 is bonded to the first bonding contact 1511.

[0330] In some embodiments, the low voltage device integrated structure 3 includes a plurality of connection contacts 313 , and the plurality of connection contacts 313 extend along the first direction z and are spaced apart from the low voltage device peripheral circuit 31 .

[0331] In some embodiments, the plurality of connection contacts 313 include adjacently arranged first connection contacts 3131 and second connection contacts 3132. The first connection contacts 3131 are connected to the low voltage device peripheral circuit 31. The second connection contacts 3132 are connected to the second bonding contacts 321. The second connection contacts 3132 are used to connect to the second through array connection contacts 192.

[0332] Since the second bonding contact 321 is connected to the low-voltage device peripheral circuit 31 and the second connection contact 3132, the plurality of first bonding contacts 1511 are respectively connected to the second connection wire 141, the first through-array connection contact 191 and the second through-array connection contact 192, the second connection wire 141 is connected to the second channel connection terminal 12b, and the second bonding contact 321 is bonded to the first bonding contact 1511. Therefore, the second through-array connection contact 192 connects the low-voltage device peripheral circuit 31 and the high-voltage device peripheral circuit 21, the low-voltage device peripheral circuit 31 is connected to the second channel connection terminal 12b of the channel structure 12, and the second connection contact 3132 is connected to the high-voltage device peripheral circuit 21 through the second through-array connection contact 192.

[0333] In some embodiments, the low voltage device integrated structure 3 includes a pad portion 4 , and the pad portion 4 is connected to the connection contact 313 .

[0334] In some embodiments, the plurality of pad portions 4 include a first pad portion 41 and a second pad portion 42 that are spaced apart. The first pad portion 41 is connected to the first connection pad 3131, so that the first pad portion 41 is connected to the low-voltage device peripheral circuit 31. The second pad portion 42 is connected to the second connection pad 3132, so that the second pad portion 42 is connected to the high-voltage device peripheral circuit 21 through the second connection pad 3132 and the second through-array connection pad 192.

[0335] In some other embodiments, the high-voltage device integrated structure 2 includes a pad portion 4 , and the second through-array connection contact 192 connects the pad portion 4 and the low-voltage device peripheral circuit 31 .

[0336] In some embodiments, the low voltage device integrated structure 3 further includes an insulating layer 5 , which is located on a side of the third semiconductor layer 03 away from the low voltage device peripheral circuit 31 , and the pad portion 4 penetrates the insulating layer 5 .

[0337] Please refer to Fig.11 and Fig.12 The present application further provides a storage system 400, which includes a memory 200 and a controller 300. The memory 200 includes any of the semiconductor devices 100 of the above embodiments. The controller 300 is connected to the memory 200 and is used to control the memory 200.

[0338] Among them, the storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0339] In some embodiments, reference Fig.11 As shown, the storage system 400 includes a memory 200 and a controller 300. The storage system 400 may be integrated into a three-dimensional memory card.

[0340] Among them, the three-dimensional memory card includes any one of PC card (PCMCIA, Personal Computer Three-Dimensional Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, three-dimensional memory, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0341] In other embodiments, referring to Fig.12 As shown, the storage system 400 includes a plurality of memories 200 and a controller 300. The storage system 400 is integrated into a solid state drive (SSD).

[0342] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0343] In other embodiments, in the storage system 400, the controller 300 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smart phones, tablets, laptops, and enterprise storage arrays.

[0344] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and communicate with an external device (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions regarding data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes for data read from or written to the memory 200.

[0345] Of course, the controller 300 may also perform any other suitable functions, such as formatting the memory 200; for example, the controller 300 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0346] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0347] Please refer to Fig.13Some embodiments of the present application further provide an electronic device 500. The electronic device 500 may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0348] The electronic device 500 may include the above-mentioned storage system 400 and a host 600 , and the host 600 includes at least one of a central processing unit (CPU) and a cache.

[0349] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A storage array structure, including a storage array; A high-voltage device integrated structure, including a high-voltage device peripheral circuit of the memory array, wherein the high-voltage device peripheral circuit includes a plurality of high-voltage semiconductor devices; and A low-voltage device integrated structure, including a low-voltage device peripheral circuit of the storage array, wherein the low-voltage device peripheral circuit includes a plurality of low-voltage semiconductor devices; Wherein, in the first direction, the storage array structure is located between the high-voltage device integrated structure and the low-voltage device integrated structure, and is connected to the high-voltage device integrated structure and the low-voltage device integrated structure.

2. The semiconductor device according to claim 1, wherein: The storage array structure includes a storage area, and the storage array structure includes: a stacking structure stacked along the first direction; and A plurality of channel structures, located in the storage area and penetrating the stack structure along the first direction, the channel structure comprising a first channel connection end and a second channel connection end located at opposite sides of the stack structure in the first direction, the first channel connection end being close to the high voltage device integrated structure, and the second channel connection end being close to the low voltage device integrated structure; The high-voltage device peripheral circuit is connected to the first channel connection terminal; The low voltage device peripheral circuit is connected to the second channel connection terminal.

3. The semiconductor device according to claim 2, characterized in that The storage array structure also includes: A common source is located on a side of the stack structure away from the high-voltage device integrated structure in the first direction, and the second channel connection ends of the plurality of channel structures extend into the common source, and the common source is connected to the low-voltage device peripheral circuit.

4. The semiconductor device according to claim 3, characterized in that The storage array structure also includes: The connecting wire is located at a side of the common source away from the stacking structure and connects the common source and the peripheral circuit of the low-voltage device.

5. The semiconductor device according to claim 4, characterized in that The storage array structure further includes a first bonding layer, which is located on a side of the connecting wire away from the stacking structure and includes a first bonding contact connected to the connecting wire; The low voltage device integrated structure further includes a second bonding layer, the second bonding layer includes a second bonding contact connected to the peripheral circuit of the low voltage device, and the second bonding contact is bonded to the first bonding contact.

6. The semiconductor device according to claim 1, wherein: The storage array structure also includes: The first through-array connection contact extends along the first direction and connects the high-voltage device peripheral circuit and the low-voltage device peripheral circuit.

7. The semiconductor device according to claim 6, characterized in that The memory array structure further includes a peripheral region and a step region adjacent to the memory region in a second direction, the second direction intersecting the first direction; The first through-array connection contacts are located in the peripheral area and / or the step area.

8. The semiconductor device according to claim 2, wherein: The storage array structure also includes: a third bonding layer, located between the stacked structure and the high-voltage device integrated structure, and comprising a third bonding contact connected to the first channel connection end; The high-voltage device integrated structure further includes a fourth bonding layer, wherein the fourth bonding layer includes a fourth bonding contact connected to the peripheral circuit of the high-voltage device, and the fourth bonding contact is bonded to the third bonding contact.

9. The semiconductor device according to claim 2, characterized in that The storage array structure further includes a step region adjacent to the storage region in a second direction, the second direction intersecting the first direction; The stacked structure comprises a plurality of gate layers spaced apart along the first direction, wherein the plurality of gate layers respectively form a plurality of step surfaces in the step region; The storage array structure also includes: multiple gate contact structures, which are located in the step area and are respectively connected to the multiple gate layers, and the multiple gate contact structures have a first contact end close to the high-voltage device integrated structure, and the first contact ends of the multiple gate contact structures are connected to the high-voltage device peripheral circuit.

10. The semiconductor device according to claim 9, characterized in that The memory array structure further includes: an isolation layer, at least a portion of which is located in the step region, and in the first direction, the isolation layer is located on a side of the stack structure away from the high-voltage device integrated structure; Wherein, in the first direction, the gate contact structure further has a second contact end arranged opposite to the first contact end, and in the first direction, the second contact end protrudes from the stack structure and extends into the isolation layer.

11. The semiconductor device according to claim 1, wherein: The memory array structure further includes a peripheral area, and the memory array structure further includes: A second through-array connection pad is located in the peripheral area and extends along the first direction; The low voltage device integrated structure includes a pad portion, and the second through array connection contact connects the pad portion and the high voltage device peripheral circuit; or, The high-voltage device integrated structure includes a pad portion, and a second through-array connection contact connects the pad portion and the low-voltage device peripheral circuit.

12. The semiconductor device according to claim 1, wherein: The high-voltage semiconductor device comprises a first transistor, wherein the first transistor comprises a first gate insulating layer; The low voltage semiconductor device includes a second transistor, the second transistor includes the second gate insulating layer, and the thickness of the second gate insulating layer is smaller than the thickness of the first gate insulating layer.

13. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a memory array on the first semiconductor layer; forming a high-voltage device peripheral circuit of the memory array on the second semiconductor layer, wherein the high-voltage device peripheral circuit includes a plurality of high-voltage semiconductor devices; Disposing the high-voltage device peripheral circuit between the second semiconductor layer and the memory array in the first direction, so that the first semiconductor layer is located on a side of the memory array away from the second semiconductor layer, and connecting the memory array and the high-voltage device peripheral circuit; forming a low-voltage device peripheral circuit of the memory array on the third semiconductor layer, wherein the low-voltage device peripheral circuit includes a plurality of low-voltage semiconductor devices; removing at least a portion of the first semiconductor layer; and The low voltage device peripheral circuit is disposed between the third semiconductor layer and the memory array in the first direction, and the memory array and the low voltage device peripheral circuit are connected.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The step of forming a memory array on the first semiconductor layer comprises: forming a stacked layer stacked along the first direction on the first semiconductor layer, the stacked layer comprising a plurality of sacrificial layers spaced apart along the first direction; forming a channel structure penetrating the stacked layer along the first direction in a first region of the first semiconductor layer, the channel structure comprising a first channel connecting end and a second channel connecting end located at opposite sides of the stacked layer in the first direction, the second channel connecting end extending into the first semiconductor layer; and Replacing the multiple sacrificial layers of the stacked layer with multiple gate layers to form a stacked structure, wherein the first channel connection end and the second channel connection end of the channel structure are located at opposite sides of the stacked structure in the first direction; The connecting the storage array and the high voltage device peripheral circuit comprises: Disposing the high-voltage device peripheral circuit close to the first channel connection end in the first direction, and connecting the first channel connection end of the channel structure with the high-voltage device peripheral circuit; The connecting the storage array and the low voltage device peripheral circuit comprises: The low voltage device peripheral circuit is arranged close to the second channel connection end in the first direction, and the second channel connection end of the channel structure and the low voltage device peripheral circuit are connected.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that: The removing at least a portion of the first semiconductor layer comprises: removing a portion of the first semiconductor layer located in the first region; The method further comprises: after removing the portion of the first semiconductor layer located in the first region, exposing the second channel connection end of the channel structure; and A common source is formed on a side of the second channel connection end away from the stack structure, and the second channel connection end of the channel structure extends into the common source and contacts the common source.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: The method further comprises: providing the first semiconductor layer; and pre-burying a common source layer in the first semiconductor layer; The forming of a channel structure penetrating the stacked layers along the first direction in the first region of the first semiconductor layer includes: extending the second channel connecting end of the channel structure into the common source layer and contacting the common source layer.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The removing at least part of the first semiconductor layer further comprises: thinning a surface of the first semiconductor layer away from the stack structure to expose the common source layer; The method also includes: removing the portion of the common source layer outside the first region and retaining the portion of the common source layer in the first region, the remaining common source layer constitutes a common source, and the second channel connection end of the channel structure extends into the common source and contacts the common source.

18. The method for manufacturing a semiconductor device according to claim 15 or 17, characterized in that: After forming the common source, the method further includes: A connecting wire is formed on a side of the common source away from the stacking structure in the first direction, and the connecting wire is connected to the common source.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that: The circuit connecting the storage array and the low-voltage device peripheral circuit comprises: forming a first bonding layer on a side of the connecting wire away from the stacking structure in the first direction, the first bonding layer comprising a first bonding contact connected to the connecting wire; forming a second bonding layer on a side of the low voltage device peripheral circuit away from the third semiconductor layer, the second bonding layer comprising a second bonding contact connected to the low voltage device peripheral circuit; and The first bonding contact and the second bonding contact are bonded.

20. The method for manufacturing a semiconductor device according to claim 14, wherein: The method further comprises: forming a first through array connection contact extending along the first direction on the first semiconductor layer; and The first through-array connection contacts are used to connect the high-voltage device peripheral circuit and the low-voltage device peripheral circuit.

21. The method for manufacturing a semiconductor device according to claim 20, wherein: The forming of a first through array connection contact on the first semiconductor layer comprises: forming the first through array connection contact in the second region of the first semiconductor layer, the second region is arranged adjacent to the first region in a second direction, the stacking structure is located in the first region and the second region, and the second direction intersects the first direction; and / or, The first through array connection pads are formed in a third region of the first semiconductor layer, and the third region is adjacent to the stacking structure in the second direction.

22. The method for manufacturing a semiconductor device according to claim 14, wherein: The method further comprises: forming a third bonding layer on a side of the stacked layer away from the first semiconductor layer, wherein the third bonding layer includes a third bonding contact connected to the first channel connection end; forming a fourth bonding layer on a side of the high-voltage device peripheral circuit away from the second semiconductor layer, the fourth bonding layer comprising a fourth bonding contact connected to the high-voltage device peripheral circuit; and The third bonding contact is bonded to the fourth bonding contact.

23. The method for manufacturing a semiconductor device according to claim 14, wherein: The method further comprises: forming a plurality of gate contact structures in a second region of the first semiconductor layer, the plurality of gate contact structures being respectively connected to the plurality of sacrificial layers, the gate contact structures having a first contact end away from the first semiconductor layer, the second region being adjacent to the first region along a second direction, and the second direction intersecting the first direction; and The high-voltage device peripheral circuit is arranged close to the first contact end, and the first contact ends of a plurality of gate contact structures are connected to the high-voltage device peripheral circuit.

24. The method for manufacturing a semiconductor device according to claim 23, wherein: Forming a plurality of gate contact structures in the second region further comprises: Extending the second contact end of the gate contact structure into the first semiconductor layer, the second contact end and the first contact end being arranged opposite to each other in the first direction; The removing at least a portion of the first semiconductor layer comprises: removing a portion of the first semiconductor layer located in the second region; The method further includes: forming an isolation layer on a side of the second contact end away from the stack structure, wherein the second contact end of the gate contact structure extends into the isolation layer.

25. The method for manufacturing a semiconductor device according to claim 14, wherein: The method further comprises: forming a second through array connection contact in a third region of the first semiconductor layer, the third region being disposed adjacent to the stacked structure in the second direction, the second direction intersecting the first direction; and A pad portion is formed on a side of the third semiconductor layer away from the low-voltage device peripheral circuit, and the second through-array connection contact connects the pad portion and the high-voltage device peripheral circuit; or, A pad portion is formed on a side of the second semiconductor layer away from the high-voltage device peripheral circuit, and the second through-array connection contact connects the pad portion and the low-voltage device peripheral circuit.

26. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The high-voltage device peripheral circuit of the memory array formed on the second semiconductor layer includes: forming a first transistor including a first gate insulating layer on the second semiconductor layer; The low-voltage device peripheral circuit of the memory array formed on the third semiconductor layer includes: A second transistor including a second gate insulating layer is formed on the third semiconductor layer, wherein the thickness of the second gate insulating layer is less than the thickness of the first gate insulating layer.

27. A storage system, characterized in that: The storage system comprises: A memory, comprising the semiconductor device according to any one of claims 1 to 12; and The controller is connected to the memory and is used to control the memory.

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