Forming method of image sensing chip and image sensing chip
By graphicizing the substrate with a mask plate containing multiple exposure areas, an image sensing chip is formed, which solves the high cost problem caused by multiple mask plates in the production of image sensor chips, and a low-cost and efficient production method is realized.
Patent Information
- Application Number
- CN202310800220.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-30
- Publication Date
- 2025-01-10
AI Technical Summary
In the production of image sensor chips, the use of multiple masks increases production costs, and the prior art is difficult to effectively reduce costs.
By using a method of forming an image sensing chip, the substrate surface is patterned by providing a mask plate including the first, second and third exposure areas, and forming a first logic circuit area, a second logic circuit area and respectively In the pixel area, the multiplexed mask plate performs multiple processing on the substrate to form multiple image sensing chips, reducing the dependence on multiple mask plates.
The production of using a mask plate to form an image sensing chip is realized, reducing production costs and improving production efficiency.
Smart Images
Figure CN119300493A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming an image sensor chip and the image sensor chip. Background Art
[0002] Image sensors are devices that convert light signals into electrical signals. Image sensor chips that are usually used commercially include two categories: charge coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensor chips. Photolithography masks are needed in the production process of image sensors. In order to improve efficiency, multiple masks are used for exposure, including masks for making analog circuits of image sensors, masks for making digital circuits of image sensors, and masks for making pixel circuits of image sensors. However, using multiple masks will increase production costs. Summary of the invention
[0003] In view of this, the present invention provides a method for forming an image sensor chip with low production cost.
[0004] A method for forming an image sensor chip, comprising:
[0005] Providing a mask, wherein the mask includes a first exposure area, a second exposure area, and a third exposure area;
[0006] A substrate to be exposed is provided, and a first patterning process is performed on the surface of the substrate using a mask, wherein the first patterning process includes forming a first logic circuit region on the surface of the substrate using a first exposure region; a second patterning process is performed on the surface of the substrate using a mask, wherein the second patterning process includes forming a second logic circuit region on the surface of the substrate using a second exposure region; a third patterning process is performed on the surface of the substrate using a mask, wherein the third patterning process includes forming a pixel region on the surface of the substrate using a third exposure region.
[0007] In an embodiment of the present invention, the substrate comprises a plurality of circuit exposure areas, and the plurality of circuit exposure areas are sequentially arranged along the width direction or the length direction of the substrate; each of the circuit exposure areas comprises a first region, a second region and at least one third region, and the third region is located between the first region and the second region, and the first region, the third region and the second region are sequentially arranged along the width direction or the length direction of the substrate;
[0008] Using the mask to form the first logic circuit area in the first region;
[0009] forming the second logic circuit area in the second region using the mask;
[0010] The pixel area is formed in the third region by using the mask.
[0011] In an embodiment of the present invention, each of the circuit exposure areas includes a plurality of the third areas;
[0012] The mask is reused to perform the third patterning process on the surface of the substrate for multiple times, and the pixel area is formed in each of the third areas in sequence.
[0013] In an embodiment of the present invention, the first exposure area includes a plurality of first exposure units, the second exposure area includes a plurality of second exposure units, and the third exposure area includes a plurality of third exposure units; the first logic circuit area includes a plurality of first logic circuit units, the second logic circuit area includes a plurality of second logic circuit units, and the pixel area includes a plurality of pixel units;
[0014] Using a plurality of first exposure units to form a plurality of first logic circuit units on the surface of the substrate;
[0015] Using a plurality of second exposure units to form a plurality of the second logic circuit units on the surface of the substrate;
[0016] A plurality of third exposure units are used to form a plurality of pixel units on the surface of the substrate.
[0017] In an embodiment of the present invention, the substrate is segmented to form a plurality of image sensor chips, each of which includes one first logic circuit unit, one second logic circuit unit, and a plurality of pixel units located between the first logic circuit unit and the second logic circuit unit.
[0018] In an embodiment of the present invention, the first exposure area and the second exposure area are arranged opposite to each other, and the third exposure area is located between the first exposure area and the second exposure area;
[0019] When performing the first patterning process on the substrate, the first exposure area is used to expose the surface of the substrate, and the second exposure area and the third exposure area are shielded;
[0020] When performing the second patterning process on the substrate, the second exposure area is used to expose the surface of the substrate, and the first exposure area and the third exposure area are shielded;
[0021] When the third patterning process is performed on the substrate, the surface of the substrate is exposed using the third exposure area, and the first exposure area and the second exposure area are shielded.
[0022] In an embodiment of the present invention, the first exposure area is adjacent to the second exposure area, the second exposure area is adjacent to the third exposure area, and the second exposure area is located between the first exposure area and the third exposure area;
[0023] When performing the first patterning process and the second patterning process on the substrate, the first exposure area and the second exposure area are used to simultaneously expose the surface of the substrate, and the third exposure area is shielded;
[0024] When the third patterning process is performed on the substrate, the surface of the substrate is exposed using the third exposure area, and the first exposure area and the second exposure area are shielded.
[0025] In an embodiment of the present invention, the width of the mask is 26 mm and the length is 33 mm.
[0026] In an embodiment of the present invention, the mask plate comprises a glass frame and a light shielding layer for shielding light, the light shielding layer is arranged on the glass frame, and the hollow area of the glass frame forms the first exposure area, the second exposure area and the third exposure area.
[0027] The present application also relates to an image sensor chip, which is obtained by using the above-mentioned method for forming the image sensor chip.
[0028] The method for forming the image sensor chip of the present invention can use one mask plate to perform patterning on the substrate to form the first logic circuit area, the second logic circuit area and the pixel area respectively, without using multiple masks, and the production cost is low. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 It is a schematic structural diagram of the mask plate of the first embodiment of the present application.
[0030] Figure 2 It is a schematic diagram of the structure of the substrate to be exposed in the present application.
[0031] Figure 3 It is a schematic diagram of the structure of the image sensor chip of the present application.
[0032] Figure 4 It is a schematic structural diagram of the mask plate of the second embodiment of the present application. DETAILED DESCRIPTION
[0033] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
[0034] In the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may be used and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered limiting, and the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0035] Although the terms first, second, etc. are used herein to describe various elements in some instances, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.
[0036] Furthermore, as used in this article, the singular forms "one", "an" and "the" are intended to include plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.
[0037] First embodiment
[0038] Figure 1 is a schematic diagram of the structure of the mask of the first embodiment of the present application, such as Figure 1 As shown, the method for forming an image sensor chip includes:
[0039] Providing a mask 10, the mask 10 includes a first exposure area 101, a second exposure area 102 and a third exposure area 103;
[0040] A substrate 20 to be exposed is provided, and a first patterning process is performed on the surface of the substrate 20 using a mask plate 10, wherein the first patterning process includes forming a first logic circuit area on the surface of the substrate 20 using a first exposure area 101; a second patterning process is performed on the surface of the substrate 20 using a mask plate 10, wherein the second patterning process includes forming a second logic circuit area on the surface of the substrate 20 using a second exposure area 102; and a third patterning process is performed on the surface of the substrate 20 using a mask plate 10, wherein the third patterning process includes forming a pixel area on the surface of the substrate 20 using a third exposure area 103. In the present embodiment, the first logic circuit area and / or the second logic circuit area include an analog circuit (row driver, etc.) or a digital circuit (ISP / DSP, etc.), but the present invention is not limited thereto.
[0041] The method for forming the image sensor chip of the present application can use one mask plate 10 to pattern the substrate 20 to form the first logic circuit area, the second logic circuit area and the pixel area respectively, without using multiple mask plates 10, and the production cost is low.
[0042] Optionally, Figure 2 is a schematic diagram of the structure of the substrate to be exposed in this application, such as Figure 1 and Figure 2 As shown, the substrate 20 includes a plurality of circuit exposure areas 201, and the plurality of circuit exposure areas 201 are sequentially arranged along the width direction or the length direction of the substrate 20; each circuit exposure area 201 includes a first area 2011, a second area 2012 and at least one third area 2013, and the third area 2013 is located between the first area 2011 and the second area 2012, and the first area 2011, the third area 2013 and the second area 2012 are sequentially arranged along the width direction or the length direction of the substrate 20;
[0043] Using the mask 10 to form a first logic circuit region in the first area 2011;
[0044] Using the mask 10 to form a second logic circuit region in the second region 2012;
[0045] A pixel region is formed in the third region 2013 using the mask 10 .
[0046] Optionally, each circuit exposure area 201 includes a plurality of third areas 2013;
[0047] The reused mask 10 performs multiple third patterning processes on the surface of the substrate 20, and pixel areas are formed in each third area 2013 in turn. Specifically, the third exposure area 103 of the mask 10 is aligned with a third area 2013, and then the third area 2013 is subjected to the third patterning process to form a pixel area in the third area 2013; then the position of the mask 10 or the substrate 20 is changed, so that the third exposure area 103 of the mask 10 is aligned with another unexposed third area 2013, and then the third patterning process is performed on the third area 2013; and so on, pixel areas are formed in each third area 2013 in turn.
[0048] Alternatively, if Figure 2 As shown, each circuit exposure area 201 includes four third areas 2013. Six exposures are required to complete the patterning of the entire circuit exposure area 201 using one mask 10. In this embodiment, the areas of the four third areas 2013 are equal; the four third areas 2013 are arranged at equal intervals.
[0049] Alternatively, if Figure 1 As shown, the first exposure area 101 includes a plurality of first exposure units, the second exposure area 102 includes a plurality of second exposure units, and the third exposure area 103 includes a plurality of third exposure units; the first logic circuit area includes a plurality of first logic circuit units, the second logic circuit area includes a plurality of second logic circuit units, and the pixel area includes a plurality of pixel units;
[0050] A plurality of first exposure units are used to form a plurality of first logic circuit units on the surface of the substrate 20, that is, the first exposure area 101 forms a plurality of first logic circuit units in one exposure process;
[0051] A plurality of second exposure units are used to form a plurality of second logic circuit units on the surface of the substrate 20, that is, the first exposure area 101 forms a plurality of second logic circuit units in one exposure process;
[0052] A plurality of third exposure units are used to form a plurality of pixel units on the surface of the substrate 20 , that is, a plurality of pixel units are formed in the first exposure area 101 in one exposure process.
[0053] Alternatively, if Figure 1As shown, the mask 10 includes a first exposure area 101, a second exposure area 102 and a third exposure area 103; the first exposure area 101 includes ten first exposure units, the second exposure area 102 includes ten second exposure units, and the third exposure area 103 includes ten third exposure units; the first logic circuit area includes ten first logic circuit units, the second logic circuit area includes ten second logic circuit units, and the pixel area includes ten pixel units. In this embodiment, the ten first exposure units are arranged at equal intervals along the length direction of the mask 10, the ten second exposure units are arranged at equal intervals along the length direction of the mask 10, and the ten third exposure units are arranged at equal intervals along the length direction of the mask 10.
[0054] Optionally, Figure 3 is a schematic diagram of the structure of the image sensor chip of the present application, such as Figure 3 As shown, the substrate 20 is divided into a plurality of image sensor chips (CIS), each image sensor chip 30 includes a first logic circuit unit, a second logic circuit unit, and a plurality of pixel units located between the first logic circuit unit and the second logic circuit unit. In this embodiment, the substrate 20 is first divided into a plurality of circuit exposure areas 201, and then the circuit exposure area 201 is divided into ten image sensor chips; each image sensor chip 30 includes a first logic circuit unit, a second logic circuit unit, and four pixel units.
[0055] Alternatively, if Figure 1 As shown, the first exposure area 101 and the second exposure area 102 are arranged opposite to each other, and the third exposure area 103 is located between the first exposure area 101 and the second exposure area 102;
[0056] When the substrate 20 is subjected to the first patterning process, the surface of the substrate 20 is exposed using the first exposure area 101, and the second exposure area 102 and the third exposure area 103 are shielded. At this time, the shielded second exposure area 102 and the third exposure area 103 are opaque.
[0057] When the substrate 20 is subjected to the second patterning process, the second exposure area 102 is used to expose the surface of the substrate 20, and the first exposure area 101 and the third exposure area 103 are shielded. At this time, the shielded first exposure area 101 and the third exposure area 103 are not transparent.
[0058] When the substrate 20 is subjected to the third patterning process, the third exposure area 103 is used to expose the surface of the substrate 20, shielding the first exposure area 101 and the second exposure area 102. At this time, the shielded first exposure area 101 and the second exposure area 102 are not transparent. In this embodiment, the first exposure area 101, the third exposure area 103, and the second exposure area 102 are arranged in sequence along the width direction of the mask 10.
[0059] Alternatively, if Figure 1 As shown, the width W of the mask 10 is 26 mm and the length L is 33 mm.
[0060] Optionally, the mask 10 includes a glass skeleton 11 and a light shielding layer (not shown) for shielding light, the light shielding layer is arranged on the glass skeleton 11, and the hollowed-out area of the glass skeleton 11 forms a first exposure area 101, a second exposure area 102 and a third exposure area 103. In this embodiment, the material of the glass skeleton 11 is quartz; the material of the light shielding layer is chromium trioxide.
[0061] Optionally, the glass skeleton 11 includes a rectangular frame 111, a plurality of first ribs 112 arranged horizontally, and a plurality of second ribs 113 arranged vertically, the plurality of first ribs 112 are arranged vertically at equal intervals, the plurality of second ribs 113 are arranged horizontally at equal intervals, the plurality of first ribs 112 are cross-connected with the plurality of second ribs 113, the ends of the plurality of first ribs 112 and the plurality of second ribs 113 are connected to the inner wall of the rectangular frame 111, and a plurality of first exposure units, a plurality of second exposure units, and a plurality of third exposure units are formed between the rectangular frame 111, the plurality of first ribs 112, and the plurality of second ribs 113. In this embodiment, the light shielding layer is arranged on the rectangular frame 111, the plurality of first ribs 112, and the plurality of second ribs 113.
[0062] Optionally, the glass skeleton 11 includes a rectangular frame 111, nine first ribs 112 and two second ribs 113, a first exposure area 101 is formed between one second rib 113 and the inner wall of the rectangular frame 111, a second exposure area 102 is formed between another second rib 113 and another inner wall opposite to the rectangular frame 111, and a third exposure area 103 is formed between the two second ribs 113. In this embodiment, the number of the first ribs 112 and the second ribs 113 can be freely increased or decreased as needed, and is not limited to the above.
[0063] Optionally, the width of the first exposure area 101 is less than or equal to 2 mm; the width of the second exposure area 102 is less than or equal to 2 mm.
[0064] Second embodiment
[0065] Figure 4 is a schematic structural diagram of a mask according to a second embodiment of the present application. Figure 4 As shown, the method for forming the image sensor chip of this embodiment is different from the method for forming the image sensor chip of the first embodiment in that the structure of the mask 10 used is different.
[0066] Alternatively, if Figure 4As shown, the first exposure area 101 is adjacent to the second exposure area 102, the second exposure area 102 is adjacent to the third exposure area 103, and the second exposure area 102 is located between the first exposure area 101 and the third exposure area 103;
[0067] When the substrate 20 is subjected to the first patterning process and the second patterning process, the surface of the substrate 20 is exposed simultaneously using the first exposure area 101 and the second exposure area 102, and the third exposure area 103 is shielded;
[0068] When the third patterning process is performed on the substrate 20 , the third exposure area 103 is used to expose the surface of the substrate 20 , and the first exposure area 101 and the second exposure area 102 are shielded.
[0069] The method for forming the image sensor chip of the present application uses a mask plate 10 to perform a patterning process on a substrate 20. Since the first exposure area 101 and the second exposure area 102 are arranged adjacent to each other, the substrate 20 can share a single exposure process, which can save the number of process passes and reduce production costs. Since the width of the first exposure area 101 and the second exposure area 102 is less than or equal to 2 mm, the first exposure area 101 and the second exposure area 102 share a single exposure process, which can increase the area of the circuit exposure area 201, improve exposure stability, and help improve product quality.
[0070] Optionally, the glass skeleton 11 includes a rectangular frame 111, nine first ribs 112 and two second ribs 113, a first exposure area 101 is formed between one second rib 113 and the inner wall of the rectangular frame 111, a third exposure area 103 is formed between another second rib 113 and the other inner wall opposite to the rectangular frame 111, and a second exposure area 102 is formed between the two second ribs 113. In this embodiment, the number of the first ribs 112 and the second ribs 113 can be freely increased or decreased as needed, and is not limited to the above.
[0071] Alternatively, if Figure 2 As shown, each circuit exposure area 201 includes four third regions 2013. The mask 10 of this embodiment only needs five exposures to complete the patterning process of the entire circuit exposure area 201.
[0072] Third embodiment
[0073] The present application also relates to an image sensor chip 30 , which is obtained by using the above-mentioned method for forming the image sensor chip.
[0074] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for forming an image sensor chip, characterized in that: include: Providing a mask, wherein the mask includes a first exposure area, a second exposure area, and a third exposure area; A substrate to be exposed is provided, and a first patterning process is performed on the surface of the substrate using the mask, wherein the first patterning process includes forming a first logic circuit area on the surface of the substrate using the first exposure area; a second patterning process is performed on the surface of the substrate using the mask, wherein the second patterning process includes forming a second logic circuit area on the surface of the substrate using the second exposure area; a third patterning process is performed on the surface of the substrate using the mask, wherein the third patterning process includes forming a pixel area on the surface of the substrate using the third exposure area.
2. The method for forming an image sensor chip according to claim 1, wherein: The substrate comprises a plurality of circuit exposure areas, which are sequentially arranged along the width direction or the length direction of the substrate; each of the circuit exposure areas comprises a first area, a second area and at least one third area, the third area is located between the first area and the second area, and the first area, the third area and the second area are sequentially arranged along the width direction or the length direction of the substrate; Using the mask to form the first logic circuit area in the first region; forming the second logic circuit area in the second region using the mask; The pixel area is formed in the third region using the mask.
3. The method for forming an image sensor chip according to claim 2, wherein: Each of the circuit exposure areas includes a plurality of the third areas; The mask is reused to perform the third patterning process on the surface of the substrate for multiple times, and the pixel area is formed in each of the third areas in sequence.
4. The method for forming an image sensor chip according to claim 2, wherein: The first exposure area includes a plurality of first exposure units, the second exposure area includes a plurality of second exposure units, and the third exposure area includes a plurality of third exposure units; the first logic circuit area includes a plurality of first logic circuit units, the second logic circuit area includes a plurality of second logic circuit units, and the pixel area includes a plurality of pixel units; Using a plurality of first exposure units to form a plurality of first logic circuit units on the surface of the substrate; Using a plurality of second exposure units to form a plurality of the second logic circuit units on the surface of the substrate; A plurality of third exposure units are used to form a plurality of pixel units on the surface of the substrate.
5. The method for forming an image sensor chip according to claim 4, wherein: The substrate is divided into a plurality of image sensor chips, each of which includes one first logic circuit unit, one second logic circuit unit, and a plurality of pixel units located between the first logic circuit unit and the second logic circuit unit.
6. The method for forming an image sensor chip according to any one of claims 1 to 5, characterized in that: The first exposure area and the second exposure area are arranged opposite to each other, and the third exposure area is located between the first exposure area and the second exposure area; When performing the first patterning process on the substrate, the first exposure area is used to expose the surface of the substrate, and the second exposure area and the third exposure area are shielded; When performing the second patterning process on the substrate, the second exposure area is used to expose the surface of the substrate, and the first exposure area and the third exposure area are shielded; When the third patterning process is performed on the substrate, the surface of the substrate is exposed using the third exposure area, and the first exposure area and the second exposure area are shielded.
7. The method for forming an image sensor chip according to any one of claims 1 to 6, characterized in that: The first exposure area is adjacent to the second exposure area, the second exposure area is adjacent to the third exposure area, and the second exposure area is located between the first exposure area and the third exposure area; When performing the first patterning process and the second patterning process on the substrate, the first exposure area and the second exposure area are used to simultaneously expose the surface of the substrate, and the third exposure area is shielded; When the third patterning process is performed on the substrate, the surface of the substrate is exposed using the third exposure area, and the first exposure area and the second exposure area are shielded.
8. The method for forming an image sensor chip according to any one of claims 1 to 5, characterized in that: The mask has a width of 26 mm and a length of 33 mm.
9. The method for forming an image sensor chip according to any one of claims 1 to 5, characterized in that: The mask plate includes a glass frame and a light shielding layer for shielding light, wherein the light shielding layer is arranged on the glass frame, and the hollowed-out area of the glass frame forms the first exposure area, the second exposure area and the third exposure area.
10. An image sensor chip, characterized in that: The image sensor chip is obtained by using the method for forming the image sensor chip according to any one of claims 1 to 9.