Method for producing group III nitride single crystal substrate

Abstract

Provided is a method for manufacturing a group III nitride single crystal substrate, which can shorten the manufacturing time of a device and can suppress cracks and deterioration in characteristics during the manufacturing of the device. The method for manufacturing a group III nitride single crystal substrate includes performing the following: a support substrate preparation step of preparing a support substrate including a nitride ceramic; a planarization layer forming step of providing a planarization layer on the upper surface of the support substrate; a seed layer forming step of providing a seed layer on the upper surface of the planarization layer; an epitaxial film formation step for forming a composite substrate by epitaxially growing a target group III nitride single crystal on the upper surface of the seed layer; and a separation step of removing at least one of the planarization layer and the seed layer to separate the group III nitride single crystal substrate made of the group III nitride single crystal from the remainder of the composite substrate.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing single crystal substrates of group III nitrides such as aluminum nitride (AlN), aluminum gallium nitride (Al x Ga 1-x N (0 < x < 1.0)), and gallium nitride (GaN). Specifically, it relates to a method for manufacturing single crystal substrates of group III nitrides in which a group III nitride-based solid substrate is manufactured with high characteristics and low cost by epitaxial film formation. Background Art

[0002] Group III nitride substrates such as crystalline AlN-based substrates and GaN-based substrates have a wide bandgap and excellent high-frequency characteristics such as short-wavelength luminescence and high breakdown voltage. Therefore, group III nitride substrates are expected to be applied to devices such as light-emitting diodes (LEDs), lasers, Schottky diodes, power devices, and high-frequency devices. In particular, it has been reported that LEDs made of single crystals of AlN and Al x Ga 1-x N (0.5 < x < 1.0) have a bactericidal effect in the emission wavelength range of deep ultraviolet (UVC; 200 to 280 nm) (see Non-Patent Document 1), and are expected to be used as devices against coronavirus infection. In addition, GaN single crystals are expected to be used as devices for 5G and 6G wireless stations and EV wireless charging, and there is a need to further improve quality, increase the diameter, and reduce costs.

[0003] Since AlN does not have a melting point under normal pressure, it is difficult to manufacture AlN by the melting method commonly used for manufacturing silicon single crystals and other materials. Under such a background, Non-Patent Documents 2 and 3 describe a method for manufacturing an AlN single crystal substrate by a sublimation method (modified Lely method) using SiC or AlN as a seed crystal in an N2 atmosphere at 1700 to 2250°C. However, due to the high temperature required for crystal growth and the large-scale equipment involved, it is difficult to reduce costs, and it is also difficult to achieve a large diameter of more than φ4 inches. Patent Document 1 describes a method of growing an AlN layer by using a silicon substrate or an AlN substrate as a support substrate and using a hydride vapor deposition (HVPE) method.

[0004] However, since the method of Patent Document 1 uses silicon or the like as a support substrate, it is difficult to reduce the dislocation density of the AlN layer due to differences in thermal expansion coefficients and lattice constants. Although an AlN substrate with excellent crystallinity obtained by the sublimation method can be used as a support substrate, the diameter of the support substrate itself is small and expensive, so it is difficult to increase the diameter of the substrate and reduce the cost of the substrate.

[0005] On the other hand, a method for manufacturing a GaN substrate is described in Patent Document 2. In this manufacturing method, an AlN ceramic having a coefficient of thermal expansion and a lattice constant relatively close to those of a GaN single crystal is used as a core, and the core is sealed with a multilayer film such as SiO2 or Si3N4 to be used as a support substrate. Then, a planarization layer such as SiO2 is formed to fill the unevenness of the support substrate. Then, a seed film of a silicon <111> single crystal is transferred onto the planarization layer to form a composite substrate, and a single crystal such as GaN is epitaxially grown on the seed to form a film.

[0006] However, when epitaxially growing a thick film of GaN, AlN, or Al x Ga 1-x GaN (0 < x < 1) single crystal, for example, due to the large difference in lattice constants between the silicon <111> seed and the GaN, AlN, or Al x Ga 1-x GaN (0 < x < 1) single crystal, it is difficult to reduce the dislocation density. In addition, due to the differences in mutual affinity and coefficient of thermal expansion between the AlN ceramic and the sealing layer, between the multilayer films, and between the multilayer film and the planarization layer, the manufactured group III nitride single crystal substrate is prone to cracking, warping, or other problems. In addition, the manufactured group III nitride single crystal substrate is usually thinned by back grinding so that it becomes thinner after device manufacturing. At this time, unlike semiconductors such as Si, the support substrate containing a hard and easily cracked AlN ceramic core needs to be ground, which requires a long processing time and is prone to resource loss due to cracking, resulting in a reduction in device yield and deterioration of characteristics, which is a major drawback in the manufacture of group III nitride single crystal substrates.

[0007] Prior Art Documents

[0008] Patent Documents

[0009] Patent Document 1: JP4565042B

[0010] Patent Document 2: JP6626607B

[0011] Non-Patent Documents

[0012] Non-Patent Document 1: LEDs Magazine Japan; December 2016, pp.30 - 31

[0013] Non-Patent Document 2: SEI Technical Review; No.177, pp.88 - 91

[0014] Non-Patent Document 3: Fujikura Technical Review; No.119, 2010, Vol.2, pp.33 - 38 Summary of the invention

[0015] Problem that the invention aims to solve

[0016] The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for manufacturing a group III nitride single crystal substrate, the manufacturing method being capable of shortening device manufacturing time and suppressing cracks and characteristic degradation during device manufacturing.

[0017] Solutions for solving problems

[0018] The manufacturing method of the III-nitride single crystal substrate according to the present invention performs the following steps: a supporting substrate preparation step of preparing a supporting substrate containing a nitride ceramic; a planarization layer formation step of forming a planarization layer on the upper surface of the supporting substrate; a seed layer formation step of forming a seed layer on the upper surface of the planarization layer; an epitaxial film formation step of epitaxially growing a target III-nitride single crystal on the upper surface of the seed layer to form an epitaxial film formation step of forming a composite substrate; and a separation step of separating the III-nitride single crystal substrate made of the III-nitride single crystal from the rest of the composite substrate by removing at least one of the planarization layer and the seed layer.

[0019] Removal of at least one of the planarization layer and the seed layer may be performed by melting using high-frequency induction heating.

[0020] At least one of the planarization layer and the seed layer may be removed by dry etching using an etching gas for Si-based compounds and / or an etching gas for Group III nitrides.

[0021] A stress adjustment layer forming step of forming a stress adjustment layer on the lower surface of the support substrate may be further performed.

[0022] The stress adjustment layer may include silicon.

[0023] The nitride ceramic may be of AlN series, GaN series or Si3N4 series.

[0024] The support substrate may have a structure in which a core composed of nitride ceramics is wrapped with a sealing layer having a thickness of 0.05 μm or more and 1.5 μm or less.

[0025] The sealing layer may include Si3N4 and SiO x N y (wherein x=1, 1≤y≤20).

[0026] The planarization layer may include SiO2 and SiO x N y (wherein 1≤x≤20, y=1).

[0027] The thickness of the planarization layer may be greater than or equal to 0.5 μm and less than or equal to 3.0 μm.

[0028] The seed layer may have a thickness of 0.04 μm or more and 1.50 μm or less.

[0029] The seed layer may be Si <111> Single crystal.

[0030] Si <111> The resistivity of the single crystal at 20° C. may be 100 Ω·cm or more.

[0031] The seed layer may be a group III nitride single crystal.

[0032] Effects of the Invention

[0033] The method for manufacturing a group III nitride single crystal substrate of the present invention can shorten the device manufacturing time and can suppress cracks and characteristic degradation during device manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a diagram showing the flow of the method for producing a group III nitride single crystal substrate according to the present invention.

[0035] Figure 2 This is a diagram for explaining a method of forming a seed crystal substrate by epitaxial film formation on a single crystal substrate by a sublimation method. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description and the accompanying drawings, the same reference numerals are given to the same parts, and parts that have been described once will be omitted or described only within a necessary scope.

[0037] Figure 1 1 is a diagram showing the flow of a method for manufacturing the group III nitride single crystal substrate 100 of the present invention.

[0038] First, a support substrate 10 containing nitride ceramics is prepared (support substrate preparation step S1 ). The support substrate 10 is a substrate in which a sealing layer 12 is formed around a core 11 .

[0039] As the material of the core 11 , nitride ceramics of AlN, GaN, or Si 3 N 4 having high thermal conductivity and a thermal expansion coefficient as close as possible to that of the group III nitride single crystal substrate 100 to be manufactured are suitable.

[0040] In order to seal impurities such as metal and carbon diffused from the ceramic of the core 11 , the sealing layer 12 is formed to wrap around the core 11 .

[0041] The sealing layer 12 may contain silicon nitride (Si3N4) and silicon oxynitride (SiO x N y) have good affinity with the ceramic of the core 11 and have high impurity barrier capability. x N y From the viewpoint of balancing the affinity with the core 11 and the impurity blocking capability, x=1 and 1≤y≤20 are suitable.

[0042] The thickness of the sealing layer 12 is preferably 0.05 μm to 1.5 μm. If the thickness is less than 0.05 μm, the impurity barrier capability is insufficient, and if the thickness exceeds 1.5 μm, the difference in thermal expansion coefficient between the nitride ceramic and the sealing layer is large, and the layers tend to delaminate.

[0043] The sealing layer 12 can be formed by film formation using, for example, the LPCVD method.

[0044] Then, the planarization layer 20 is formed on the upper surface of the support substrate 10 (planarization layer forming step S2 ). Thus, the unevenness of the support substrate 10 is planarized.

[0045] The planarization layer 20 is formed by forming a film of silicon dioxide (SiO2) and silicon oxynitride (Si x N y ) or both thereof and further smoothed to a surface accuracy that enables thin film transfer of the seed layer 32. For example, the smoothing can be performed by CMP polishing or etching.

[0046] When using Si x N y When the planarizing layer 20 is used, 1≤x≤20 and y=1 are suitable because of its affinity with the sealing layer 12 , film-forming property on a concavo-convex surface, and ease of polishing and etching.

[0047] The planarization layer 20 may be formed by, for example, a plasma CVD method, a LPCVD method, or a low-pressure MOCVD method.

[0048] After grinding and etching, the thickness of the planarization layer 20 is preferably 0.5 μm or more and 3.0 μm or less. If the thickness is less than 0.5 μm, the unevenness of the support substrate 10 cannot be filled, resulting in voids. If the thickness exceeds 3.0 μm, the thick SiO2 and Si x N y This results in reduced thermal conductivity, leading to poor device characteristics.

[0049] In the present invention, as needed, a stress adjustment layer 21 can be formed on the side of the support substrate 10 opposite to the side on which the planarization layer 20 is formed (stress adjustment layer forming step S3). The stress adjustment layer 21 corrects the warping of the epitaxial growth substrate 50 mainly caused by the formation of the planarization layer 20. The stress adjustment layer 21 can also play a role in preventing cracks and electrostatic chucking. For the stress adjustment layer 21, a film material and thickness having a thermal expansion coefficient capable of correcting the warping of the epitaxial growth substrate 50 are selected. Although not limited to a specific film material, it is preferably a single substance including, for example, silicon. The stress adjustment layer 21 can be formed simultaneously with the planarization layer 20.

[0050] Next, a seed layer 32 is formed on the upper surface of the planarization layer 20. Before formation, after selecting the material of the seed substrate 30 from which the seed layer 32 is to be cut (seed substrate preparation step S4), ions are implanted on one side (ion implantation surface) of the seed substrate 30 to form a peeling position (embrittled layer) 31 in the seed substrate 30 (ion implantation step S5). For example, H + 、H2 + ,Ar + and He + Suitable as ions to be implanted.

[0051] The thickness of the seed layer 32 is preferably 0.04 μm or more and 1.50 μm or less. If the thickness of the seed layer 32 is less than 0.04 μm, the seed for epitaxial film formation is too thin, and its thickness and surface state vary greatly, making it difficult to obtain uniform epitaxial film formation on the entire surface. On the other hand, if the thickness of the seed layer 32 exceeds 1.50 μm, the ion implantation depth must be extremely deep, and the ion implanter for this purpose becomes bulky, which leads to safety and economic problems.

[0052] When ions are implanted into the seed crystal substrate 30, a peeling position 31 is formed in the seed crystal substrate 30, a damaged layer is generated, and crystallinity is degraded or lost (amorphized), etc. Therefore, after the seed crystal layer 32 is separated from the seed crystal substrate 30, grinding and / or etching or other processes are generally required to remove the damaged layer. Therefore, the ion implantation depth should be determined by considering the desired thickness of the seed crystal layer 32 and the thickness of the damaged layer to be removed.

[0053] A suitable material for the seed crystal substrate 30 is Si <111> Single crystal, SiC single crystal, sapphire single crystal or III-nitride single crystal such as aluminum nitride, aluminum gallium nitride or GaN. This is because unless the seed crystal has the same or similar crystal system as the target III-nitride single crystal, and the lattice constant and thermal expansion coefficient of the seed crystal are as close as possible to the lattice constant and thermal expansion coefficient of the target single crystal, it is impossible to obtain a good crystal by epitaxial growth.

[0054] From the perspective of cost reduction, it is preferred to select large-diameter Si <111> Single crystal, SiC single crystal or sapphire single crystal. <111> Single crystals are the most mass-producible and have large diameters, high quality, and are relatively inexpensive, so they are more preferred. In addition, Si with a resistivity of 100 Ω·cm or more at 20°C is most preferred. <111> This is because when the Si seed <111> When the resistivity of the single crystal at 20°C is 100 Ω·cm or more, the influence of the diffusion of the doping material in Si is hardly seen on the manufactured III-nitride single crystal substrate 100, and the high-frequency device made of the substrate has low power consumption at high frequencies. <111> If the resistivity of the single crystal at 20° C. is less than 100 Ω·cm, diffusion of doping materials in Si is observed in the manufactured III-nitride single crystal substrate 100 , and high-frequency devices made from the substrate consume large power at high frequencies.

[0055] On the other hand, if aluminum nitride or gallium nitride single crystals or the like which are still difficult to obtain even at large diameters are selected, a substrate obtained by epitaxially forming aluminum nitride single crystals or gallium nitride single crystals by MOCVD or HVPE using a large-diameter sapphire substrate as a base substrate may be used as the seed crystal substrate 30. If extremely high characteristics are important, a substrate obtained by epitaxially forming aluminum nitride single crystals or gallium nitride single crystals by MOCVD, HVPE or THVPE using a small-diameter single crystal substrate by sublimation or a sublimation AlN single crystal substrate as a base substrate may be used as the seed crystal substrate 30.

[0056] In this case, a lift-off site can be formed in the epitaxial layer by implanting ions from the surface of the epitaxial layer formed by epitaxial film formation.

[0057] For example, Figure 2 As shown, using an AlN substrate 34 prepared by a sublimation method as a base substrate, an epitaxial layer 35 of AlN is epitaxially formed thereon by MOCVD, HVPE or THVPE to form a seed substrate 30 (step S11). Then, by injecting ions from the surface (ion implantation surface) of the epitaxial layer 35, a peeling position 31 of the seed layer 32 can be formed in the epitaxial layer 35 (step S12).

[0058] According to this method, even if an expensive AlN substrate 34 manufactured by a sublimation method is used as a base substrate, a good-quality seed layer 32 can be formed economically and relatively quickly because only a part of the epitaxial layer 35 is consumed as the seed layer 32. If the thickness of the epitaxial layer 35 is sufficient after the seed layer 32 is formed, the seed substrate 30 can be reused, and if the epitaxial layer 35 becomes thinner due to the repeated use of the seed substrate 30, the thickness can be restored by performing epitaxial film formation again, so it is effective for reducing the manufacturing cost.

[0059] After the seed crystal substrate 30 with ion implantation is prepared, the ion implantation surface of the seed crystal substrate 30 is bonded to the planarization layer 20 formed on the support substrate 10 to form a bonded structure 40 (bonding step S6 ).

[0060] Then, the bonded body 40 is separated at the peeling position 31 (seed layer forming step S7). This separates the epitaxial growth substrate 50 in which the seed layer 32 is thin-film-transferred onto the planarization layer 20 formed on the support substrate 10 and the remaining portion 33 in which the seed layer 32 is removed from the seed substrate 30. The remaining portion 33 of the seed substrate 30 can be reused as a further seed substrate.

[0061] The ion implantation surface of the seed crystal substrate 30 may be temporarily bonded to another temporary support substrate such as a silicon wafer, and then separated at the peeling position 31, leaving the seed crystal layer 32 bonded to the temporary support substrate. Then, the seed crystal layer 32 on the temporary support substrate may be bonded to the planarization layer 20, and the temporary support substrate may be separated from the seed crystal layer 32 by any method, thereby transferring the seed crystal layer 32 to the planarization layer 20. In this way, the epitaxial growth substrate 50 in which the seed crystal layer 32 bonded to the planarization layer 20 is turned upside down may be formed.

[0062] Then, the target group III nitride single crystal is epitaxially grown to a target thickness on the upper surface of the seed layer 32 of the epitaxial growth substrate 50 (epitaxial film forming step S8 ). Thus, the target group III nitride single crystal composite substrate 70 is formed.

[0063] Then, at least one of the planarization layer 20 and the seed layer 32 of the composite substrate 70 is removed by melting using high-frequency induction heating in an inert gas at substantially atmospheric pressure, or by dry etching using an etching gas under reduced pressure heating, so that the target III-nitride single crystal layer 60 formed on the epitaxial growth substrate 50 is separated from the composite substrate 70 to obtain the III-nitride single crystal substrate 100 (separation step S9). Specifically, the separation is performed, for example, as follows.

[0064] In the case of melting using high-frequency induction heating, the composite substrate 70 is first placed in a chamber device capable of rotating and moving up and down, and the chamber device is equipped with an induction coil and a fixture capable of precise gradient heating. Then, after the interior of the chamber device is made into an inert gas atmosphere such as Ar at about 1 atmosphere, a high frequency is applied by a high-frequency oscillator of 1 to 3 MHz to heat the induction coil and the fixture so that the circumferential portion of the planarization layer 20 and / or the seed layer 32 to be removed reaches a maximum temperature of 1300 to 1600°C. In this case, it is preferred to adjust the induction coil and the fixture so that the layer to be removed is thermally compensated so that its temperature is not reduced by heat conduction, and the other parts of the layer are heated as little as possible. In addition, it is preferred to apply vertical tensile stress to the composite substrate 70 during heating. The reason for limiting the maximum temperature to the range of 1300 to 1600°C is that the layer to be removed will not melt at a temperature below 1300°C, and the thermal degradation of the device components is significant at a temperature exceeding 1600°C.

[0065] When dry etching using an etching gas, the layer to be removed is etched by a gas that selectively etches the target layer while heating from 300° C. to 1400° C. If the heating temperature is lower than 300° C., etching at the junction between the epitaxial growth substrate 50 and the layer 60 of the group III nitride single crystal cannot be sufficiently performed from the outer peripheral direction toward the inside. If the heating temperature exceeds 1400° C., the layer 60 of the group III nitride single crystal may be significantly etched or device components may be damaged.

[0066] In order to etch more effectively, for example, the dry etching speed can be increased by introducing etching gas into the layer to be removed at 950°C and reduced pressure (hundreds of mPa to tens of Pa) while applying a high frequency of hundreds of kHz to tens of MHz to generate plasma. The dry etching device used in this case can be, for example, a common reactive ion etching device (RIE) or a high-density plasma etching device (ECR, ICP) with modified equipment and fixtures to achieve precise gradient heating.

[0067] The etching gas to be introduced should be selected according to the layer to be removed. For example, if the seed layer 32 is a group III nitride system, provided that the etching gas for Si-based compounds and the etching gas for group III nitrides do not react with each other, both the planarization layer 20 and the seed layer 32 can be removed by using a mixture of the etching gas for Si-based compounds and the etching gas for group III nitrides. On the other hand, if the etching gases react strongly with each other when mixed, either the etching gas for Si-based compounds or the etching gas for group III nitrides can be used, but it is preferred to select an etching gas that can remove the planarization layer 20, which is thicker than the seed layer 32 and is more effectively separated. Specifically, since the composition of the planarization layer 20 is silicon dioxide (SiO2) or silicon oxynitride (SiO x N y ), so Si-based compounds are suitable as etching gases.

[0068] Etching gases for Si-based compounds include perfluorocarbons (CF4, C2F6, C3F8) and hydrofluorocarbons (CHF3, CH2F2, CH3F, C2H2F4), etc. Etching gases for Group III nitrides include inorganic halogen gases and hydrocarbon gases, etc.

[0069] Additional gases such as H2, O2, He and Ar can be added to these gases as needed. The etching rate can be adjusted by changing the ratio of the added gases. If the seed layer 32 is Si, the etching rate can be increased by adding 10-20% O2 to CF4. If the planarization layer 20 is SiO2 and the seed layer 32 is Si <111> For example, when separating by removing SiO2, 50% H2 can be added to CF4. <111> When performing separation, CF4 etching gas alone can be used.

[0070] If melting by high-frequency induction heating or dry etching by etching gas alone is not sufficient for separation, other means may be further performed to ensure more reliable separation.

[0071] If a portion of the seed layer 32 adheres to the group III nitride single crystal substrate 100 during separation, it can be removed by a method suitable for the composition of the seed layer 32 .

[0072] Furthermore, the remaining portion 101 of the group III nitride single crystal substrate 100 separated from the composite substrate 70 can be appropriately recycled, thereby reducing the manufacturing cost.

[0073] According to the method for manufacturing a III-nitride single crystal substrate of the present invention described above, a III-nitride single crystal substrate in which a hard and easily breakable support substrate portion is removed by melting or etching can be obtained. Therefore, it is possible to avoid the waste of manufacturing time, reduction in yield, and degradation of characteristics caused by device cracks caused by back grinding of the support substrate portion after device manufacturing. In addition, the remaining portion removed from the composite substrate can be reused, thereby reducing manufacturing costs.

[0074] Furthermore, by optimizing the thickness of each layer constituting the composite substrate and the resistivity of the seed layer, cracking and warping of the III-nitride single crystal substrate separated from the composite substrate can be prevented, and degradation of the characteristics of a device using the III-nitride single crystal substrate can be prevented.

[0075] Examples and comparative examples of a method for producing a group III nitride single crystal substrate are shown below.

[0076] <Example 1>

[0077] (Preparation of Support Substrate)

[0078] After 100 parts by weight of AlN powder and 5 parts by weight of Y2O3 as a sintering aid were mixed with an organic binder and a solvent to make a green sheet, the sheet was degreased, sintered at 1900°C in N2, and ground on both sides to produce a polycrystalline AlN substrate having a diameter of 8 inches and a thickness of 725 μm. The polycrystalline AlN substrate was used as a core of a supporting substrate. The entire core was wrapped and covered with a 0.4 μm thick silicon oxynitride layer formed by an LPCVD method, and then the entire core was wrapped with a 1.0 μm thick silicon nitride (Si3N4) layer formed using an LPCVD device. In this way, a supporting substrate in which the core was covered with a 1.4 μm thick sealing layer was formed.

[0079] (Stacking of planarization layers)

[0080] On the sealing layer on one side (upper surface) of the supporting substrate, a 6 μm thick SiO2 was stacked as a planarization layer by plasma CVD method (ICP-CVD device). The SiO2 was then baked at 1000°C and polished and planarized to a thickness of 3 μm by CMP polishing, resulting in a surface roughness Ra = 0.14 nm.

[0081] (Seed Crystal Preparation)

[0082] The commercially available Si with a diameter of 8 inches was increased by the CZ method. <111> The substrate (resistivity of 150Ω·cm at 20℃) was tested at 100keV with 6×10 17 / cm 2The hydrogen ions were implanted to a depth of 0.7 μm (stripping position). <111> The ion implantation surface of the substrate is bonded to the planarization layer formed on the support substrate, and a thin film is transferred to form a Si substrate on the support substrate. <111> Seed layer. The portion of the seed layer that was damaged during ion implantation and transfer was completely removed by etching after being gently polished by CMP. The final thickness of the seed layer was 0.04 μm. Si after transfer <111> The remaining portion of the substrate (i.e., the portion to be separated without film transfer to the support substrate) can be used as multiple seeds by repeatedly performing ion implantation, making it extremely economical. As a result, a substrate for epitaxial growth with a diameter of 8 inches was obtained, in which a 3 μm thick planarizing layer and a 0.04 μm thick Si layer were provided on a support substrate having an AlN ceramic core sealed by a sealing layer. <111> Seed layer.

[0083] (Implementation of GaN epitaxial film formation)

[0084] Then, the epitaxial growth substrate prepared as described above was placed in a GaN epitaxial growth furnace (HVPE device) and subjected to high temperature nitridation for 30 minutes at a substrate temperature of 900°C. Then, a GaN buffer layer with a thickness of 20 nm was formed at a substrate temperature of 400°C, and then GaN was epitaxially formed to a thickness of 12 mm using GaCl3 and NH3 as process gases at a substrate temperature of 1050°C to obtain a GaN composite substrate.

[0085] (Separation of GaN epitaxial film formation part and composite substrate)

[0086] The GaN composite substrate prepared as described above is placed in a chamber device capable of rotating and moving up and down, and the chamber device is equipped with an induction coil and a clamp capable of precise gradient heating. Then, the inside of the device is made into an Ar gas atmosphere of about 1 atmosphere, and the induction coil and the clamp are locally heated by applying a high frequency of 3 MHz to the induction coil and the clamp so that the circumferential portion of the seed layer 32 reaches 1500°C. At this time, the induction coil and the clamp are adjusted to ensure thermal compensation of the seed layer to prevent the temperature of the seed layer from dropping due to heat conduction, while the other parts of the crystal are heated as little as possible. During the heating, a slight tensile force is continuously applied to the upper and lower parts of the GaN composite substrate. As a result, the GaN composite substrate can be separated into a GaN epitaxial film-forming portion and a small amount of remaining Si <111> The support substrate portion of the seed layer.

[0087] (Evaluation of GaN epitaxial film formation)

[0088] For the crystal evaluation of the GaN epitaxial film part, the 12mm thick GaN epitaxial film part was cylindrically ground, cut into 900μm thickness using a wire saw, roughly ground, and CMP polished to obtain 5 single crystal GaN substrates with a final size of 8 inches in diameter and 725μm in thickness. The remaining support substrate part after the GaN epitaxial film part was separated was gently CMP polished on the separation side surface to remove Si <111> The remaining part of the seed layer is then transferred to Si <111> The film is designed for recycling.

[0089] The FWHM (full width at half maximum) of the X-ray rocking curves of the five evaluation GaN single crystal substrates with a diameter of 8 inches and a thickness of 725 μm obtained by the above treatment slightly changed between the seed side and the upper side, but they had extremely excellent crystallinity of 291 to 350 arcsec. Etch pits were also generated by the solution alkali (KOH+NaOH) etching method, and the EPD (etch pit density) was measured, showing 2×10 5 / cm 2 The extremely low dislocation density. In addition, power devices with a breakdown voltage of 600V and RF devices at 28GHz were manufactured on these GaN single crystal substrates, and each device manufacturing substrate was thinned to 200μm by back grinding on the back side. After cutting into individual devices, the yield of power devices with a breakdown voltage of 600V and RF devices at 28GHz on these substrates was extremely high, about 98% and about 93%, respectively. The loss of RF devices at 28GHz was as low as about 1.5dB.

[0090] <Comparative Example>

[0091] In addition to the Si used to form the seed layer <111> Except that the resistivity of the substrate at 20°C was 85 Ω·cm, GaN was epitaxially grown to a thickness of 35 μm under the same conditions as in Example 1, thereby obtaining a GaN composite substrate of about 760 μm in thickness. The obtained GaN composite substrate showed poorer crystallinity than that of Example 1, with a FWHM of 780 arcsec at the center of the x-ray rocking curve. The EPD was 8×10 5 / cm 2, the dislocation density is higher than that in Example 1. In addition, power devices with a breakdown voltage of 600V and RF devices at 28GHz were manufactured on these GaN composite substrates in the same manner as in Example 1, and each device manufacturing substrate was thinned to 200μm by back grinding on the back side of the supporting substrate with the AlN ceramic core. Due to the hardness of the AlN ceramic core, the thinning process time is 5 to 6 times longer than that in Example 1, and crack defects appear in some locations on the substrate with the device. In addition, when trying to cut the device manufacturing substrate into individual devices, there are many areas that cannot be cut due to cracks in the device manufacturing substrate. Therefore, the yield of power devices with a breakdown voltage of 600V and RF devices at 28GHz is extremely low, at about 24% and about 31%, respectively. The loss of the RF device at 28GHz is very high, at about 5.3dB.

[0092] <Example 2>

[0093] (Preparation of Support Substrate)

[0094] A commercially available GaN polycrystalline ceramic substrate with a metal impurity level of 4N and a diameter of 2 inches was prepared as the core of the support substrate. A 0.06 μm thick silicon oxynitride (Si2O2) layer was formed by LPCVD using SiH4 and N2O gases. x N y , having an approximate average composition of x=3 and y=15) wraps and covers the entire core to form a supporting substrate.

[0095] (Stacking of planarization layer and stress adjustment layer)

[0096] A 1.3 μm thick silicon oxynitride (Si 2O3) layer was formed on the sealing layer on one side (upper surface) of the support substrate by LPCVD. x N y , having an approximate average composition of x=17 and y=2) layer as a planarization layer. Then, it is ground to a thickness of 0.5μm by CMP grinding. Since the formation of the planarization layer causes the substrate to warp about 50μm as a whole, in order to correct the warping, a 0.5μm thick stress adjustment layer with the same composition as the planarization layer is formed on the lower surface of the supporting substrate by LPCVD. In addition, 0.05μm of polycrystalline silicon is added by using the LPCVD method to cope with the adsorption and desorption of the electrostatic chuck. As a result, the warping is basically eliminated, and the adsorption and desorption of the electrostatic chuck become possible.

[0097] (Seed Crystal Preparation)

[0098] A commercially available AlN single crystal (280 μm thick) with a diameter of 2 inches obtained by a sublimation method (modified Lely method) is used as a base substrate, and AlN epitaxial film formation is performed thereon at 1050°C by an MOCVD method (reaction gas: trimethylaluminum (TMAI) + NH3, carrier gas: N2 and H2) to obtain a 550 μm epitaxial layer. Ion implantation is performed on the epitaxial layer at a depth of 1.6 μm, and the ion implantation surface is bonded to a planarization layer formed on a supporting substrate, and then the film is transferred to form a 1.6 μm thick AlN seed layer on the supporting substrate. After being gently polished by CMP, the portion of the seed layer damaged during the ion implantation and transfer is completely removed by etching. The final thickness of the seed layer after removing the damaged portion is 1.4 μm. Through the above process, a 2-inch diameter epitaxial growth substrate was obtained, in which a 0.5 μm thick planarization layer, a 1.4 μm thick AlN seed layer, and a 0.55 μm thick stress adjustment layer were provided on a supporting substrate in which a GaN ceramic core was sealed by a sealing layer.

[0099] (Implementation of AlN Epitaxial Film Formation)

[0100] Then, the epitaxial growth substrate prepared as described above was placed in an AlN epitaxial growth furnace (HVPE device) and subjected to high-temperature nitridation for 30 minutes at a substrate temperature of 900° C. At a substrate temperature of 1300° C., AlN was epitaxially grown to a thickness of 10 mm using AlCl 3 and NH 3 as process gases to obtain an AlN composite substrate.

[0101] (Separation of AlN epitaxial film forming part and composite substrate)

[0102] The AlN composite substrate prepared as described above was placed in a reactive ion etching (RIE) apparatus capable of rotating and moving up and down, which was equipped with an induction coil and a fixture capable of precise gradient heating. Then, the temperature in the apparatus was raised to 950°C, and a gas containing 10% H2 added to CF4 was introduced as a flattening layer (Si x N y ) The planarization layer is etched using an etching gas while maintaining a reduced pressure of 15 Pa. As a result, the AlN composite substrate can be separated into an AlN epitaxial film-forming portion and a supporting substrate portion where a small amount of the AlN seed crystal layer remains.

[0103] (Evaluation of AlN epitaxial film formation)

[0104] For the crystal evaluation of the AlN epitaxial film part, the 10mm thick AlN epitaxial film part was cylindrically ground, cut into 330μm thickness using a wire saw, roughly ground, and CMP ground to obtain 5 single crystal AlN substrates with a final size of 2 inches in diameter and 280μm thickness. The remaining support substrate part after the AlN epitaxial film part was separated was gently CMP ground on the separation side surface to remove the remaining part of the AlN seed layer, and then the AlN film was transferred again for recycling.

[0105] The FWHM (full width at half maximum) of the X-ray rocking curves of the five evaluation AlN single crystal substrates with a diameter of 2 inches and a thickness of 280 μm obtained by the above treatment slightly changed between the seed side and the upper side, but they had extremely excellent crystallinity of 189 to 280 arcsec. Etching pits were also generated by the solution alkali (KOH+NaOH) etching method, and the EPD (etching pit density) was measured, showing that 0.1×10 5 / cm 2 The extremely low dislocation density of AlN substrates is shown in Figure 2. In addition, LED devices are fabricated on these AlN single crystal substrates, which are thinned to 150 μm by back grinding on the back side. The yield of these substrates after cutting into individual devices is extremely high, at about 99%.

[0106] The above embodiments and examples are merely examples, and any configuration that is substantially the same as the technical concept described in the claims of the present invention and produces a similar effect is included in the technical scope of the present invention.

[0107] Description of Reference Numerals

[0108] 10 Support base plate

[0109] 11 cores

[0110] 12 Sealing layer

[0111] 20 Planarization layer

[0112] 21 Stress Adjustment Layer

[0113] 30 seed substrate

[0114] 31 Peeling position

[0115] 32 Seed layer

[0116] 33,101Remainder

[0117] 34 AlN substrate

[0118] 35 Epitaxial layer

[0119] 40 joint

[0120] 50 Epitaxial growth substrate

[0121] 60 Planarization layer

[0122] 70 Composite substrate

[0123] 100 Group III Nitride Single Crystal Substrate

Claims

1. A method for manufacturing a group III nitride single crystal substrate, comprising the steps of: a supporting substrate preparation step of preparing a supporting substrate containing nitride ceramics; a planarization layer forming step of forming a planarization layer on the upper surface of the support substrate; A seed layer forming step of forming a seed layer on an upper surface of the planarization layer; An epitaxial film forming step of epitaxially growing a target III-nitride single crystal on an upper surface of the seed layer to form a composite substrate; and A separation step of separating a Group III nitride single crystal substrate made of the Group III nitride single crystal from a remaining portion of the composite substrate by removing at least one of the planarization layer and the seed layer. 2 . The method for manufacturing a group III nitride single crystal substrate according to claim 1 , wherein the removal of at least one of the planarization layer and the seed layer is performed by melting using high-frequency induction heating.

3. The method for manufacturing a group III nitride single crystal substrate according to claim 1, wherein the removal of at least one of the planarization layer and the seed layer is performed by dry etching using an etching gas for Si-based compounds and / or an etching gas for group III nitrides. 4 . The method for manufacturing a group III nitride single crystal substrate according to claim 1 , further comprising a stress adjustment layer forming step of forming a stress adjustment layer on a lower surface of the support substrate. 5 . The method for manufacturing a group III nitride single crystal substrate according to claim 4 , wherein the stress adjustment layer comprises silicon. 6 . The method for manufacturing a group III nitride single crystal substrate according to claim 1 , wherein the nitride ceramic is of AlN series, GaN series or Si 3 N 4 series. 7 . The method for producing a group III nitride single crystal substrate according to claim 1 , wherein the support substrate has a structure in which a core composed of nitride ceramic is wrapped by a sealing layer having a thickness of 0.05 μm or more and 1.5 μm or less.

8. The method for manufacturing a group III nitride single crystal substrate according to claim 7, wherein the sealing layer comprises Si3N4 and SiO x N y At least one of the following, where x=1, 1≤y≤20.

9. The method for manufacturing a group III nitride single crystal substrate according to claim 1, wherein the planarization layer comprises SiO2 and SiO x N y At least one of the following, where 1≤x≤20, y=1. 10 . The method for manufacturing a group III nitride single crystal substrate according to claim 1 , wherein a thickness of the planarization layer is greater than or equal to 0.5 μm and less than or equal to 3.0 μm. 11 . The method for manufacturing a group III nitride single crystal substrate according to claim 1 , wherein the seed layer has a thickness of 0.04 μm or more and 1.50 μm or less.

12. The method for manufacturing a group III nitride single crystal substrate according to claim 1, wherein the seed layer is Si <111> Single crystal.

13. The method for manufacturing a III-nitride single crystal substrate according to claim 12, wherein the Si <111> The resistivity of the single crystal at 20°C is 100 Ω·cm or more. 14 . The method for manufacturing a group III nitride single crystal substrate according to claim 1 , wherein the seed layer is a group III nitride single crystal.

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