Configuration method and device, storage medium and computer program product
By using register address mapping allocation table to generate configuration programs, design error and redundancy problems in SoC chip design are solved, verification efficiency and efficiency are improved, and the accuracy and efficiency of functional verification are ensured.
Patent Information
- Application Number
- CN202411311284.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2025-01-14
AI Technical Summary
In SoC chip design, complex data paths and manual participation lead to design errors, resulting in design and verification understanding deviations, extending the design cycle, increasing the redundancy bit width, causing data redundancy and delay, affecting the efficiency and effectiveness of functional verification .
By using register address mapping the structural characteristics of the allocation table, generate configuration programs, filter unreadable or unwritable member variables, define appropriate data types, integrate member variables, generate write statements, and verify the read and write functions of the register module, ensure that The correctness and efficiency of the configuration program.
Save simulation time, improve verification efficiency, ensure the effectiveness of functional verification, reduce design cycle and personnel waste, improve register usage efficiency, and reduce delay.
Smart Images
Figure CN119312745A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of wireless communication technology, and in particular, to a configuration method, device, storage medium, and computer program product. Background Art
[0002] With the rapid development of the integrated circuit industry, the design scale of system-on-chip (SoC) is getting larger and larger, which makes the functional verification of chips more and more complicated and time-consuming. In the research and development cycle of chip design, the proportion of verification workload is also increasing. As a high-investment and high-risk field, the chip industry is fully determined by whether the functional verification of the chip is sufficient to determine the final chip tape-out time and success rate.
[0003] At present, the system-level verification of SoC chip design usually adopts simulation verification of software and hardware collaboration, such as Figure 1 As shown, firstly, a C-based compiler is used to compile and generate binary drive instructions, and then the hardware description languages such as Verilog are used to encode them in the test platform. On the one hand, the binary drive instructions are read and stored in the memory of the SoC chip for scheduling by the central processing unit (CPU). On the other hand, hardware stimuli are generated to perform functional verification of the module to be verified.
[0004] However, today's SoC chips have very complex data paths. Designers need to actively extract corresponding configuration items, namely system-level registers, directly from the codes of each module. In this link, there are often many design errors caused by manual participation, resulting in misunderstandings between design and verification of the verification points, which ultimately leads to an extension of the design cycle and a waste of personnel. In addition, directly setting each configuration item to a data type with a high bit ratio will cause many invalid bit widths to be compiled, resulting in data redundancy. In addition, when using the write function to configure the register, it will work on the rising edge of the clock. When the redundant data is configured using the write function, it will cause an increase in latency and a longer waiting time to start normal operation. Based on this, the current functional verification scheme for the module to be tested in the chip has a lag and is less effective. Summary of the invention
[0005] The present application provides a configuration method, device, storage medium and computer program product.
[0006] The technical solution of the embodiment of the present application is implemented as follows:
[0007] The present application provides a configuration method, the method comprising:
[0008] Using the structural characteristics of the register address mapping allocation table, a configuration program of the register module in the chip under test is generated;
[0009] Verifying the read and write functions of the register module;
[0010] In the case where the register module passes the verification, the register module is configured using the configuration program to support the module under test in the chip under test to perform functional verification.
[0011] In the above method, the structural features include at least:
[0012] It includes the base address of the register module, the register data bit width of the register module, each sub-module in the register module, the offset address of the member variable in each sub-module, and the bit width of the member variable in each sub-module.
[0013] In the above method, the configuration program of the register module in the chip to be tested is generated by utilizing the structural characteristics of the register address mapping allocation table, including:
[0014] The following processing is performed on the first submodule in the register module:
[0015] Filter out and delete each member variable that is unreadable or unwritable from the first submodule; the first submodule is any submodule in the register module;
[0016] For each readable and writable member variable in the first submodule, define a data type based on the respective bit width;
[0017] For each readable and writable member variable in the first submodule, based on the respective offset addresses, the base address, and the register data bit width, the member variables are integrated to generate a statement for writing into the register module;
[0018] Continue to perform the same processing on the submodules in the register module that are different from the first submodule, and generate the configuration program based on the processing results of each submodule.
[0019] In the above method, for each readable and writable member variable in the first submodule, defining the data type based on the respective bit width includes:
[0020] If the bit width of the first member variable is less than or equal to 8, define the data type of the first member variable as an unsigned byte type;
[0021] If the bit width of the first member variable is greater than 8 and less than or equal to 15, define the data type of the first member variable as an unsigned short integer type;
[0022] If the bit width of the first member variable is greater than 15, define the data type of the first member variable as an unsigned integer type;
[0023] The first member variable is any readable and writable member variable in the first submodule.
[0024] In the above method, for each readable and writable member variable in the first submodule, based on the respective offset addresses, the base address, and the register data bit width, member variables are integrated to generate a statement for writing into the register module, including:
[0025] Divide each readable and writable member variable in the first submodule into N sets; wherein N is a positive integer, each set includes one or more member variables, the offset addresses of the member variables in the same set are the same, and the offset addresses of the member variables in different sets are different;
[0026] For each set, if there are multiple member variables in the set, the member variables in the set are integrated into data that meets the data bit width of the register and determined as the corresponding target data; if there are only one member variable in the set, the member variable in the set is determined as the corresponding target data;
[0027] Generate a statement written into the register module for the target data corresponding to each set;
[0028] Wherein, for each set, the storage address of the corresponding target data in the register module is determined based on the offset address of the member variable in the set and the base address.
[0029] In the above method, the verifying the read and write functions of the register module includes:
[0030] Performing a first read-write operation of setting all addresses in the register module to 1;
[0031] XOR the data written by executing the first read-write operation with the data read out to obtain a first XOR result;
[0032] Performing a second read-write operation of setting all addresses in the register module to 0;
[0033] XOR the data written by executing the second read-write operation with the data read out to obtain a second XOR result;
[0034] If the first XOR result and the second XOR result are both 0, it is determined that the register module verification has passed;
[0035] If the first XOR result or the second XOR result is 1, it is determined that the register module verification fails.
[0036] In the above method, it also includes:
[0037] Input the test stimulus into the module to be tested and the reference model respectively for functional verification; wherein the reference model supports simulating the expected functions of the module to be tested;
[0038] Periodically obtaining and comparing the output results of the module to be tested and the reference model;
[0039] If the output results of the module to be tested are different from those of the reference model, the module to be tested is controlled to end the function verification, and the module to be tested is corrected and then the function verification is performed again.
[0040] The present application provides a configuration device, including:
[0041] A generation module is used to generate a configuration program of a register module in the chip to be tested by utilizing the structural characteristics of the register address mapping allocation table;
[0042] A verification module, used to verify the read and write functions of the register module;
[0043] The configuration module is used to configure the register module using the configuration program when the register module is verified, so as to support the module under test in the chip under test to perform function verification.
[0044] An embodiment of the present application provides a configuration device, including: a processor, a memory, and a communication bus;
[0045] The communication bus is used to realize the communication connection between the processor and the memory;
[0046] The processor is used to execute one or more computer programs stored in the memory to implement the above configuration method.
[0047] An embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned configuration method is implemented.
[0048] An embodiment of the present application provides a computer program product, including a computer program, which implements the above configuration method when executed.
[0049] The embodiments of the present application provide a configuration method, device, storage medium and computer program product. The configuration method includes: using the structural features of the register address mapping allocation table to generate a configuration program for the register module in the chip to be tested; verifying the read and write functions of the register module; and when the register module verification passes, configuring the register module using the configuration program to support the function verification of the module to be tested in the chip to be tested. The technical solution provided by the embodiments of the present application automatically generates a configuration program for the register module that can be compiled by the software platform according to the structural features of the register address mapping allocation table, which greatly saves simulation time and improves verification efficiency. In addition, the read and write functions of the register module are verified before the function of the module to be tested is simulated and verified to ensure the effectiveness of the function verification of the module to be tested. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] Figure 1 A schematic diagram of a chip system-level verification framework in the prior art;
[0051] Figure 2 A flowchart of a configuration method provided in an embodiment of the present application;
[0052] Figure 3 A schematic diagram of an exemplary flow chart of generating a configuration program provided in an embodiment of the present application;
[0053] Figure 4 A schematic diagram of an exemplary register module read and write function verification process provided in an embodiment of the present application;
[0054] Figure 5 A schematic diagram of an exemplary module system-level functional verification process provided in an embodiment of the present application;
[0055] Figure 6 A schematic diagram of a configuration device provided in an embodiment of the present application Figure 1 ;
[0056] Figure 7 A schematic diagram of a configuration device provided in an embodiment of the present application Figure 2 . DETAILED DESCRIPTION
[0057] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0058] The following will specifically describe the technical solution of the present application and how the technical solution of the present application solves the above technical problems through embodiments and in conjunction with the accompanying drawings. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.
[0059] In addition, the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.
[0060] An embodiment of the present application provides a configuration method, which is implemented by a configuration device. Figure 2 A flow chart of a configuration method provided in an embodiment of the present application. Figure 2 As shown, in the embodiment of the present application, the configuration method mainly includes the following steps:
[0061] S101. Generate a configuration program for a register module in a chip to be tested by utilizing structural features of a register address mapping allocation table.
[0062] In an embodiment of the present application, the configuration device may utilize the structural features of the register address mapping allocation table to generate a configuration program for the register module in the chip to be tested.
[0063] It should be noted that in the embodiments of the present application, the chip to be tested includes a register module and a module to be tested that needs to be functionally verified. The specific chip to be tested and the functions of the modules to be tested in the chip to be tested can be designed according to actual needs and are not limited by the embodiments of the present application.
[0064] In an embodiment of the present application, the configuration device can analyze the structural features of the register address mapping allocation table, wherein the structural features include at least: the base address of the register module, the register data bit width of the register module, the various sub-modules in the register module, the offset address of the member variables in each sub-module, and the bit width of the member variables in each sub-module.
[0065] In an embodiment of the present application, a configuration device utilizes the structural features of a register address mapping allocation table to generate a configuration program for a register module in a chip to be tested, including: performing the following processing on a first submodule in the register module: filtering out and deleting each unreadable or unwritable member variable from the first submodule; the first submodule is any submodule in the register module; for each readable and writable member variable in the first submodule, defining a data type based on each bit width; for each readable and writable member variable in the first submodule, integrating the member variables based on their offset addresses, base addresses, and register data bit widths, generating a statement to write to the register module; continuing to perform the same processing on submodules in the register module that are different from the first submodule, and generating a configuration program based on the processing results of each submodule.
[0066] It should be noted that in the embodiments of the present application, the sub-module is defined as a structure type for easy access and management. Specifically, for a sub-module, for example, the first sub-module, it is first determined whether each member variable in the sub-module is readable and writable. For each member variable, if it is readable and writable, the data type is defined for it according to the bit width of the member variable, thereby improving the utilization rate of the register space and being able to prevent overflow in time according to the data type of the member variable. If it is not readable or writable, that is, the member variable is invalid and can be deleted.
[0067] In an embodiment of the present application, the configuration device defines the data type for each readable and writable member variable in the first sub-module based on their respective bit widths, including: if the bit width of the first member variable is less than or equal to 8, defining the data type of the first member variable as an unsigned byte type (unsigned char); if the bit width of the first member variable is greater than 8 and less than or equal to 15, defining the data type of the first member variable as an unsigned short integer type (unsigned short); if the bit width of the first member variable is greater than 15, defining the data type of the first member variable as an unsigned integer type (unsigned int); wherein the first member variable is any readable and writable member variable in the first sub-module.
[0068] In an embodiment of the present application, the configuration device integrates the member variables for each readable and writable member variable in the first submodule based on their respective offset addresses, base addresses, and register data bit widths, and then generates a statement to write to the register module, including: dividing the readable and writable member variables in the first submodule into N sets; wherein N is a positive integer, each set includes one or more member variables, the offset addresses of the member variables in the same set are the same, and the offset addresses of the member variables in different sets are different; for each set, if the number of member variables in the set is multiple, the member variables in the set are integrated into data that meets the register data bit width and determined as the corresponding target data, and if the number of member variables in the set is one, the member variables in the set are determined as the corresponding target data; a statement to write to the register module is generated for the target data corresponding to each set; wherein, for each set, the storage address of the corresponding target data in the register module is determined based on the offset address and base address of the member variables in the set.
[0069] Exemplarily, in an embodiment of the present application, the configuration device can start to traverse each readable and writable member variable in each sub-module through a loop operation, determine whether the offset address of the current member variable a is the same as that of the previous member variable b, and if they are the same, put the member variable a and the member variable b into the same set and wait for subsequent processing; if they are different, the member variable a can be put into a set alone and wait for subsequent processing. In addition, considering that the member variables can be arranged in the order of gradually increasing or decreasing offset addresses, the offset addresses of member variables a and member variables b are different, and then other member variables thereafter will not be the same as the offset address of member variable b. Based on this, the member variables in the set where member variable b is located can be integrated into data that meets the register data bit width, and a write function is used to generate a statement for writing it into the register module, and its storage address in the register module is determined based on the same offset address and base address of the member variables in the set. If the set where member variable b is located has only one member variable, that is, only includes member variable b, then the write function can be directly used to generate a statement for writing it into the register module for member variable b, and its storage address in the register module is determined based on the offset address and base address of member variable b, and so on, and the traversal is continuously looped.
[0070] Figure 3 The following is a flow chart of an exemplary configuration program generation process provided in the present application embodiment. Figure 3 As shown, in the embodiment of the present application, the structural features of the address mapping allocation table are read and analyzed; wherein, the structural features at least have the following structural features: including the base address of the register module, the register data bit width, each submodule, the offset address of the member variable in each submodule, the bit width of the member variable in each submodule, etc. Based on the above features, a configuration file that can be recognized by the software platform is generated by using the following method:
[0071] 1. Read the register address mapping allocation table;
[0072] 2. Process the submodule list and define each submodule as a structure type;
[0073] 3. Traverse the i-th submodule; where i is a positive integer;
[0074] 4. Determine whether the member variables in the i-th submodule are readable and writable. If yes, start executing steps 5a and 6a. If no, go to step 7.
[0075] 5a. Determine whether the bit width is less than or equal to 8. If yes, go to step 5b. If no, go to step 5c.
[0076] 5b. Define the data type of the member variable as unsigned char;
[0077] 5c. Determine whether the bit width is less than or equal to 15. If yes, go to step 5d. If no, go to step 5e.
[0078] 5d. Define the data type of the member variable as unsigned short;
[0079] 5e. Define the data type of the member variable as unsigned int;
[0080] 6a. Determine whether the offset address of the member variable is consistent with the previous member variable. If yes, execute step 6b. If no, execute steps 6c, 6d, and 6e in sequence.
[0081] 6b. Get the bit position of the member variable in the register data bit width; go to step 8;
[0082] 6c. Integrate all member variables under the same previous offset address into one target data;
[0083] 6d. Use the write function to generate a statement to write the integrated target data into the corresponding address in the register module;
[0084] 6e. Get the bit position of the member variable at its offset address in the register data bit width; go to step 8;
[0085] 7. Discard the member variable; go to step 8;
[0086] 8. Determine whether the member variable traversal is complete. If yes, execute step 9. If no, return to step 4 to continue processing the next member variable.
[0087] 9. Determine whether the sub-module traversal is complete. If yes, end the process. If no, return to step 3 to start traversing the next module.
[0088] It should be noted that, in the embodiments of the present application, the above-mentioned method of dividing the member variable set and integrating the member variables through a loop operation to generate a statement to write to the register module is only an exemplary specific implementation method. Of course, other methods can also be used to divide the member variables with the same offset address together, which is not limited by the embodiments of the present application.
[0089] It can be understood that in the embodiments of the present application, the refined processing of member variables can improve the utilization efficiency of registers, reduce data redundancy, and at the same time reduce the cycle of serial bus configuration registers, thereby accelerating the startup process of normal operation.
[0090] S102, verifying the read and write functions of the register module.
[0091] In an embodiment of the present application, the configuration device verifies the read and write functions of the register module.
[0092] In an embodiment of the present application, a configuration device verifies the read and write functions of a register module, including: performing a first read and write operation to set all addresses in the register module to 1; performing an XOR operation on the data written by the first read and write operation and the data read out to obtain a first XOR result; performing a second read and write operation to set all addresses in the register module to 0; performing an XOR operation on the data written by the second read and write operation and the data read out to obtain a second XOR result; if the first XOR result and the second XOR result are both 0, it is determined that the register module verification has passed; if the first XOR result or the second XOR result is 1, it is determined that the register module verification has failed.
[0093] It should be noted that in the embodiments of the present application, the read and write operations of setting all 1s or all 0s are performed on each address in the register module. Specifically, a traversal method can be adopted to perform read and write operations of setting all 1s or all 0s on the bits of the member variables in each sub-module in turn. Of course, it is also possible to directly perform read and write operations of setting all 1s or all 0s on each address at one time, or to perform read and write operations of setting all 1s or all 0s on the addresses in the register module in multiple times according to other address division methods.
[0094] Figure 4 The following is a flow chart of an exemplary register module read and write function verification provided in an embodiment of the present application. Figure 4 As shown, it mainly includes the following steps:
[0095] 1. Traverse the i-th submodule;
[0096] 2. Set all bits of the member variables to 1 and use the write function to write data to the corresponding address;
[0097] 3. Use the read function to read the data in the address;
[0098] 4. Determine whether the XOR result of the read data and the written data is 0. If yes, it proves that all bit widths of the register can be written as 1, and continue to step 5. If no, go to step 10;
[0099] 5. Set all bits of the member variables to 0 and use the write function to write the data to the corresponding address;
[0100] 6. Use the read function to read the data in the address;
[0101] 7. Determine whether the XOR result of the read data and the written data is 0. If yes, it proves that all bit widths of the register can be written as 0, and continue to step 8. If no, go to step 10;
[0102] 8. Determine whether the traversal of the member variables is complete. If yes, continue to step 9. If no, return to step 2 and continue to perform read and write operations on the bits of the next member variable.
[0103] 9. Determine whether the submodule traversal is complete. If yes, end the process. If no, return to step 1 to start the next module traversal.
[0104] 10. Report abnormality.
[0105] It can be understood that in the embodiments of the present application, in order to improve the coverage of register function verification, when performing simulation verification, the serial peripheral interface (SPI) bus protocol is first used to perform read and write (RAW) operations on each address in the register module with all 1s and all 0s, that is, the above-mentioned first read and write operations and the second read and write operations, to verify that all bit widths of the register module can be accessed normally. In this way, the failure of subsequent function verification caused by bus configuration problems can be avoided.
[0106] S103 . When the register module verification passes, configure the register module using a configuration program to support the module under test in the chip under test to perform functional verification.
[0107] In an embodiment of the present application, the configuration device verifies the read and write functions of the register module. When the register module verification passes, the configuration program is used to configure the register module to support the function verification of the module under test in the chip under test.
[0108] It should be noted that in the embodiments of the present application, the module to be tested can be any module in the chip to be tested that needs to perform functional verification. The module to be tested and the functions of the module to be tested that need to be verified can be set according to actual needs and application scenarios, and the embodiments of the present application are not limited.
[0109] It can be understood that, in the embodiment of the present application, the configuration device configures the register module using the configuration program, so that the required information can be scheduled from the register module to support the module under test to perform functional verification.
[0110] In an embodiment of the present application, the configuration device can also perform the following steps: input the test stimulus into the module to be tested and the reference model respectively for functional verification; wherein the reference model supports simulating the expected functions of the module to be tested; periodically obtain the output results of the module to be tested and the reference model and compare them; if the output results of the module to be tested and the reference model are different, control the module to be tested to end the functional verification, and re-perform the functional verification after the module to be tested is corrected.
[0111] Figure 5 The following is a flow chart of an exemplary module system-level functional verification process provided by the present application. Figure 5 As shown, it mainly includes the following steps:
[0112] 1. According to the functional requirements, correctly configure the registers that the module to be tested needs to read and compile them into configuration files;
[0113] 2. Generate test stimulus; after executing step 2, execute steps 3a and 3b on the one hand, and execute 4a and 4b on the other hand;
[0114] 3a. Input the test stimulus to the module under test for functional simulation;
[0115] 3b. Periodically obtain the output results of the module to be tested;
[0116] 4a. Input the test stimulus into the reference model for compilation;
[0117] 4b. Periodically obtain the output results of the reference model;
[0118] 5. Periodically compare the output results of the module under test and the reference model on the functional comparison platform;
[0119] 6. Determine whether the output results are the same; if yes, go to step 7; if no, go to step 8;
[0120] 7. Determine whether the output results of all cycles have been compared; if yes, end the process; if no, return to step 5;
[0121] 8. Output an interrupt signal to end the simulation, analyze and correct the module under test, and then return to step 2.
[0122] It should be noted that in the embodiment of the present application, when performing multi-module system-level simulation verification, on the one hand, the simulation tool is used to input the test stimulus into the module to be tested for functional simulation verification and periodically obtain the output result; on the other hand, the test stimulus is input into the reference model for compilation and periodically obtain the output result; the output results are compared periodically, and if the comparison results are completely consistent, the output in the next cycle is waited for comparison until the output results in all cycles are compared; if they are not completely consistent, an exception is reported, and an interrupt signal is returned to the module to be tested to end the simulation and analyze and correct the code of the module to be tested before re-performing functional verification. By using this method, on the one hand, it is possible to avoid using waveform viewing tools for a large number of manual comparisons, improve the efficiency of verification work, and on the other hand, by periodically exporting the output results in real time for verification, terminating the simulation in case of an abnormality, modifying the abnormal code, and restarting the verification, it is possible to avoid running all the test stimuli before starting the comparison, and reduce unnecessary time waste.
[0123] The technical solution provided in the embodiment of the present application automatically generates a configuration program for a register module that can be compiled by a software platform based on the structural characteristics of the register address mapping allocation table, which greatly saves simulation time and improves verification efficiency. In addition, a standardized verification process is proposed during system-level simulation verification, which first performs read and write operations on all registers to ensure that the register functions are correct, and then performs system-level simulation verification of the module to be tested and automatically compares the results with the reference model, which reduces the threshold for verification staff and can greatly improve verification efficiency.
[0124] An embodiment of the present application provides a configuration device. Figure 6 A schematic diagram of a configuration device provided in an embodiment of the present application Figure 1 .like Figure 6 As shown, the configuration device includes:
[0125] A generating module 201 is used to generate a configuration program of a register module in a chip to be tested by using the structural characteristics of a register address mapping allocation table;
[0126] Verification module 202, used to verify the read and write functions of the register module;
[0127] The configuration module 203 is used to configure the register module using the configuration program when the register module is verified, so as to support the module under test in the chip under test to perform function verification.
[0128] In one embodiment of the present application, the structural features at least include:
[0129] It includes the base address of the register module, the register data bit width of the register module, each sub-module in the register module, the offset address of the member variable in each sub-module, and the bit width of the member variable in each sub-module.
[0130] In one embodiment of the present application, the generation module 201 is used to perform the following processing on the first sub-module in the register module: filter out and delete each unreadable or unwritable member variable from the first sub-module; the first sub-module is any sub-module in the register module; for each readable and writable member variable in the first sub-module, define the data type based on the respective bit width; for each readable and writable member variable in the first sub-module, based on the respective offset address, the base address, and the register data bit width, integrate the member variables and generate a statement to write to the register module; and continue to perform the same processing on the sub-modules in the register module that are different from the first sub-module, and generate the configuration program based on the processing results of each sub-module.
[0131] In one embodiment of the present application, the generation module 201 is used to define the data type of the first member variable as an unsigned byte type if the bit width of the first member variable is less than or equal to 8; if the bit width of the first member variable is greater than 8 and less than or equal to 15, define the data type of the first member variable as an unsigned short integer type; if the bit width of the first member variable is greater than 15, define the data type of the first member variable as an unsigned integer type; wherein the first member variable is any readable and writable member variable in the first submodule.
[0132] In one embodiment of the present application, the generation module 201 is used to divide the readable and writable member variables in the first submodule into N sets; wherein N is a positive integer, each set includes one or more member variables, the offset addresses of the member variables in the same set are the same, and the offset addresses of the member variables in different sets are different; for each set, if the number of member variables in the set is multiple, the member variables in the set are integrated into data that meets the register data bit width and are determined as corresponding target data; if the number of member variables in the set is one, the member variables in the set are determined as corresponding target data; a statement written into the register module is generated for the target data corresponding to each set; wherein, for each set, the storage address of the corresponding target data in the register module is determined based on the offset address of the member variable in the set and the base address.
[0133] In one embodiment of the present application, the verification module 202 is used to perform a first read-write operation to set all addresses in the register module to 1; perform an XOR operation on the data written by the first read-write operation and the data read out to obtain a first XOR result; perform a second read-write operation to set all addresses in the register module to 0; perform an XOR operation on the data written by the second read-write operation and the data read out to obtain a second XOR result; if the first XOR result and the second XOR result are both 0, it is determined that the register module verification has passed; if the first XOR result or the second XOR result is 1, it is determined that the register module verification has failed.
[0134] In one embodiment of the present application, the verification module 202 is further used to input the test stimulus into the module to be tested and the reference model respectively for functional verification; wherein the reference model supports simulating the expected functions of the module to be tested; periodically obtain the output results of the module to be tested and the reference model and compare them; if the output results of the module to be tested and the reference model are different, control the module to be tested to end the functional verification, and re-perform the functional verification after correcting the module to be tested.
[0135] Based on the same inventive concept, Figure 7 A schematic diagram of a configuration device provided in an embodiment of the present application Figure 2 .like Figure 7 As shown, the configuration device includes: a processor 301, a memory 302 and a communication bus 303;
[0136] The communication bus 303 is used to realize the communication connection between the processor 301 and the memory 302;
[0137] The processor 301 is used to execute one or more computer programs stored in the memory 302 to implement the above configuration method.
[0138] An embodiment of the present application provides a computer program product, including a computer program, which implements the above configuration method when executed.
[0139] The embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and the computer program implements the above configuration method when executed by a processor. The computer-readable storage medium can be a volatile memory (volatile memory), such as a random access memory (Random-Access Memory, RAM); or a non-volatile memory (non-volatile memory), such as a read-only memory (Read-Only Memory, ROM), a flash memory (flash memory), a hard disk (Hard Disk Drive, HDD) or a solid-state drive (Solid-State Drive, SSD); or it can be a respective device including one or any combination of the above memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc.
[0140] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of hardware embodiments, software embodiments, or embodiments in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.
[0141] The present application is described with reference to implementation flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0142] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which is implemented in the implementation flow diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0143] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing the steps in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0144] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the utility application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A configuration method, characterized in that: The method comprises: Using the structural characteristics of the register address mapping allocation table, a configuration program of the register module in the chip to be tested is generated; Verifying the read and write functions of the register module; In the case where the register module passes the verification, the register module is configured using the configuration program to support the module under test in the chip under test to perform functional verification.
2. The method according to claim 1, characterized in that The structural features at least include: It includes the base address of the register module, the register data bit width of the register module, each sub-module in the register module, the offset address of the member variable in each sub-module, and the bit width of the member variable in each sub-module.
3. The method according to claim 2, characterized in that The configuration program of the register module in the chip to be tested is generated by utilizing the structural characteristics of the register address mapping allocation table, including: The following processing is performed on the first submodule in the register module: Filter out and delete each member variable that is unreadable or unwritable from the first submodule; the first submodule is any submodule in the register module; For each readable and writable member variable in the first submodule, define a data type based on the respective bit width; For each readable and writable member variable in the first submodule, based on the respective offset addresses, the base address, and the register data bit width, the member variables are integrated to generate a statement for writing into the register module; Continue to perform the same processing on the submodules in the register module that are different from the first submodule, and generate the configuration program based on the processing results of each submodule.
4. The method according to claim 3, characterized in that: The data types of the readable and writable member variables in the first submodule are defined based on their respective bit widths, including: If the bit width of the first member variable is less than or equal to 8, define the data type of the first member variable as an unsigned byte type; If the bit width of the first member variable is greater than 8 and less than or equal to 15, define the data type of the first member variable as an unsigned short integer type; If the bit width of the first member variable is greater than 15, define the data type of the first member variable as an unsigned integer type; The first member variable is any readable and writable member variable in the first submodule.
5. The method according to claim 3, characterized in that: The step of integrating the member variables of the first submodule that are readable and writable based on their respective offset addresses, the base address, and the register data bit width to generate a statement for writing into the register module includes: Divide each readable and writable member variable in the first submodule into N sets; wherein N is a positive integer, each set includes one or more member variables, the offset addresses of the member variables in the same set are the same, and the offset addresses of the member variables in different sets are different; For each set, if there are multiple member variables in the set, the member variables in the set are integrated into data that meets the data bit width of the register and determined as the corresponding target data; if there are only one member variable in the set, the member variable in the set is determined as the corresponding target data; Generate a statement written into the register module for the target data corresponding to each set; Wherein, for each set, the storage address of the corresponding target data in the register module is determined based on the offset address of the member variable in the set and the base address.
6. The method according to claim 1, characterized in that The verifying the read and write functions of the register module includes: Performing a first read-write operation of setting all addresses in the register module to 1; XOR the data written by executing the first read-write operation with the data read out to obtain a first XOR result; Performing a second read-write operation of setting all addresses in the register module to 0; XOR the data written by executing the second read-write operation with the data read out to obtain a second XOR result; If the first XOR result and the second XOR result are both 0, it is determined that the register module verification has passed; If the first XOR result or the second XOR result is 1, it is determined that the register module verification fails.
7. The method according to claim 1, characterized in that The method further comprises: Input the test stimulus into the module to be tested and the reference model respectively for functional verification; wherein the reference model supports simulating the expected functions of the module to be tested; Periodically obtaining and comparing the output results of the module to be tested and the reference model; If the output results of the module to be tested are different from those of the reference model, the module to be tested is controlled to end the function verification, and the module to be tested is corrected and then the function verification is performed again.
8. A configuration device, characterized in that: include: A generation module is used to generate a configuration program of a register module in the chip to be tested by utilizing the structural characteristics of the register address mapping allocation table; A verification module, used to verify the read and write functions of the register module; The configuration module is used to configure the register module using the configuration program when the register module is verified, so as to support the module under test in the chip under test to perform function verification.
9. A configuration device, characterized in that: include: processor, memory, and communications bus; The communication bus is used to realize the communication connection between the processor and the memory; The processor is used to execute one or more computer programs stored in the memory to implement the configuration method according to any one of claims 1 to 7.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the configuration method according to any one of claims 1 to 7 is implemented.
11. A computer program product, comprising a computer program, characterized in that When the computer program is executed, the configuration method according to any one of claims 1 to 7 is implemented.