Layout optimization method, device and equipment and computer storage medium

Abstract

The invention discloses a layout optimization method, device and equipment and a computer storage medium. The method comprises the steps that an original layout and a virtual network are obtained, and the virtual network comprises grid units arranged in a matrix mode; stacking the virtual network on the original layout according to the first stacking position so as to divide the original layout into a plurality of grid areas arranged in an array according to the grid units; performing iterative optimization on graphs in each grid region of the original layout until a preset optimization condition is met, and obtaining a target layout; updating the original layout into a target layout; and translating the virtual network to obtain an updated first stacking position, and returning to stack the virtual network on the original layout according to the first stacking position so as to divide the original layout into a plurality of grid regions arranged in an array until the number of times of movement of the virtual network reaches a first preset number of times. According to the embodiment of the invention, the layout optimization effect can be improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a layout optimization method, device, equipment and computer storage medium. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, people's requirements for chip performance and integration are gradually increasing. This trend has led to a continuous reduction in key dimensions in chip layout.

[0003] The manufacturing process of key dimensions in chip layout has reached the nanometer level, so any slight deviation may affect the overall performance and reliability of the chip. In particular, due to the optical proximity effect, the mask layout may have graphic distortion problems during exposure, which will affect chip performance and even cause chip failure.

[0004] In the related art, the mask layout can be corrected by computational lithography, so that the pattern exposed by the corrected mask layout can be closer to the requirements of the design layout. However, when optimizing the mask layout by computational lithography, some discontinuities may exist, which affect the quality and accuracy of the pattern formed on the wafer, resulting in a decrease in chip yield. Summary of the invention

[0005] The embodiments of the present application provide a layout optimization method, device, equipment and computer storage medium, which can reduce discontinuities in the layout optimization process and improve product yield.

[0006] In a first aspect, an embodiment of the present application provides a method for layout optimization, comprising: obtaining an original layout and a virtual network, the virtual network comprising grid units arranged in a matrix; superimposing the virtual network on the original layout according to a first superimposed position, so as to divide the original layout into a plurality of grid areas arranged in an array according to the grid units; iteratively optimizing the graphics in each grid area of ​​the original layout until a preset optimization condition is met to obtain a target layout; updating the original layout to the target layout; translating the virtual network to obtain an updated first superimposed position, and returning to superimposing the virtual network on the original layout according to the first superimposed position, so as to divide the original layout into a plurality of grid areas arranged in an array, until the number of moves of the virtual network reaches a preset number of times.

[0007] In a possible implementation of the first aspect, the outline of the grid area is a rectangle, and translating the virtual network to obtain an updated first stacking position includes: translating the virtual network along a diagonal direction of the grid area to obtain the updated first stacking position.

[0008] In a possible implementation of the first aspect, translating the virtual network to obtain an updated first stacking position includes: determining a translation distance according to a side length of a grid area; and translating the virtual network according to the translation distance to obtain an updated first stacking position.

[0009] In a possible implementation of the first aspect, the translation distance is smaller than the side length.

[0010] In a possible implementation of the first aspect, the graphics in each grid area of ​​the original layout are iteratively optimized until a preset optimization condition is met to obtain a target layout, including: iteratively performing the following operations until the preset optimization condition is met to obtain the target layout: determining a graphic correction strategy for the graphics in each grid area according to an optical proximity effect; determining correction parameters for different graphics in different grid areas according to the graphic correction strategy and a lithography process model; correcting different graphics in different grid areas according to the correction parameters to obtain corrected graphics; predicting key size information of the corrected graphics according to the lithography process model to obtain predicted key size information; calculating a deviation between the predicted key size information and the preset key size threshold information to obtain deviation information; and updating the corrected graphics to the graphics in the grid area when it is determined that the preset optimization condition is not met.

[0011] In a possible implementation of the first aspect, critical dimension information of a corrected graphic is predicted based on a lithography process model to obtain predicted critical dimension information, including: determining a mask image based on the corrected graphic; and inputting the mask image into a lithography reaction model to obtain predicted critical dimension information of the graphic.

[0012] In a possible implementation of the first aspect, the graphic correction strategy includes at least one of the following: graphic edge adjustment, adding auxiliary graphics, and adjusting graphic shape; accordingly, the correction parameters include at least one of the following: graphic edge adjustment amount, auxiliary graphic size, position and shape.

[0013] In a possible implementation of the first aspect, preset optimization conditions in different iterative optimization processes are different.

[0014] In a possible implementation of the first aspect, the preset optimization conditions include that the number of iterations is less than the preset number, and the preset numbers in the preset optimization conditions in two adjacent iterative optimization processes are different; or, the deviation information is less than the preset deviation; and the preset deviations in the preset optimization conditions in two adjacent iterative optimization processes are different.

[0015] In a second aspect, an embodiment of the present application provides a layout optimization device, comprising: an acquisition module, used to acquire an original layout and a virtual network, the virtual network comprising grid units arranged in a matrix; a division module, used to overlay the virtual network on the original layout according to a first stacking position, so as to divide the original layout into a plurality of grid areas arranged in an array according to the grid units; an optimization module, used to iteratively optimize the graphics in each grid area of ​​the original layout until a preset optimization condition is met to obtain a target layout; an update module, used to update the original layout to a target layout; a translation module, used to translate the virtual network to obtain an updated first stacking position, and return to overlaying the virtual network on the original layout according to the first stacking position, so as to divide the original layout into a plurality of grid areas arranged in an array, until the number of moves of the virtual network reaches a preset number of times.

[0016] In a third aspect, an embodiment of the present application provides a layout optimization device, comprising: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the method for layout optimization in the first aspect or any one of the embodiments of the first aspect is implemented.

[0017] In a fourth aspect, a computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the method for layout optimization in the first aspect or any one of the embodiments of the first aspect is implemented.

[0018] In a fifth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes a method for layout optimization as described in the first aspect or any one of the implementations of the first aspect.

[0019] A method, device, equipment and computer storage medium for layout optimization in an embodiment of the present application, a method for layout optimization in an embodiment of the present application, by obtaining the original layout and the virtual network, and superimposing the virtual network on the original layout according to the first stacking position, so that the original layout can be divided according to the grid units in the virtual network to obtain multiple grid areas. And optimize the grid area so that each area meets the optimization conditions to obtain the target layout. Further, the virtual network can be translated to the updated first stacking position, and it is determined whether the number of moves of the virtual network reaches the first preset number of times. If it is reached, it is determined that the layout optimization is completed, and the optimized layout can be obtained. If the first preset number is not reached, the optimized layout is divided according to the virtual network located in the updated first stacking position, and each grid area is optimized again until the preset number is reached. It can be understood that in the process of iterative optimization of the graphics in each grid area, the optimization effect of the graphics located in the center is better. Therefore, in the embodiment of the present application, by continuously adjusting the position of the graphics in the grid area, the graphics in the layout have the opportunity to be located in the center of the grid area, thereby improving the layout optimization effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 A schematic diagram of a design layout division provided in an embodiment of the present application is shown;

[0022] Figure 2 A schematic flow chart of a layout optimization method provided by an embodiment of the present application is shown;

[0023] Figure 3 A schematic diagram showing a stacking method of a virtual network according to a first stacking position provided by an embodiment of the present application is shown;

[0024] Figure 4 A schematic diagram showing a stacking method of a virtual network according to an updated first stacking position provided by an embodiment of the present application is shown;

[0025] Figure 5 A schematic diagram of the process of S230 provided in one embodiment of the present application is shown;

[0026] Figure 6 A schematic diagram showing the division of the expansion area provided by an embodiment of the present application is shown;

[0027] Figure 7is a structural schematic diagram of a layout optimization device provided by another embodiment of the present application;

[0028] Figure 8 It is a structural schematic diagram of a layout optimization device provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0029] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0030] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0031] With the rapid development of semiconductor integrated circuit manufacturing technology, the critical size of chip design layout is constantly reduced, and the exposure pattern of chip design layout is distorted due to the optical proximity effect.

[0032] Therefore, computational lithography is needed to correct the graphics in the mask layout. Computational lithography consumes computing resources. In order to increase the computing speed and reduce the bottleneck of resource consumption of a single task, this problem can be solved through distributed computational lithography. Distributed computational lithography can divide the entire design layout into multiple small areas of equal size, optimize each small area separately, and obtain the overall optimization result by splicing the optimization results of each small area, thus realizing the parallel processing solution of "division, parallel computing, and splicing" to improve the optimization speed of the layout. In one example, Figure 1 A schematic diagram of a design layout division provided in an embodiment of the present application is shown, such as Figure 1As shown, the layout 10 can be divided according to a preset size to obtain a plurality of small areas 11. Among them, the small area 11 can completely cover the layout 10 ( Figure 1 Not all small areas are drawn), and each small area 11 can be called a box.

[0033] However, in the process of layout division, there may be a situation where a complete graphic is divided into different small areas. At this time, the complete graphic at the boundary of the small area will be cut off and the geometric properties of the graphic will be destroyed. In the simulation process of computational lithography, the results are heavily dependent on the surrounding environment, and changes in the surrounding environment will affect the simulation results. It is understandable that since a complete graphic is divided into different small areas, the geometric properties of the graphic are destroyed, and when each small area is optimized, its optimization result will be affected by the geometric properties of the graphic. Therefore, optimizing different parts of the same graphic in different small areas may lead to slight differences in optimization. And these differences may cause discontinuity at the splicing when the small areas are spliced. Therefore, how to ensure the continuity of the splicing boundaries when the divided small areas are spliced ​​into a whole layout in the distributed computational lithography process is a technical problem that needs to be solved urgently by relevant technical personnel.

[0034] In order to solve the problems of the prior art, the embodiments of the present application provide a layout optimization method, device, equipment and computer storage medium. The layout optimization method provided by the embodiments of the present application is first introduced below.

[0035] Figure 2 FIG. 1 is a flow chart of a layout optimization method provided by an embodiment of the present application. Figure 2 As shown, the layout optimization method provided in the embodiment of the present application includes the following steps:

[0036] S210, obtaining an original layout and a virtual network, where the virtual network includes grid cells arranged in a matrix.

[0037] S220, overlaying the virtual network on the original layout according to the first overlay position, so as to divide the original layout into a plurality of grid areas arranged in an array according to grid units.

[0038] S230, iteratively optimizing the graphics in each grid area of ​​the original layout until the preset optimization conditions are met to obtain the target layout.

[0039] S240, updating the original layout to the target layout.

[0040] S250, determining whether the number of times the layout is divided reaches a first preset number, if not, executing S260; if yes, ending the training.

[0041] S260: translating the virtual network to obtain an updated first stacking position.

[0042] Exemplarily, in step S210, the original layout may be a design drawing of an integrated circuit. The original layout may be a pattern drawn by a technician using an electronic design automation tool according to functional requirements. In addition, the original layout describes in detail the shape, position, size, and connection relationship of each component in the circuit. In one example, the components in the circuit may include transistors, resistors, capacitors, and the like.

[0043] Exemplarily, the virtual network may be composed of a plurality of grid units arranged in an array. In one example, each grid unit in the virtual network has the same size.

[0044] For example, in step S220, the virtual network can be superimposed on the original layout according to the first superposition position, so that the original layout is divided into a plurality of grid areas arranged in an array according to each grid unit in the virtual network. Each grid area can be an area of ​​equal size and arranged in a row, and the virtual network can completely cover the original layout.

[0045] Exemplarily, the first stacking position may be any position in the original layout. In one example, stacking the virtual network on the original layout according to the first stacking position may be aligning the lower left corner of the original layout with the lower left corner of the virtual network, thereby stacking the virtual network on the original layout. Figure 3 A schematic diagram of a stacking method of a virtual network according to a first stacking position provided by an embodiment of the present application is shown, such as Figure 3 As shown, the lower left corner of the original layout is aligned with the lower left corner of the virtual network, and the virtual network can completely cover the original layout. Wherein, each grid unit in the virtual network can be a rectangle, and the side length of each rectangle can be set to m microns. The original layout 10 is divided according to the m*m grid units, thereby obtaining multiple grid areas, including box1, box2, ..., boxn. Wherein, m is a positive number.

[0046] For ease of understanding, if the coordinates corresponding to the left position of the lower left corner of the target layout are (0,0), then the coordinates corresponding to the first stacking position and the lower left corner of the target layout can also be (0,0). Point 1 and point 2 can represent points contained in different graphics, and when the virtual grid is located at the first stacking position to divide the original layout, point 1 and point 2 are both located in box1, where point 2 is located at the center of box1 and point 1 is located at the edge of box1. At this time, the graphics containing point 1 can be completely located in box1, and the graphics containing point 2 may have some areas located in other boxes.

[0047] For example, in step S230, the graphics in multiple grid areas may be optimized in parallel until a preset optimization condition is met, and the multiple optimized grid areas are spliced ​​to obtain a target layout.

[0048] In one example, when box1 is optimized, box1 can optimize the graphics containing point 2. Since the graphics containing point 2 are all located in box1, the geometric properties of the graphics at point 2 are not destroyed. Therefore, when the graphics containing point 2 are optimized, there is no discontinuity problem in the optimized graphics. When box1 optimizes the graphics containing point 1, since part of the graphics containing point 1 is located in other boxes, the geometric properties of the graphics at point 1 are destroyed. Therefore, when the graphics containing point 1 are optimized, discontinuities appear when the optimized graphics are spliced ​​with other boxes, that is, the graphics containing point 1 will have discontinuities after optimization.

[0049] Exemplarily, in step S240, the original layout may be updated to a target layout, wherein the target layout may be an optimized layout.

[0050] Exemplarily, in step S250, it can be determined whether the number of times the layout is divided reaches a first preset number. If so, that is, the number of times the layout is divided reaches the first preset number, it is determined that the layout optimization is completed, the training is terminated, and the optimized layout is obtained; if not, that is, the number of times the layout is divided does not reach the first preset number, then S260 is executed, that is, the virtual network is translated to obtain an updated first stacking position, and the virtual network is stacked on the target layout according to the updated first stacking position to divide the target layout into multiple grid areas arranged in an array, until the number of times the virtual network is moved reaches the first preset number of times.

[0051] Furthermore, after the virtual network is stacked on the optimized layout according to the updated first stacking position, the original layout can be divided according to the virtual network located at the updated first stacking position. Figure 4 A schematic diagram of a stacking method of a virtual network according to an updated first stacking position provided by an embodiment of the present application is shown, such as Figure 4As shown, the updated first stacking position can be to move the lower left corner of the virtual network along the diagonal of the grid area by a distance of (2m√2) / 3. It can be understood that, for ease of understanding, if the coordinates corresponding to the left position of the lower left corner of the target layout are (0,0), the coordinates corresponding to the updated first stacking position can be (-2m / 3,-2m / 3). Further, the virtual grid is stacked on the target layout according to the updated first stacking position, that is, the lower left corner of the virtual network can be aligned with the updated first stacking position, and the target layout can be divided according to the grid area. Among them, the target layout 20 can be divided according to the m*m grid area to obtain multiple second divided areas, including box1', box2',..., boxn'. Among them, m is a positive number. Among them, in the process of this division, point 1 and point 2 can be located in different grid areas, that is, point 2 is located in box1, and point 1 is located in box4. In addition, point 2 is located at the edge of box1, and point 1 is located at the center of box4. At this time, the discontinuity point in the figure containing point 2 at the time of the first splicing can be located in box4.

[0052] Furthermore, the graphics in the re-divided grid area may be optimized in parallel. In one example, when box4 is optimized, box4 may optimize the position of the discontinuity points in the graphics containing point 2, so that the graphics of point 2 meet the requirements.

[0053] A method for optimizing a layout in an embodiment of the present application, by obtaining an original layout and a virtual network, and superimposing the virtual network on the original layout according to a first stacking position, the original layout can be divided according to the grid units in the virtual network to obtain multiple grid areas. And the grid area is optimized so that each area meets the optimization conditions to obtain a target layout. Further, the virtual network can be translated to the updated first stacking position, and it is determined whether the number of moves of the virtual network reaches the first preset number of times. If it is reached, it is determined that the layout optimization is completed, and the optimized layout can be obtained. If the first preset number is not reached, the optimized layout is divided according to the virtual network located in the updated first stacking position, and each grid area is optimized again until the preset number is reached. It can be understood that in the process of iteratively optimizing the graphics in each grid area, the optimization effect of the graphics located in the center is better. Therefore, in the embodiment of the present application, by continuously adjusting the position of the graphics in the grid area, the graphics in the layout have the opportunity to be located in the center of the grid area, thereby improving the layout optimization effect.

[0054] In some optional embodiments, if the outline of the grid area is a rectangle, the virtual network may be translated along the diagonal direction of the grid area to obtain an updated first stacking position.

[0055] Exemplarily, based on the first stacking position, the virtual network may be translated along the diagonal line of the grid area to the updated first stacking position.

[0056] In one example, the outline of the grid area may be a square, and the outline of the grid area may be determined by a technician based on the original layout.

[0057] In an embodiment of the present application, when the outline of the grid area is a rectangle, the virtual network can be translated along the diagonal direction of the grid area to obtain an updated first stacking position, thereby ensuring that the multiple grid areas divided according to the updated first stacking position can be different from the grid areas divided before, further ensuring that the graphics in the original layout can be located at different positions of the grid area, and ensuring that when the layout is optimized, each graphic in the layout has the opportunity to be located at the center of the grid area, thereby improving the effect of layout optimization.

[0058] In some optional embodiments, the updated first stacking position may be determined by a translation distance according to the side length of the grid area, and then the virtual network is translated according to the translation distance to obtain the updated first stacking position.

[0059] In the embodiment of the present application, the translation distance can be determined according to the side length of the grid area, and the virtual network can be translated according to the translation distance so that the virtual grid is located in the first stacking position after the update. It can be understood that determining the translation distance according to the side length of the grid area can avoid the problem of overlapping of each grid area with the previous one after the virtual network is translated. In this way, the graphics in the layout can be located at different positions of the grid area in different subdivisions.

[0060] In some optional embodiments, the translation distance is less than the side length. It is understandable that a smaller distance can be moved so that the graphics in the layout can be located at different positions of the grid area in different subdivisions, thereby improving the layout optimization efficiency.

[0061] For example, each divided region can be optimized separately, thereby reducing the time required for the entire optimization task and improving the optimization efficiency. In one example, each divided region can be distributed to multiple computers or computing nodes in parallel, so that multiple computers or computing nodes can process multiple regions in parallel, thereby improving computing efficiency and reducing memory consumption.

[0062] For example, the following is combined Figure 5 as well as Figure 7 , the process of iterative optimization of the graphics in the grid area in the original layout and the graphics in the second area in the target layout are explained respectively.

[0063] Figure 5FIG. 2 shows a flow chart of S230 provided by an embodiment of the present application. Figure 5 As shown, S230 provided in the embodiment of the present application includes the following steps:

[0064] S231. Determine a graphic correction strategy for the graphics in each grid area according to the optical proximity effect.

[0065] For example, the optical proximity effect (OPE) causes the pattern obtained by exposure to deviate from the size and shape of the desired pattern during the photolithography process. Therefore, the specific correction strategy can be determined based on the result of the optical proximity effect evaluation.

[0066] In some optional embodiments, the first graphic correction strategy includes at least one of the following: graphic edge adjustment, adding auxiliary graphics, and adjusting graphic shape.

[0067] In one example, pattern edge adjustment may refer to fine-tuning the edge of the pattern, such as increasing or decreasing the width of the edge to compensate for the problem of line widening or narrowing caused by the optical proximity effect during the photolithography process.

[0068] In another example, adding auxiliary graphics may refer to adding some auxiliary graphics in the layout, thereby changing the light intensity distribution and improving the photolithography effect of adjacent graphics. For example, adding a small rectangular auxiliary graphic between two closely adjacent lines can reduce the mutual interference between the lines.

[0069] In another example, adjusting the shape of the graphic may refer to fine-tuning the shape of the graphic, such as changing a right angle to a rounded angle, so as to reduce scattering and diffraction effects during the photolithography process.

[0070] In the embodiment of the present application, since the optical proximity effect may cause different defects in the graphics during the lithography process, different correction strategies can be formulated to correct the graphics according to the different defects occurring in the lithography process, thereby reducing lithography defects and improving product yield.

[0071] S232, determining correction parameters of different graphics in different grid areas according to the graphic correction strategy and the photolithography process model.

[0072] Exemplarily, the correction parameters corresponding to the pattern correction strategy can be determined according to the relevant parameters in the lithography process model. In one example, the relevant parameters in the lithography process model may include parameters of the lithography process, properties of the photoresist, and material properties of the wafer, etc. Among them, the parameters of the lithography process include the wavelength of the light source, the exposure dose, the focal length, etc.

[0073] In some optional embodiments, the correction parameter includes at least one of the following: a graphic edge adjustment amount, a size, a position, and a shape of the auxiliary graphic.

[0074] In the embodiment of the present application, for different graphic correction strategies, correction parameters matching the strategies can be determined through relevant parameters in the lithography process model, so that the graphics can be corrected.

[0075] S233. Correct different graphics in different grid areas according to the correction parameters to obtain corrected graphics.

[0076] Exemplarily, different graphics in different grid areas can be corrected according to different correction parameters to obtain corrected graphics. It is understandable that since different graphics are affected differently by the optical proximity effect, the correction strategies for different graphics can be different, and the correction parameters corresponding to the correction strategies can also be different.

[0077] S234. Predict critical dimension information of the corrected pattern according to the photolithography process model to obtain predicted critical dimension information.

[0078] Exemplarily, the photolithography process model may include simulating the light intensity distribution in the photolithography process through an optical model, and simulating the photoresist reaction process.

[0079] Exemplarily, by inputting the graphics of multiple grid areas into the photoresist process model, the photoresist process model can predict the predicted critical dimension information corresponding to the pattern on the crystal source under the input graphics. The predicted critical dimension information may include the shape and / or surface morphology of the pattern on the crystal source.

[0080] In some optional embodiments, a mask image may be determined based on the corrected pattern, and the mask image may be input into a photolithography reaction model to obtain predicted pattern critical dimension information.

[0081] Exemplarily, since the input of the photolithography process model needs to be a mask pattern, the mask pattern can be determined by the correction pattern, and then the mask pattern is input into the photolithography reaction model to obtain the predicted pattern critical dimension information.

[0082] S235 , calculating the deviation between the predicted key size information and the preset key size threshold information to obtain deviation information.

[0083] Exemplarily, the root mean square (RMS) of the deviation may be calculated, and the calculated RMS may be used as the deviation information.

[0084] S236, determine whether the preset optimization conditions are met, if so, determine the corrected pattern as the target layout; if not, execute step S237.

[0085] S237, updating the corrected graphic to the graphic in the grid area.

[0086] In some optional embodiments, the preset optimization condition includes at least one of the number of iterations being less than a second preset threshold value or the deviation information being less than a preset deviation threshold value. The second preset threshold value and the preset deviation threshold value can be set by a technician.

[0087] Exemplarily, the preset optimization conditions in two adjacent iterative optimization processes may be different. Among them, the second preset number of times in two adjacent iterative optimization processes may be different; or, the preset deviation thresholds in two adjacent iterative optimization processes may be different. In one example, if in two adjacent optimization processes, the preset optimization conditions of the previous optimization process at least include the second number of iterations being less than the first preset threshold; or the deviation information being less than any one of the second deviation thresholds. The preset optimization conditions of the next optimization process at least include the second number of iterations being less than the third preset threshold; or the deviation information being less than any one of the fourth deviation thresholds. At this time, the first preset threshold may be set to be greater than the third preset threshold; and the second deviation threshold may be set to be less than the fourth deviation threshold.

[0088] Exemplarily, after determining that the preset optimization condition is satisfied, the revised layout can be determined as the target layout. Further, the target layout can be divided according to the virtual network located at the first stacking position after the update.

[0089] Exemplarily, after determining that the preset optimization conditions are not met, the corrected graphics can be updated to graphics in the grid area, and the correction strategy corresponding to the updated graphics can be re-determined, and then the correction parameters can be determined, and the updated graphics can be corrected using the correction parameters until it is determined that the preset optimization conditions are met.

[0090] Furthermore, since the optimization result of the graphics in each grid area depends on the surrounding environment of the grid area, an expansion area can be set for each divided grid area, and the graphics in the grid area including the expansion area are optimized iteratively.

[0091] In one example, Figure 6 FIG. 1 shows a schematic diagram of the division of the expansion area provided by an embodiment of the present application. Figure 6As shown, the expansion area 12 can be a fixed expansion distance added to the periphery of the divided area. It is understandable that the larger the expansion distance of each area is set, the closer its optimization environment is to the environment of the entire map, and the higher the boundary consistency will be, but optimizing each area will also consume more computing resources. Therefore, it is necessary to reasonably set the range of the expansion area.

[0092] In the embodiment of the present application, the optimization speed of the layout is improved by optimizing multiple grid areas simultaneously.

[0093] Based on the layout optimization method provided in the above embodiment, the present application also provides a specific implementation of the layout optimization device. Please refer to the following embodiment.

[0094] See first Figure 7 , the layout optimization device provided in the embodiment of the present application includes the following units:

[0095] An acquisition module 701 is used to acquire an original layout and a virtual network, where the virtual network includes grid cells arranged in a matrix;

[0096] A division module 72, configured to overlay the virtual network on the original layout according to the first stacking position, so as to divide the original layout into a plurality of grid areas arranged in an array according to the grid units;

[0097] The optimization module 703 is used to iteratively optimize the graphics in each grid area of ​​the original layout until the preset optimization conditions are met to obtain the target layout;

[0098] An updating module 704 is used to update the original layout to a target layout;

[0099] The translation module 705 is used to translate the virtual network to obtain an updated first stacking position, and return to stack the virtual network on the original layout according to the first stacking position to divide the original layout into multiple grid areas arranged in an array, until the number of moves of the virtual network reaches a first preset number of times.

[0100] As an implementation of the present application, the outline of the grid area is a rectangle, and the translation module 705 translates the virtual network in the following manner to obtain the updated first stacking position: translate the virtual network along the diagonal direction of the grid area to obtain the updated first stacking position.

[0101] As an implementation method of the present application, the translation module 705 translates the virtual network in the following manner to obtain an updated first stacking position: determine the translation distance according to the side length of the grid area; translate the virtual network according to the translation distance to obtain an updated first stacking position.

[0102] As an implementation of the present application, the translation distance is smaller than the side length.

[0103] The optimization module 703 iteratively optimizes the graphics in the grid area in the original layout in the following manner until the preset optimization conditions are met to obtain the target layout: iteratively perform the following operations until the preset optimization conditions are met to obtain the target layout: determine the first graphic correction strategy for the graphics in each grid area according to the optical proximity effect; determine the first correction parameters for different graphics in different grid areas according to the first graphic correction strategy and the lithography process model; correct the different graphics in different grid areas according to the first correction parameters to obtain the corrected first corrected graphics; predict the key size information of the first corrected graphics according to the lithography process model to obtain the first predicted key size information; calculate the deviation between the first predicted key size information and the preset key size threshold information to obtain the first deviation information; if it is determined that the preset optimization conditions are not met, update the first corrected graphics to the graphics in the grid area.

[0104] As an implementation method of the present application, the optimization module 703 predicts the key dimension information of the first corrected graphic according to the lithography process model to obtain the first predicted key dimension information: determine the first mask image according to the first corrected graphic; input the first mask image into the lithography reaction model to obtain the first predicted graphic key dimension information.

[0105] As an implementation method of the present application, the graphic correction strategy includes at least one of the following: graphic edge adjustment, adding auxiliary graphics, and adjusting graphic shape; accordingly, the correction parameters include at least one of the following: graphic edge adjustment amount, auxiliary graphic size, position and shape.

[0106] As an implementation method of the present application, the preset optimization condition includes any one of the following: the preset optimization condition includes that the number of iterations is less than a second preset number, and the second preset number of times in the preset optimization conditions in two adjacent iterative optimization processes is different; or, the deviation information is less than a preset deviation threshold; the preset deviation thresholds in the preset optimization conditions in two adjacent iterative optimization processes are different.

[0107] Figure 8 A schematic diagram of the hardware structure of the layout optimization provided in the embodiment of the present application is shown.

[0108] The layout optimization device may include a processor 801 and a memory 802 storing computer program instructions.

[0109] Specifically, the processor 801 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0110] The memory 802 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 802 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 802 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 802 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 802 is a non-volatile solid-state memory.

[0111] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical or other physical / tangible memory storage devices. Thus, typically, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to an aspect of the present disclosure.

[0112] The processor 801 implements any one of the layout optimization methods in the above embodiments by reading and executing computer program instructions stored in the memory 802 .

[0113] In one example, the layout optimization device may further include a communication interface 803 and a bus 810. Figure 8 As shown, the processor 801, the memory 802, and the communication interface 803 are connected via a bus 810 and communicate with each other.

[0114] The communication interface 803 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0115] Bus 810 includes hardware, software or both, and the parts of online data flow billing equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front-end bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 810 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the application considers any suitable bus or interconnection.

[0116] The layout optimization device can execute the layout optimization method in the embodiment of the present application according to the regions obtained by different division methods, thereby realizing the combination of Figure 2 and Figure 7 Described layout optimization method and device.

[0117] In addition, in combination with the layout optimization method in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any one of the layout optimization methods in the above embodiment is implemented.

[0118] The present embodiment also provides a computer program product, including a computer program, which implements any one of the layout optimization methods in the above embodiments when the computer program is processed and executed.

[0119] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0120] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0121] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0122] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0123] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A layout optimization method, characterized in that: include: Acquire an original layout and a virtual network, wherein the virtual network includes grid cells arranged in a matrix; Overlaying the virtual network on the original layout according to a first stacking position, so as to divide the original layout into a plurality of grid areas arranged in an array according to the grid units; Iteratively optimizing the graphics in each grid area of ​​the original layout until the preset optimization conditions are met to obtain the target layout; Updating the original layout to the target layout; The virtual network is translated to obtain an updated first stacking position, and the virtual network is returned to be stacked on the original layout according to the first stacking position to divide the original layout into a plurality of grid areas arranged in an array, until the number of moves of the virtual network reaches a first preset number of times.

2. The method according to claim 1, characterized in that The outline of the grid area is a rectangle, and translating the virtual network to obtain an updated first stacking position includes: The virtual network is translated along the diagonal direction of the grid area to obtain an updated first stacking position.

3. The method according to any one of claims 1 or 2, characterized in that The translating the virtual network to obtain an updated first stacking position includes: Determining a translation distance according to the side length of the grid area; The virtual network is translated according to the translation distance to obtain an updated first stacking position.

4. The method according to claim 3, characterized in that The translation distance is smaller than the side length.

5. The method according to claim 1, characterized in that The iterative optimization of the graphics in each grid area of ​​the original layout until the preset optimization conditions are met to obtain the target layout includes: Iterate the following operations until the preset optimization conditions are met and the target layout is obtained: Determine the graphic correction strategy of the graphics in each grid area according to the optical proximity effect; Determining correction parameters of different graphics in different grid areas according to the graphic correction strategy and the photolithography process model; According to the correction parameters, different graphics in different grid areas are corrected to obtain corrected graphics; Predicting critical dimension information of the corrected pattern according to a photolithography process model to obtain predicted critical dimension information; Calculate the deviation between the predicted key size information and the preset key size threshold information to obtain deviation information; When it is determined that the preset optimization condition is not satisfied, the correction graph is updated to a graph in the grid area.

6. The method according to claim 5, characterized in that The step of predicting the critical dimension information of the corrected pattern according to the photolithography process model to obtain the predicted critical dimension information includes: Determining a mask image according to the correction image; The mask image is input into a photolithography reaction model to obtain predicted graphic critical dimension information.

7. The method according to claim 5, characterized in that The graphic correction strategy includes at least one of the following: graphic edge adjustment, adding auxiliary graphics, and adjusting the shape of the graphic; Accordingly, the correction parameter includes at least one of the following: the amount of adjustment of the edge of the graphic, the size, position and shape of the auxiliary graphic.

8. The method according to any one of claims 1 to 7, characterized in that: The preset optimization conditions in different iterative optimization processes are different.

9. The method according to claim 8, characterized in that The preset optimization condition includes that the number of iterations is less than a second preset number, and the second preset numbers in the preset optimization conditions in two adjacent iterative optimization processes are different; or, The deviation information is less than a preset deviation threshold; and the preset deviation thresholds in the preset optimization conditions in two adjacent iterative optimization processes are different.

10. A layout optimization device, characterized in that: include: An acquisition module, used to acquire an original layout and a virtual network, wherein the virtual network includes grid cells arranged in a matrix; A division module, used for superimposing the virtual network on the original layout according to a first stacking position, so as to divide the original layout into a plurality of grid areas arranged in an array according to the grid units; An optimization module, used for iteratively optimizing the graphics in each grid area of ​​the original layout until a preset optimization condition is met to obtain a target layout; An updating module, used for updating the original layout to the target layout; A translation module is used to translate the virtual network to obtain an updated first stacking position, and return to the first stacking position to stack the virtual network on the original layout to divide the original layout into a plurality of grid areas arranged in an array, until the number of moves of the virtual network reaches a first preset number of times.

11. A layout optimization device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the layout optimization method as described in any one of claims 1 to 9 is implemented.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the layout optimization method according to any one of claims 1 to 9 is implemented.

13. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the layout optimization method as described in any one of claims 1 to 9.

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