Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate, a first metal pattern and a second metal pattern, the first metal pattern and the second metal pattern are arranged on the substrate, and the first metal pattern and the second metal pattern are sequentially arranged in the direction away from the substrate; the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate are at least partially overlapped, and the minimum distance between the adjacent second metal patterns is greater than 2.5 microns at the edge of the overlapped area of the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate; the first metal pattern is formed on the first metal layer, and the second metal pattern is formed on the second metal layer. According to the invention, the adjacent second metal patterns are set to be in a pull-open design at the edge of the overlapping area of the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate, so that the product yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In the related art, the long-strip screen project has a long gate metal trace, which results in a large resistance of the trace formed on the gate metal layer, a high RC (resistance-capacitance) loading, and is prone to risks such as insufficient charging or increased power consumption. Usually, the thickness of the gate metal layer is set to be thicker during metal trace design to reduce the resistance of the trace formed on the gate metal layer. When the source and drain metal traces cross the steps of the gate metal layer, the adjacent source and drain metal traces will be short-circuited. Summary of the invention

[0003] The main purpose of the present invention is to provide a display substrate and a display device for solving the problem that when the gate metal layer is thick and the source and drain metal lines cross the steps of the gate metal layer, adjacent source and drain metal lines will be short-circuited with each other.

[0004] In one aspect, an embodiment of the present invention provides a display substrate, including a base, a first metal pattern, and a second metal pattern;

[0005] The first metal pattern and the second metal pattern are disposed on the substrate, and the first metal pattern and the second metal pattern are arranged in sequence along a direction away from the substrate;

[0006] The orthographic projection of the first metal pattern on the substrate at least partially overlaps with the orthographic projection of the second metal pattern on the substrate, and at the edge of the overlapping area of ​​the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate, the minimum distance between adjacent second metal patterns is greater than 2.5 μm;

[0007] The first metal pattern is formed on a first metal layer, and the second metal pattern is formed on a second metal layer.

[0008] Optionally, the first metal layer is a gate metal layer, and the second metal layer is a source / drain metal layer.

[0009] Optionally, the thickness of the gate metal layer is greater than or equal to 5000 angstroms.

[0010] Optionally, the display substrate includes a transistor;

[0011] The first metal pattern is a gate pattern of the transistor, and the second metal pattern includes a first electrode portion and a second electrode portion; the first electrode portion includes a first lead and a first electrode of the transistor, and the second electrode portion includes a second lead and a second electrode of the transistor; the first lead is electrically connected to the first electrode of the transistor, and the second lead is electrically connected to the second electrode of the transistor;

[0012] The orthographic projection of the gate pattern on the substrate has a plurality of side edges;

[0013] The orthographic projection of the first electrode portion on the substrate overlaps with the first side portion of the orthographic projection of the gate pattern on the substrate, and the orthographic projection of the second electrode portion on the substrate overlaps with the second side portion of the orthographic projection of the gate pattern on the substrate; the first side and the second side are different sides.

[0014] Optionally, a position where the orthographic projection of the first electrode portion on the substrate overlaps with the first side portion is located at an end of the first side close to the second side, and the first side is adjacent to the second side.

[0015] Optionally, the orthographic projection of the first electrode portion on the substrate overlaps with the first side portion at a first end of the first side, the first side is adjacent to the second side, and an extension direction of the first lead wire is the same as an extension direction of the second lead wire;

[0016] The first end of the first side is an end of the first side electrically connected to the second side.

[0017] Optionally, the first electrode portion includes a first portion, a second portion and a third portion electrically connected to each other; an orthographic projection of the first portion on the substrate is included within an orthographic projection of the gate pattern on the substrate;

[0018] The orthographic projection of the second portion on the substrate overlaps with the first side portion; and / or, the orthographic projection of the second portion on the substrate overlaps with the first end of the second side; the first end of the second side is the end of the second side electrically connected to the first side;

[0019] The orthographic projection of the third portion on the substrate does not overlap with the orthographic projection of the gate pattern on the substrate;

[0020] The third portion extends in a direction away from the second side edge;

[0021] The width of the second portion is greater than the width of the first portion.

[0022] Optionally, the channel of the transistor is a U-shaped channel or an I-shaped channel;

[0023] The first lead wire is electrically connected to an end of the first electrode, and the second lead wire is electrically connected to an end of the second electrode; or,

[0024] The first lead wire is electrically connected to a middle portion of the first electrode, and the second lead wire is electrically connected to a middle portion of the second electrode.

[0025] Optionally, the channel of the transistor is a U-shaped channel or an I-shaped channel;

[0026] The first lead wire is electrically connected to the middle portion of the first electrode, and the second lead wire is electrically connected to the end portion of the second electrode; or,

[0027] The first lead wire is electrically connected to an end portion of the first electrode, and the second lead wire is electrically connected to a middle portion of the second electrode.

[0028] Optionally, the first metal pattern includes a plurality of first signal lines; the second metal pattern includes a plurality of second signal lines;

[0029] The first signal line extends along a first direction, the second signal line extends along a second direction, and the first direction intersects the second direction; the plurality of first signal lines are adjacent in the second direction, and the plurality of second signal lines are adjacent in the first direction;

[0030] The orthographic projection of the first signal line on the substrate overlaps with the orthographic projection of the second signal line on the substrate;

[0031] In a region between two adjacent first signal lines, a shortest distance between adjacent second signal lines is greater than 2.5 μm.

[0032] Optionally, in an overlapping area of ​​an orthographic projection of the first signal line on the substrate and an orthographic projection of the second signal line on the substrate, a shortest distance between adjacent second signal lines is greater than 2.5 μm.

[0033] Optionally, the first signal line includes a virtual drive circuit load line, and the second signal line includes a data line and a touch signal line.

[0034] Optionally, the distance between adjacent first signal lines is less than 6 μm.

[0035] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display substrate.

[0036] In an embodiment of the present invention, at the edge of the overlapping area of ​​the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate, the minimum distance between adjacent second metal patterns is set to be greater than 2.5 μm, and the adjacent second metal patterns are set to be separated by a design, thereby improving product yield and ensuring process margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a circuit diagram of at least one embodiment of a drive circuit;

[0038] Figure 2A yes Figure 1 An operation timing diagram of at least one embodiment of the driving circuit shown;

[0039] Figure 2B is a partial layout diagram of the first transistor M1 in the related art;

[0040] Figure 2C yes Figure 2B A-A' cross-section diagram;

[0041] Figure 3A and Figure 3C is a partial layout diagram of M1 in at least one embodiment of the present invention;

[0042] Figure 3B yes Figure 3A Layout diagram of gate G1 of M1 in FIG.

[0043] Figure 4A and Figure 4C is a partial layout diagram of M1 in at least one embodiment of the present invention;

[0044] Figure 4B yes Figure 4A Layout diagram of gate G1 of M1 in FIG.

[0045] Figure 5 is a partial layout diagram of at least one embodiment of a transistor included in a display substrate;

[0046] Figure 6 is a partial layout diagram of at least one embodiment of a transistor included in a display substrate;

[0047] Fig. 7A and Figure 7B is a partial layout diagram of at least one embodiment of a transistor included in a display substrate;

[0048] Figure 7C is a layout diagram of a related display substrate;

[0049] Fig.7D yes Figure 7C B-B' cross section diagram;

[0050] Fig. 8A is a layout diagram of a display substrate according to at least one embodiment of the present invention;

[0051] Figure 8B yes Fig. 8A The waveform diagram of the data voltage provided by DL and the touch signal provided by TXL;

[0052] Fig. 9 is a layout diagram of a display substrate according to at least one embodiment of the present invention;

[0053] Fig.10 It is a layout diagram of a display substrate according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0056] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0057] The display substrate described in the embodiment of the present invention includes a base, a first metal pattern and a second metal pattern;

[0058] The first metal pattern and the second metal pattern are disposed on the substrate, and the first metal pattern and the second metal pattern are arranged in sequence along a direction away from the substrate;

[0059] The orthographic projection of the first metal pattern on the substrate at least partially overlaps with the orthographic projection of the second metal pattern on the substrate, and at the edge of the overlapping area of ​​the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate, the minimum distance between adjacent second metal patterns is greater than 2.5 μm;

[0060] The first metal pattern is formed on a first metal layer, and the second metal pattern is formed on a second metal layer.

[0061] Optionally, at the edge of the overlapping area of ​​the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate, the minimum distance between adjacent second metal patterns is greater than 2.5μm, for example, it may be equal to 2.6μm, 2.8μm, 3μm, 3.2μm, 3.4μm, 3.5μm, 3.6μm, 3.8μm, 4μm, 4.2μm, 4.4μm, 4.5μm, 4.6μm, 4.8μm or 5μm, but is not limited to this.

[0062] In the related art, high-specification display products are limited in wiring space by the frame, resulting in dense wiring arrangement. In the GOA (Gate Driver On Array, a gate driver circuit set on an array substrate) module set in the frame area, the transistor includes a gate, a first electrode, and a second electrode. The gate is formed on a gate metal layer, and the first electrode and the second electrode are formed on a source-drain metal layer. The orthographic projection of the gate of the transistor on the substrate partially overlaps with the orthographic projection of the first electrode of the transistor on the substrate, and the orthographic projection of the gate of the transistor on the substrate partially overlaps with the orthographic projection of the second electrode of the transistor on the substrate. At the overlapping steps of the gate of the transistor and the first and second electrodes of the transistor, a weak exposure area is prone to appear in the source-drain metal layer. In the AA (active display) area, when the spacing between adjacent signal lines formed on the gate metal layer is small, a weak exposure area will appear at the conductive pattern formed on the source-drain metal layer across the signal line, and the same-layer source-drain metal remain is prone to occur, resulting in signal short circuit and functional abnormality. Based on the above problems, in an embodiment of the present invention, at the edge of the overlapping area of ​​the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate, the minimum distance between adjacent second metal patterns is set to be greater than 2.5 μm, and the adjacent second metal patterns are set to be separated by a design, so as to improve product yield and ensure process margin.

[0063] In the related art, the long-strip screen project has a long in-plane gate metal trace, which leads to a large resistance of the trace formed in the gate metal layer and a high RC (resistance-capacitance) loading, which is prone to risks such as insufficient charging or increased power consumption. Usually, the thickness of the gate metal layer is set to be thicker during metal trace design, and the thickness of the gate metal layer is set to be greater than or equal to 5000 angstroms to reduce the resistance of the trace formed in the gate metal layer. For example, the gate metal layer may include a stacked Al (aluminum) layer and a Mo (molybdenum) layer, the thickness of the Al layer is 4000 angstroms, and the thickness of the Mo layer is 1000 angstroms. Alternatively, the gate metal layer may include a stacked MoNb (molybdenum-niobium) layer, a Cu (copper) layer and an MTD layer, the thickness of the MoNb layer is 200 angstroms, the thickness of the Cu layer is 6000 angstroms, and the thickness of the MTD layer is 150 angstroms.

[0064] In at least one embodiment of the present invention, at the edge of the overlapping area of ​​the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate, no conductive pattern is arranged between the first metal pattern and the second metal pattern.

[0065] Optionally, the first metal layer is a gate metal layer, and the second metal layer is a source / drain metal layer.

[0066] In at least one embodiment of the present invention, the thickness of the gate metal layer is greater than or equal to 5000 angstroms.

[0067] In at least one embodiment of the present invention, the display substrate includes a transistor;

[0068] The first metal pattern is a gate pattern of the transistor, and the second metal pattern includes a first electrode portion and a second electrode portion; the first electrode portion includes a first lead and a first electrode of the transistor, and the second electrode portion includes a second lead and a second electrode of the transistor; the first lead is electrically connected to the first electrode of the transistor, and the second lead is electrically connected to the second electrode of the transistor;

[0069] The orthographic projection of the gate pattern on the substrate has a plurality of side edges;

[0070] The orthographic projection of the first electrode portion on the substrate overlaps with the first side portion of the orthographic projection of the gate pattern on the substrate, and the orthographic projection of the second electrode portion on the substrate overlaps with the second side portion of the orthographic projection of the gate pattern on the substrate; the first side and the second side are different sides, so that the edge of the overlapping portion of the first electrode portion and the gate pattern is far away from the edge of the overlapping portion of the second electrode portion and the gate pattern, thereby preventing a short circuit between the first electrode portion and the second electrode portion.

[0071] Optionally, the channel of the transistor is a U-shaped channel or an I-shaped channel;

[0072] The first lead wire is electrically connected to an end of the first electrode, and the second lead wire is electrically connected to an end of the second electrode; or,

[0073] The first lead wire is electrically connected to a middle portion of the first electrode, and the second lead wire is electrically connected to a middle portion of the second electrode.

[0074] Optionally, the channel of the transistor is a U-shaped channel or an I-shaped channel;

[0075] The first lead wire is electrically connected to the middle portion of the first electrode, and the second lead wire is electrically connected to the end portion of the second electrode; or,

[0076] The first lead wire is electrically connected to an end portion of the first electrode, and the second lead wire is electrically connected to a middle portion of the second electrode.

[0077] like Figure 1 As shown, at least one embodiment of the driving circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17 and a first capacitor C1;

[0078] The gate of M1 is electrically connected to the input terminal INPUT, the first electrode of M1 is electrically connected to the first voltage terminal VDS, and the second electrode of M1 is electrically connected to the first node PU;

[0079] The gate of M2 is electrically connected to the reset terminal RST, the first electrode of M2 is electrically connected to the first node PU, and the second electrode of M2 is electrically connected to the second voltage terminal VSD;

[0080] The gate of M3 is electrically connected to the first node PU, the first electrode of M3 is electrically connected to the clock signal terminal CLK, and the second electrode of M3 is electrically connected to the driving output terminal OT;

[0081] The gate of M4 is electrically connected to the frame reset terminal STV0, the first electrode of M4 is electrically connected to the first node PU, and the second electrode of M4 is electrically connected to the low voltage terminal VGL;

[0082] The gate of M5 is electrically connected to the frame reset terminal STV0, the first electrode of M5 is electrically connected to the driving output terminal OT, and the second electrode of M5 is electrically connected to the low voltage terminal VGL;

[0083] The gate of M6 and the first electrode of M6 are electrically connected to the first control voltage terminal VDDO, and the second electrode of M6 is electrically connected to the first electrode of M7;

[0084] The gate electrode of M7 is electrically connected to the first node PU, and the second electrode of M7 is electrically connected to the low voltage terminal VGL;

[0085] The gate of M8 is electrically connected to the second electrode of M6, the first electrode of M8 is electrically connected to the first control voltage terminal VDDO, and the second electrode of M8 is electrically connected to the first pull-down node PD1;

[0086] The gate of M9 is electrically connected to the first node PU, the first electrode of M9 is electrically connected to the first pull-down node PD1, and the second electrode of M9 is electrically connected to the low voltage terminal VGL;

[0087] The gate of M10 and the first electrode of M10 are electrically connected to the second control voltage terminal VDDE, and the second electrode of M10 is electrically connected to the first electrode of M11;

[0088] The gate electrode of M11 is electrically connected to the first node PU, and the second electrode of M11 is electrically connected to the low voltage terminal VGL;

[0089] The gate of M12 is electrically connected to the second electrode of M10, the first electrode of M12 is electrically connected to the second control voltage terminal VDDE, and the second electrode of M12 is electrically connected to the second pull-down node PD2;

[0090] The gate of M13 is electrically connected to the first node PU, the first electrode of M13 is electrically connected to the second pull-down node PD2, and the second electrode of M13 is electrically connected to the low voltage terminal VGL;

[0091] The gate of M14 is electrically connected to the first pull-down node PD1, the first electrode of M14 is electrically connected to the first node PU, and the second electrode of M14 is electrically connected to the low voltage terminal VGL;

[0092] The gate of M15 is electrically connected to the second pull-down node PD2, the first electrode of M15 is electrically connected to the first node PU, and the second electrode of M15 is electrically connected to the low voltage terminal VGL;

[0093] The gate of M16 is electrically connected to the first pull-down node PD1, the first electrode of M16 is electrically connected to the driving output terminal OT, and the second electrode of M16 is electrically connected to the low voltage terminal VGL;

[0094] The gate of M17 is electrically connected to the second pull-down node PD2, the first electrode of M17 is electrically connected to the driving output terminal OT, and the second electrode of M17 is electrically connected to the low voltage terminal VGL;

[0095] A first end of C1 is electrically connected to the first node PU, and a second end of C1 is electrically connected to the driving output terminal OT.

[0096] exist Figure 1 In at least one embodiment of the driving circuit shown, M1 charges PU, the gate is connected to the input signal, the first electrode of M1 is connected to the first voltage signal, and the second electrode of M1 is electrically connected to the first node PU.

[0097] Figure 2A yes Figure 1 FIG. 1 is a timing diagram of the operation of at least one embodiment of the driving circuit shown.

[0098] In the related art, a partial layout diagram of the first transistor M1 is shown in FIG. Figure 2B As shown;

[0099] In 2B, G1 is the gate electrode of M1, S1 is the first electrode of M1, and D1 is the second electrode of M1.

[0100] Figure 2C yes Figure 2B A-A' cross-section diagram.

[0101] exist Figure 2C In the figure, reference numeral 21 is a gate insulating layer, reference numeral 22 is a source / drain metal layer, reference numeral 23 is a first passivation layer, reference numeral 24 is an organic layer, and reference numeral 25 is a second passivation layer;

[0102] exist Figure 2B , Figure 2C In the figure, at the A-A' position, the climbing height of the source and drain metal pattern is 6350 angstroms. Here, the distance between S1 and D1 is 2.5μm. The step position of the gate metal layer under the source and drain metal pattern is very likely to become a weak exposure area, which is prone to the same-layer source and drain metal routing Remain and signal short circuit.

[0103] Figure 3A and Figure 3C In at least one embodiment of the present invention, a partial layout diagram of M1 (in Figure 3A and Figure 3C , a pattern formed on a gate metal layer and a pattern formed on a source / drain metal layer, including M1, are shown).

[0104] exist Figure 3AIn the figure, G1 is the gate of M1, S1 is the first electrode of M1, D1 is the second electrode of M1, L1 is the first lead, and L2 is the second lead; G1 is formed in the gate metal layer, S1, L1, D1 and L2 are all formed in the source-drain metal layer, and the gate metal layer is arranged between the substrate 30 and the source-drain metal layer; G1 is arranged between S1 and the substrate 30, and G1 is arranged between D1 and the substrate 30;

[0105] The first electrode portion includes the first electrode S1 and the first lead wire L1 of M1, and the second electrode portion includes the second electrode D1 and the second lead wire L2 of M1;

[0106] S1 is electrically connected to L1, and D1 is electrically connected to L2;

[0107] In the dotted box, by pulling apart the pattern formed on the source-drain metal layer, at the edge of the overlapping area of ​​the orthographic projection of the gate metal pattern on the substrate 30 and the orthographic projection of the source-drain metal pattern on the substrate 30, the minimum distance between L1 and L2 is 5 μm;

[0108] The gate metal pattern includes a gate G1 of M1 , and the source-drain metal pattern includes a first electrode S1 of M1 , a second electrode D1 of M1 , a first lead line L1 , and a second lead line L2 .

[0109] Figure 3B yes Figure 3A The layout diagram of the gate G1 of M1 in Figure 3A In the embodiment, the gate G1 of M1 is disposed between the first electrode portion and the substrate 30 .

[0110] Figure 4A and Figure 4C In at least one embodiment of the present invention, a partial layout diagram of M1 (in Figure 4A and Figure 4C , a pattern formed on a gate metal layer and a pattern formed on a source / drain metal layer, including M1, are shown).

[0111] exist Figure 4A In the figure, G1 is the gate of M1, S1 is the first electrode of M1, D1 is the second electrode of M1, L1 is the first lead, and L2 is the second lead; G1 is formed in the gate metal layer, S1, L1, D1 and L2 are all formed in the source-drain metal layer, and the gate metal layer is arranged between the substrate 30 and the source-drain metal layer; G1 is arranged between S1 and the substrate 30, and G1 is arranged between D1 and the substrate 30;

[0112] The first electrode portion includes the first electrode S1 and the first lead wire L1 of M1, and the second electrode portion includes the second electrode D1 and the second lead wire L2 of M1;

[0113] L1 is electrically connected to S1, and D1 is electrically connected to L2;

[0114] In the dotted box, by pulling apart the pattern formed on the source-drain metal layer, at the edge of the overlapping area of ​​the orthographic projection of the gate metal pattern on the substrate 30 and the orthographic projection of the source-drain metal pattern on the substrate 30, the minimum distance between L1 and L2 is 5 μm;

[0115] The gate metal pattern includes a gate G1 of M1 , and the source-drain metal pattern includes a first electrode S1 of M1 , a second electrode D1 of M1 , a first lead line L1 , and a second lead line L2 .

[0116] Figure 4B yes Figure 4A The layout diagram of the gate G1 of M1 in Figure 4A In the embodiment, the gate G1 of M1 is disposed between the first electrode portion and the substrate 30 .

[0117] exist Figure 3A In at least one embodiment shown, the first lead line L1 electrically connected to the first electrode S1 of the first transistor M1 is changed to a step down from the lower side of the gate of M1 (the step is a step caused by the gate of M1), so that at the step, the shortest distance between the first lead line L1 and the second lead line L1 is changed from 2.5 μm to 5 μm;

[0118] exist Figure 4A In at least one embodiment shown, the first lead line L1 electrically connected to the first electrode S1 of the first transistor M1 is changed to a step down from the upper side of the gate of M1 (the step is a step caused by the gate of M1), so that at the step, the shortest distance between the first lead line L1 and the second lead line L1 is changed from 2.5 μm to 5 μm;

[0119] Through the above arrangement, it is possible to effectively avoid the metal wiring on the same layer being too close to each other at the step of the lower gate metal layer, resulting in weak exposure areas, and the defective rate can be reduced to 0%, which can greatly improve the profitability of the product.

[0120] In at least one embodiment of the present invention, there are no restrictions on the position of the step of the lower gate metal layer, the specific opening position and opening angle of the source and drain metal layer opening design, and other details, as long as the spacing between metal traces on the same layer can be opened.

[0121] In at least one embodiment of the present invention, the position where the orthographic projection of the first electrode portion on the substrate overlaps with the first side portion is located at an end of the first side close to the second side, and the first side is adjacent to the second side.

[0122] like Figure 4AAs shown, the orthographic projection of the first lead wire L1 on the substrate overlaps with an end of the upper side edge of the orthographic projection of the gate G1 of M1 on the substrate close to the right side edge; the orthographic projection of the second lead wire L2 on the substrate overlaps with the right side edge of the orthographic projection of the gate G1 of M1 on the substrate at least partially;

[0123] The upper side edge of the orthographic projection of G1 on the base is adjacent to the right side edge of the orthographic projection of G1 on the base.

[0124] In at least one embodiment of the present invention, the position where the orthographic projection of the first electrode portion on the substrate overlaps with the first side portion is located at the first end of the first side, the first side is adjacent to the second side, and the extension direction of the first lead wire is the same as the extension direction of the second lead wire;

[0125] The first end of the first side is an end of the first side electrically connected to the second side.

[0126] like Figure 3A As shown, the orthographic projection of the first lead line L1 on the substrate at least partially overlaps with the left end portion of the lower side of the orthographic projection of the gate G1 of M1 on the substrate;

[0127] The orthographic projection of the second lead line L2 on the substrate at least partially overlaps with the left side of the orthographic projection of the gate G1 of M1 on the substrate;

[0128] The lower side edge of the orthographic projection of G1 on the base is adjacent to the left side edge of the orthographic projection of G1 on the base.

[0129] In at least one embodiment of the present invention, the first electrode portion includes a first portion, a second portion, and a third portion that are electrically connected to each other; an orthographic projection of the first portion on the substrate is included within an orthographic projection of the gate pattern on the substrate;

[0130] The orthographic projection of the second portion on the substrate overlaps with the first side portion; and / or, the orthographic projection of the second portion on the substrate overlaps with the first end of the second side; the first end of the second side is the end of the second side electrically connected to the first side;

[0131] The orthographic projection of the third portion on the substrate does not overlap with the orthographic projection of the gate pattern on the substrate;

[0132] The third portion extends in a direction away from the second side edge;

[0133] The width of the second portion is greater than the width of the first portion.

[0134] In a specific implementation, the first electrode portion may include an integrally formed first portion, a second portion, and a third portion, the orthographic projection of the first portion on the substrate being included in the orthographic projection of the gate pattern on the substrate, the second portion being a portion overlapping with a side of the gate pattern, the orthographic projection of the third portion on the substrate not overlapping with the orthographic projection of the gate pattern on the substrate, the width of the second portion may be set to be greater than the width of the first portion so that the second portion will not break when climbing a slope, and the extension direction of the third portion is away from the second side so that the source-drain metal pattern is set apart.

[0135] like Figure 3A-3C As shown, the first electrode portion S1 includes a first portion B1, a second portion B2 and a third portion B3 formed integrally;

[0136] The orthographic projection of the first part B1 on the base is inside the orthographic projection of G1 on the base;

[0137] The orthographic projection of the second portion B2 on the base overlaps at least partially with the side edge of the orthographic projection of G1 on the base;

[0138] The orthographic projection of the third part B3 on the base does not overlap with the orthographic projection of G1 on the base;

[0139] The orthographic projection of B2 on the base overlaps with the lower side of the orthographic projection of G1 on the base, and the orthographic projection of B2 on the base overlaps with the lower end of the left side of the orthographic projection of G1 on the base;

[0140] The width of B2 is greater than that of B1 , and the extending direction of B3 is away from the left side of the orthographic projection of G1 on the substrate.

[0141] like Figure 4A-4C As shown, the first electrode portion S1 includes a first portion B1, a second portion B2 and a third portion B3 formed integrally;

[0142] The orthographic projection of the first part B1 on the base is inside the orthographic projection of G1 on the base;

[0143] The orthographic projection of the second portion B2 on the base overlaps at least partially with the side edge of the orthographic projection of G1 on the base;

[0144] The orthographic projection of the third part B3 on the base does not overlap with the orthographic projection of G1 on the base;

[0145] The orthographic projection of B2 on the base overlaps with the upper side of the orthographic projection of G1 on the base, and the orthographic projection of B2 on the base overlaps with the upper end of the right side of the orthographic projection of G1 on the base;

[0146] The width of B2 is greater than that of B1 , and the extending direction of B3 is away from the right side of the orthographic projection of G1 on the substrate.

[0147] Figure 5 is a partial layout diagram of at least one embodiment of a transistor included in a display substrate (in Figure 5 , a transistor includes a pattern formed on a gate metal layer and a pattern formed on a source / drain metal layer).

[0148] exist Figure 5 In the figure, the gate pattern of the transistor is labeled G0, the first electrode of the transistor is labeled S0, and the second electrode of the transistor is labeled D0; the first lead is labeled L1, and the second lead is labeled L2;

[0149] L1 is electrically connected to S0, and L2 is electrically connected to D0;

[0150] The gate pattern G0 of the transistor has a plurality of sides;

[0151] The orthographic projection of the first lead line L1 on the substrate overlaps with the orthographic projection of the right side of G0 on the substrate, and the orthographic projection of the second lead line L2 on the substrate overlaps with the orthographic projection of the lower side of G0 on the substrate;

[0152] The channel of the transistor is a U-shaped channel;

[0153] The first lead wire L1 is electrically connected to an end of S0 , and the second lead wire L2 is electrically connected to an end of D0 .

[0154] In at least one embodiment of the present invention, the gate pattern may be formed in a gate metal layer, the first electrode and the second electrode may be formed in a source-drain metal layer, and the gate metal layer may be disposed between the substrate and the source-drain metal layer.

[0155] Figure 6 is a partial layout diagram of at least one embodiment of a transistor included in a display substrate (in Figure 6 , a transistor includes a pattern formed on a gate metal layer and a pattern formed on a source / drain metal layer).

[0156] exist Figure 6 In the figure, the gate pattern of the transistor is labeled G0, the first electrode of the transistor is labeled S0, and the second electrode of the transistor is labeled D0; the first lead is labeled L1, and the second lead is labeled L2;

[0157] L1 is electrically connected to S0, and L2 is electrically connected to D0;

[0158] The gate pattern G0 of the transistor has a plurality of sides;

[0159] The orthographic projection of the first lead line L1 on the substrate overlaps with the orthographic projection of the right side of G0 on the substrate, and the orthographic projection of the second lead line L2 on the substrate overlaps with the orthographic projection of the lower side of G0 on the substrate;

[0160] The channel of the transistor is a U-shaped channel;

[0161] The first lead wire L1 is electrically connected to the middle portion of S0 , and the second lead wire L2 is electrically connected to the end portion of D0 .

[0162] Fig. 7A and Figure 7B is a partial layout diagram of at least one embodiment of a transistor included in a display substrate (in Fig. 7A and Figure 7B , a transistor includes a pattern formed on a gate metal layer and a pattern formed on a source / drain metal layer).

[0163] exist Fig. 7A In the figure, the gate pattern of the transistor is labeled G0, the first electrode portion is labeled SX0, and the second electrode portion is labeled DX0;

[0164] like Figure 7B As shown, the first electrode portion includes the first electrode S0 of the transistor and a first lead wire L1 electrically connected thereto, and the second electrode portion includes the second electrode D0 of the transistor and a second lead wire L2 electrically connected thereto;

[0165] like Fig. 7A , Figure 7B As shown, the gate pattern G0 of the transistor has multiple sides;

[0166] The orthographic projection of the first lead line L1 on the substrate overlaps with the orthographic projection of the right side of G0 on the substrate, and the orthographic projection of the second lead line L2 on the substrate overlaps with the orthographic projection of the upper side of G0 on the substrate;

[0167] The channel of the transistor is an I-type channel.

[0168] In the relevant display substrate, such as Figure 7C As shown, the line labeled LM1 is the first virtual drive circuit load line, the line labeled LM2 is the second virtual drive circuit load line, and the line labeled LM3 is the third virtual drive circuit load line;

[0169] The line labeled DL is the data line, and the line labeled TXL is the touch signal line;

[0170] Fig.7D yes Figure 7C B-B' cross section diagram.

[0171] exist Fig.7D In the figure, the number 21 is a gate insulating layer, the number 22 is a source-drain metal layer, and the number 23 is a first passivation layer.

[0172] like Figure 7C , Fig.7D As shown, in the groove between two adjacent virtual drive circuit load lines, such as the BB' section, DL and TXL are adjacent source-drain metal wirings, and the presence of the weak exposure area will cause the adjacent data voltage signals and touch voltage signals to be short-circuited.

[0173] exist Figure 7C , Fig.7D In the related display substrate shown, the gate metal layer may include a first Al layer and a Mo layer stacked together, the thickness of the first Al layer is 2800 angstroms, and the thickness of the Mo layer is 600 angstroms; the source and drain metal layer may include a first Mo layer, a second Al layer, and a second Mo layer stacked together, the thickness of the first Mo layer is 150 angstroms, the thickness of the second Al layer is 3000 angstroms, and the thickness of the second Mo layer is 300 angstroms.

[0174] In at least one embodiment of the present invention, the first metal pattern includes a plurality of first signal lines; the second metal pattern includes a plurality of second signal lines;

[0175] The first signal line extends along a first direction, the second signal line extends along a second direction, and the first direction intersects the second direction; the plurality of first signal lines are adjacent in the second direction, and the plurality of second signal lines are adjacent in the first direction;

[0176] The orthographic projection of the first signal line on the substrate overlaps with the orthographic projection of the second signal line on the substrate;

[0177] In a region between two adjacent first signal lines, a shortest distance between adjacent second signal lines is greater than 2.5 μm.

[0178] In a specific implementation, when the distance between two adjacent first signal lines is relatively close, the shortest distance between two adjacent second signal lines can be set to be greater than 2.5 μm in the area between the two adjacent first signal lines to prevent short circuit between the two adjacent second signal lines in the weak exposure area.

[0179] Optionally, the first direction may be a horizontal direction, and the second direction may be a vertical direction, or a direction intersecting the horizontal direction.

[0180] Optionally, in an overlapping area of ​​an orthographic projection of the first signal line on the substrate and an orthographic projection of the second signal line on the substrate, a shortest distance between adjacent second signal lines is greater than 2.5 μm.

[0181] In a specific implementation, in the overlapping area of ​​the orthographic projection of the first signal line and the orthographic projection of the second signal line on the substrate, the shortest distance between two adjacent second signal lines can be set to be greater than 2.5 μm to prevent short circuit between two adjacent second signal lines.

[0182] Optionally, the first signal line includes a virtual drive circuit load line, and the second signal line includes a data line and a touch signal line.

[0183] In at least one embodiment of the present invention, a distance between adjacent first signal lines is less than 6 μm.

[0184] In a specific implementation, a driving module is provided in the peripheral area, and the driving module is used to provide a driving signal for a pixel circuit provided in the display area;

[0185] A virtual driving circuit can be provided in the driving module, and the virtual driving circuit can be used to provide a reset signal for the last few driving circuits included in the driving module. In order to ensure process consistency, multiple virtual driving circuit load lines can be provided below the display area, and the driving output end of the virtual driving circuit can be electrically connected to the virtual driving circuit load line, but the virtual driving circuit load line is not electrically connected to the pixel circuit.

[0186] exist Fig. 8A , the line labeled LM1 is a first virtual drive circuit load line, the line labeled LM2 is a second virtual drive circuit load line, the line labeled LM3 is a third virtual drive circuit load line, and the line labeled LM4 is a fourth virtual drive circuit load line;

[0187] The line labeled DL is the data line, and the line labeled TXL is the touch signal line;

[0188] like Fig. 8A As shown, in the first area A1, the minimum distance between DL and TXL is greater than 2.5 μm;

[0189] The distance between LM1 and LM2 is less than 6 μm;

[0190] The distance between LM2 and LM3 is less than 6 μm;

[0191] The distance between LM3 and LM4 is less than 6 μm.

[0192] exist Fig. 8A In at least one embodiment shown, LM1, LM2, LM3 and LM4 are all formed in the gate metal layer, and DL and TXL are both formed in the source and drain metal layer.

[0193] exist Fig. 8AIn at least one embodiment shown, in the groove region between LM1 and LM2, the spacing between DL and TXL is 2.6 μm;

[0194] In the groove area between LM2 and LM3, the spacing between DL and TXL is 2.6 μm;

[0195] In the groove area between LM3 and LM4, the spacing between DL and TXL is 2.6 μm;

[0196] Between two adjacent virtual drive circuit load lines, the source-drain metal wiring is designed to be separated to prevent short circuits between adjacent source-drain metal wirings.

[0197] Figure 8B yes Fig. 8A Waveform diagram of the data voltage provided by DL and the touch signal provided by TXL.

[0198] exist Figure 8B In the figure, the time labeled F1 is the first frame time, the time labeled F2 is the second frame time, and the time labeled F0 is the blank time period.

[0199] Fig. 9 It is a layout diagram of a display substrate according to at least one embodiment of the present invention.

[0200] exist Fig. 9 In the figure, LM1 is a first virtual drive circuit load line, LM2 is a second virtual drive circuit load line, LM3 is a third virtual drive circuit load line, and LM4 is a fourth virtual drive circuit load line. LM1, LM2, LM3 and LM4 are all formed in the gate metal layer;

[0201] The line labeled DL1 is the first data line, the line labeled DL2 is the second data line, the line labeled DL3 is the third data line, and the line labeled TXL is the touch signal line;

[0202] In the region between LM1 and LM2, the distance between DL2 and TXL is greater than 2.5 μm;

[0203] In the region between LM2 and LM3, the distance between DL2 and TXL is greater than 2.5 μm;

[0204] In the region between LM3 and LM4, the distance between DL2 and TXL is greater than 2.5 μm;

[0205] The source and drain metal traces are separated to prevent short circuit between DL2 and TXL.

[0206] Fig.10 It is a layout diagram of a display substrate according to at least one embodiment of the present invention.

[0207] exist Fig.10 Among them, the one labeled LM1 is the first virtual drive circuit load line;

[0208] The first load line portion of the second virtual drive circuit load line is labeled LM21, the second load line portion of the second virtual drive circuit load line is labeled LM22, and the third load line portion of the second virtual drive circuit load line is labeled LM23;

[0209] The first load line portion of the third virtual drive circuit load line is labeled LM31, the second load line portion of the third virtual drive circuit load line is labeled LM32, and the third load line portion of the third virtual drive circuit load line is labeled LM33;

[0210] The line labeled LM3 is a third virtual driving circuit load line, the line labeled LM4 is a fourth virtual driving circuit load line, and LM1, LM2, LM3 and LM4 are all formed in the gate metal layer;

[0211] The line labeled DL is the data line; the line labeled TXL is the touch signal line;

[0212] DL1 is adjacent to TXL2;

[0213] In the region between LM1 and LM22, the distance between DL and TXL is greater than 2.5 μm;

[0214] In the area between LM22 and LM32, the distance between DL and TXL is greater than 2.5 μm;

[0215] In the area between LM32 and LM4, the distance between DL and TXL is greater than 2.5 μm;

[0216] The source and drain metal traces are separated to prevent short circuit between DL2 and TXL1.

[0217] The display device described in the embodiment of the present invention includes the above-mentioned display substrate.

[0218] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: comprising a substrate, a first metal pattern and a second metal pattern; The first metal pattern and the second metal pattern are disposed on the substrate, and the first metal pattern and the second metal pattern are arranged in sequence along a direction away from the substrate; The orthographic projection of the first metal pattern on the substrate at least partially overlaps with the orthographic projection of the second metal pattern on the substrate, and at the edge of the overlapping area of ​​the orthographic projection of the first metal pattern on the substrate and the orthographic projection of the second metal pattern on the substrate, the minimum distance between adjacent second metal patterns is greater than 2.5 μm; The first metal pattern is formed on a first metal layer, and the second metal pattern is formed on a second metal layer.

2. The display substrate according to claim 1, wherein: The first metal layer is a gate metal layer, and the second metal layer is a source / drain metal layer.

3. The display substrate according to claim 2, wherein: The thickness of the gate metal layer is greater than or equal to 5000 angstroms.

4. The display substrate according to claim 1, wherein: The display substrate includes a transistor; The first metal pattern is a gate pattern of the transistor, and the second metal pattern includes a first electrode portion and a second electrode portion; the first electrode portion includes a first lead and a first electrode of the transistor, and the second electrode portion includes a second lead and a second electrode of the transistor; The first lead is electrically connected to the first electrode of the transistor, and the second lead is electrically connected to the second electrode of the transistor; The orthographic projection of the gate pattern on the substrate has a plurality of side edges; The orthographic projection of the first electrode portion on the substrate overlaps with a first side portion of the orthographic projection of the gate pattern on the substrate, and the orthographic projection of the second electrode portion on the substrate overlaps with a second side portion of the orthographic projection of the gate pattern on the substrate; The first side edge and the second side edge are different sides.

5. The display substrate according to claim 4, wherein: The position where the orthographic projection of the first electrode portion on the substrate overlaps with the first side portion is located at an end of the first side close to the second side, and the first side is adjacent to the second side.

6. The display substrate according to claim 4, wherein: The orthographic projection of the first electrode portion on the substrate overlaps with the first side portion and is located at a first end of the first side, the first side is adjacent to the second side, and an extension direction of the first lead wire is the same as an extension direction of the second lead wire; The first end of the first side is an end of the first side electrically connected to the second side.

7. The display substrate according to claim 4, wherein: The first electrode portion includes a first portion, a second portion and a third portion that are electrically connected to each other; an orthographic projection of the first portion on the substrate is included within an orthographic projection of the gate pattern on the substrate; The orthographic projection of the second portion on the substrate overlaps with the first side portion; And / or, the orthographic projection of the second portion on the substrate overlaps with the first end of the second side; the first end of the second side is the end of the second side electrically connected to the first side; The orthographic projection of the third portion on the substrate does not overlap with the orthographic projection of the gate pattern on the substrate; The third portion extends in a direction away from the second side edge; The width of the second portion is greater than the width of the first portion.

8. The display substrate according to claim 4, wherein: The channel of the transistor is a U-shaped channel or an I-shaped channel; The first lead wire is electrically connected to an end of the first electrode, and the second lead wire is electrically connected to an end of the second electrode; or, The first lead wire is electrically connected to a middle portion of the first electrode, and the second lead wire is electrically connected to a middle portion of the second electrode.

9. The display substrate according to claim 4, wherein: The channel of the transistor is a U-shaped channel or an I-shaped channel; The first lead wire is electrically connected to the middle portion of the first electrode, and the second lead wire is electrically connected to the end portion of the second electrode; or, The first lead wire is electrically connected to an end portion of the first electrode, and the second lead wire is electrically connected to a middle portion of the second electrode.

10. The display substrate according to any one of claims 1 to 3, characterized in that: The first metal pattern includes a plurality of first signal lines; the second metal pattern includes a plurality of second signal lines; The first signal line extends along a first direction, the second signal line extends along a second direction, and the first direction intersects the second direction; The plurality of first signal lines are adjacent in the second direction, and the plurality of second signal lines are adjacent in the first direction; The orthographic projection of the first signal line on the substrate overlaps with the orthographic projection of the second signal line on the substrate; In a region between two adjacent first signal lines, a shortest distance between adjacent second signal lines is greater than 2.5 μm.

11. The display substrate according to claim 10, wherein: In an overlapping area of ​​an orthographic projection of the first signal line on the substrate and an orthographic projection of the second signal line on the substrate, a shortest distance between adjacent second signal lines is greater than 2.5 μm.

12. The display substrate according to claim 10 or 11, characterized in that: The first signal line includes a virtual driving circuit load line, and the second signal line includes a data line and a touch signal line.

13. The display substrate according to claim 10, wherein: The distance between adjacent first signal lines is less than 6 μm.

14. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 13.

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