Multilayer ceramic capacitor

Abstract

Provided is an LW inversion type multilayer ceramic capacitor capable of suppressing deterioration of a self-alignment effect and performing stable mounting. A multilayer ceramic capacitor (1) is at wgt, where l is the length in the longitudinal direction connecting a first end surface (LS1) and a second end surface (LS2) of a multilayer body (10), w is the length in the width direction connecting a first side surface (WS1) and a second side surface (WS2), and t is the length in the height direction connecting a first main surface (TS1) and a second main surface (TS2); lgt; the dimensions of a fourth surface portion (40A4) and a fifth surface portion (40A5) of the first external electrode (40A) in the longitudinal direction (L) are larger than the dimensions of a second surface portion (40A2) and a third surface portion (40A2) of the first external electrode (40A) in the longitudinal direction (L), and the dimensions of a ninth surface portion (40B4) and a tenth surface portion (40B5) of the second external electrode (40B) in the longitudinal direction (L) are larger than the dimensions of a seventh surface portion (40B2) and an eighth surface portion (40B3) of the second external electrode (40B) in the longitudinal direction (L).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, laminated ceramic capacitors are known. A typical laminated ceramic capacitor has a substantially rectangular parallelepiped laminate whose dimension in the length direction L is longer than that in the width direction W, and external electrodes are provided at both ends of the laminate in the length direction L. On the other hand, in order to reduce ESL, so-called LW inversion type laminated ceramic capacitors are also known in which the size relationship between the dimension in the length direction L and the dimension in the width direction W of the laminate is reversed (see Patent Documents 1 and 2).

[0003] Furthermore, in recent years, as the mounting density of substrates has increased, the mounting area of ​​multilayer ceramic capacitors has decreased. Therefore, the demand for multilayer ceramic capacitors mounted in the lower end of the substrate in the LSC (Land side Capacitor) type using the PoP (Package on Package) mounting method has increased. As such multilayer ceramic capacitors mounted in the LSC (Land side Capacitor) type, a multilayer ceramic capacitor with a reduced height and a thin thickness in the height direction is required.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-57753

[0007] Patent Document 2: Japanese Patent Application Publication No. 2020-61524 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] Patent document 2 discloses an LW inversion type stacked ceramic electronic component, wherein a recessed portion extending from the end edge toward the first face portion is provided at at least one end edge of the fourth face portion and the fifth face portion of the external electrode, and the two side portions of the recess in the third direction serve as a covering portion that covers the edges of the two faces in the second direction of the component body.

[0010] However, in the laminated ceramic electronic component disclosed in Patent Document 2, it is considered that the area and shape of the covering portion covering the edges of the two surfaces in the second direction of the component body are deviated due to the formation position and thickness deviation of the base conductor layer and the covering conductor layer arranged thereon. Here, when the LW inversion type laminated ceramic electronic component is mounted on the mounting substrate using solder, due to the left and right differences in the area and shape of the covering portion, the wetting method of the solder on the covering portion changes on each surface, and the tensile stress of the solder may be different. As a result, it is considered that the self-alignment effect is deteriorated. As a result, the laminated ceramic electronic component becomes easy to rotate or tilt, and the mounting performance may be reduced. In addition, the connection pads of the substrate on which the LW inversion type laminated ceramic electronic component is mounted are short in distance between the connection pads, so the self-alignment effect is deteriorated. When the laminated ceramic electronic component is rotated significantly, it will be installed as one external electrode across the connection pads with different polarities, which may cause a short circuit defect.

[0011] An object of the present invention is to provide an LW inversion type multilayer ceramic capacitor capable of suppressing deterioration of the self-alignment effect and performing stable mounting.

[0012] Technical solutions to solve problems

[0013] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having a first main surface and a second main surface opposite to each other in the height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having at least any one of a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, and a third face portion located on a portion of the second main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; and a second external electrode having a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, and a seventh face portion located on a portion of the second side surface. At least any one of the 8th face portion which is a portion of the second main surface, the 9th face portion which is a portion of the first side surface, and the 10th face portion which is a portion of the second side surface, wherein, when the length in the longitudinal direction connecting the first end surface and the second end surface of the stack is set to l, the length in the width direction connecting the first side surface and the second side surface is set to w, and the length in the height direction connecting the first main surface and the second main surface is set to t, the dimensions are in a w>l>t relationship, the dimensions of the 4th face portion and the 5th face portion of the first external electrode in the longitudinal direction are larger than the dimensions of the 2nd face portion and the 3rd face portion in the longitudinal direction, and the dimensions of the 9th face portion and the 10th face portion of the second external electrode in the longitudinal direction are larger than the dimensions of the 7th face portion and the 8th face portion in the longitudinal direction.

[0014] Effects of the Invention

[0015] According to the present invention, it is possible to provide an LW inversion type multilayer ceramic capacitor capable of suppressing deterioration of the self-alignment effect and performing stable mounting. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment.

[0017] Figure 2 Yes Figure 1 The illustrated multilayer ceramic capacitor is an arrow view when the first side surface is viewed along the direction of arrow II.

[0018] Figure 3 Yes Figure 1 The illustrated multilayer ceramic capacitor is an arrow view when the second side surface is viewed along the direction of arrow III.

[0019] Figure 4 Yes Figure 2 The illustrated multilayer ceramic capacitor is an arrow view when the first main surface side is viewed along the direction of arrow IV.

[0020] Figure 5 Yes Figure 2 The illustrated multilayer ceramic capacitor is an arrow view when the second main surface side is viewed along the direction of arrow V.

[0021] Figure 6 It is along Figure 4 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line VI-VI shown in FIG.

[0022] Figure 7 It is along Figure 6 A cross-sectional view taken along line VII-VII of the multilayer ceramic capacitor shown.

[0023] Fig. 8A It is along Figure 6 The cross-sectional view taken along line VIIIA-VIIIA of the multilayer ceramic capacitor shown is a view showing the first internal electrode layer.

[0024] Figure 8B It is along Figure 6 The cross-sectional view taken along line VIIIB-VIIIB of the multilayer ceramic capacitor shown shows the second internal electrode layer.

[0025] Fig. 9 It is along Figure 4 The cross-sectional view taken along line IX-IX of the multilayer ceramic capacitor shown is a view showing a first side surface of the multilayer body.

[0026] Fig. 10A yes Figure 6 The enlarged view of the XA portion in is a view showing the cross section of the first external electrode.

[0027] Fig. 10B yes Figure 6 The enlarged view of the XB portion in is a view showing the cross section of the second external electrode.

[0028] Fig.11A is a cross-sectional view showing a modified example of the layer structure of the external electrode of the multilayer ceramic capacitor of the above-mentioned embodiment, Fig. 10A The corresponding figure.

[0029] Fig. 11B is a cross-sectional view showing a modified example of the layer structure of the external electrode of the multilayer ceramic capacitor of the above-mentioned embodiment, Fig. 10B The corresponding figure.

[0030] Fig.12 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above-mentioned embodiment.

[0031] Fig.13 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above-mentioned embodiment.

[0032] Fig.14 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above-mentioned embodiment.

[0033] Fig.15 is a cross-sectional view showing a modified example of the arrangement position of the external electrodes of the multilayer ceramic capacitor according to the above embodiment, Figure 1 The corresponding figure.

[0034] Fig.16A is a perspective view of the appearance of the multilayer ceramic capacitor of Comparative Example 1, which is similar to Figure 1 The corresponding figure.

[0035] Fig. 16B is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the comparative example, Fig. 8A The corresponding figure.

[0036] Fig. 16C is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8B The corresponding figure.

[0037] Fig.17A is a perspective view of the appearance of the multilayer ceramic capacitor of Comparative Example 2. Figure 1 The corresponding figure.

[0038] Fig. 17B is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the comparative example, Fig. 8A The corresponding figure.

[0039] Fig. 17C is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8B The corresponding figure.

[0040] Fig.18A It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0041] Fig.18B It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0042] Fig.18C It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0043] Fig.18D It is a figure for demonstrating the evaluation method of the mountability in the experimental example. DETAILED DESCRIPTION

[0044] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 Yes Figure 1 The illustrated multilayer ceramic capacitor 1 is an arrow view when the first side surface WS1 is viewed along the direction of arrow II. Figure 3 Yes Figure 1 The illustrated multilayer ceramic capacitor 1 is an arrow view when the second side surface WS2 is viewed along the direction of arrow III. Figure 4 Yes Figure 2 The illustrated multilayer ceramic capacitor 1 is a view when the first main surface TS1 side is viewed along the direction of arrow IV. Figure 5 Yes Figure 2 The illustrated multilayer ceramic capacitor 1 is a view when the second main surface TS2 side is viewed along the direction of arrow V. Figure 6 It is along Figure 4 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VI-VI. Figure 7 It is along Figure 6 1 is a cross-sectional view taken along line VII-VII of the multilayer ceramic capacitor 1 shown. Fig. 8A It is along Figure 6 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VIIIA-VIIIA. Figure 8B It is along Figure 6 VIIIB-VIIIB line cross-sectional view of the multilayer ceramic capacitor 1 shown. Fig. 9 It is along Figure 4 The cross-sectional view taken along line IX-IX of the multilayer ceramic capacitor 1 shown is a view showing the first side surface WS1 of the multilayer body 10 . Fig. 10A yes Figure 6 The enlarged view of the XA portion in FIG. 1 is a view showing a cross section of the first external electrode 40A. Fig. 10B yes Figure 6 The enlarged view of the XB portion in FIG. 1 is a view showing a cross section of the second external electrode 40B.

[0045] The multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 .

[0046] exist Figures 1 to 9 , an XYZ orthogonal coordinate system is shown. The length direction L of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Y direction. The width direction W of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the X direction. The height direction T of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Z direction. Here, Figure 6 The section shown is also referred to as the LT section. Figure 7 The section shown is also referred to as the WT section. Fig. 8A as well as Figure 8B The section shown is also referred to as the LW section.

[0047] like Figure 1 to Figure 5 As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in a height direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction L perpendicular to the height direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction W perpendicular to the height direction T and the length direction L.

[0048] The laminate 10 has a substantially rectangular parallelepiped shape. Preferably, the corners and ridges of the laminate 10 are rounded. The corners are the portions where three faces of the laminate intersect, and the ridges are the portions where two faces of the laminate intersect. In addition, a portion or all of the surface constituting the laminate 10 may be formed with concavities and convexities.

[0049] like Figure 6 as well as Figure 7 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the height direction T so as to sandwich the inner layer portion 11 .

[0050] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes, in the height direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite to each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor. In addition, the inner layer portion 11 is also referred to as an effective layer portion.

[0051] The plurality of dielectric layers 20 are made of dielectric material. The dielectric material is, for example, a ceramic material. The dielectric material may also be, for example, BaTiO 3 、CaTiO 3 、SrTiO 3 or CaZrO 3 When these components are the main components, it is also possible to add subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc., whose content is less than that of the main components, depending on the desired properties of the laminate.

[0052] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 700 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers of the inner layer portion 11 and the number of dielectric layers of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0053] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layers 31 are arranged on the plurality of dielectric layers 20 and are led out to the first end surface LS1. The second internal electrode layers 32 are arranged on the plurality of dielectric layers 20 and are led out to the second end surface LS2. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the height direction T of the laminate 10 with the dielectric layers 20 interposed therebetween. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0054] like Fig. 8A As shown, the first internal electrode layer 31 includes a first opposing electrode portion 31A opposed to the second internal electrode layer 32, and a first lead portion 31B led out from the first opposing electrode portion 31A to the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2. The first opposing electrode portion 31A is located inside the stacked body 10. The first lead portion 31B is connected to the first opposing electrode portion 31A and is exposed at the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0055] Thus, the width of the first lead portion 31B of the first internal electrode layer 31 can be ensured, so the connection area between the first lead portion 31B and the first external electrode 40A becomes wider, thereby increasing the current path. As a result, the ESL can be reduced. In addition, the first lead portion 31B of the first internal electrode layer 31 is arranged on a part of the first side surface WS1 and the second side surface WS2 of the laminate 10, so that the distance between the first lead portion 31B and the second lead portion 32B of the second internal electrode layer 32 described later can be shortened, and the ESL can be further reduced.

[0056] like Figure 8B As shown, the second internal electrode layer 32 has a second opposing electrode portion 32A opposed to the first internal electrode layer 31, and a second lead portion 32B led out from the second opposing electrode portion 32A to the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. The second opposing electrode portion 32A is located inside the stacked body 10. The second lead portion 32B is connected to the second opposing electrode portion 32A and is exposed at the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0057] Thus, the width of the second lead portion 32B of the second internal electrode layer 32 can be ensured, so the connection area between the second lead portion 32B and the second external electrode 40B becomes wider, thereby increasing the current path. As a result, ESL can be reduced. In addition, the second lead portion 32B of the second internal electrode layer 32 is arranged on a part of the first side surface WS1 and the second side surface WS2 of the laminate 10, so that the distance between the second lead portion 32B and the first lead portion 31B of the first internal electrode layer 31 can be shortened, and ESL can be further reduced.

[0058] Fig. 9 It is along Figure 4 The cross-sectional view of the multilayer ceramic capacitor 1 taken along line IX-IX is a view showing the first side surface WS1 of the multilayer body 10. Fig. 8A as well as Figure 8B It is also shown in Fig. 9 The IX-IX line of the cross-sectional view is located. Fig. 9 As shown, on the first side surface WS1 of the laminated body 10 , the first lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second internal electrode layer 32 are exposed.

[0059] like Fig. 9 As shown, the dimensions of the length direction L of the plurality of first lead portions 31B arranged in the height direction T are all larger than the dimensions of the length direction L of the second surface portion 40A2 and the third surface portion 40A3 of the first external electrode 40A described later.

[0060] On the other hand, the same is true for the multiple second lead portions 32B of the second internal electrode layer 32 arranged in the height direction T. The dimensions of the multiple second lead portions 32B in the length direction L are larger than the dimensions of the later-described 7th face portion 40B2 and the 8th face portion 40B3 in the length direction L of the second external electrode 40B.

[0061] Although not shown in the figure, the first lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second internal electrode layer 32 are exposed on the second side surface WS2 side, similarly to the first side surface WS1 side. On the second side surface WS2 side, similarly to the first side surface WS1 side, the dimensions of the plurality of first lead portions 31B in the length direction L are all larger than the dimensions of the second face portion 40A2 and the third face portion 40A3 in the first external electrode 40A in the length direction L. Furthermore, the dimensions of the plurality of second lead portions 31B in the length direction L are all larger than the dimensions of the seventh face portion 40B2 and the eighth face portion 40B3 in the second external electrode 40B in the length direction L.

[0062] The length direction L of the portion of the first lead portion 31B and the second lead portion 32B exposed at a portion of the first side surface WS1 is preferably 30 μm or more and 230 μm or less. The length direction L of the portion of the first lead portion 31B and the second lead portion 32B exposed at a portion of the second side surface WS2 is preferably 30 μm or more and 230 μm or less. The sizes of the lead portions exposed at the side of the laminate 10 may be substantially equal.

[0063] Thus, the first external electrode 40A having the fourth surface 40A4 and the fifth surface 40A5 described later and the second external electrode 40B having the ninth surface 40B4 and the tenth surface 40B5 can be realized. Furthermore, the distance between the first lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second internal electrode layer 32 can be shortened, so the path through which the current flows can be shortened. Therefore, the ESL can be reduced.

[0064] In the present embodiment, the first counter electrode portion 31A and the second counter electrode portion 32A face each other via the dielectric layer 20 , thereby forming capacitance and exhibiting capacitor characteristics.

[0065] The shapes of the first counter electrode portion 31A and the second counter electrode portion 32A are not particularly limited, but are preferably rectangular shapes. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed to be inclined.

[0066] The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely. In the present embodiment, the shapes of the first lead-out portion 31B and the second lead-out portion 32B are substantially T-shaped with a portion of the corners of the rectangular shape removed.

[0067] The portion of the first lead portion 31B exposed at the first end surface LS1 has a larger dimension in the width direction W than the first opposing electrode portion 31A. The portion of the second lead portion 32B exposed at the second end surface LS2 has a larger dimension in the width direction W than the second opposing electrode portion 32A.

[0068] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0069] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm or more and 2.0 μm or less, for example. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 200 or less.

[0070] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the stacked body 10. The first main surface side outer layer portion 12 is a collection of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. That is, the first main surface side outer layer portion 12 is formed by a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 located closest to the first main surface TS1 among the plurality of internal electrode layers 30. The dielectric layer 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0071] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the stacked body 10. The second main surface side outer layer portion 13 is a collection of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. That is, the second main surface side outer layer portion 13 is formed by a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 located closest to the second main surface TS2 side among the plurality of internal electrode layers 30. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0072] As described above, the laminated body 10 includes the plurality of laminated dielectric layers 20 and the plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the laminated ceramic capacitor 1 includes the laminated body 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0073] The laminate 10 also includes an opposing electrode portion 11E. The opposing electrode portion 11E is a portion where the first opposing electrode portion 31A of the first internal electrode layer 31 and the second opposing electrode portion 32A of the second internal electrode layer 32 face each other. The opposing electrode portion 11E is configured as a part of the inner layer portion 11. Fig. 8A as well as Figure 8B , the range of the opposing electrode portion 11E in the width direction W and the length direction L is shown. In addition, the opposing electrode portion 11E is also referred to as a capacitor effective portion.

[0074] In addition, the stacked body 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 located on the first end face LS1 side, and a second end face side outer layer portion LG2 located on the second end face LS2 side. The first end face side outer layer portion LG1 is a portion including the dielectric layer 20 and the first lead portion 31B located between the opposing electrode portion 11E and the first end face LS1. That is, the first end face side outer layer portion LG1 is a collection of a plurality of pieces of portions on the first end face LS1 side of the dielectric layer 20 and a plurality of pieces of first lead portions 31B. The second end face side outer layer portion LG2 is a portion including the dielectric layer 20 and the second lead portion 32B located between the opposing electrode portion 11E and the second end face LS2. That is, the second end face side outer layer portion LG2 is a collection of a plurality of pieces of portions on the second end face LS2 side of the dielectric layer 20 and a plurality of pieces of second lead portions 32B. Figure 6 , Fig. 8A as well as Figure 8B , the range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L is shown. In addition, the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 are also referred to as L gaps or end gaps.

[0075] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 located on the first side WS1 side, and a second side outer layer portion WG2 located on the second side WS2 side. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. That is, the first side outer layer portion WG1 is a collection of portions of the dielectric layer 20 on the first side WS1 side of a plurality of sheets. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. That is, the second side outer layer portion WG2 is a collection of portions of the dielectric layer 20 on the second side WS2 side of a plurality of sheets. Figure 7 , Fig. 8A as well as Figure 8B , the range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W is shown. In addition, the first side outer layer portion WG1 and the second side outer layer portion WG2 are also referred to as W gaps or side gaps.

[0076] like Figures 6 to 8BAs shown in FIG. 1 , when the length of the length direction L connecting the first end face LS1 and the second end face LS2 of the stacked body 10 is set to l, the length of the width direction W connecting the first side face WS1 and the second side face WS2 is set to w, and the length of the height direction T connecting the first main face TS1 and the second main face TS2 is set to t, the relationship between these dimensions is w>l>t. As a result, the width of the lead portion in the end face of the internal electrode layer 30 can be widened. In addition, the distance between the first external electrode 40A and the second external electrode 40B can be shortened, so that the ESL of the stacked ceramic capacitor 1 can be reduced.

[0077] The length l of the length direction L connecting the first end face LS1 and the second end face LS2 of the stack 10 is preferably greater than 0.05mm and less than 0.7mm. In addition, the length w of the width direction W connecting the first side surface WS1 and the second side surface WS2 of the stack 10 is preferably greater than 0.15mm and less than 1.5mm. In addition, the length t of the height direction T connecting the first main surface TS1 and the second main surface TS2 of the stack 10 is preferably less than 150μm. Thus, high-density mounting can be achieved. In addition, the length t of the height direction T connecting the first main surface TS1 and the second main surface TS2 of the stack 10 is preferably less than 100μm, more preferably less than 50μm. Thus, higher-density mounting can be achieved.

[0078] In addition, each dimension of l, w, and t of the laminated body 10 was measured by the following method.

[0079] First, the w dimension of the laminated body 10 is measured. Specifically, the w dimension of the laminated body 10 is measured at the exact center of the laminated ceramic capacitor 1 in the longitudinal direction L, that is, at the position L / 2 of the laminated ceramic capacitor 1 using a micrometer.

[0080] Next, the l dimension and t dimension of the laminated body 10 are measured. First, the laminated ceramic capacitor 1 which is the same as the laminated ceramic capacitor 1 whose w dimension is measured is ground to the exact center position in the width direction W of the laminated ceramic capacitor 1, that is, it is ground to the W / 2 position of the laminated ceramic capacitor 1 so as to be parallel to the LT plane. Then, the LT cross section exposed by grinding is observed under a microscope. The l dimension of the laminated body 10 is measured under a microscope at the exact center position in the height direction T of the laminated body 10 in the LT cross section, that is, at the t / 2 position of the laminated body 10. The t dimension of the laminated body 10 is measured under a microscope at the exact center position in the length direction L of the laminated body 10 in the LT cross section, that is, at the l / 2 position of the laminated body 10.

[0081] The external electrode 40 includes a first external electrode 40A disposed on the first end surface LS1 side and a second external electrode 40B disposed on the second end surface LS2 side.

[0082] The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A of the present embodiment includes a first face portion 40A1 located on the first end surface LS1, a second face portion 40A2 located on a portion of the first main surface TS1, a third face portion 40A3 located on a portion of the second main surface TS2, a fourth face portion 40A4 located on a portion of the first side surface WS1, and a fifth face portion 40A5 located on a portion of the second side surface WS2. In addition, the first external electrode 40A preferably includes at least one of the second face portion 40A2 located on a portion of the first main surface TS1 and the third face portion 40A3 located on a portion of the second main surface TS2, the first face portion 40A1 located on the first end surface LS1, the fourth face portion 40A4 located on a portion of the first side surface WS1, and the fifth face portion 40A5 located on a portion of the second side surface WS2.

[0083] The first surface portion 40A1 is a portion that covers the entire first end surface LS1 and is connected to the first internal electrode layer 31. Any of the second surface portion 40A2 and the third surface portion 40A3 is a portion that is connected to a land of a mounting substrate.

[0084] The fourth surface portion 40A4 is a portion connected to the first lead portion 31B exposed on the first side surface WS1. Figure 2 , Figure 4 as well as Figure 5 As shown, the dimension L4 of the fourth face portion 40A4 in the longitudinal direction L is larger than the dimension L2 of the second face portion 40A2 in the longitudinal direction L. In addition, the dimension L4 of the fourth face portion 40A4 in the longitudinal direction L is larger than the dimension L3 of the third face portion 40A3 in the longitudinal direction L. That is, the longitudinal center side of the fourth face portion 40A4 protrudes toward the longitudinal center side compared to the end portion 40A2a of the second face portion 40A2, and protrudes toward the longitudinal center side compared to the end portion 40A3a of the third face portion 40A3.

[0085] The fifth surface portion 40A5 is a portion connected to the first lead portion 31B exposed on the second side surface WS2. Figure 3 to Figure 5 As shown, the dimension L5 of the fifth face portion 40A5 in the longitudinal direction L is larger than the dimension L2 of the second face portion 40A2 in the longitudinal direction L. In addition, the dimension L5 of the fifth face portion 40A5 in the longitudinal direction L is larger than the dimension L3 of the third face portion 40A3 in the longitudinal direction L. That is, the longitudinal center side of the fifth face portion 40A5 protrudes toward the longitudinal center side compared to the end portion 40A2a of the second face portion 40A2, and protrudes toward the longitudinal center side compared to the end portion 40A3a of the third face portion 40A3.

[0086] The dimension L4 of the fourth face 40A4 of the first external electrode 40A in the longitudinal direction L and the dimension L5 of the fifth face 40A5 in the longitudinal direction L are preferably greater than 110% and less than 245% relative to the dimension L2 of the second face 40A2 in the longitudinal direction L and the dimension L3 of the third face 40A3 in the longitudinal direction L.

[0087] The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B of the present embodiment has a sixth face portion 40B1 located on the second end surface LS2, a seventh face portion 40B2 located on a portion of the first main surface TS1, an eighth face portion 40B3 located on a portion of the second main surface TS2, a ninth face portion 40B4 located on a portion of the first side surface WS1, and a tenth face portion 40B5 located on a portion of the second side surface WS2. In addition, the second external electrode 40B preferably has at least any one of the seventh face portion 40B2 located on a portion of the first main surface TS1 and the eighth face portion 40B3 located on a portion of the second main surface TS2, the first external electrode 40A, the sixth face portion 40B1 located on the second end surface LS2, the ninth face portion 40B4 located on a portion of the first side surface WS1, and the tenth face portion 40B5 located on a portion of the second side surface WS2.

[0088] The sixth surface portion 40B1 is a portion that covers the entire second end surface LS2 and is connected to the second internal electrode layer 32. Either the seventh surface portion 40B2 or the eighth surface portion 40B3 is a portion that is connected to a land of the mounting substrate.

[0089] The ninth surface portion 40B4 is a portion connected to the second lead portion 32B exposed on the first side surface WS1. Figure 2 , Figure 4 as well as Figure 5 As shown, the dimension L9 of the 9th face portion 40B4 in the longitudinal direction L is larger than the dimension L7 of the 7th face portion 40B2 in the longitudinal direction L. In addition, the dimension L9 of the 9th face portion 40B4 in the longitudinal direction L is larger than the dimension L8 of the 8th face portion 40B3 in the longitudinal direction L. That is, the longitudinal center side of the 9th face portion 40B4 protrudes toward the longitudinal center side compared to the end portion 40B2a of the 7th face portion 40B2, and protrudes toward the longitudinal center side compared to the end portion 40B3a of the 8th face portion 40B3.

[0090] The tenth surface portion 40B5 is a portion connected to the second lead portion 32B exposed on the second side surface WS2. Figure 3 to Figure 5As shown, the dimension L10 of the length direction L of the tenth face portion 40B5 is larger than the dimension L7 of the length direction L of the seventh face portion 40B2. In addition, the dimension L10 of the length direction L of the tenth face portion 40B5 is larger than the dimension L8 of the length direction L of the eighth face portion 40B3. That is, the length direction center side of the tenth face portion 40B5 protrudes toward the length direction center side compared to the end portion 40B2a of the seventh face portion 40B2, and protrudes toward the length direction center side compared to the end portion 40B3a of the eighth face portion 40B3.

[0091] The dimension L9 of the 9th face 40B4 of the second external electrode 40B in the longitudinal direction L and the dimension L10 of the 10th face 40B5 in the longitudinal direction L are preferably 110% or more and 245% or less relative to the dimension L7 of the 7th face 40B2 and the dimension L8 of the 8th face 40B3 in the longitudinal direction L.

[0092] In addition, the dimensions of the length direction L of the second face 40A2 and the third face 40A3 of the first external electrode 40A serving as the faces on the main surface side and the seventh face 40B2 and the eighth face 40B3 of the second external electrode 40B, and the dimensions of the length direction L of the fourth face 40A4 and the fifth face 40A5 of the first external electrode 40A serving as the faces on the side surface side and the ninth face 40B4 and the tenth face 40B5 of the second external electrode 40B are measured by the following method.

[0093] The dimensions of the second face 40A2 and the seventh face 40B2 in the length direction L are measured by a microscope at a position 1 / 2 of the width direction W when observing from the first main surface TS1 of the stack 10. Similarly, the dimensions of the third face 40A3 and the eighth face 40B3 in the length direction L are measured by a microscope at a position 1 / 2 of the width direction W when observing from the second main surface TS2 of the stack 10.

[0094] The dimensions of the length direction L of the fourth face 40A4 and the ninth face 40B4 are measured by a microscope at a position 1 / 2 of the height direction T when observed from the first side WS1 of the stack 10. Similarly, the dimensions of the length direction L of the fifth face 40A5 and the tenth face 40B5 are measured by a microscope at a position 1 / 2 of the height direction T when observed from the second side WS2 of the stack 10.

[0095] Based on the dimensions of the face in the length direction L on the main surface side and the dimensions of the face in the length direction L on the side surface measured in this way, the ratio of the dimension of the face in the length direction L on the side surface side to the dimension of the face in the length direction L on the main surface side is calculated.

[0096] like Fig. 10AAs shown, the first external electrode 40A includes a first foundation electrode layer 50A and a first plating layer 60A disposed on the first foundation electrode layer 50A. The first foundation electrode layer 50A is disposed on the surface of the laminate 10. The first plating layer 60A is disposed to cover the first foundation electrode layer 50A.

[0097] like Fig. 10B As shown, the second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B disposed on the second foundation electrode layer 50B. The second foundation electrode layer 50B is disposed on the surface of the laminate 10. The second plating layer 60B is disposed to cover the second foundation electrode layer 50B.

[0098] The first foundation electrode layer 50A and the second foundation electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0099] In the present embodiment, the first foundation electrode layer 50A and the second foundation electrode layer 50B are thin film layers. The thin film layer is a layer where metal particles are deposited.

[0100] When the first foundation electrode layer 50A and the second foundation electrode layer 50B are formed by thin film layers, they are preferably formed by a thin film forming method such as sputtering or vapor deposition. Here, a sputtering electrode formed by sputtering will be described.

[0101] The first base electrode layer 50A of the present embodiment is composed of a first thin film layer 51A formed by a sputtering electrode. The second base electrode layer 50B is composed of a second thin film layer 51B formed by a sputtering electrode. When the base electrode layer is formed by a sputtering electrode, it is preferable to directly form the sputtering electrode on the first main surface TS1 and the second main surface TS2 of the stacked body 10.

[0102] like Figure 6 , Fig. 10A As shown in FIG. 1 , the first thin film layer 51A formed by the sputtered electrode is arranged on a portion of the first end face LS1 side on the first main surface TS1 and a portion of the first end face LS1 side on the second main surface TS2. Specifically, the first thin film layer 51A is preferably arranged on the first main surface TS1. Figure 4 The first thin film layer 51A is preferably arranged on the second main surface TS2 and is covered by the first external electrode 40A. Figure 5 The portion covered by the first external electrode 40A is shown.

[0103] Furthermore, if Fig. 9As shown, the first thin film layer 51A is preferably configured on a portion of the first main surface TS1 and is configured to be slightly surrounded from a portion of the first main surface TS1 to a portion of the first side surface WS1. The first thin film layer 51A is preferably configured on a portion of the second main surface TS2 and is configured to be slightly surrounded from a portion of the second main surface TS2 to a portion of the first side surface WS1.

[0104] In addition, although not shown in the figure, similarly to the first side surface WS1 side, on the second side surface WS2 side, the first thin film layer 51A is also preferably configured on a portion of the first main surface TS1 and is configured to be slightly surrounded from a portion on the first main surface TS1 to a portion of the second side surface WS2 continuously. In addition, the first thin film layer 51A is also preferably configured on a portion of the second main surface TS2 and is configured to be slightly surrounded from a portion on the second main surface TS2 to a portion of the second side surface WS2 continuously.

[0105] For example, when a chamfered portion such as a rounded corner is formed on the ridgeline portion of the stacked body 10, the first thin film layer 51A is preferably arranged on a portion of the first end face LS1 side of the first main surface TS1, and the chamfered portion of the first side face WS1 side continuous with the portion, and the chamfered portion of the second side face WS2 side. The first thin film layer 51A is preferably arranged on a portion of the first end face LS1 side of the second main surface TS2, and the chamfered portion of the first side face WS1 side continuous with the portion, and the chamfered portion of the second side face WS2 side. In this case, it is easy to form the thin film layer by sputtering or the like.

[0106] The longitudinal center side of the first lead portion 31B protrudes toward the longitudinal center side compared to the end portion on the longitudinal center side of the first thin film layer 51A arranged on the first main surface TS1 and the end portion on the longitudinal center side of the first thin film layer 51A arranged on the second main surface TS2. Similarly, the longitudinal center side of the second lead portion 32B protrudes toward the longitudinal center side compared to the end portion on the longitudinal center side of the second thin film layer 51B arranged on the first main surface TS1 and the end portion on the longitudinal center side of the second thin film layer 51B arranged on the second main surface TS2.

[0107] By the above method, when forming the plating layer, the distance between the first thin film layer 51A disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2 can be controlled. Therefore, the plating layer can also be easily deposited on the surface of the stacked body 10 between the first thin film layer 51A disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2.

[0108] like Figure 6 , Fig. 10B As shown in FIG. 1 , the second thin film layer 51B formed by the sputtered electrode is arranged on a portion of the first main surface TS1 on the second end surface LS2 side and a portion of the second main surface TS2 on the second end surface LS2 side. Specifically, the second thin film layer 51B is preferably arranged on the first main surface TS1 and on the second end surface LS2 side. Figure 4 The second thin film layer 51B is preferably arranged on the second main surface TS2 and is covered by the second external electrode 40B. Figure 5 The portion covered by the second external electrode 40B is shown.

[0109] Furthermore, if Fig. 9 As shown, the second thin film layer 51B is preferably configured on a portion of the first main surface TS1 and is configured to be slightly surrounded from a portion on the first main surface TS1 to a portion of the first side surface WS1. The second thin film layer 51B is preferably configured on a portion of the second main surface TS2 and is configured to be slightly surrounded from a portion on the second main surface TS2 to a portion of the first side surface WS1.

[0110] In addition, although not shown in the figure, similarly to the first side surface WS1 side, on the second side surface WS2 side, the second thin film layer 51B is also preferably configured on a portion of the first main surface TS1 and is configured to be slightly surrounded from a portion on the first main surface TS1 to a portion of the second side surface WS2 continuously. In addition, the second thin film layer 51B is also preferably configured on a portion of the second main surface TS2 and is configured to be slightly surrounded from a portion on the second main surface TS2 to a portion of the second side surface WS2 continuously.

[0111] For example, when a chamfered portion such as a rounded corner is formed on the ridgeline portion of the stacked body 10, the second thin film layer 51B is preferably arranged on a portion of the first main surface TS1 on the second end surface LS2 side, and the chamfered portion of the first side surface WS1 side and the chamfered portion of the second side surface WS2 side continuous with the portion. The second thin film layer 51B is preferably arranged on a portion of the second main surface TS2 on the second end surface LS2 side, and the chamfered portion of the first side surface WS1 side and the chamfered portion of the second side surface WS2 side continuous with the portion. In this case, it is easy to form the thin film layer by sputtering or the like.

[0112] By the above method, when forming the plating layer, the distance between the second thin film layer 51B arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2 can be controlled. Therefore, it is also easy to deposit the plating layer on the surface of the stacked body 10 between the second thin film layer 51B arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2.

[0113] The thin film layer formed by the sputtering electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo and V. This can improve the fixing force of the external electrode 40 to the stacked body 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure of a Ni-Cr alloy layer and a Ni-Cu alloy layer.

[0114] The thickness of the sputtering electrode in the lamination direction connecting the first main surface TS1 and the second main surface TS2 is preferably 50 nm to 400 nm, and more preferably 50 nm to 130 nm.

[0115] In the case where a sputtering electrode is directly formed on the first main surface TS1 and the second main surface TS2 of the stacked body 10 to configure a base electrode layer, it is preferred to form a base electrode layer of a sintered layer on the first end surface LS1 and the second end surface LS2, or to directly form a plating layer described later without forming a base electrode layer. In the present embodiment, a plating layer described later is directly formed on the first end surface LS1 and the second end surface LS2 without forming a base electrode layer.

[0116] In addition, as described later in the modification, the first base electrode layer 50A and the second base electrode layer 50B may also be sintered layers. The sintered layer preferably contains a metal component and either a glass component or a ceramic component, or both. The metal component, for example, contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component, for example, contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may use the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material from the dielectric layer 20. The ceramic component, for example, contains BaTiO 3 、CaTiO 3 、(Ba,Ca)TiO 3 、SrTiO 3 、CaZrO 3 etc. Select at least one.

[0117] The sintered layer is, for example, a sintered layer obtained by applying a conductive paste containing glass and metal to the stacked body 10 and sintering it. The sintered layer may be a sintered layer obtained by simultaneously sintering a stacked chip having an internal electrode layer and a dielectric layer and a conductive paste applied to the stacked chip, or a sintered layer obtained by sintering a stacked chip having an internal electrode layer and a dielectric layer, and then applying a conductive paste to the stacked body 10 and sintering it. In addition, when the stacked chip having an internal electrode layer and a dielectric layer and the conductive paste applied to the stacked chip are sintered simultaneously, the sintered layer is preferably formed by sintering a paste to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. The sintered layer may also be a multilayer.

[0118] Alternatively, a configuration may be adopted in which the first and second base electrode layers 50A and 50B are not provided, and the first and second plated layers 60A and 60B described below are directly disposed on the laminate 10 .

[0119] The first plating layer 60A is arranged to cover the first base electrode layer 50A.

[0120] The second plating layer 60B is arranged to cover the second base electrode layer 50B.

[0121] The first plating layer 60A and the second plating layer 60B may include at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of a plurality of layers.

[0122] When the base electrode layer is formed by a thin film layer, the plating layer is preferably formed by a three-layer structure of a Cu plating layer as a lower plating layer, a Ni plating layer as a middle plating layer, and a Sn plating layer as an upper plating layer. That is, the first plating layer 60A preferably has a first Cu plating layer 61A, a first Ni plating layer 62A, and a first Sn plating layer 63A. The second plating layer 60B preferably has a second Cu plating layer 61B, a second Ni plating layer 62B, and a second Sn plating layer 63B. However, the first plating layer 60A and the second plating layer 60B are not limited to a three-layer structure, and may also be other layer structures.

[0123] The first Cu plating layer 61A is configured to cover the first end surface LS1 of the stack 10 and the first thin film layer 51A as the first base electrode layer 50A configured on the first main surface TS1 and the second main surface TS2 of the stack 10. In the present embodiment, the first Cu plating layer 61A is configured to also cover the exposed portion of the internal electrode layer 30 in the first side surface WS1 and the second side surface WS2 of the stack 10. At this time, the gap between the first thin film layer 51A and the internal electrode layer 30 exposed on the surface of the stack 10 and the gaps between the plurality of internal electrode layers 30 exposed on the surface of the stack 10 are formed narrow, so the plating layer is also deposited in the region of these gaps.

[0124] The first Ni plating layer 62A is arranged to cover the first Cu plating layer 61A. The first Sn plating layer 63A is arranged to cover the first Ni plating layer 62A. In the present embodiment, the first plating layer 60A is directly electrically connected to the first internal electrode layer 31 .

[0125] The second Cu plating layer 61B is configured to cover the second end surface LS2 of the stack 10 and the second thin film layer 51B as the second base electrode layer 50B configured on the first main surface TS1 and the second main surface TS2 of the stack 10. In the present embodiment, the second Cu plating layer 61B is configured to also cover the exposed portion of the internal electrode layer 30 in the first side surface WS1 and the second side surface WS2 of the stack 10. At this time, the gap between the second thin film layer 51B and the internal electrode layer 30 exposed on the surface of the stack 10 and the gaps between the plurality of internal electrode layers 30 exposed on the surface of the stack 10 are formed narrow, so the plating layer is also deposited in the region of these gaps.

[0126] The second Ni plating layer 62B is arranged so as to cover the second Cu plating layer 61B. The second Sn plating layer 63B is arranged so as to cover the second Ni plating layer 62B. In the present embodiment, the second plating layer 60B is directly electrically connected to the second internal electrode layer 32 .

[0127] By providing the plated layer including the Cu plated layer and the Ni plated layer to cover the base electrode layer, the base electrode layer is prevented from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, by further providing the Sn plated layer on the surface of the Ni plated layer, the wettability of the solder when mounting the multilayer ceramic capacitor 1 is improved. Thus, the multilayer ceramic capacitor 1 can be easily mounted.

[0128] The thickness of each layer of the plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Cu plating layer 61A, the first Ni plating layer 62A, the first Sn plating layer 63A, the second Cu plating layer 61B, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Cu plating layer 61A and the second Cu plating layer 61B is more preferably 5 μm or more and 8 μm or less. In addition, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0129] In addition, if the dimension in the length direction of the first end surface LS1 and the second end surface LS2 of the multilayer ceramic capacitor 1 including the stack 10 and the external electrode 40 is set to L dimension, the L dimension is preferably 0.1 mm or more and 0.8 mm or less. In addition, if the dimension in the width direction of the first side surface WS1 and the second side surface WS2 of the multilayer ceramic capacitor 1 is set to W dimension, the W dimension is preferably 0.2 mm or more and 1.6 mm or less. In addition, if the dimension in the height direction of the first main surface TS1 and the second main surface TS2 of the multilayer ceramic capacitor 1 is set to T dimension, the T dimension is preferably 0.05 mm or more and 0.2 mm or less. The L dimension in the length direction of the multilayer ceramic capacitor 1 of the present embodiment is smaller than the W dimension in the width direction of the multilayer ceramic capacitor 1. In addition, in the present embodiment, the height direction of the first main surface TS1 and the second main surface TS2 of the multilayer ceramic capacitor 1 is the stacking direction of the dielectric layer 20 and the internal electrode layer 30.

[0130] As described above, in the multilayer ceramic capacitor 1 of the present embodiment, when the length in the length direction L connecting the first end surface LS1 and the second end surface LS2 of the multilayer body 10 is set to l, the length in the width direction W connecting the first side surface WS1 and the second side surface WS2 is set to w, and the length in the height direction T connecting the first main surface TS1 and the second main surface TS2 is set to t, the dimensional relationship is w>l>t. As a result, the width of the lead portion in the end surface of the internal electrode layer 30 can be widened. In addition, the distance between the first external electrode 40A and the second external electrode 40B can be shortened, so that the ESL of the multilayer ceramic capacitor 1 can be reduced.

[0131] Furthermore, in the multilayer ceramic capacitor 1 of the present embodiment, a dimension L4 of the fourth face 40A4 of the first external electrode 40A in the length direction L and a dimension L5 of the fifth face 40A5 in the length direction L are larger than a dimension L2 of the second face 40A2 and a dimension L3 of the third face 40A3 in the length direction L, and a dimension L9 of the ninth face 40B4 of the second external electrode 40B and a dimension L10 of the tenth face 40B5 in the length direction L are larger than a dimension L7 of the seventh face 40B2 and a dimension L8 of the eighth face 40B3 in the length direction L. Thus, when the first external electrode 40A and the second external electrode 40B are soldered to the connection pad and the multilayer ceramic capacitor 1 is mounted on the substrate, the solder can be sufficiently wetted and climbed even in the fourth face 40A4 and the fifth face 40A5 of the first external electrode 40A and the ninth face 40B4 and the tenth face 40B5 of the second external electrode 40B, where the amount of solder wetting and climbing is likely to decrease. Therefore, in each of the fourth face 40A4 and the fifth face 40A5 and the ninth face 40B4 and the tenth face 40B5 of the second external electrode 40B, the amount of solder can be suppressed, and the difference in tensile stress caused by the solder can be suppressed. Therefore, the deterioration of the self-alignment effect can be suppressed, and stable mounting can be performed. As a result, it is possible to suppress short circuit failure caused by tilting or rotating the multilayer ceramic capacitor 1. The so-called self-alignment effect is the effect that the surface area of ​​the molten solder is reduced by the surface tension during soldering, and the electronic component to be mounted supported by the molten solder is moved and positioned. Since the self-alignment effect can be obtained, it is possible to prevent position deviation during mounting.

[0132] As described above, the dimension L4 of the fourth face 40A4 of the first external electrode 40A in the longitudinal direction L and the dimension L5 of the fifth face 40A5 in the longitudinal direction L are preferably 110% or more and 245% or less relative to the dimension L2 of the second face 40A2 in the longitudinal direction L and the dimension L3 of the third face 40A3 in the longitudinal direction L. In addition, the dimension L9 of the ninth face 40B4 of the second external electrode 40B in the longitudinal direction L and the dimension L10 of the tenth face 40B5 in the longitudinal direction L are preferably 110% or more and 245% or less relative to the dimension L7 of the seventh face 40B2 in the longitudinal direction L and the dimension L8 of the eighth face 40B3 in the longitudinal direction L. When the above ratio becomes less than 110%, it becomes difficult to suppress the change in the amount of solder in each of the fourth face 40A4 and the fifth face 40A5 and the ninth face 40B4 and the tenth face 40B5 of the second external electrode 40B. As a result, it becomes difficult to suppress the difference in tensile stress caused by the solder, and the multilayer ceramic capacitor 1 may rotate during mounting. On the other hand, when the ratio is greater than 245%, the first external electrode 40A and the second external electrode 40B may be electrically connected to each other due to the amount of solder, thereby causing a short circuit. Therefore, the ratio is preferably 110% to 245%.

[0133] Hereinafter, a modification of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are used for the same structures as those in the above embodiment, and detailed description thereof will be omitted. Fig.11A as well as Fig. 11B is a cross-sectional view showing a modified example of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment, and is similar to Fig. 10A as well as Fig. 10B The corresponding figure.

[0134] In this modification, the structure of the external electrode 40 is different from that of the above-described embodiment.

[0135] The first external electrode 40A includes a first base electrode layer 50A and a first plated layer 60A. The first base electrode layer 50A of this modification example is composed of a first sintered layer 52A. The first plated layer 60A of this modification example includes a first Ni plated layer 62A and a first Sn plated layer 63A.

[0136] The second external electrode 40B includes a second base electrode layer 50B and a second plated layer 60B. The second base electrode layer 50B of this modification example is composed of a second sintered layer 52B. The second plated layer 60B of this modification example includes a second Ni plated layer 62B and a second Sn plated layer 63B.

[0137] In this modification, the first base electrode layer 50A has, for example, a first face portion located on the first end surface LS1, a second face portion located on a portion of the first main surface TS1, a third face portion located on a portion of the second main surface TS2, a fourth face portion located on a portion of the first side surface WS1, and a fifth face portion located on a portion of the second side surface WS2, similarly to the first external electrode 40A described above. In addition, in this modification, the first base electrode layer 50A is connected to the first internal electrode layer 31.

[0138] The first Ni plating layer 62A is disposed so as to cover the first base electrode layer 50A. The first Sn plating layer 63A is disposed so as to cover the first Ni plating layer 62A.

[0139] In this modification, the second base electrode layer 50B has, for example, a sixth face portion located on the second end surface LS2, a seventh face portion located on a portion of the first main surface TS1, an eighth face portion located on a portion of the second main surface TS2, a ninth face portion located on a portion of the first side surface WS1, and a tenth face portion located on a portion of the second side surface WS2, similarly to the second external electrode 40B described above. In addition, in this modification, the second base electrode layer 50B is connected to the second internal electrode layer 32.

[0140] The second Ni plating layer 62B is arranged to cover the second base electrode layer 50B. The second Sn plating layer 63B is arranged to cover the second Ni plating layer 62B.

[0141] The first sintered layer 52A constituting the first base electrode layer 50A and the second sintered layer 52B constituting the second base electrode layer 50B may be, for example, sintered layers obtained by applying a conductive paste containing glass and metal to the laminate and sintering it. In addition, when the laminated small pieces before sintering and the conductive paste applied to the laminated small pieces are sintered at the same time, the sintered layers are preferably formed by sintering a paste to which a ceramic material is added instead of a glass component. At this time, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20.

[0142] When the base electrode layer is formed of a sintered layer, the first plating layer 60A and the second plating layer 60B are preferably a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. In this case, the Ni plating layer prevents the base electrode layer from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. As a result, it becomes easy to mount the multilayer ceramic capacitor 1.

[0143] In addition, the first plating layer 60A and the second plating layer 60B are not limited to a two-layer structure, and may be formed of a three-layer structure including Cu plating as in the above-described embodiment, or may have other layer structures.

[0144] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0145] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described.

[0146] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The conductive paste for the dielectric sheet and the internal electrode contains a binder and a solvent. The binder and the solvent may be known binders and solvents. The paste containing the conductive material is, for example, a paste in which an organic binder and an organic solvent are added to metal powder.

[0147] On the dielectric sheet, a conductive paste for the internal electrode layer 30 is printed, for example, by screen printing, gravure printing, etc., using a printing plate whose pattern is designed to form the shape of the internal electrode layer 30 of the present embodiment. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 and a dielectric sheet having a pattern of the second internal electrode layer 32 are prepared.

[0148] By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed, a portion of the first main surface side outer layer portion 12 on the first main surface TS1 side is formed. By alternately stacking dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed, a portion of the inner layer portion 11 is formed. By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed on the portion that is to become the inner layer portion 11, a portion of the second main surface side outer layer portion 13 on the second main surface TS2 side is formed. In this way, a laminated sheet is produced.

[0149] The laminated sheets are pressed in the lamination direction by isostatic pressing or the like, thereby producing a laminated block.

[0150] The stacked blocks are cut into predetermined sizes to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0151] The stacked small pieces are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0152] In this embodiment, the base electrode layer is formed by a thin film layer. When the base electrode layer is formed by a thin film layer, the thin film layer is formed on a portion of the laminate 10 where an external electrode is to be formed by masking or the like. The thin film layer is formed by a thin film forming method such as sputtering or evaporation. In this embodiment, a sputtering electrode as a thin film layer is formed by sputtering.

[0153] Figure 12 to Figure 14 1 is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor of the present embodiment, and is a diagram showing a state after the thin film layer is arranged on the multilayer body 10 and before the plating layer is arranged. Fig.12 1 is a diagram showing a state in which a first thin film layer 51A and a second thin film layer 51B as thin film layers are arranged in a laminate 10, and is similar to Figure 6 The LT section corresponds to the figure. Fig.13 1 is a diagram showing a state in which a first thin film layer 51A as a thin film layer is arranged in the laminate 10, and is similar to Figure 7 The WT cross section corresponds to Fig. Fig.14 1 is a diagram showing a state where the first thin film layer 51A and the second thin film layer 51B are arranged in the laminate 10, and Fig. 9 The corresponding figure is a view of the surface of the first side surface WS1 of the stacked body 10 .

[0154] The first thin film layer 51A formed by the sputtering electrode is arranged on a portion of the first end face LS1 side on the first main surface TS1 and a portion of the first end face LS1 side on the second main surface TS2. The second thin film layer 51B formed by the sputtering electrode is arranged on a portion of the second end face LS2 side on the first main surface TS1 and a portion of the second end face LS2 side on the second main surface TS2.

[0155] In the present embodiment, the thin film layer formed by the sputtering electrode is arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2 and is arranged to slightly surround a portion of the first side surface WS1 and a portion of the second side surface WS2 continuously from a portion of the first main surface TS1 and a portion of the second main surface TS2. Thus, the distance between the thin film layer arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode film exposed on the first side surface WS1 and the second side surface WS2 can be controlled. Therefore, a plating layer can also be deposited on the surface of the stacked body 10 between the thin film layer arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2.

[0156] Then, a plating layer is formed on the surface of the base electrode layer including the thin film layer and the laminate. In this embodiment, a three-layer plating layer of a Cu plating layer, a Ni plating layer, and a Sn plating layer is formed as the plating layer.

[0157] When forming the plated layer, it is formed by electrolytic plating. As the plating method, barrel plating is preferably used.

[0158] Here, when the thin film layer is formed to also wrap around a portion on the first side WS1 and a portion on the second side WS2, it is possible to control the distance between the thin film layer and the internal electrode layer exposed on the first side WS1 and the second side WS2 of the stacked body 10. Therefore, it is also easy to deposit a plating layer on the surface of the stacked body 10 between the thin film layer arranged on a portion on the first side WS1 and a portion on the second side WS2 and the internal electrode layer exposed on the first side WS1 and the second side WS2.

[0159] In addition, the plating layer is configured to cover the exposed portions of the internal electrode layer in the first side surface WS1 and the second side surface WS2 of the stack 10. At this time, the gap between the thin film layer and the internal electrode layer exposed on the surface of the stack 10 and the gaps between the multiple internal electrode layers exposed on the surface of the stack 10 are formed narrow, so the plating layer is also deposited in the areas of these gaps.

[0160] In addition, when the base electrode layer is formed by a sintered layer, a conductive paste that becomes the first base electrode layer is applied to the first face portion located on the first end face LS1 of the stack 10, the second face portion located on a portion of the first main surface TS1, the third face portion located on a portion of the second main surface TS2, the fourth face portion located on a portion of the first side surface WS1, and the fifth face portion located on a portion of the second side surface WS2. In addition, a conductive paste that becomes the second base electrode layer is applied to the sixth face portion located on the second end face LS2 of the stack 10, the seventh face portion located on a portion of the first main surface TS1, the eighth face portion located on a portion of the second main surface TS2, the ninth face portion located on a portion of the first side surface WS1, and the tenth face portion located on a portion of the second side surface WS2 on the second end face LS2 of the stack 10.

[0161] In addition, when the stacked small pieces before firing and the conductive paste applied to the stacked small pieces are fired at the same time, the sintered layer is preferably formed by firing a paste to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. In this case, the conductive paste is applied to the stacked small pieces before firing, and the stacked small pieces and the conductive paste applied to the stacked small pieces are fired at the same time, thereby forming a stacked body 10 formed with a sintered layer.

[0162] Then, a plating layer is formed on the surface of the base electrode layer including the sintered layer and the laminate 10. When the base electrode layer is formed by the sintered layer, a two-layer plating layer of, for example, a Ni plating layer and a Sn plating layer is formed as the plating layer. When forming the plating layer, it is formed by an electrolytic plating method. As the plating method, preferably, drum plating is used.

[0163] Through such manufacturing steps, the multilayer ceramic capacitor 1 can be manufactured.

[0164] In addition, the structure of the external electrode 40 is not limited to the above-mentioned structure. Hereinafter, a modification of the arrangement position of the external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment will be described. In addition, in the following description, the same reference numerals are used for the same structure as the above-mentioned embodiment, and detailed description thereof will be omitted. Fig.15 is a cross-sectional view showing a modified example of the arrangement position of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment, and is similar to Figure 1 The corresponding figure.

[0165] In this modification, the arrangement position of the external electrode 40 is different from that of the above-mentioned embodiment. In this modification, the first external electrode 40A and the second external electrode 40B are arranged only on either the first main surface TS1 or the second main surface TS2.

[0166] For example, the first external electrode 40A of the present modification example includes a first face portion 40A1 located on the first end surface LS1, a third face portion 40A3 located as a portion on the second main surface TS2, a fourth face portion 40A4 located as a portion on the first side surface WS1, and a fifth face portion 40A5 located as a portion on the second side surface WS2. That is, the first external electrode 40A of the present modification example is not formed on the first main surface TS1.

[0167] For example, the second external electrode 40B of this modification example has a sixth face 40B1 located on the second end face LS2, an eighth face 40B3 located on a portion of the second main surface TS2, a ninth face 40B4 located on a portion of the first side surface WS1, and a tenth face 40B5 located on a portion of the second side surface WS2. That is, the second external electrode 40B of this modification example is not formed on the first main surface TS1.

[0168] With such a structure, it is also possible to suppress the deterioration of the self-alignment effect and perform stable mounting. Furthermore, by not configuring the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the dimension of the height direction T of the multilayer ceramic capacitor 1 can be reduced, and the height of the multilayer ceramic capacitor 1 can be further reduced. In addition, by not configuring the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the height dimension of the multilayer body 10 can be ensured according to the thickness of the external electrode 40. Therefore, the volume of the effective layer portion of the multilayer body 10 can be increased, and the capacity of the multilayer ceramic capacitor 1 can be increased.

[0169] According to the multilayer ceramic capacitor 1 of the present embodiment, the following effects are achieved.

[0170] (1) A multilayer ceramic capacitor 1 according to the present embodiment comprises: a multilayer body 10 having a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction perpendicular to the height direction, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction perpendicular to the height direction and the length direction; a first external electrode 40A having a first main surface TS1 and a second main surface TS2 located on the first end surface LS1 and the second end surface LS2; The second external electrode 40B comprises a first face portion 40A1 located on the second end face LS2, a second face portion 40A2 located on a portion of the first main surface TS1, and a third face portion 40A3 located on a portion of the second main surface TS2, a fourth face portion 40A4 located on a portion of the first side surface WS1, and a fifth face portion 40A5 located on a portion of the second side surface WS2; and a second external electrode 40B having a sixth face portion 40B1 located on the second end face LS2, a seventh face portion 40B2 located on a portion of the first main surface TS1, and a seventh face portion 40B3 located on a portion of the second main surface TS2. At least any one of the 8th face 40B3 of the portion, the 9th face 40B4 of the portion located on the 1st side surface WS1, and the 10th face 40B5 of the portion located on the second side surface WS2, wherein, when the length of the stack 10 in the longitudinal direction connecting the first end surface LS1 and the second end surface LS2 is set to l, the length in the width direction connecting the first side surface WS1 and the second side surface WS2 is set to w, and the length in the height direction connecting the first main surface TS1 and the second main surface TS2 is set to t, the size relationship is w>l>t, and the first The dimension L4 of the fourth surface portion 40A4 and the dimension L5 of the fifth surface portion 40A5 in the longitudinal direction L of the first external electrode 40A are larger than the dimension L2 of the second surface portion 40A2 and the dimension L3 of the third surface portion 40A3 in the longitudinal direction L, and the dimension L9 of the ninth surface portion 40B4 and the dimension L10 of the tenth surface portion 40B5 in the longitudinal direction L of the second external electrode 40B are larger than the dimension L7 of the seventh surface portion 40B2 and the dimension L8 of the eighth surface portion 40B3 in the longitudinal direction L. Thus, the width of the lead portion at the end surface of the internal electrode layer 30 can be widened. In addition, the distance between the first external electrode 40A and the second external electrode 40B can be shortened, so that the ESL of the multilayer ceramic capacitor 1 can be reduced.

[0171] Furthermore, when the first external electrode 40A and the second external electrode 40B are soldered to mount the multilayer ceramic capacitor 1 on the substrate, the solder can be sufficiently wetted and climbed even in the fourth face portion 40A4 and the fifth face portion 40A5 of the first external electrode 40A and the ninth face portion 40B4 and the tenth face portion 40B5 of the second external electrode 40B, where the amount of solder wetting and climbing tends to decrease. Therefore, in each of the fourth face portion 40A4 and the fifth face portion 40A5 and the ninth face portion 40B4 and the tenth face portion 40B5 of the second external electrode 40B, the amount of solder can be suppressed from varying, and the difference in tensile stress due to the solder can be suppressed. Therefore, it is possible to provide a multilayer ceramic capacitor of an LW inversion type that can suppress the deterioration of the self-alignment effect and can be stably mounted.

[0172] (2) In the multilayer ceramic capacitor 1 of the present embodiment, the dimension L4 of the fourth surface portion 40A4 of the first external electrode 40A in the longitudinal direction L and the dimension L5 of the fifth surface portion 40A5 in the longitudinal direction L are 110% or more and 245% or less relative to the dimension L2 of the second surface portion 40A2 in the longitudinal direction L and the dimension L3 of the third surface portion 40A3 in the longitudinal direction L, and the dimension L9 of the ninth surface portion 40B4 of the second external electrode 40B in the longitudinal direction L and the dimension L10 of the tenth surface portion 40B5 in the longitudinal direction L are 110% or more and 245% or less relative to the dimension L7 of the seventh surface portion 40B2 in the longitudinal direction L and the dimension L8 of the eighth surface portion 40B3 in the longitudinal direction L. Thus, the above-mentioned effect can be made more significant.

[0173] (3) In the multilayer ceramic capacitor 1 of the present embodiment, the internal electrode layer 30 includes a first internal electrode layer 31 and a second internal electrode layer 32. The first internal electrode layer 31 includes a first opposing electrode portion 31A located inside the multilayer body 10 and a first lead portion 31B connected to the first opposing electrode portion 31A and exposed at the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2. The second internal electrode layer 32 includes a second opposing electrode portion 32A located inside the multilayer body 10 and a second lead portion 32B connected to the second opposing electrode portion 32A and exposed at the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. As a result, the distance between the second lead portion 31B of the first internal electrode layer 31 and the second lead portion 32B of the second external electrode 40B can be shortened, so that the path through which the current flows can be shortened. As a result, the ESL can be reduced.

[0174] (4) In the multilayer ceramic capacitor 1 of the present embodiment, the first external electrode 40A includes the first base electrode layer 50A and the first plated layer 60A disposed on the first base electrode layer 50A, and the second external electrode 40B includes the second base electrode layer 50B and the second plated layer 60B disposed on the second base electrode layer 50B, and the first base electrode layer 50A and the second base electrode layer 50B are sputtered electrodes. Thus, the thickness of the external electrodes can be formed thin, and the thickness of the multilayer body 10 can be easily ensured, so that the capacitance can be ensured and the strength of the multilayer body 10 can be ensured.

[0175] (5) In the multilayer ceramic capacitor 1 of the present embodiment, the length t of the multilayer body 10 in the height direction T connecting the first main surface TS1 and the second main surface TS2 is 150 μm or less. In such a low-profile multilayer ceramic capacitor, the effects of the present embodiment can be appropriately obtained.

[0176] (6) In the multilayer ceramic capacitor 1 of the present embodiment, the length t of the stacked body 10 in the height direction T connecting the first main surface TS1 and the second main surface TS2 is 100 μm or less. In such a low-profile multilayer ceramic capacitor, the effects of the present embodiment can be appropriately obtained.

[0177] (7) In the multilayer ceramic capacitor 1 of the present embodiment, the length t of the multilayer body 10 in the height direction T connecting the first main surface TS1 and the second main surface TS2 is 50 μm or less. In such a low-profile multilayer ceramic capacitor, the effects of the present embodiment can be appropriately obtained.

[0178] <Experimental example>

[0179] As samples of experimental examples, multilayer ceramic capacitors were produced and their mountability was evaluated.

[0180] First, as a sample of Example 1, according to the above-mentioned manufacturing method, Figure 1 to Figure 10B A multilayer ceramic capacitor 1 having the following specifications is shown. In addition, as a sample of Comparative Example 1, Fig.16A The multilayer ceramic capacitor 101 shown in FIG. 1 is a multilayer ceramic capacitor in which the lengthwise dimension of the side surface of the external electrode 140 (first external electrode 140A, second external electrode 140B) is equal to the lengthwise dimension of the main surface. Fig.17A The illustrated multilayer ceramic capacitor 201 has a side surface of an external electrode 240 (first external electrode 240A, second external electrode 240B) whose lengthwise dimension is equal to that of a main surface and has a recess R that is recessed from the end edge of the external electrode toward the end surface of the stack 10 .

[0181] Fig.16A is a perspective view of the appearance of a multilayer ceramic capacitor 101 of Comparative Example 1. Figure 1 The corresponding figure. Fig. 16B is a diagram showing the first internal electrode layer 131 of the multilayer ceramic capacitor 101 of Comparative Example 1, and is similar to Fig. 8A The corresponding figure. Fig. 16C is a diagram showing the second internal electrode layer 132 of the multilayer ceramic capacitor 101 of Comparative Example 1, and is similar to Figure 8B The corresponding figure. Fig.17A is a perspective view of the appearance of a multilayer ceramic capacitor 201 of Comparative Example 2. Figure 1 The corresponding figure. Fig. 17B is a diagram showing the first internal electrode layer 231 of the multilayer ceramic capacitor 201 of Comparative Example 2, and is similar to Fig. 8A The corresponding figure. Fig. 17C is a diagram showing the second internal electrode layer 232 of the multilayer ceramic capacitor 201 of Comparative Example 2, and is similar to Figure 8B In addition, Fig. 16B , Fig. 16C , Fig. 17B , Fig. 17C In the example, the external electrodes are omitted.

[0182] (Structure of Example 1)

[0183] ･Dimensions of multilayer ceramic capacitors: L×W×T=0.520mm×1.000mm×0.100mm

[0184] ･Ceramic material for dielectric layer: BaTiO 3

[0185] ･Capacitance: 0.47μF

[0186] ･Rated voltage: 4V

[0187] ･Material of internal electrode layer: Ni

[0188] ･Pattern of internal electrode layer: Fig. 8A , Figure 8B The pattern shown

[0189] ･External electrode structure:

[0190] Substrate electrode layer: thin film layer (sputtered electrode)

[0191] Material of base electrode layer: 2-layer structure of NiCr layer and NiCu layer

[0192] Thickness of the underlying electrode layer: main surface thickness 0.2 μm (thickness of the underlying electrode layer disposed on the first main surface TS1 and the second main surface TS2 )

[0193] Plating layer: 3-layer structure of Cu plating, Ni plating, and Sn plating

[0194] Cu plating thickness: 5.5μm

[0195] Ni plating thickness: 2.5μm

[0196] Sn plating thickness: 3.2μm

[0197] ･The length dimension of each surface portion (the fourth surface portion and the fifth surface portion) on the side surface side of the first external electrode is 180% of the length dimension of each surface portion (the second surface portion and the third surface portion) on the main surface side of the first external electrode

[0198] ･The length dimension of each face portion (9th face portion and 10th face portion) on the side surface side of the second external electrode is 180% of the length dimension of each face portion (7th face portion and 8th face portion) on the main surface side of the second external electrode

[0199] (Structure of Comparative Example 1)

[0200] ･Dimensions of multilayer ceramic capacitors: L×W×T=0.520mm×1.000mm×0.100mm

[0201] ･Ceramic material for dielectric layer: BaTiO 3

[0202] ･Capacitance: 0.47μF

[0203] ･Rated voltage: 4V

[0204] ･Material of internal electrode layer: Ni

[0205] ･Pattern of internal electrode layer: Fig. 16B , Fig. 16C The pattern shown

[0206] ･External electrode structure:

[0207] Base electrode layer: A sintered layer on which a conductive paste is applied and sintered

[0208] Material of base electrode layer: Ni

[0209] Thickness of the underlying electrode layer: end surface thickness 10 μm, side surface thickness 5 μm, main surface thickness 5 μm (the thickness of the underlying electrode layer disposed on the first main surface TS1 and the second main surface TS2, respectively)

[0210] Plating layer: 3-layer structure of Cu plating, Ni plating, and Sn plating

[0211] Cu plating thickness: 5.5μm

[0212] Ni plating thickness: 2.5μm

[0213] Sn plating thickness: 3.2μm

[0214] (Structure of Comparative Example 2)

[0215] ･Dimensions of multilayer ceramic capacitors: L×W×T=0.520mm×1.000mm×0.100mm

[0216] ･Ceramic material for dielectric layer: BaTiO 3

[0217] ･Capacitance: 0.47μF

[0218] ･Rated voltage: 4V

[0219] ･Material of internal electrode layer: Ni

[0220] ･Pattern of internal electrode layer: Fig. 17B , Fig. 17C The pattern shown

[0221] ･External electrode structure:

[0222] Substrate electrode layer: thin film layer (sputtered electrode)

[0223] Material of base electrode layer: 2 layers of NiCr and NiCu

[0224] Thickness of the underlying electrode layer: main surface thickness 0.2 μm (thickness of the underlying electrode layer disposed on the first main surface TS1 and the second main surface TS2 )

[0225] Plating layer: 3-layer structure of Cu plating, Ni plating, and Sn plating

[0226] Cu plating thickness: 5.5μm

[0227] Ni plating thickness: 2.5μm

[0228] Sn plating thickness: 3.2μm

[0229] Next, the mountability was evaluated using the produced samples.

[0230] (Evaluation of installability 1)

[0231] The mountability was evaluated using the sample of Example 1 and the samples of Comparative Examples 1 and 2. 100 samples were used for each evaluation. Table 1 shows the results of the mountability evaluation.

[0232] [Table 1]

[0233]

[0234] In Comparative Example 1, eight samples suffered from rotation failure. By increasing the amount of solder for evaluation, it is presumed that the rotation failure occurred due to a difference in the way the solder wetting and climbing to the first external electrode and the second external electrode.

[0235] In Comparative Example 2, 15 samples were found to have poor rotation. Two of them had large rotation amounts and were installed with one external electrode crossing over connection pads with different polarities, resulting in a short circuit. In the samples of Comparative Example 2, due to the deviation in the formation position and thickness of the base electrode layer and the plating layer disposed thereon, the area and shape of the external electrode covering the ridgeline of the first side and second side of the laminated body were deviated, and the wetting mode of the external electrode on the first side and second side of the laminated body was easily changed by the solder, and it is believed that the wetting climb amount of the solder sometimes has a large difference. As a result, it is speculated that the poor rotation occurred due to the difference in the way the solder applied the tensile stress to the laminated ceramic capacitor.

[0236] The evaluation method in this experimental example is shown below.

[0237] (Evaluation method for installability)

[0238] FIG. 18A to FIG. 18D This is a diagram for explaining the evaluation method of installability. Fig.18A Solder (solder composition Sn-3.0Ag-0.5Cu) is printed on two connection pads 310A and 310B arranged on the glass epoxy substrate 300. In order to set the conditions more stringent than those in the usual test, the amount of solder at this time is set to 1.5 times the amount of the usual test. Specifically, a solder with a thickness of 150um is printed on each connection pad. In addition, as shown in FIG. Fig.18A As shown, the length of the connection pad in the width direction is set to 1.0 mm, the length of the connection pad in the length direction is set to 0.3 mm, and the distance between the two connection pads is set to 0.2 mm.

[0239] Next, the multilayer ceramic capacitor is placed on the lands coated with solder. Fig.18B As shown in FIG. 1 , a reference line perpendicular to the width direction of the connection pad is selected at the center of the width direction of the connection pad, and the multilayer ceramic capacitor is placed so that the center of the width direction W of the multilayer ceramic capacitor is located at a position deviated by 0.1 mm from the reference line along the width direction of the connection pad. Fig.18CThe angle θ formed between the connecting pad shown and the stacked ceramic capacitor is within 5°, that is, the angle θ on the acute angle side formed by either of the opposing inner edges of the two connecting pads and the surface on the first end face LS1 side or the surface on the second end face LS2 side of the external electrode of the stacked ceramic capacitor is within 5°.

[0240] Then, by reflow soldering, the external electrodes of the multilayer ceramic capacitor are soldered to the connection pads, and the multilayer ceramic capacitor is mounted on the substrate. After mounting, the mounting state of the multilayer ceramic capacitor is observed, and the case where the angle θ between the connection pad and the multilayer ceramic capacitor is 5° or more is considered to be a rotational failure. Fig.18D As shown in FIG. 1 , a case where the multilayer ceramic capacitor is greatly rotated and mounted so that the first external electrode or the second external electrode straddles two lands is regarded as a short-circuit failure.

[0241] (Evaluation of installability 2)

[0242] In the multilayer ceramic capacitor of Example 1 of the above specifications, 100 samples of Examples 2 to 5 were additionally produced in which the following ratio A and ratio B were changed, and the mountability was evaluated in the same manner as above. Table 2 shows the ratio A and ratio B of Examples 1 to 6, and also describes the evaluation results of the mountability.

[0243] “Ratio A”: ratio of the lengthwise dimension of each surface portion (fourth surface portion and fifth surface portion) of the side surface side of the first external electrode to the lengthwise dimension of each surface portion (second surface portion and third surface portion) of the main surface side of the first external electrode.

[0244] “Ratio B”: ratio of the lengthwise dimension of each surface portion (9th surface portion and 10th surface portion) of the side surface side of the second external electrode to the lengthwise dimension of each surface portion (7th surface portion and 8th surface portion) of the main surface side of the second external electrode.

[0245] [Table 2]

[0246]

[0247] In Example 2 where the ratio A and the ratio B were 105%, one sample was rotated. This is presumed to be because it became difficult to suppress the difference in tensile stress caused by the solder, and rotation occurred. On the other hand, in Example 6 where the ratio A and the ratio B were 250%, it is presumed that the distance between the face of the first external electrode on the side and the face of the second external electrode became shorter, so the solder adhered to both and was connected, causing a short circuit. Therefore, the ratio A and the ratio B are preferably 110% or more and 245% or less.

[0248] In addition, when calculating the above-mentioned ratio A and ratio B, the dimensions of the length direction L of the second face 40A2 and the third face 40A3 of the first external electrode 40A which are the faces on the main surface side and the seventh face 40B2 and the eighth face 40B3 of the second external electrode 40B, and the dimensions of the length direction L of the fourth face 40A4 and the fifth face 40A5 of the first external electrode 40A which are the faces on the side surface and the ninth face 40B4 and the tenth face 40B5 of the second external electrode 40B are measured by the following method.

[0249] (Method for measuring the face on the main surface side)

[0250] The dimensions of the second face 40A2 and the seventh face 40B2 in the length direction L are measured by a microscope at a position 1 / 2 of the width direction W when observing from the first main surface TS1 of the stack 10. Similarly, the dimensions of the third face 40A3 and the eighth face 40B3 in the length direction L are measured by a microscope at a position 1 / 2 of the width direction W when observing from the second main surface TS2 of the stack 10.

[0251] (Method for measuring the side of the face)

[0252] The dimensions of the length direction L of the fourth face 40A4 and the ninth face 40B4 are measured by a microscope at a position 1 / 2 of the height direction T when observed from the first side WS1 of the stack 10. Similarly, the dimensions of the length direction L of the fifth face 40A5 and the tenth face 40B5 are measured by a microscope at a position 1 / 2 of the height direction T when observed from the second side WS2 of the stack 10.

[0253] The present invention is not limited to the configuration of the above-described embodiment, and can be appropriately modified and applied within the scope of the gist of the present invention. In addition, a combination of two or more of the preferred configurations described in the above-described embodiment also constitutes the present invention.

[0254] (1) A multilayer ceramic capacitor comprising:

[0255] A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated in a height direction, and having a first main surface and a second main surface opposite to each other in the height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction;

[0256] a first external electrode having at least any one of a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, and a third face portion located on a portion of the second main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; and

[0257] The second external electrode has at least one of a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, and an eighth face portion located on a portion of the second main surface, a ninth face portion located on a portion of the first side surface, and a tenth face portion located on a portion of the second side surface.

[0258] in,

[0259] When the length of the stack connecting the first end face and the second end face in the longitudinal direction is set to l, the length of the stack connecting the first side face and the second side face in the width direction is set to w, and the length of the stack connecting the first main face and the second main face in the height direction is set to t, the stack is in a dimensional relationship of w>l>t.

[0260] The fourth face portion and the fifth face portion of the first external electrode have a larger dimension in the longitudinal direction than the second face portion and the third face portion.

[0261] The ninth surface portion and the tenth surface portion of the second external electrode have dimensions in the longitudinal direction that are larger than dimensions in the longitudinal direction of the seventh surface portion and the eighth surface portion.

[0262] (2) In the multilayer ceramic capacitor described in (1),

[0263] The lengthwise dimensions of the fourth and fifth face portions of the first external electrode are not less than 110% and not more than 245% of the lengthwise dimensions of the second and third face portions.

[0264] The lengthwise dimensions of the ninth and tenth surface portions of the second external electrode are greater than or equal to 110% and less than or equal to 245% of the lengthwise dimensions of the seventh and eighth surface portions.

[0265] (3) In the multilayer ceramic capacitor described in (1) or (2),

[0266] The internal electrode layer includes a first internal electrode layer and a second internal electrode layer,

[0267] The first internal electrode layer includes a first opposing electrode portion located inside the stacked body, and a first lead portion connected to the first opposing electrode portion and exposed at the first end surface, a portion of the first side surface, and a portion of the second side surface.

[0268] The second internal electrode layer includes a second opposing electrode portion located inside the stacked body, and a second lead portion connected to the second opposing electrode portion and exposed at the second end surface, a portion of the first side surface, and a portion of the second side surface.

[0269] (4) In the multilayer ceramic capacitor according to any one of (1) to (3),

[0270] The first external electrode includes a first base electrode layer and a first plating layer disposed on the first base electrode layer.

[0271] The second external electrode includes a second base electrode layer and a second plating layer disposed on the second base electrode layer.

[0272] The first foundation electrode layer and the second foundation electrode layer are sputtered electrodes.

[0273] (5) In the multilayer ceramic capacitor according to any one of (1) to (4),

[0274] The length of the stacked body in a height direction connecting the first main surface and the second main surface is 150 μm or less.

[0275] (6) In the multilayer ceramic capacitor according to any one of (1) to (4),

[0276] The length of the stacked body in a height direction connecting the first main surface and the second main surface is 100 μm or less.

[0277] (7) In the multilayer ceramic capacitor described in any one of (1) to (4),

[0278] The length of the stacked body in a height direction connecting the first main surface and the second main surface is 50 μm or less.

[0279] Description of Reference Numerals

[0280] 1: Multilayer ceramic capacitor;

[0281] 10: laminate;

[0282] 11: inner layer;

[0283] 12: first main surface side outer layer portion;

[0284] 13: outer layer portion on the second main surface side;

[0285] 20: dielectric layer;

[0286] 30: internal electrode layer;

[0287] 31: first internal electrode layer;

[0288] 31A: first opposing electrode portion;

[0289] 31B: 1st lead-out portion;

[0290] 31C: 2nd lead-out portion;

[0291] 31D: 3rd lead-out section;

[0292] 32: second internal electrode layer;

[0293] 32A: second opposing electrode portion;

[0294] 32B: 4th lead-out portion;

[0295] 32C: 5th lead;

[0296] 32D: 6th lead-out section;

[0297] 40: external electrode;

[0298] 40A: 1st external electrode;

[0299] 40A1: face 1;

[0300] 40A2: second face;

[0301] 40A3: face 3;

[0302] 40A4: face 4;

[0303] 40A5: face 5;

[0304] 40B: second external electrode;

[0305] 40B1: face 6;

[0306] 40B2: face 7;

[0307] 40B3: face 8;

[0308] 40B4: 9th face;

[0309] 40B5: 10th face;

[0310] 50A: 1st base electrode layer;

[0311] 50B: second base electrode layer;

[0312] 51A: 1st film layer;

[0313] 51B: second film layer;

[0314] 60A: 1st plating layer;

[0315] 60B: second plating layer;

[0316] L: length direction;

[0317] W: width direction;

[0318] T: stacking direction;

[0319] LS1: 1st end face;

[0320] LS2: 2nd end face;

[0321] WS1: side 1;

[0322] WS2: side 2;

[0323] TS1: 1st main surface;

[0324] TS2: 2nd main surface;

[0325] l: length in the longitudinal direction;

[0326] w: length in width direction;

[0327] t: length in height direction.

Claims

1. A laminated ceramic capacitor comprising: A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated in a height direction, and having a first main surface and a second main surface opposite to each other in the height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having at least any one of a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, and a third face portion located on a portion of the second main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; and The second external electrode has at least one of a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, and an eighth face portion located on a portion of the second main surface, a ninth face portion located on a portion of the first side surface, and a tenth face portion located on a portion of the second side surface. in, When the length of the stack connecting the first end face and the second end face in the longitudinal direction is set to l, the length of the stack connecting the first side face and the second side face in the width direction is set to w, and the length of the stack connecting the first main face and the second main face in the height direction is set to t, the stack is in a dimensional relationship of w>l>t. The fourth face portion and the fifth face portion of the first external electrode have a larger dimension in the longitudinal direction than the second face portion and the third face portion. The ninth surface portion and the tenth surface portion of the second external electrode have dimensions in the longitudinal direction that are larger than dimensions in the longitudinal direction of the seventh surface portion and the eighth surface portion.

2. The multilayer ceramic capacitor according to claim 1, wherein The lengthwise dimensions of the fourth and fifth face portions of the first external electrode are not less than 110% and not more than 245% of the lengthwise dimensions of the second and third face portions. The lengthwise dimensions of the ninth and tenth surface portions of the second external electrode are greater than or equal to 110% and less than or equal to 245% of the lengthwise dimensions of the seventh and eighth surface portions.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The internal electrode layer includes a first internal electrode layer and a second internal electrode layer, The first internal electrode layer includes a first opposing electrode portion located inside the stacked body, and a first lead portion connected to the first opposing electrode portion and exposed at the first end surface, a portion of the first side surface, and a portion of the second side surface. The second internal electrode layer includes a second opposing electrode portion located inside the stacked body, and a second lead portion connected to the second opposing electrode portion and exposed at the second end surface, a portion of the first side surface, and a portion of the second side surface.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The first external electrode includes a first base electrode layer and a first plating layer disposed on the first base electrode layer. The second external electrode includes a second base electrode layer and a second plating layer disposed on the second base electrode layer. The first foundation electrode layer and the second foundation electrode layer are sputtered electrodes.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein The length of the stacked body in a height direction connecting the first main surface and the second main surface is 150 μm or less.

6. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein The length of the stacked body in a height direction connecting the first main surface and the second main surface is 100 μm or less.

7. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein The length of the stacked body in a height direction connecting the first main surface and the second main surface is 50 μm or less.

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