Waveform control circuit and test system

Abstract

The invention discloses a waveform control circuit and a test system. The waveform control circuit comprises a control unit, a low dropout regulator and a discharge circuit. The low dropout linear regulator is coupled with the control unit and the power supply; the discharging circuit is coupled with the low dropout linear regulator, the control unit and the tested chip; wherein the control unit is used for sending a first control signal to the low-dropout linear regulator and the discharging circuit, so that the low-dropout linear regulator is matched with the discharging circuit, and slope rising voltage is output from the output end of the discharging circuit; and / or the control unit is used for sending a second control signal to the low-dropout linear regulator and the discharge circuit, so that the low-dropout linear regulator is matched with the discharge circuit, and the slope drop voltage is output from the output end of the discharge circuit. Through the above mode, the real abnormal power-on and power-off conditions can be better simulated, and the test of the tested chip is completed.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a waveform control circuit and a testing system. Background Art

[0002] The power-on and power-off test of the chip is a very important test method in the production test process. Therefore, it is very important to simulate a more realistic abnormal environment. At present, the commonly used method for power-on and power-off testing in production testing is to directly control the output to the chip under test through an analog switch, and control the on and off of the power supply line of the chip under test, so as to simulate abnormal power-on and power-off behavior. Summary of the invention

[0003] The present application provides a waveform control circuit and a test system, which can better simulate the actual abnormal power-on and power-off conditions and complete the test of the chip under test.

[0004] In a first aspect, the present application provides a waveform control circuit, which includes: a control unit; a low-voltage difference linear regulator, a first input end of the low-voltage difference linear regulator is coupled to the control unit, and a second input end of the low-voltage difference linear regulator is used to couple a power supply; a discharge circuit, a first input end of the discharge circuit is coupled to the low-voltage difference linear regulator, a second input end of the discharge circuit is coupled to the control unit, and an output end of the discharge circuit is used to couple a chip under test; wherein the control unit is used to send a first control signal to the low-voltage difference linear regulator and the discharge circuit so that the low-voltage difference linear regulator and the discharge circuit cooperate to output a slope-rising voltage from the output end of the discharge circuit; and / or the control unit is used to send a second control signal to the low-voltage difference linear regulator and the discharge circuit so that the low-voltage difference linear regulator and the discharge circuit cooperate to output a slope-decreasing voltage from the output end of the discharge circuit.

[0005] The discharge circuit includes: a digital-to-analog converter, the input end of the digital-to-analog converter is coupled to the control unit as the second input end of the discharge circuit; an operational amplifier, the non-inverting input end of the operational amplifier is coupled to the digital-to-analog converter; a switch unit, the control end of the switch unit is coupled to the output end of the operational amplifier, the first channel end of the switch unit is coupled to the output end of the low-voltage difference linear regulator, the second channel end of the switch unit is coupled to the inverting input end of the operational amplifier, and the coupling point between the first channel end of the switch unit and the output end of the low-voltage difference linear regulator serves as the output end of the discharge circuit.

[0006] Among them, the digital-to-analog converter sends a first analog signal to the operational amplifier based on the first control signal; the operational amplifier sends a cutoff signal to the switch unit based on the first analog signal to put the switch unit in a cutoff state; the low-voltage difference linear regulator outputs a slope-rising voltage to the discharge circuit based on the first control signal, and outputs it from the output end of the discharge circuit to the chip under test.

[0007] Among them, the digital-to-analog converter sends a second analog signal to the operational amplifier based on the second control signal; the operational amplifier sends a conduction signal to the switch unit based on the second analog signal, so that the switch unit is in a conductive state, stably pulling down the target voltage output by the low-voltage difference linear regulator, and forming a slope-down voltage.

[0008] Wherein, the discharge circuit also includes: a first resistor, a first end of the first resistor is coupled to the output end of the digital-to-analog converter, and a second end of the first resistor is coupled to the in-phase input end of the operational amplifier; a second resistor, a first end of the second resistor is coupled to the output end of the operational amplifier, and a second end of the second resistor is coupled to the control end of the switch unit; a third resistor, a first end of the third resistor is coupled to the second path end of the switch unit, and a second end of the second resistor is grounded.

[0009] The digital signal value of the first control signal is determined by the third resistor.

[0010] The positive power supply terminal of the operational amplifier is coupled to the output terminal of the low voltage drop linear regulator.

[0011] Among them, the switch unit is a MOS tube.

[0012] The waveform control circuit further includes: a DC converter, the input end of the DC converter is coupled to an external power supply, and the output end of the DC converter is coupled to a low voltage drop linear regulator for stabilizing an external input voltage to a fixed voltage and inputting the voltage to the low voltage drop linear regulator.

[0013] In a second aspect, the present application provides a test system, which includes: a host computer; a waveform control circuit, the waveform control circuit is coupled to the host computer, and the waveform control circuit is such as the waveform control circuit provided in the first aspect.

[0014] The beneficial effect of the present application is that, different from the prior art, the waveform control circuit and test system provided by the present application utilize the fast dynamic response speed of the low-voltage difference linear regulator, and can control the low-voltage difference linear regulator to generate voltages with different rising or falling slopes through the control unit, and utilize the discharge circuit to improve the power-off response speed when the slope decreases. Based on this, the control unit, low-voltage difference linear regulator and discharge circuit of the present application can better simulate the real abnormal power-on and power-off situations and complete the test of the chip under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0016] Figure 1 It is a structural schematic diagram of an embodiment of a waveform control circuit provided by the present application;

[0017] Figure 2 is a schematic diagram of the slope rising voltage provided by the present application;

[0018] Figure 3 is a schematic diagram of a slope-down voltage provided by the present application;

[0019] Figure 4 It is a schematic diagram of alternating a slope-rising voltage and a slope-decreasing voltage provided by the present application;

[0020] Figure 5 It is a structural schematic diagram of an embodiment of a discharge circuit provided by the present application;

[0021] Figure 6 is a structural schematic diagram of another embodiment of the discharge circuit provided by the present application;

[0022] Figure 7 is a structural diagram of another embodiment of the server system provided by the present application;

[0023] Figure 8 It is a structural diagram of an embodiment of a test system provided by the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] The power-on and power-off test of the chip is a very important test method in the production test process. Therefore, it is very important to simulate a more realistic abnormal environment. At present, the commonly used method for power-on and power-off testing in production testing is to directly control the output to the chip under test through an analog switch, and control the on and off of the power supply line of the chip under test, so as to simulate abnormal power-on and power-off behavior.

[0027] Although the analog switch can be used to control the power on and off mode to realize the analog power-on and power-off function, there are some disadvantages. (1) The analog switch method cannot simulate the power supply waveform of the step-type abnormal power-on and power-off model; (2) The analog switch method cannot simulate the abnormal jitter of the complex voltage waveform; (3) The analog switch method cannot simulate the abnormal power-off with a fixed slope.

[0028] Based on this, the present application proposes any of the following embodiments to solve at least one of the above technical problems.

[0029] See also Figure 1 , Figure 1 1 is a schematic diagram of a waveform control circuit according to an embodiment of the present application. The waveform control circuit 100 comprises: a control unit 10 , a low voltage dropout linear regulator 20 and a discharge circuit 30 .

[0030] The first input terminal of the low voltage dropout linear regulator 20 is coupled to the control unit 10 , and the second input terminal of the low voltage dropout linear regulator 20 is used for coupling to a power source.

[0031] The low-dropout linear regulator 20 is a micro-chip system with very low self-consumption. It can be used for current main channel control. The low-dropout linear regulator 20 integrates MOS tubes with extremely low online on-resistance, Schottky diodes, sampling resistors, voltage divider resistors and other hardware circuits, and has functions such as overcurrent protection, overtemperature protection, precision reference source, differential amplifier, delay, etc. The low-dropout linear regulator 20 usually has extremely low self-noise and high power supply rejection ratio.

[0032] The low voltage dropout linear regulator 20 is used to reduce the voltage ripple generated by the input circuit and improve the load response efficiency, and can cooperate with the control unit 10 to control the output voltage.

[0033] A first input terminal of the discharge circuit 30 is coupled to the low voltage dropout linear regulator 20 , a second input terminal of the discharge circuit 30 is coupled to the control unit 10 , and an output terminal of the discharge circuit 30 is coupled to the chip under test 200 .

[0034] In some embodiments, the control unit 10 is used to send a first control signal to the low voltage difference linear regulator 20 and the discharge circuit 30, so that the low voltage difference linear regulator 20 and the discharge circuit 30 cooperate to output a slope-rising voltage from the output end of the discharge circuit 30. Under the action of the first control signal, the low voltage difference linear regulator 20 generates a slope-rising voltage, and the discharge circuit 30 does not work (does not discharge), then the output end of the discharge circuit 30 can directly output the slope-rising voltage to the chip under test 200, such as Figure 2 As shown, the voltage increases gradually over time, and the slope is stable.

[0035] In some embodiments, the control unit 10 is used to send a second control signal to the low voltage difference linear regulator 20 and the discharge circuit 30, so that the low voltage difference linear regulator 20 and the discharge circuit 30 cooperate to output a slope-down voltage from the output end of the discharge circuit 30. Under the action of the second control signal, the low voltage difference linear regulator 20 generates a slope-down voltage, and the discharge circuit 30 works to discharge, thereby improving the power-off response speed, and then the output end of the discharge circuit 30 can directly output the slope-down voltage to the chip under test 200, such as Figure 3 As shown, the voltage gradually decreases with time and the slope is stable.

[0036] In some embodiments, the control unit 10 is used to send a first control signal to the low-voltage difference linear regulator 20 and the discharge circuit 30, so that the low-voltage difference linear regulator 20 and the discharge circuit 30 cooperate to output a slope-increasing voltage from the output end of the discharge circuit 30; and the control unit 10 is used to send a second control signal to the low-voltage difference linear regulator 20 and the discharge circuit 30, so that the low-voltage difference linear regulator 20 and the discharge circuit 30 cooperate to output a slope-decreasing voltage from the output end of the discharge circuit 30. That is, the first control signal and the second control signal can alternately control the low-voltage difference linear regulator 20 and the discharge circuit 30 to alternately form a slope-increasing voltage and a slope-decreasing voltage. Figure 4 As shown, a rising slope voltage and a falling slope voltage are alternately formed over time.

[0037] In this embodiment, the low voltage difference linear regulator 20 has the characteristic of fast dynamic response speed, and the control unit 10 can control the low voltage difference linear regulator 20 to generate voltages with different rising or falling slopes, and use the discharge circuit 30 to improve the power-off response speed when the slope decreases. Based on this, the control unit 10, the low voltage difference linear regulator 20 and the discharge circuit 30 of the present application can better simulate the actual abnormal power-on and power-off situations and complete the test of the chip under test 200.

[0038] Furthermore, the waveform control circuit 100 can generate various voltage waveforms to simulate real abnormal power-on and power-off conditions, perform product reliability tests on the chip under test 200, improve the authenticity of the power-on and power-off test model, improve the reliability of the chip under test 200, and solve the shortcomings of the analog switch test method. That is, the waveform control circuit 100 can simulate the power supply waveform of the step-type abnormal power-on and power-off model, the waveform control circuit 100 can simulate the abnormal jitter of the voltage complex waveform, and the waveform control circuit 100 can simulate the abnormal power-off of the fixed slope.

[0039] It can be understood that the chip under test 200 also corresponds to a corresponding detection module for detecting the corresponding function of the chip under test 200 under the voltage provided by the waveform control circuit 100 .

[0040] See also Figure 5 , Figure 5 3 is a schematic diagram of a structure of an embodiment of a discharge circuit provided in the present application. The discharge circuit 30 comprises: a digital-to-analog converter 31 , an operational amplifier AMP and a switch unit 32 .

[0041] An input terminal of the digital-to-analog converter 31 is coupled to the control unit 10 as a second input terminal of the discharge circuit 30 .

[0042] The non-inverting input terminal of the operational amplifier AMP is coupled to the digital-to-analog converter 31 .

[0043] The control end of the switch unit 32 is coupled to the output end of the operational amplifier AMP, the first channel end of the switch unit 32 is coupled to the output end of the low-voltage dropout linear regulator 20, the second channel end of the switch unit 32 is coupled to the inverting input end of the operational amplifier AMP, and the coupling point A between the first channel end of the switch unit 32 and the output end of the low-voltage dropout linear regulator 20 serves as the output end of the discharge circuit 30, coupled to the chip under test 200.

[0044] In some embodiments, the digital-to-analog converter 31 sends a first analog signal to the operational amplifier AMP based on the first control signal; the operational amplifier AMP sends a cutoff signal to the switch unit 32 based on the first analog signal to put the switch unit 32 in a cutoff state; the low-voltage difference linear regulator 20 outputs a slope-rising voltage to the discharge circuit 30 based on the first control signal, and outputs it from the output end of the discharge circuit 30 to the chip under test 200.

[0045] In some embodiments, the digital-to-analog converter 31 sends a second analog signal to the operational amplifier AMP based on the second control signal; the operational amplifier AMP sends a conduction signal to the switch unit 32 based on the second analog signal, so that the switch unit 32 is in a conduction state, stably pulling down the target voltage output by the low-dropout linear regulator 20, and forming a slope-down voltage.

[0046] The digital-to-analog converter 31 can convert the control signal of the digital signal into an analog signal. The operational amplifier AMP can output a corresponding electrical signal (a cut-off signal or a conduction signal) according to the voltage value corresponding to the analog signal, and the switch unit 32 can be turned on or off according to the electrical signal.

[0047] When the switch unit 32 is in the on state, it will quickly pull down the target voltage output by the low-dropout linear regulator 20 to quickly form a slope-down voltage.

[0048] When the switch unit 32 is in the off state, the low voltage dropout linear regulator 20 outputs a slope-increasing voltage to the discharge circuit 30 based on the first control signal, and outputs the voltage from the output end of the discharge circuit 30 to the chip under test 200 .

[0049] In this embodiment, the discharge circuit 30 is used to improve the power-off response speed when the slope decreases. Based on this, the control unit 10, low-voltage difference linear regulator 20 and discharge circuit 30 of the present application can better simulate the actual abnormal power-on and power-off conditions and complete the test of the chip under test 200.

[0050] See also Figure 6 The discharge circuit 30 includes: a digital-to-analog converter 31, an operational amplifier AMP, a switch unit 32, a first resistor R1, a second resistor R2 and a third resistor R3.

[0051] An input terminal of the digital-to-analog converter 31 is coupled to the control unit 10 as a second input terminal of the discharge circuit 30 .

[0052] A first end of the first resistor R1 is coupled to the output end of the digital-to-analog converter 31 , and a second end of the first resistor R1 is coupled to the non-inverting input end of the operational amplifier AMP.

[0053] A first end of the second resistor R2 is coupled to the output end of the operational amplifier AMP, and a second end of the second resistor R2 is coupled to the control end of the switch unit 32 .

[0054] A first end of the third resistor R3 is coupled to the second path end of the switch unit 32 , and a second end of the second resistor R2 is grounded.

[0055] The control end of the switch unit 32 is coupled to the second end of the second resistor R2, the first channel end of the switch unit 32 is coupled to the output end of the low-voltage dropout linear regulator 20, the second channel end of the switch unit 32 is coupled to the inverting input end of the operational amplifier AMP, and the coupling point A between the first channel end of the switch unit 32 and the output end of the low-voltage dropout linear regulator 20 serves as the output end of the discharge circuit 30, coupled to the chip under test 200.

[0056] The digital signal value of the first control signal is determined by the third resistor R3, that is, the resistance value of the third resistor R3 determines the digital signal value.

[0057] The positive power supply terminal of the operational amplifier AMP is coupled to the output terminal of the low voltage dropout linear regulator 20 , that is, the output terminal of the low voltage dropout linear regulator 20 provides the VCC voltage.

[0058] The switch unit 32 is a MOS tube, a gate of the MOS tube is coupled to the second resistor R2 , a source of the MOS tube is coupled to the third resistor R3 , and a drain of the MOS tube is coupled to the output end of the low voltage difference linear regulator 20 .

[0059] In this embodiment, the discharge circuit 30 is used to improve the power-off response speed when the slope decreases. Based on this, the control unit 10, low-voltage difference linear regulator 20 and discharge circuit 30 of the present application can better simulate the actual abnormal power-on and power-off conditions and complete the test of the chip under test 200.

[0060] See also Figure 7 The waveform control circuit 100 includes: a control unit 10, a low voltage dropout linear regulator 20, a discharge circuit 30 and a DC converter 40. The input end of the DC converter 40 is coupled to an external power supply, and the output end of the DC converter 40 is coupled to the low voltage dropout linear regulator 20, for stabilizing the external input voltage to a fixed voltage and inputting it to the low voltage dropout linear regulator 20. The connection relationship between the control unit 10, the low voltage dropout linear regulator 20 and the discharge circuit 30 can refer to any of the above embodiments, and will not be repeated here.

[0061] See also Figure 8 The test system 1000 includes: a host computer 300 and a waveform control circuit 100. The waveform control circuit 100 is coupled to the host computer 300, and the waveform control circuit 100 is the waveform control circuit 100 of any of the above embodiments.

[0062] In one application scenario, combined with Figure 7 and Figure 8 , the test process of the above-mentioned chip under test 200 is described:

[0063] The host computer 300 sends a control instruction to the control unit 10 in the waveform control circuit 100 so that the control unit 10 performs waveform control.

[0064] Specifically, the waveform control circuit 100 uses a DC converter 40 to stabilize the external input voltage to a fixed value, and uses a low voltage dropout linear regulator 20 to reduce the voltage ripple generated by the input circuit and improve the load response efficiency, and can cooperate with the control unit 10 to control the output voltage.

[0065] The discharge circuit 30 forms a constant current circuit for discharge through the operational amplifier AMP. By controlling the voltage of the non-inverting input terminal of the operational amplifier AMP, the output voltage of the MOS tube source stage in the switch unit 32 can be controlled, and the specific constant current value can be obtained by combining the resistor (third resistor R3) after the MOS tube source stage.

[0066] The control unit 10 controls the digital-to-analog converter 31 to convert the digital signal into an analog voltage signal and outputs it to the non-inverting input terminal of the operational amplifier AMP.

[0067] Assuming that the digital-to-analog converter 31 is 14 bits, the supply voltage of the low-dropout linear regulator 20 and the reference voltage of the digital-to-analog converter 31 Vref=VCC=5V, the digital signal value input to the digital-to-analog converter 31 for processing is M, and the following constant current discharge formula is obtained:

[0068]

[0069] Wherein, R represents the resistance value of the third resistor R3.

[0070] The control unit 10 controls the voltage output to the chip under test 200 by controlling the low voltage drop linear regulator 20. The low voltage drop linear regulator 20 has a fast dynamic response speed, so the control unit 10 can be used to control the voltage to rise and fall slowly. When the voltage falls, the switch unit 32 in the discharge circuit 30 can be turned on to increase the power-off response speed, thereby achieving the purpose of slope power-on and power-off testing.

[0071] To summarize, the waveform control circuit 100 and the test system 1000 provided in the present application utilize the fast dynamic response speed of the low voltage difference linear regulator 20. The control unit 10 can control the low voltage difference linear regulator 20 to generate voltages with different rising or falling slopes, and utilize the discharge circuit 30 to improve the power-off response speed when the slope decreases. Based on this, the control unit 10, the low voltage difference linear regulator 20 and the discharge circuit 30 of the present application can better simulate the actual abnormal power-on and power-off situations and complete the test of the chip under test 200.

[0072] Furthermore, the host computer 300 can send command control to the control unit 10 to implement automated testing.

[0073] Furthermore, the waveform control circuit 100 may also supply power to the chip under test 200 to simulate the noise waveform.

[0074] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0075] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program codes.

[0076] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A waveform control circuit, characterized in that: The waveform control circuit comprises: Control unit; A low voltage dropout linear regulator, wherein a first input terminal of the low voltage dropout linear regulator is coupled to the control unit, and a second input terminal of the low voltage dropout linear regulator is used to couple to a power source; A discharge circuit, wherein a first input end of the discharge circuit is coupled to the low voltage drop linear regulator, a second input end of the discharge circuit is coupled to the control unit, and an output end of the discharge circuit is used to couple to a chip under test; The control unit is used to send a first control signal to the low voltage dropout linear regulator and the discharge circuit, so that the low voltage dropout linear regulator and the discharge circuit cooperate to output a slope-rising voltage from the output end of the discharge circuit; And / or, the control unit is used to send a second control signal to the low voltage dropout linear regulator and the discharge circuit, so that the low voltage dropout linear regulator and the discharge circuit cooperate to output a slope-decreasing voltage from the output end of the discharge circuit.

2. The waveform control circuit according to claim 1, characterized in that: The discharge circuit comprises: A digital-to-analog converter, wherein an input terminal of the digital-to-analog converter is coupled to the control unit as a second input terminal of the discharge circuit; an operational amplifier, wherein a non-inverting input terminal of the operational amplifier is coupled to the digital-to-analog converter; A switch unit, wherein the control end of the switch unit is coupled to the output end of the operational amplifier, the first path end of the switch unit is coupled to the output end of the low voltage drop linear regulator, the second path end of the switch unit is coupled to the inverting input end of the operational amplifier, and the coupling point between the first path end of the switch unit and the output end of the low voltage drop linear regulator serves as the output end of the discharge circuit.

3. The waveform control circuit according to claim 2, characterized in that: in, The digital-to-analog converter sends a first analog signal to the operational amplifier based on the first control signal; The operational amplifier sends a cutoff signal to the switch unit based on the first analog signal, so that the switch unit is in a cutoff state; The low voltage difference linear regulator outputs a slope rising voltage to the discharge circuit based on the first control signal, and outputs the voltage to the chip under test from an output end of the discharge circuit.

4. The waveform control circuit according to claim 2, characterized in that: in, The digital-to-analog converter sends a second analog signal to the operational amplifier based on the second control signal; The operational amplifier sends a conduction signal to the switch unit based on the second analog signal, so that the switch unit is in a conduction state, stably pulling down the target voltage output by the low-dropout linear regulator to form the slope-down voltage.

5. The waveform control circuit according to claim 2, characterized in that: The discharge circuit further comprises: a first resistor, wherein a first end of the first resistor is coupled to the output end of the digital-to-analog converter, and a second end of the first resistor is coupled to the non-inverting input end of the operational amplifier; a second resistor, wherein a first end of the second resistor is coupled to the output end of the operational amplifier, and a second end of the second resistor is coupled to the control end of the switch unit; A third resistor, wherein a first end of the third resistor is coupled to the second path end of the switch unit, and a second end of the second resistor is grounded.

6. The waveform control circuit according to claim 5, characterized in that: The digital signal value of the first control signal is determined by the third resistor.

7. The waveform control circuit according to claim 2, characterized in that: The positive power supply terminal of the operational amplifier is coupled to the output terminal of the low voltage drop linear regulator.

8. The waveform control circuit according to claim 2, characterized in that: The switch unit is a MOS tube.

9. The waveform control circuit according to claim 1, characterized in that: The waveform control circuit also includes: A DC converter, wherein the input end of the DC converter is coupled to an external power source, and the output end of the DC converter is coupled to the low voltage drop linear regulator, for stabilizing an external input voltage to a fixed voltage and inputting the fixed voltage to the low voltage drop linear regulator.

10. A testing system, characterized in that: The test system comprises: Host computer; A waveform control circuit, wherein the waveform control circuit is coupled to the host computer, and the waveform control circuit is the waveform control circuit as described in any one of claims 1-9.

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