Instruction processing method and device, equipment, medium and product

Abstract

The invention relates to the technical field of communication, and particularly provides an instruction processing method and device, equipment, a medium and a product, and the method comprises the steps: obtaining a to-be-processed data processing instruction; determining a register assignment of a register assignment instruction in the data processing instruction; according to a target numerical range to which the register assignment belongs, performing length optimization processing on the data processing instruction to obtain a target compiling instruction of which the instruction length is smaller than that of the data processing instruction; the target compilation instruction is loaded through the virtual machine of the SIM card, the target compilation instruction is executed through the virtual machine, through the processing mode, the instruction length of the data processing instruction is shortened, the target compilation instruction is obtained, the target compilation instruction can be executed according to the virtual machine of the SIM card, and therefore the use efficiency of the SIM card is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of communications, and in particular, to an instruction processing method, device, equipment, medium and product. Background Art

[0002] Existing SIM cards not only support network authentication, but also can load other applications, such as third-party applications for public transportation and user identity authentication. Since SIM cards usually need to load multiple applications, SIM cards are usually designed with a register architecture to increase the storage space of the SIM card.

[0003] In the related art, data processing instructions of various applications are stored in a chip, and the chip is set in a SIM card to process the data processing instructions through the chip. However, since the processing capability of the SIM card cannot meet the processing requirements of the chip, the data processing instructions cannot be processed according to the chip, which affects the use efficiency of the SIM card. Summary of the invention

[0004] In view of the above problems, the present disclosure is proposed. The present disclosure provides an instruction processing method, device, equipment, medium and product.

[0005] According to one aspect of the present disclosure, there is provided an instruction processing method, comprising:

[0006] Obtaining data processing instructions to be processed;

[0007] determining a register assignment of a register assignment instruction in the data processing instruction;

[0008] According to the target numerical range to which the register assignment belongs, the data processing instruction is optimized in length to obtain a target compiled instruction with an instruction length smaller than that of the data processing instruction;

[0009] The target compilation instruction is loaded through the virtual machine of the SIM card, so as to execute the target compilation instruction through the virtual machine.

[0010] In addition, according to one aspect of the present disclosure, the data processing instruction is optimized in length according to the target numerical range to which the register assignment belongs, so as to obtain a target compiled instruction with an instruction length smaller than that of the data processing instruction, further comprising:

[0011] According to the target numerical range, the number of bytes occupied by the register assignment and the instruction information of the data processing instruction is optimized to obtain the target compiled instruction; wherein the instruction information includes an instruction opcode and address information of the register corresponding to the register assignment.

[0012] In addition, according to one aspect of the present disclosure, the number of bytes occupied by the instruction information of the register assignment and the data processing instruction is optimized according to the target numerical range to obtain the target compilation instruction, further comprising:

[0013] Determine an instruction encoding format corresponding to a target numerical range to which the register assignment belongs; wherein the instruction encoding format is used to indicate a shortening mode of bytes occupied by the register assignment and the instruction information;

[0014] The register assignment and the instruction information are subjected to instruction optimization processing according to the instruction encoding format to obtain the target compilation instruction.

[0015] In addition, according to one aspect of the present disclosure, the register assignment and the instruction information are subjected to instruction optimization processing according to the instruction encoding format to obtain the target compilation instruction, further comprising:

[0016] When the target numerical range is a first preset numerical range, the register assignment and the address information in the instruction information are filtered, and the valid data bits of the instruction opcode in the instruction information are extracted to obtain the target compilation instruction; wherein the values ​​included in the first preset numerical range are values ​​whose assignment frequency is higher than the target frequency threshold.

[0017] In addition, according to one aspect of the present disclosure, the register assignment and the instruction information are subjected to instruction optimization processing according to the instruction encoding format to obtain the target compilation instruction, further comprising:

[0018] When the target numerical value range is within the second preset numerical value range, determining valid data bits of the instruction operation code of the data processing instruction to obtain a first encoding byte;

[0019] Combining the address information in the instruction information and the valid data bits of the register assignment to obtain a second coded byte;

[0020] The first encoding byte and the second encoding byte are combined to obtain the target compilation instruction.

[0021] In addition, according to one aspect of the present disclosure, the register assignment and the instruction information are subjected to instruction optimization processing according to the instruction encoding format to obtain the target compilation instruction, further comprising:

[0022] In the case where the target value range does not belong to the preset value range, determining whether the data bit of the register assignment is greater than the data bit of the address information;

[0023] In the case where it is determined that the data bit of the register value is greater than the data bit of the address information, the target compiled instruction is determined based on the instruction operation code and the valid data bit of the register value.

[0024] In addition, according to one aspect of the present disclosure, it also includes:

[0025] In case it is determined that the data bits of the register assignment are less than or equal to the data bits of the address information, the target compiled instruction is determined based on the instruction operation code, the register assignment and the valid data bits of the address information.

[0026] In addition, according to one aspect of the present disclosure, the register assignment and the instruction information are subjected to instruction optimization processing according to the instruction encoding format to obtain the target compilation instruction, further comprising:

[0027] In a case where the target numerical range does not belong to a preset numerical range, the target compilation instruction is determined based on the original data bits of the register assignment.

[0028] In addition, according to one aspect of the present disclosure, the data processing instruction is optimized in length according to the target numerical range to which the register assignment belongs, so as to obtain a target compiled instruction with an instruction length smaller than that of the data processing instruction, further comprising:

[0029] When it is determined that the target numerical range to which the register value is assigned does not belong to the preset numerical range, the target compilation instruction is determined according to the valid data bits of the address information and the original data bits of the register value assigned.

[0030] According to another aspect of the present disclosure, there is provided an instruction processing device, comprising:

[0031] An acquisition unit, used for acquiring data processing instructions to be processed;

[0032] an assignment determination unit, used to determine a register assignment of a register assignment instruction in the data processing instruction;

[0033] A processing unit, configured to perform length optimization processing on the data processing instruction according to a target numerical range to which the register assignment belongs, to obtain a target compiled instruction having an instruction length smaller than that of the data processing instruction;

[0034] The instruction execution unit is used to load the target compiled instruction through the virtual machine of the SIM card, so as to execute the target compiled instruction through the virtual machine.

[0035] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps in the above-mentioned instruction processing method are performed.

[0036] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above instruction processing method are executed.

[0037] According to another aspect of the present disclosure, a computer program product is provided. The computer program product is stored in a storage medium and is executed by at least one processor to implement the steps in the above instruction processing method.

[0038] As will be described in detail below, according to the instruction processing method, apparatus, device, medium and product of the embodiments of the present disclosure, first, a data processing instruction to be processed is obtained; then, a register assignment of a register assignment instruction in the data processing instruction is determined; and according to a target numerical range to which the register assignment belongs, the data processing instruction is length optimized to obtain a target compiled instruction whose instruction length is less than that of the data processing instruction; finally, the target compiled instruction is loaded through a virtual machine of a SIM card so as to execute the target compiled instruction through the virtual machine, thereby shortening the instruction length of the data processing instruction, obtaining the target compiled instruction, and being able to execute the target compiled instruction according to the virtual machine of the SIM card, thereby improving the use efficiency of the SIM card.

[0039] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0041] Figure 1 is a flowchart illustrating an instruction processing method according to an embodiment of the present disclosure.

[0042] Figure 2 Detailed description is a flowchart illustrating a method for determining a target compile instruction in an instruction processing method according to an embodiment of the present disclosure.

[0043] Figure 3 is a schematic diagram of an instruction processing system illustrating an instruction processing method according to an embodiment of the present disclosure.

[0044] Figure 4 is a block diagram illustrating an instruction processing apparatus according to an embodiment of the present disclosure.

[0045] Figure 5 is a hardware block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0046] Figure 6 is a schematic diagram illustrating a computer program product according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present disclosure more obvious, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0048] To facilitate understanding of this embodiment, a method for processing instructions disclosed in an embodiment of the present disclosure is first introduced in detail. The execution subject of the method for processing instructions provided in an embodiment of the present disclosure is generally an electronic device with certain computing capabilities, and the electronic device includes, for example, a terminal device or a server or other processing device. In some possible implementations, the method for processing instructions can be implemented by a processor calling a computer-readable instruction stored in a memory.

[0049] See also Figure 1 FIG. 1 is a flowchart of an instruction processing method provided by an embodiment of the present disclosure, wherein the method includes steps S101 to S104, wherein:

[0050] Step S101: Obtain data processing instructions to be processed.

[0051] Here, data processing instructions are control instructions for indicating the data content input into the register by the platform, for example, register assignment instructions, arithmetic instructions, logical instructions and displacement instructions, and each type of data processing instruction is used to indicate a function that can be implemented by the register.

[0052] Among them, register assignment instructions are used to indicate the assignment of values ​​to registers, for example, MOV instructions; arithmetic instructions are used to indicate arithmetic operations on data contents, for example, addition operation ADD instructions, subtraction operation SUB instructions, multiplication operation MUL instructions, and division operation DIV instructions; logical instructions are used to indicate logical operations on data contents, for example, AND instructions and OR instructions; displacement instructions are used to indicate displacement operations on data contents, for example, left shift SHL instructions and right shift SHR instructions.

[0053] In the embodiment of the present application, the platform inputs a programming language (eg, Java) into a compiler, and the compiler compiles the programming language to obtain data processing instructions after compilation.

[0054] Step S102: Determine the register assignment of the register assignment instruction in the data processing instruction.

[0055] Here, each register assignment instruction corresponds to a mnemonic. For example, the mnemonic of r1=0 is const-0 / r1, which is used to indicate that the register value 0 is assigned to register r1.

[0056] Step S103: Optimizing the length of the data processing instruction according to the target numerical range to which the register assignment belongs, to obtain a target compiled instruction whose instruction length is smaller than that of the data processing instruction.

[0057] Here, the target value range is used to indicate the value range of the register assignment.

[0058] In an embodiment of the present application, the platform obtains a data processing instruction obtained after compilation by a compiler, and optimizes the length of the data processing instruction according to a target numerical range to which the register assignment of the data processing instruction belongs, and outputs a target compiled instruction whose instruction length is less than that of the data processing instruction through the compiler.

[0059] Step S104: loading the target compilation instruction through the virtual machine of the SIM card, so as to execute the target compilation instruction through the virtual machine.

[0060] In an embodiment of the present application, the platform transmits the target compilation instructions output by the compiler to the SIM card, the virtual machine of the SIM card loads the target compilation instructions, and executes the target compilation instructions through the execution engine of the virtual machine.

[0061] In the above implementation, the platform optimizes the data processing instructions according to the target numerical range to which the register assignment belongs, and obtains a target compiled instruction whose instruction length is smaller than that of the data processing instruction, thereby shortening the instruction length of the data processing instruction, obtaining the target compiled instruction, and being able to execute the target compiled instruction according to the virtual machine of the SIM card, thereby improving the use efficiency of the SIM card.

[0062] In an optional implementation, the above steps perform length optimization processing on the data processing instruction according to the target numerical range to which the register assignment belongs, to obtain a target compiled instruction whose instruction length is smaller than that of the data processing instruction, specifically comprising the following steps:

[0063] According to the target numerical range, the number of bytes occupied by the register assignment and the instruction information of the data processing instruction is optimized to obtain the target compiled instruction; wherein the instruction information includes an instruction opcode and address information of the register corresponding to the register assignment.

[0064] Here, the instruction opcode is used to indicate the instruction identifier of the data processing instruction, for example, 0x01; the address information of the register is used to indicate the register identifier of the register, for example, the address information of the register r1 is 01.

[0065] In an embodiment of the present application, the platform optimizes the number of bytes occupied by the register assignment, instruction opcode, and address information of the register corresponding to the register assignment of the data processing instruction according to the target numerical range to which the register assignment belongs, and after optimization, a target compiled instruction is obtained whose instruction length is smaller than that of the data processing instruction.

[0066] In the above implementation, the register assignment and instruction information of the data processing instruction are optimized to shorten the instruction length of the data processing instruction, thereby reducing the space occupied by the data processing instruction and improving the execution efficiency of the data processing instruction.

[0067] In an optional implementation, the above steps optimize the number of bytes occupied by the register assignment and the instruction information of the data processing instruction according to the target numerical range to obtain the target compilation instruction, specifically comprising the following steps:

[0068] Determine an instruction encoding format corresponding to a target numerical range to which the register assignment belongs; wherein the instruction encoding format is used to indicate a shortening mode of bytes occupied by the register assignment and the instruction information;

[0069] The register assignment and the instruction information are subjected to instruction optimization processing according to the instruction encoding format to obtain the target compilation instruction.

[0070] Here, the instruction encoding format corresponds to the instruction operation code in one or more instruction information. For example, in the case of the instruction encoding format op, the instruction operation code corresponding to the instruction encoding format is 0x01~0x0F; in the case of the instruction encoding format op A|B, the instruction operation code corresponding to the instruction encoding format is 0x10.

[0071] Among them, op is the valid data bit of the instruction operation code, A is the address information of the register, and B is the valid data bit of the register assignment. If the instruction operation code is 0x01 and the register assignment value of register r1 is 1, then the instruction encoding format corresponding to the instruction operation code is op 01, A is 01, and B is 01.

[0072] In an embodiment of the present application, the platform determines the instruction encoding format corresponding to the register assignment according to the target numerical range to which the register assignment belongs, and performs instruction optimization processing on the register assignment and instruction information according to the instruction encoding format to obtain the target compilation instruction.

[0073] In an optional implementation, the above steps perform instruction optimization processing on the register assignment and the instruction information according to the instruction encoding format to obtain the target compilation instruction, specifically including the following steps:

[0074] When the target numerical range is a first preset numerical range, the register assignment and the address information in the instruction information are filtered, and the valid data bits of the instruction opcode in the instruction information are extracted to obtain the target compilation instruction; wherein the values ​​included in the first preset numerical range are values ​​whose assignment frequency is higher than the target frequency threshold.

[0075] Here, the first preset numerical range is used to indicate numerical values ​​whose assignment frequency is higher than the target frequency threshold. For example, if the assignment frequency of register assignments 0 to 4 is higher than the target frequency threshold, the first preset numerical range is 0 to 4.

[0076] The target frequency threshold may be set according to the usage frequency of the data processing instruction or the register model. For example, the target frequency threshold may be set to 0.5.

[0077] In an embodiment of the present application, when the platform determines that the target numerical range to which the register assignment belongs is a first preset numerical range, it filters the register assignment and the address information in the instruction information, extracts the valid data bits of the instruction opcode in the instruction information after filtering, and obtains the target compiled instruction (i.e., a single-byte instruction) after extraction.

[0078] For example, if the register assignment instruction is 0x010203, it means that the instruction opcode of the register assignment instruction is 0x01, and the value assigned to register r2 (that is, address information 02) is 3 (that is, register assignment 03), and the target compilation instruction corresponding to the register assignment instruction is 01 (that is, the valid data bit of the instruction opcode). That is, when the target numerical range to which the register assignment belongs is the first preset numerical range, the address information in the register assignment and the instruction information is filtered, and the valid data bits of the instruction opcode in the instruction information are extracted to obtain the target compilation instruction.

[0079] In an optional implementation, the above steps perform instruction optimization processing on the register assignment and the instruction information according to the instruction encoding format to obtain the target compilation instruction, specifically including the following steps:

[0080] When the target numerical value range is within the second preset numerical value range, determining valid data bits of the instruction operation code of the data processing instruction to obtain a first encoding byte;

[0081] Combining the address information in the instruction information and the valid data bits of the register assignment to obtain a second coded byte;

[0082] The first encoding byte and the second encoding byte are combined to obtain the target compilation instruction.

[0083] Here, the second preset numerical range is used to indicate that the register value assignment number is a 4-bit signed constant, that is, the second preset numerical range is -8 to 7.

[0084] For example, if the register assignment instruction is 0x100304, it means that the instruction opcode of the register assignment instruction is 0x10, and the value assigned to register r3 (ie, address information 03) is 4 (ie, register assignment 04), and the target compilation instruction corresponding to the register assignment instruction is 1034.

[0085] The first encoding byte is 10, which is the valid data bit of the instruction operation code; the second encoding byte is 34, which is obtained by combining the valid data bits of the address information and the register assignment.

[0086] In an embodiment of the present application, when the platform determines that the target numerical range to which the register assignment belongs is the second preset numerical range, it first determines the first coding byte based on the valid data bits of the instruction opcode of the data processing instruction, then merges the address information in the instruction information of the data processing instruction and the valid data bits of the register assignment to obtain the second coding byte, and finally merges the first coding byte and the second coding byte to obtain the target compiled instruction (i.e., a double-byte instruction).

[0087] In addition, for a specified register or a register exceeding a usage frequency threshold, the data processing instructions of the register may be optimized through the above processing method to obtain a target compilation instruction, but this application does not make any requirements for this.

[0088] In an optional implementation, the above steps perform instruction optimization processing on the register assignment and the instruction information according to the instruction encoding format to obtain the target compilation instruction, specifically including the following steps:

[0089] In the case where the target value range does not belong to the preset value range, determining whether the data bit of the register assignment is greater than the data bit of the address information;

[0090] In the case where it is determined that the data bit of the register value is greater than the data bit of the address information, the target compiled instruction is determined based on the instruction operation code and the valid data bit of the register value.

[0091] For example, if the register assignment instruction is 0x11030127, it means that the instruction opcode of the register assignment instruction is 0x11, and the value assigned to register r3 (that is, address information 03) is 127 (that is, register assignment 0127), and the data bit of the register assignment is greater than the data bit of the address information, then the target compilation instruction corresponding to the register assignment instruction is 117F. 7F is the form of converting the register assignment 0127 into hexadecimal.

[0092] In an embodiment of the present application, when the platform determines that the target numerical range to which the register assignment belongs does not belong to the preset numerical range (the first preset numerical range or the second preset numerical range), if the register assignment number of the data processing instruction is an 8-bit signed constant (i.e., -128 to 127), it determines whether the data bits of the register assignment are greater than the data bits of the address information. When it is determined that the data bits of the register assignment are greater than the data bits of the address information, the target compilation instruction (i.e., a double-byte instruction) of the data processing instruction is determined based on the instruction opcode and the valid data bits of the register assignment.

[0093] See also Figure 2 As shown, it is a flowchart of determining a target compilation instruction provided by an embodiment of the present disclosure, including the following steps:

[0094] Step S201: when it is determined that the data bits of the register value are less than or equal to the data bits of the address information, the target compilation instruction is determined based on the instruction operation code, the register value and the valid data bits of the address information.

[0095] For example, if the register assignment instruction is 0x17039, it means that the instruction opcode of the register assignment instruction is 0x17, and the value assigned to register r3 (that is, address information 03) is 9 (that is, register assignment 9), and the data bit of the register assignment is smaller than the data bit of the address information, then the target compilation instruction corresponding to the register assignment instruction is 170309 or 170311. 11 is the form of converting the register assignment 9 into octal.

[0096] For example, if the register assignment instruction is 0x170320, it means that the instruction opcode of the register assignment instruction is 0x17, and the value assigned to register r3 (that is, address information 03) is 20 (that is, register assignment 20), and the data bit of the register assignment is equal to the data bit of the address information, then the target compilation instruction corresponding to the register assignment instruction is 170320 or 170314. 14 is the register assignment 20 converted to hexadecimal form.

[0097] In an embodiment of the present application, when the platform determines that the data bits of the register assignment of the data processing instruction are less than or equal to the data bits of the address information, it determines the target compilation instruction (i.e., a three-byte instruction) of the data processing instruction based on the instruction opcode, the register assignment, and the valid data bits of the address information.

[0098] In an optional implementation, the above steps perform instruction optimization processing on the register assignment and the instruction information according to the instruction encoding format to obtain the target compilation instruction, specifically including the following steps:

[0099] In a case where the target numerical range does not belong to a preset numerical range, the target compilation instruction is determined based on the original data bits of the register assignment.

[0100] For example, if the register assignment instruction is 0x18031000, it means that the instruction opcode of the register assignment instruction is 0x17, and the value of 1000 is assigned to register r3 (ie, address information 03) (ie, register assignment 1000), then the target compilation instruction corresponding to the register assignment instruction is 181000.

[0101] In an embodiment of the present application, when the platform determines that the target numerical range of the register assignment of the data processing instruction does not belong to the preset numerical range (the first preset numerical range or the second preset numerical range), if the register assignment number of the data processing instruction is a 16-bit signed constant (i.e., -32768 to 32767), the address information of the data processing instruction is filtered and the target compilation instruction (i.e., a three-byte instruction) of the data processing instruction is determined based on the original data bits of the register assignment.

[0102] In an optional implementation, the above steps perform length optimization processing on the data processing instruction according to the target numerical range to which the register assignment belongs, to obtain a target compiled instruction whose instruction length is smaller than that of the data processing instruction, specifically comprising the following steps:

[0103] When it is determined that the target numerical range to which the register value is assigned does not belong to the preset numerical range, the target compilation instruction is determined according to the valid data bits of the address information and the original data bits of the register value assigned.

[0104] For example, if the register assignment instruction is 0x1E01001000, it means that the instruction opcode of the register assignment instruction is 0x1E, and the value of 1000 is assigned to register r100 (that is, address information 0100) (that is, register assignment 1000), then the target compilation instruction corresponding to the register assignment instruction is 1E641000. 64 is the address information 100 converted into hexadecimal form.

[0105] In an embodiment of the present application, when the platform determines that the target numerical range of the register assignment of the data processing instruction does not belong to the preset numerical range (the first preset numerical range or the second preset numerical range), if the register assignment number is greater than a 16-bit signed constant, the target compilation instruction (i.e., four bytes) of the data processing instruction is determined according to the valid data bits of the address information of the data processing instruction and the original data bits of the register assignment.

[0106] In addition, the target compilation instruction of the data processing instruction may be determined according to the original data bits of the address information of the data processing instruction and the valid data bits of the register assignment.

[0107] For example, if the register assignment instruction is 0x1E0340000, it means that the instruction opcode of the register assignment instruction is 0x1E, and the value of 40000 is assigned to register r3 (that is, address information 03) (that is, register assignment 40000), then the target compilation instruction corresponding to the register assignment instruction is 1E039C40. 9C40 is the register assignment 40000 converted to hexadecimal form.

[0108] In the above implementation, the integrity of each type of data processing instruction is retained by determining the target compilation instruction according to the valid data bits of the address information and the original data bits of the register assignment.

[0109] In addition, if the target value range to which the register assignment belongs is within multiple preset value ranges, the number of bytes of the target compilation instruction corresponding to each preset value range is determined, and the target compilation instruction with the least number of bytes is selected as the target compilation instruction for the register assignment.

[0110] For example, if the register assignment is 0, that is, the target numerical range to which the register assignment belongs is within the first preset numerical range and the second preset numerical range, since the number of bytes of the target compilation instruction corresponding to the first preset numerical range is single-byte, and the number of bytes of the target compilation instruction corresponding to the second preset numerical range is double-byte, then the target compilation instruction of the register assignment is the target compilation instruction corresponding to the first preset numerical range (that is, a single-byte instruction).

[0111] Reference Figure 3 As shown, it is a schematic diagram of an instruction processing system provided by the present application, and the instruction processing system includes a programming language module, an off-card link module and an on-card virtual machine module. The programming language module is used to store various types of programming languages, such as Java, Python; the off-card link module includes a link file, a compiler and an executable file (i.e., a target compilation instruction); the on-card virtual machine module includes a data running area, an execution engine and a Native method.

[0112] Among them, the link file is used to instruct the compiler to compile the programming language into the file generated during the compilation process of data processing instructions, for example, the web page link file; the Native method is used to indicate the conversion of the executable file into a method that can be called by the virtual machine; the execution engine is used to process the executable file according to the Native method so as to execute the executable file through the virtual machine; the data running area includes the heap, stack, and program counter, which are used to store file information during the execution process of the virtual machine executing the executable file.

[0113] According to the above description, the programming language is first input into the external card link module through the programming language module, and then the compiler in the external card link module compiles the programming language into data processing instructions, and compiles the data processing instructions through the link file, and outputs an executable file (i.e., target compilation instructions) to load and execute the executable file through the virtual machine module inside the card.

[0114] Based on the same inventive concept, an instruction processing device corresponding to the instruction processing method is also provided in the embodiment of the present disclosure. Since the principle of solving the problem by the device in the embodiment of the present disclosure is similar to the above-mentioned instruction processing method in the embodiment of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0115] Reference Figure 4 FIG. 1 is a schematic diagram of an instruction processing device provided by an embodiment of the present disclosure, wherein the device comprises: an acquisition unit 40, a value determination unit 41, a processing unit 42, and an instruction execution unit 43; wherein:

[0116] An acquisition unit, used for acquiring data processing instructions to be processed;

[0117] an assignment determination unit, used to determine a register assignment of a register assignment instruction in the data processing instruction;

[0118] A processing unit, configured to perform length optimization processing on the data processing instruction according to a target numerical range to which the register assignment belongs, to obtain a target compiled instruction having an instruction length smaller than that of the data processing instruction;

[0119] The instruction execution unit is used to load the target compiled instruction through the virtual machine of the SIM card, so as to execute the target compiled instruction through the virtual machine.

[0120] In a possible implementation manner, the device is also used for:

[0121] According to the target numerical range, the number of bytes occupied by the register assignment and the instruction information of the data processing instruction is optimized to obtain the target compiled instruction; wherein the instruction information includes an instruction opcode and address information of the register corresponding to the register assignment.

[0122] In a possible implementation manner, the device is also used for:

[0123] Determine an instruction encoding format corresponding to a target numerical range to which the register assignment belongs; wherein the instruction encoding format is used to indicate a shortening mode of bytes occupied by the register assignment and the instruction information;

[0124] The register assignment and the instruction information are subjected to instruction optimization processing according to the instruction encoding format to obtain the target compilation instruction.

[0125] In a possible implementation manner, the device is also used for:

[0126] When the target numerical range is a first preset numerical range, the register assignment and the address information in the instruction information are filtered, and the valid data bits of the instruction opcode in the instruction information are extracted to obtain the target compilation instruction; wherein the values ​​included in the first preset numerical range are values ​​whose assignment frequency is higher than the target frequency threshold.

[0127] In a possible implementation manner, the device is also used for:

[0128] When the target numerical value range is within the second preset numerical value range, determining valid data bits of the instruction operation code of the data processing instruction to obtain a first encoding byte;

[0129] Combining the address information in the instruction information and the valid data bits of the register assignment to obtain a second coded byte;

[0130] The first encoding byte and the second encoding byte are combined to obtain the target compilation instruction.

[0131] In a possible implementation manner, the device is also used for:

[0132] In the case where the target value range does not belong to the preset value range, determining whether the data bit of the register assignment is greater than the data bit of the address information;

[0133] In the case where it is determined that the data bit of the register value is greater than the data bit of the address information, the target compiled instruction is determined based on the instruction operation code and the valid data bit of the register value.

[0134] In a possible implementation manner, the device is also used for:

[0135] In case it is determined that the data bits of the register assignment are less than or equal to the data bits of the address information, the target compiled instruction is determined based on the instruction operation code, the register assignment and the valid data bits of the address information.

[0136] In a possible implementation manner, the device is also used for:

[0137] In a case where the target numerical range does not belong to a preset numerical range, the target compilation instruction is determined based on the original data bits of the register assignment.

[0138] In a possible implementation manner, the device is also used for:

[0139] When it is determined that the target numerical range to which the register value is assigned does not belong to the preset numerical range, the target compilation instruction is determined according to the valid data bits of the address information and the original data bits of the register value assigned.

[0140] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference may be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.

[0141] Corresponds to Figure 1 The instruction processing method in the present disclosure also provides an electronic device 50, such as Figure 5 FIG. 1 is a schematic diagram of the structure of an electronic device 50 provided in an embodiment of the present disclosure, including:

[0142] Processor 51, memory 52, and bus 53; memory 52 is used to store execution instructions, including internal memory 521 and external memory 522; the internal memory 521 is also called internal memory, which is used to temporarily store the operation data in the processor 51 and the data exchanged with the external memory 522 such as a hard disk. The processor 51 exchanges data with the external memory 522 through the internal memory 521. When the electronic device 50 is running, the processor 51 communicates with the memory 52 through the bus 53, so that the processor 51 executes the following instructions:

[0143] Obtaining data processing instructions to be processed;

[0144] determining a register assignment of a register assignment instruction in the data processing instruction;

[0145] According to the target numerical range to which the register assignment belongs, the data processing instruction is optimized in length to obtain a target compiled instruction with an instruction length smaller than that of the data processing instruction;

[0146] The target compilation instruction is loaded through the virtual machine of the SIM card, so as to execute the target compilation instruction through the virtual machine.

[0147] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the instruction processing method described in the above method embodiment are executed. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0148] The present disclosure also provides a computer program product 60, such as Figure 6 As shown, it is a structural schematic diagram of a computer program product 60 provided in an embodiment of the present disclosure. The computer program product 60 carries a computer program 61. The program included in the computer program 61 can be used to execute the steps of the instruction processing method described in the above method embodiment. For details, please refer to the above method embodiment, which will not be repeated here.

[0149] In the above, the instruction processing method, apparatus, device, medium and product according to the embodiments of the present disclosure are described with reference to the accompanying drawings. First, a data processing instruction to be processed is obtained; then, a register assignment of a register assignment instruction in the data processing instruction is determined; and according to a target numerical range to which the register assignment belongs, the length of the data processing instruction is optimized to obtain a target compiled instruction whose instruction length is less than that of the data processing instruction. Finally, the target compiled instruction is loaded through a virtual machine of a SIM card so as to execute the target compiled instruction through the virtual machine, thereby shortening the instruction length of the data processing instruction and reducing the space occupied by the data processing instruction, obtaining the target compiled instruction, and being able to execute the target compiled instruction according to the virtual machine of the SIM card, thereby improving the use efficiency of the SIM card.

[0150] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0151] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0152] Additionally, as used herein, "or" used in a list of items beginning with "at least one" indicates a separate list, so that, for example, a list of "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not mean that the example described is preferred or better than other examples.

[0153] It should also be noted that in the system and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0154] Various changes, substitutions, and modifications of the techniques described herein may be made without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of the present disclosure is not limited to the specific aspects of the processes, machines, manufactures, compositions of events, means, methods, and actions described above. Currently existing or later to be developed processes, machines, manufactures, compositions of events, means, methods, or actions that perform substantially the same functions or achieve substantially the same results as the corresponding aspects described herein may be utilized. Thus, the appended claims include such processes, machines, manufactures, compositions of events, means, methods, or actions within their scope.

[0155] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0156] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A command processing method, characterized in that: include: Obtaining data processing instructions to be processed; determining a register assignment of a register assignment instruction in the data processing instruction; According to the target numerical range to which the register assignment belongs, the data processing instruction is optimized in length to obtain a target compiled instruction with an instruction length smaller than that of the data processing instruction; The target compilation instruction is loaded through the virtual machine of the SIM card, so as to execute the target compilation instruction through the virtual machine.

2. The method according to claim 1, characterized in that The step of performing length optimization processing on the data processing instruction according to the target numerical range to which the register assignment belongs, to obtain a target compilation instruction with an instruction length smaller than that of the data processing instruction, comprises: According to the target numerical range, the number of bytes occupied by the register assignment and the instruction information of the data processing instruction is optimized to obtain the target compiled instruction; wherein the instruction information includes an instruction opcode and address information of the register corresponding to the register assignment.

3. The method according to claim 2, characterized in that The step of optimizing the number of bytes occupied by the register assignment and the instruction information of the data processing instruction according to the target numerical range to obtain the target compilation instruction includes: Determine an instruction encoding format corresponding to a target numerical range to which the register assignment belongs; wherein the instruction encoding format is used to indicate a shortening mode of bytes occupied by the register assignment and the instruction information; The register assignment and the instruction information are subjected to instruction optimization processing according to the instruction encoding format to obtain the target compilation instruction.

4. The method according to claim 3, characterized in that The performing instruction optimization processing on the register assignment and the instruction information according to the instruction encoding format to obtain the target compilation instruction includes: When the target numerical range is a first preset numerical range, the register assignment and the address information in the instruction information are filtered, and the valid data bits of the instruction opcode in the instruction information are extracted to obtain the target compilation instruction; wherein the values ​​included in the first preset numerical range are values ​​whose assignment frequency is higher than the target frequency threshold.

5. The method according to claim 3, characterized in that: The performing instruction optimization processing on the register assignment and the instruction information according to the instruction encoding format to obtain the target compilation instruction includes: When the target numerical value range is within the second preset numerical value range, determining valid data bits of the instruction operation code of the data processing instruction to obtain a first encoding byte; Combining the address information in the instruction information and the valid data bits of the register assignment to obtain a second coded byte; The first encoding byte and the second encoding byte are combined to obtain the target compilation instruction.

6. The method according to claim 3, characterized in that The performing instruction optimization processing on the register assignment and the instruction information according to the instruction encoding format to obtain the target compilation instruction includes: In the case where the target value range does not belong to the preset value range, determining whether the data bit of the register assignment is greater than the data bit of the address information; In the case where it is determined that the data bit of the register value is greater than the data bit of the address information, the target compiled instruction is determined based on the instruction operation code and the valid data bit of the register value.

7. The method according to claim 6, characterized in that The method further comprises: In case it is determined that the data bits of the register assignment are less than or equal to the data bits of the address information, the target compiled instruction is determined based on the instruction operation code, the register assignment and the valid data bits of the address information.

8. The method according to claim 3, characterized in that The performing instruction optimization processing on the register assignment and the instruction information according to the instruction encoding format to obtain the target compilation instruction includes: In a case where the target numerical range does not belong to a preset numerical range, the target compilation instruction is determined based on the original data bits of the register assignment.

9. The method according to claim 1, characterized in that: The step of performing length optimization processing on the data processing instruction according to the target numerical range to which the register assignment belongs, to obtain a target compilation instruction with an instruction length smaller than that of the data processing instruction, comprises: When it is determined that the target numerical range to which the register value is assigned does not belong to the preset numerical range, the target compilation instruction is determined according to the valid data bits of the address information and the original data bits of the register value assigned.

10. An instruction processing device, characterized in that: include: An acquisition unit, used for acquiring data processing instructions to be processed; an assignment determination unit, used to determine a register assignment of a register assignment instruction in the data processing instruction; A processing unit, configured to perform length optimization processing on the data processing instruction according to a target numerical range to which the register assignment belongs, to obtain a target compiled instruction having an instruction length smaller than that of the data processing instruction; The instruction execution unit is used to load the target compiled instruction through the virtual machine of the SIM card, so as to execute the target compiled instruction through the virtual machine.

11. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the instruction processing method as described in any one of claims 1 to 9 are performed.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the instruction processing method according to any one of claims 1 to 9 are executed.

13. A computer program product, characterized in that The computer program product is stored in a storage medium, and the program product is executed by at least one processor to implement the instruction processing method according to any one of claims 1 to 9.

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